HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · designs/EGSE_ICI/top_designer_act.tcl

MiniSpartan6:...

MiniSpartan6: added ftdi chip config to switch between UART and Async FIFO. added few WIP designs with either spwlight core, FIFO_deom IP... Libs: added SpaceWire Light IP (Works really well!) started design of ahb_ftdi_fifo -> same protocol than AHBUART but over FTDI's Async FIFO interface. This might lead to much faster transfers UP to 12MB/s.

Alexis Jeandet - - Load All Authors

File last commit:

r217:13429b36c676 alexis


                r681:9d85f9f8f05a

default

Download file

             top_designer_act.tcl
        
                    8 lines
            
             | 535 B
            
                | application/x-tcl
            
             |
                TclLexer
            
             / designs / EGSE_ICI / top_designer_act.tcl
          
                    History
                
                 |
                  Annotation
                 | Raw
                 |Copy content
                 |Copy permalink

      new_design -name "top" -family "PROASIC3" 

      set_device -die "A3PE1500" -package "208 PQFP" -speed "Std" -voltage "1.5" -iostd "LVTTL" -jtag "yes" -probe "yes" -trst "yes" -temprange "COM" -voltrange "COM" 

      if {[file exist top.pdc]} {

      import_source -format "edif" -edif_flavor "GENERIC"  -merge_physical "no" -merge_timing "no" {synplify/top.edf} -format "pdc" -abort_on_error "no" {top.pdc}

      } else {

      import_source -format "edif" -edif_flavor "GENERIC"  -merge_physical "no" -merge_timing "no" {synplify/top.edf}

      }

      save_design {top.adb}

	Site-wide shortcuts
/	Use quick search box
g h	Goto home page
g g	Goto my private gists page
g G	Goto my public gists page
g 0-9	Goto bookmarked items from 0-9
n r	New repository page
n g	New gist page

	Repositories
g s	Goto summary page
g c	Goto changelog page
g f	Goto files page
g F	Goto files page with file search activated
g p	Goto pull requests page
g o	Goto repository settings
g O	Goto repository access permissions settings
t s	Toggle sidebar on some pages

				new_design -name "top" -family "PROASIC3"
				set_device -die "A3PE1500" -package "208 PQFP" -speed "Std" -voltage "1.5" -iostd "LVTTL" -jtag "yes" -probe "yes" -trst "yes" -temprange "COM" -voltrange "COM"
				if {[file exist top.pdc]} {
				import_source -format "edif" -edif_flavor "GENERIC" -merge_physical "no" -merge_timing "no" {synplify/top.edf} -format "pdc" -abort_on_error "no" {top.pdc}
				} else {
				import_source -format "edif" -edif_flavor "GENERIC" -merge_physical "no" -merge_timing "no" {synplify/top.edf}
				}
				save_design {top.adb}