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update CAL 1/2
martin -
r236:e34a2fdaf0b1 martin
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@@ -45,10 +45,7 use lpp.lpp_ad_conv.all;
45 use lpp.iir_filter.all;
45 use lpp.iir_filter.all;
46 use lpp.general_purpose.all;
46 use lpp.general_purpose.all;
47 use lpp.Filtercfg.all;
47 use lpp.Filtercfg.all;
48 use lpp.lpp_demux.all;
48 use lpp.lpp_cna.all;
49 use lpp.lpp_top_lfr_pkg.all;
50 use lpp.lpp_dma_pkg.all;
51 use lpp.lpp_Header.all;
52
49
53 entity leon3mp is
50 entity leon3mp is
54 generic (
51 generic (
@@ -96,28 +93,13 entity leon3mp is
96 ---------------------------------------------------------------------
93 ---------------------------------------------------------------------
97 --- AJOUT TEST ------------------------In/Out-----------------------
94 --- AJOUT TEST ------------------------In/Out-----------------------
98 ---------------------------------------------------------------------
95 ---------------------------------------------------------------------
96 -- DAC
97 DAC_SYNC : out std_logic;
98 DAC_SCLK : out std_logic;
99 DAC_DATA : out std_logic;
99 -- UART
100 -- UART
100 UART_RXD : in std_logic;
101 UART_RXD : in std_logic;
101 UART_TXD : out std_logic;
102 UART_TXD : out std_logic;
102 -- ACQ
103 CNV_CH1 : OUT STD_LOGIC;
104 SCK_CH1 : OUT STD_LOGIC;
105 SDO_CH1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
106 Bias_Fails : out std_logic;
107 -- ADC
108 -- ADC_in : in AD7688_in(4 downto 0);
109 -- ADC_out : out AD7688_out;
110
111 -- CNA
112 -- DAC_SYNC : out std_logic;
113 -- DAC_SCLK : out std_logic;
114 -- DAC_DATA : out std_logic;
115 -- Diver
116 SPW1_EN : out std_logic;
117 SPW2_EN : out std_logic;
118 TEST : out std_logic_vector(3 downto 0);
119
120 BP : in std_logic;
121 ---------------------------------------------------------------------
103 ---------------------------------------------------------------------
122 led : out std_logic_vector(1 downto 0)
104 led : out std_logic_vector(1 downto 0)
123 );
105 );
@@ -126,7 +108,7 end;
126 architecture Behavioral of leon3mp is
108 architecture Behavioral of leon3mp is
127
109
128 constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
110 constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
129 CFG_GRETH+CFG_AHB_JTAG+1; -- +1 pour le DMA
111 CFG_GRETH+CFG_AHB_JTAG;
130 constant maxahbm : integer := maxahbmsp;
112 constant maxahbm : integer := maxahbmsp;
131
113
132 --Clk & Rst gοΏ½nοΏ½
114 --Clk & Rst gοΏ½nοΏ½
@@ -178,103 +160,7 signal dsuo : dsu_out_type;
178 ---------------------------------------------------------------------
160 ---------------------------------------------------------------------
179 --- AJOUT TEST ------------------------Signaux----------------------
161 --- AJOUT TEST ------------------------Signaux----------------------
180 ---------------------------------------------------------------------
162 ---------------------------------------------------------------------
181 -- FIFOs
182 signal FifoF0_Empty : std_logic_vector(4 downto 0);
183 signal FifoF0_Data : std_logic_vector(79 downto 0);
184 signal FifoF1_Empty : std_logic_vector(4 downto 0);
185 signal FifoF1_Data : std_logic_vector(79 downto 0);
186 signal FifoF3_Empty : std_logic_vector(4 downto 0);
187 signal FifoF3_Data : std_logic_vector(79 downto 0);
188
163
189 signal FifoINT_Full : std_logic_vector(4 downto 0);
190 signal FifoINT_Data : std_logic_vector(79 downto 0);
191
192 signal FifoOUT_Full : std_logic_vector(1 downto 0);
193 signal FifoOUT_Empty : std_logic_vector(1 downto 0);
194 signal FifoOUT_Data : std_logic_vector(63 downto 0);
195
196
197 -- MATRICE SPECTRALE
198 signal SM_FlagError : std_logic;
199 signal SM_Pong : std_logic;
200 signal SM_Wen : std_logic;
201 signal SM_Read : std_logic_vector(4 downto 0);
202 signal SM_Write : std_logic_vector(1 downto 0);
203 signal SM_ReUse : std_logic_vector(4 downto 0);
204 signal SM_Param : std_logic_vector(3 downto 0);
205 signal SM_Data : std_logic_vector(63 downto 0);
206
207 --signal Dma_acq : std_logic;
208 --signal Head_Valid : std_logic;
209
210 -- FFT
211 signal FFT_Load : std_logic;
212 signal FFT_Read : std_logic_vector(4 downto 0);
213 signal FFT_Write : std_logic_vector(4 downto 0);
214 signal FFT_ReUse : std_logic_vector(4 downto 0);
215 signal FFT_Data : std_logic_vector(79 downto 0);
216
217 -- DEMUX
218 signal DMUX_Read : std_logic_vector(14 downto 0);
219 signal DMUX_Empty : std_logic_vector(4 downto 0);
220 signal DMUX_Data : std_logic_vector(79 downto 0);
221 signal DMUX_WorkFreq : std_logic_vector(1 downto 0);
222
223 -- ACQ
224 signal sample_val : STD_LOGIC;
225 signal sample : Samples(8-1 DOWNTO 0);
226
227 signal ACQ_WenF0 : STD_LOGIC_VECTOR(4 DOWNTO 0);
228 signal ACQ_DataF0 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
229 signal ACQ_WenF1 : STD_LOGIC_VECTOR(4 DOWNTO 0);
230 signal ACQ_DataF1 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
231 signal ACQ_WenF3 : STD_LOGIC_VECTOR(4 DOWNTO 0);
232 signal ACQ_DataF3 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
233
234 -- Header
235 signal Head_Read : std_logic_vector(1 downto 0);
236 signal Head_Data : std_logic_vector(31 downto 0);
237 signal Head_Empty : std_logic;
238 signal Head_Header : std_logic_vector(31 DOWNTO 0);
239 signal Head_Valid : std_logic;
240 signal Head_Val : std_logic;
241
242 --DMA
243 signal DMA_Read : std_logic;
244 signal DMA_ack : std_logic;
245 --signal AHB_Master_In : AHB_Mst_In_Type;
246 --signal AHB_Master_Out : AHB_Mst_Out_Type;
247
248
249 -- ADC
250 --signal SmplClk : std_logic;
251 --signal ADC_DataReady : std_logic;
252 --signal ADC_SmplOut : Samples_out(4 downto 0);
253 --signal enableADC : std_logic;
254 --
255 --signal WG_Write : std_logic_vector(4 downto 0);
256 --signal WG_ReUse : std_logic_vector(4 downto 0);
257 --signal WG_DATA : std_logic_vector(79 downto 0);
258 --signal s_out : std_logic_vector(79 downto 0);
259 --
260 --signal fuller : std_logic_vector(4 downto 0);
261 --signal reader : std_logic_vector(4 downto 0);
262 --signal try : std_logic_vector(1 downto 0);
263 --signal TXDint : std_logic;
264 --
265 ---- IIR Filter
266 --signal sample_clk_out : std_logic;
267 --
268 --signal Rd : std_logic_vector(0 downto 0);
269 --signal Ept : std_logic_vector(4 downto 0);
270 --
271 --signal Bwr : std_logic_vector(0 downto 0);
272 --signal Bre : std_logic_vector(0 downto 0);
273 --signal DataTMP : std_logic_vector(15 downto 0);
274 --signal FullUp : std_logic_vector(0 downto 0);
275 --signal EmptyUp : std_logic_vector(0 downto 0);
276 --signal FullDown : std_logic_vector(0 downto 0);
277 --signal EmptyDown : std_logic_vector(0 downto 0);
278 ---------------------------------------------------------------------
164 ---------------------------------------------------------------------
279 constant IOAEN : integer := CFG_CAN;
165 constant IOAEN : integer := CFG_CAN;
280 constant boardfreq : integer := 50000;
166 constant boardfreq : integer := 50000;
@@ -284,245 +170,29 begin
284 ---------------------------------------------------------------------
170 ---------------------------------------------------------------------
285 --- AJOUT TEST -------------------------------------IPs-------------
171 --- AJOUT TEST -------------------------------------IPs-------------
286 ---------------------------------------------------------------------
172 ---------------------------------------------------------------------
287 led(1 downto 0) <= gpio(1 downto 0);
288
289 --- COM USB ---------------------------------------------------------
290 -- MemIn0 : APB_FifoWrite
291 -- generic map (5,5, Data_sz => 8, Addr_sz => 8, addr_max_int => 256)
292 -- port map (clkm,rstn,apbi,USB_Read,open,open,InOutData,apbo(5));
293 --
294 -- BUF0 : APB_USB
295 -- generic map (6,6,DataMax => 1024)
296 -- port map(clkm,rstn,flagC,flagB,ifclk,sloe,USB_Read,USB_Write,pktend,fifoadr,InOutData,apbi,apbo(6));
297 --
298 -- MemOut0 : APB_FifoRead
299 -- generic map (7,7, Data_sz => 8, Addr_sz => 8, addr_max_int => 256)
300 -- port map (clkm,rstn,apbi,USB_Write,open,open,InOutData,apbo(7));
301 --
302 --slrd <= usb_Read;
303 --slwr <= usb_Write;
304
305 --- CNA -------------------------------------------------------------
306
307 -- CONV : APB_CNA
308 -- generic map (5,5)
309 -- port map(clkm,rstn,apbi,apbo(5),DAC_SYNC,DAC_SCLK,DAC_DATA);
310
311 --TEST(0) <= SmplClk;
312 --TEST(1) <= WG_Write(0);
313 --TEST(2) <= Fuller(0);
314 --TEST(3) <= s_out(s_out'length-1);
315
316
317 --SPW1_EN <= '1';
318 --SPW2_EN <= '0';
319
320 --- CAN -------------------------------------------------------------
321
173
322 -- Divider : Clk_divider
174 -- apbo not free : 0 1 2 3 7 11
323 -- generic map(OSC_freqHz => 24_576_000, TargetFreq_Hz => 24_576)
324 -- Port map(clkm,rstn,SmplClk);
325 --
326 -- ADC : AD7688_drvr
327 -- generic map (ChanelCount => 5, clkkHz => 24_576)
328 -- port map (clkm,rstn,enableADC,SmplClk,ADC_DataReady,ADC_SmplOut,ADC_in,ADC_out);
329 --
330 -- WG : WriteGen_ADC
331 -- port map (clkm,rstn,SmplClk,ADC_DataReady,Fuller,WG_ReUse,WG_Write);
332 --
333 --enableADC <= gpio(0);
334
175
335 --WG_DATA <= ADC_SmplOut(4) & ADC_SmplOut(3) & ADC_SmplOut(2) & ADC_SmplOut(1) & ADC_SmplOut(0);
176 --- DAC -------------------------------------------------------------
336 --
337 --
338 -- MemIn1 : APB_FIFO
339 -- generic map (pindex => 6, paddr => 6, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
340 -- port map (clkm,rstn,clkm,clkm,WG_ReUse,(others => '1'),WG_Write,open,Fuller,open,WG_DATA,open,open,apbi,apbo(6));
341
342 -- DIGITAL_acquisition : ADS7886_drvr
343 -- GENERIC MAP (
344 -- ChanelCount => 8,
345 -- ncycle_cnv_high => 79,
346 -- ncycle_cnv => 500)
347 -- PORT MAP (
348 -- cnv_clk => clk50MHz, --
349 -- cnv_rstn => rstn, --
350 -- cnv_run => '1', --
351 -- cnv => CNV_CH1, --
352 -- clk => clkm, --
353 -- rstn => rstn, --
354 -- sck => SCK_CH1, --
355 -- sdo => SDO_CH1, --
356 -- sample => sample,
357 -- sample_val => sample_val);
358 --
359 --TopACQ_WenF0 <= not sample_filter_v2_out_val & not sample_filter_v2_out_val & not sample_filter_v2_out_val & not sample_filter_v2_out_val & not sample_filter_v2_out_val;
360 --TopACQ_DataF0 <= E & D & C & B & A;
361
362 --
363 --TEST(0) <= TopACQ_WenF0(1);
364 --TEST(1) <= SDO_CH1(1);
365 --
366 --process(clkm,rstn)
367 --begin
368 -- if(rstn='0')then
369 -- TopACQ_WenF0a <= (others => '1');
370 --
371 -- elsif(clkm'event and clkm='1')then
372 -- TopACQ_WenF0a <= not sample_val & not sample_val & not sample_val & not sample_val & not sample_val;
373 --
374 -- end if;
375 --end process;
376
377 ACQ0 : lpp_top_acq
378 port map('1',CNV_CH1,SCK_CH1,SDO_CH1,clk50MHz,rstn,clkm,rstn,ACQ_WenF0,ACQ_DataF0,ACQ_WenF1,ACQ_DataF1,open,open,ACQ_WenF3,ACQ_DataF3);
379
177
380 Bias_Fails <= '0';
178 CAL0 : APB_CNA
381 --------- FIFO IN -------------------------------------------------------------
179 generic map (pindex => 4, paddr => 4)
382 ----
180 port map(clkm,rstn,apbi,apbo(4),DAC_SYNC,DAC_SCLK,DAC_DATA);
383 -- Memf0 : APB_FIFO
384 -- generic map (pindex => 9, paddr => 9, FifoCnt => 5, Data_sz => 16, Addr_sz => 9, Enable_ReUse => '0', R => 1, W => 0)
385 -- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),ACQ_WenF0,open,open,open,ACQ_DataF0,open,open,apbi,apbo(9));
386 --
387 -- Memf1 : APB_FIFO
388 -- generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
389 -- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),ACQ_WenF1,open,open,open,ACQ_DataF1,open,open,apbi,apbo(8));
390 --
391 -- Memf3 : APB_FIFO
392 -- generic map (pindex => 5, paddr => 5, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
393 -- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),ACQ_WenF3,open,open,open,ACQ_DataF3,open,open,apbi,apbo(5));
394
395 Memf0 : lppFIFOxN
396 generic map(Data_sz => 16, Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0')
397 port map(rstn,clkm,clkm,(others => '0'),ACQ_WenF0,DMUX_Read(4 downto 0),ACQ_DataF0,FifoF0_Data,open,FifoF0_Empty);
398
399 Memf1 : lppFIFOxN
400 generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
401 port map(rstn,clkm,clkm,(others => '0'),ACQ_WenF1,DMUX_Read(9 downto 5),ACQ_DataF1,FifoF1_Data,open,FifoF1_Empty);
402
403 Memf3 : lppFIFOxN
404 generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
405 port map(rstn,clkm,clkm,(others => '0'),ACQ_WenF3,DMUX_Read(14 downto 10),ACQ_DataF3,FifoF3_Data,open,FifoF3_Empty);
406 --
407 ----- DEMUX -------------------------------------------------------------
408
409 DMUX0 : DEMUX
410 generic map(Data_sz => 16)
411 port map(clkm,rstn,FFT_Read,FFT_Load,FifoF0_Empty,FifoF1_Empty,FifoF3_Empty,FifoF0_Data,FifoF1_Data,FifoF3_Data,DMUX_WorkFreq,DMUX_Read,DMUX_Empty,DMUX_Data);
412
413 ------- FFT -------------------------------------------------------------
414
415 -- MemIn : APB_FIFO
416 -- generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1)
417 -- port map (clkm,rstn,clkm,clkm,(others => '0'),FFT_Read,(others => '1'),DMUX_Empty,open,DMUX_Data,(others => '0'),open,open,apbi,apbo(8));
418
419 FFT0 : FFT
420 generic map(Data_sz => 16,NbData => 256)
421 port map(clkm,rstn,DMUX_Empty,DMUX_Data,FifoINT_Full,FFT_Load,FFT_Read,FFT_Write,FFT_ReUse,FFT_Data);
422
423 --------- LINK MEMORY -------------------------------------------------------
424
425 -- MemOut : APB_FIFO
426 -- generic map (pindex => 9, paddr => 9, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 0)
427 -- port map (clkm,rstn,clkm,clkm,FFT_ReUse,(others =>'1'),FFT_Write,open,FifoINT_Full,open,FFT_Data,open,open,apbi,apbo(9));
428
429 MemInt : lppFIFOxN
430 generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '1')
431 port map(rstn,clkm,clkm,SM_ReUse,FFT_Write,SM_Read,FFT_Data,FifoINT_Data,FifoINT_Full,open);
432
181
433 -- MemIn : APB_FIFO
434 -- generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 0, W => 1)
435 -- port map (clkm,rstn,clkm,clkm,(others => '0'),SM_Read,(others => '1'),open,FifoINT_Full,FifoINT_Data,(others => '0'),open,open,apbi,apbo(8));
436
437 ----- MATRICE SPECTRALE ---------------------5 FIFO Input---------------
438
439 SM0 : MatriceSpectrale
440 generic map(Input_SZ => 16,Result_SZ => 32)
441 port map(clkm,rstn,FifoINT_Full,FFT_ReUse,Head_Valid,FifoINT_Data,DMA_ack,SM_Wen,SM_FlagError,SM_Pong,SM_Param,SM_Write,SM_Read,SM_ReUse,SM_Data);
442
443
444 --DMA_ack <= '1';
445 --Head_Valid <= '1';
446
447 -- MemOut : APB_FIFO
448 -- generic map (pindex => 9, paddr => 9, FifoCnt => 2, Data_sz => 32, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
449 -- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),SM_Write,open,FifoOUT_Full,open,SM_Data,open,open,apbi,apbo(9));
450
451 MemOut : lppFIFOxN
452 generic map(Data_sz => 32, Addr_sz => 8, FifoCnt => 2, Enable_ReUse => '0')
453 port map(rstn,clkm,clkm,(others => '0'),SM_Write,Head_Read,SM_Data,FifoOUT_Data,FifoOUT_Full,FifoOUT_Empty);
454
455 ----------- Header -------------------------------------------------------
456
457 Head0 : HeaderBuilder
458 generic map(Data_sz => 32)
459 port map(clkm,rstn,SM_Pong,SM_Param,DMUX_WorkFreq,SM_Wen,Head_Valid,FifoOUT_Data,FifoOUT_Empty,Head_Read,Head_Data,Head_Empty,DMA_Read,Head_Header,Head_Val,DMA_ack);
460
461
462 --- DMA -------------------------------------------------------
463
464 DMA0 : lpp_dma
465 generic map(hindex => 1,pindex => 9, paddr => 9,pirq => 14, pmask =>16#fff#,tech => CFG_FABTECH)
466 port map(clkm,rstn,apbi,apbo(9),ahbmi,ahbmo(1),Head_Data,Head_Empty,DMA_Read,Head_Header,Head_Val,DMA_ack);
467
468
469 ----- FIFO -------------------------------------------------------------
470
471 -- Memtest : APB_FIFO
472 -- generic map (pindex => 5, paddr => 5, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 1)
473 -- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),(others => '1'),open,open,open,(others => '0'),open,open,apbi,apbo(5));
474
475 --***************************************TEST DEMI-FIFO********************************************************************************
476 -- MemIn : APB_FIFO
477 -- generic map (pindex => 8, paddr => 8, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1)
478 -- port map (clkm,rstn,clkm,clkm,(others => '0'),Bre,(others => '1'),EmptyUp,FullUp,DataTMP,(others => '0'),open,open,apbi,apbo(8));
479 --
480 -- Pont : Bridge
481 -- port map(clkm,rstn,EmptyUp(0),FullDown(0),Bwr(0),Bre(0));
482 --
483 -- MemOut : APB_FIFO
484 -- generic map (pindex => 9, paddr => 9, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
485 -- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),Bwr,EmptyDown,FullDown,open,DataTMP,open,open,apbi,apbo(9));
486 --*************************************************************************************************************************************
487
182
488 --- UART -------------------------------------------------------------
183 --- UART -------------------------------------------------------------
489
184
490 COM0 : APB_UART
185 COM0 : APB_UART
491 generic map (pindex => 4, paddr => 4)
186 generic map (pindex => 5, paddr => 5)
492 port map (clkm,rstn,apbi,apbo(4),UART_TXD,UART_RXD);
187 port map (clkm,rstn,apbi,apbo(5),UART_TXD,UART_RXD);
493
188
494 --- DELAY ------------------------------------------------------------
495
496 -- Delay0 : APB_Delay
497 -- generic map (pindex => 4, paddr => 4)
498 -- port map (clkm,rstn,apbi,apbo(4));
499
189
500 --- IIR Filter -------------------------------------------------------
190 --- FIFO -------------------------------------------------------------
501 --Test(0) <= sample_clk_out;
191
502 --
192 Memtest : APB_FIFO
503 --
193 generic map (pindex => 6, paddr => 6, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 1)
504 -- IIR1: APB_IIR_Filter
194 port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),(others => '1'),open,open,open,(others => '0'),open,open,apbi,apbo(6));
505 -- generic map(
195
506 -- tech => CFG_MEMTECH,
507 -- pindex => 8,
508 -- paddr => 8,
509 -- Sample_SZ => Sample_SZ,
510 -- ChanelsCount => ChanelsCount,
511 -- Coef_SZ => Coef_SZ,
512 -- CoefCntPerCel => CoefCntPerCel,
513 -- Cels_count => Cels_count,
514 -- virgPos => virgPos
515 -- )
516 -- port map(
517 -- rst => rstn,
518 -- clk => clkm,
519 -- apbi => apbi,
520 -- apbo => apbo(8),
521 -- sample_clk_out => sample_clk_out,
522 -- GOtest => Test(1),
523 -- CoefsInitVal => (others => '1')
524 -- );
525 ----------------------------------------------------------------------
526
196
527 ----------------------------------------------------------------------
197 ----------------------------------------------------------------------
528 --- Reset and Clock generation -------------------------------------
198 --- Reset and Clock generation -------------------------------------
@@ -637,8 +307,8 end process;
637
307
638 dcomgen : if CFG_AHB_UART = 1 generate
308 dcomgen : if CFG_AHB_UART = 1 generate
639 dcom0: ahbuart -- Debug UART
309 dcom0: ahbuart -- Debug UART
640 generic map (hindex => 2, pindex => 7, paddr => 7)
310 generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
641 port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(2));
311 port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
642 dsurx_pad : inpad generic map (tech => padtech) port map (ahbrxd, ahbuarti.rxd);
312 dsurx_pad : inpad generic map (tech => padtech) port map (ahbrxd, ahbuarti.rxd);
643 dsutx_pad : outpad generic map (tech => padtech) port map (ahbtxd, ahbuarto.txd);
313 dsutx_pad : outpad generic map (tech => padtech) port map (ahbtxd, ahbuarto.txd);
644 -- led(0) <= not ahbuarti.rxd; led(1) <= not ahbuarto.txd;
314 -- led(0) <= not ahbuarti.rxd; led(1) <= not ahbuarto.txd;
@@ -687,6 +357,7 end process;
687 ----------------------------------------------------------------------
357 ----------------------------------------------------------------------
688 --- GPIO -----------------------------------------------------------
358 --- GPIO -----------------------------------------------------------
689 ----------------------------------------------------------------------
359 ----------------------------------------------------------------------
360 led(0) <= gpio(0); led(1) <= gpio(1);
690
361
691 gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
362 gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
692 grgpio0: grgpio
363 grgpio0: grgpio
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@@ -30,7 +30,6 entity HeaderBuilder is
30 clkm : in std_logic;
30 clkm : in std_logic;
31 rstn : in std_logic;
31 rstn : in std_logic;
32
32
33 pong : in std_logic;
34 Statu : in std_logic_vector(3 downto 0);
33 Statu : in std_logic_vector(3 downto 0);
35 Matrix_Type : in std_logic_vector(1 downto 0);
34 Matrix_Type : in std_logic_vector(1 downto 0);
36 Matrix_Write : in std_logic;
35 Matrix_Write : in std_logic;
@@ -57,7 +56,6 signal Matrix_Param : std_logic_vect
57 signal Write_reg : std_logic;
56 signal Write_reg : std_logic;
58 signal Data_cpt : integer;
57 signal Data_cpt : integer;
59 signal MAX : integer;
58 signal MAX : integer;
60 signal pong_reg : std_logic;
61
59
62 type etat is (idle0,idle1,pong0,pong1);
60 type etat is (idle0,idle1,pong0,pong1);
63 signal ect : etat;
61 signal ect : etat;
@@ -69,7 +67,6 begin
69 if(rstn='0')then
67 if(rstn='0')then
70 ect <= idle0;
68 ect <= idle0;
71 Valid <= '0';
69 Valid <= '0';
72 pong_reg <= '0';
73 header_val <= '0';
70 header_val <= '0';
74 header(5 downto 0) <= (others => '0');
71 header(5 downto 0) <= (others => '0');
75 Write_reg <= '0';
72 Write_reg <= '0';
@@ -79,7 +76,6 begin
79
76
80 elsif(clkm' event and clkm='1')then
77 elsif(clkm' event and clkm='1')then
81 Write_reg <= Matrix_Write;
78 Write_reg <= Matrix_Write;
82 pong_reg <= pong;
83
79
84 if(Statu="0001" or Statu="0011" or Statu="0110" or Statu="1010" or Statu="1111")then
80 if(Statu="0001" or Statu="0011" or Statu="0110" or Statu="1010" or Statu="1111")then
85 MAX <= 128;
81 MAX <= 128;
@@ -87,17 +83,6 begin
87 MAX <= 256;
83 MAX <= 256;
88 end if;
84 end if;
89
85
90 -- if(Write_reg = '0' and Matrix_Write = '1')then
91 -- if(Data_cpt = MAX)then
92 -- Data_cpt <= 0;
93 -- Valid <= '1';
94 -- header_val <= '1';
95 -- else
96 -- Data_cpt <= Data_cpt + 1;
97 -- Valid <= '0';
98 -- end if;
99 -- end if;
100
101 if(Write_reg = '0' and Matrix_Write = '1')then
86 if(Write_reg = '0' and Matrix_Write = '1')then
102 Data_cpt <= Data_cpt + 1;
87 Data_cpt <= Data_cpt + 1;
103 Valid <= '0';
88 Valid <= '0';
@@ -107,19 +92,7 begin
107 header_val <= '1';
92 header_val <= '1';
108 else
93 else
109 Valid <= '0';
94 Valid <= '0';
110 end if;
95 end if;
111
112 -- if(header_ack = '1')then
113 -- header_val <= '0';
114 -- end if;
115
116 -- if(emptyIN = "10")then
117 -- ping <= '0';
118 -- elsif(emptyIN = "01")then
119 -- ping <= '1';
120 -- else
121 -- ping <= ping;
122 -- end if;
123
96
124
97
125 case ect is
98 case ect is
@@ -127,11 +100,7 begin
127 when idle0 =>
100 when idle0 =>
128 if(header_ack = '1')then
101 if(header_ack = '1')then
129 header_val <= '0';
102 header_val <= '0';
130 --if(pong = '1')then
103 ect <= pong0;
131 ect <= pong0;
132 --elsif(pong = '0')then
133 --ect <= pong1;
134 --end if;
135 end if;
104 end if;
136
105
137 when pong0 =>
106 when pong0 =>
@@ -160,8 +129,6 begin
160
129
161 Matrix_Param <= std_logic_vector(to_unsigned(to_integer(unsigned(Statu))-1,4));
130 Matrix_Param <= std_logic_vector(to_unsigned(to_integer(unsigned(Statu))-1,4));
162
131
163 --header(1 downto 0) <= Matrix_Type;
164 --header(5 downto 2) <= Matrix_Param;
165 header(31 downto 6) <= (others => '0');
132 header(31 downto 6) <= (others => '0');
166
133
167 with ect select
134 with ect select
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@@ -38,7 +38,6 component HeaderBuilder is
38 clkm : in std_logic;
38 clkm : in std_logic;
39 rstn : in std_logic;
39 rstn : in std_logic;
40
40
41 pong : in std_logic;
42 Statu : in std_logic_vector(3 downto 0);
41 Statu : in std_logic_vector(3 downto 0);
43 Matrix_Type : in std_logic_vector(1 downto 0);
42 Matrix_Type : in std_logic_vector(1 downto 0);
44 Matrix_Write : in std_logic;
43 Matrix_Write : in std_logic;
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@@ -44,37 +44,37 end CNA_TabloC;
44
44
45 architecture ar_CNA_TabloC of CNA_TabloC is
45 architecture ar_CNA_TabloC of CNA_TabloC is
46
46
47 component CLKINT
47 --component CLKINT
48 port( A : in std_logic := 'U';
48 --port( A : in std_logic := 'U';
49 Y : out std_logic);
49 -- Y : out std_logic);
50 end component;
50 --end component;
51
51
52 signal clk : std_logic;
52 --signal clk : std_logic;
53
53
54 signal raz : std_logic;
54 --signal raz : std_logic;
55 signal s_SCLK : std_logic;
55 signal s_SCLK : std_logic;
56 signal OKAI_send : std_logic;
56 signal OKAI_send : std_logic;
57
57
58 begin
58 begin
59
59
60 CLKINT_0 : CLKINT
60 --CLKINT_0 : CLKINT
61 port map(A => clock, Y => clk);
61 -- port map(A => clock, Y => clk);
62
62
63 CLKINT_1 : CLKINT
63 --CLKINT_1 : CLKINT
64 port map(A => rst, Y => raz);
64 -- port map(A => rst, Y => raz);
65
65
66
66
67 SystemCLK : entity work.Systeme_Clock
67 SystemCLK : entity work.Systeme_Clock
68 generic map (nb_serial)
68 generic map (nb_serial)
69 port map (clk,raz,s_SCLK);
69 port map (clock,rst,s_SCLK);
70
70
71
71
72 Signal_sync : entity work.Gene_SYNC
72 Signal_sync : entity work.Gene_SYNC
73 port map (s_SCLK,raz,enable,OKAI_send,SYNC);
73 port map (s_SCLK,rst,enable,OKAI_send,SYNC);
74
74
75
75
76 Serial : entity work.serialize
76 Serial : entity work.serialize
77 port map (clk,raz,s_SCLK,Data_C,OKAI_send,flag_sd,Data);
77 port map (clock,rst,s_SCLK,Data_C,OKAI_send,flag_sd,Data);
78
78
79
79
80 SCLK <= s_SCLK;
80 SCLK <= s_SCLK;
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@@ -29,14 +29,12 generic(
29 port(
29 port(
30 clk : in std_logic;
30 clk : in std_logic;
31 reset : in std_logic;
31 reset : in std_logic;
32 Acq : in std_logic;
32 Ack : in std_logic;
33 Data : in std_logic_vector(Data_SZ-1 downto 0);
33 Data : in std_logic_vector(Data_SZ-1 downto 0);
34 Write : in std_logic;
34 Write : in std_logic;
35 Valid : in std_logic;
35 Valid : in std_logic;
36 -- Full : in std_logic_vector(1 downto 0);
37 FifoData : out std_logic_vector(2*Data_SZ-1 downto 0);
36 FifoData : out std_logic_vector(2*Data_SZ-1 downto 0);
38 FifoWrite : out std_logic_vector(1 downto 0);
37 FifoWrite : out std_logic_vector(1 downto 0);
39 Pong : out std_logic;
40 Error : out std_logic
38 Error : out std_logic
41 );
39 );
42 end entity;
40 end entity;
@@ -47,15 +45,14 architecture ar_Dispatch of Dispatch is
47 type etat is (eX,e0,e1,e2);
45 type etat is (eX,e0,e1,e2);
48 signal ect : etat;
46 signal ect : etat;
49
47
50 signal Pong_int : std_logic;
48 signal Pong : std_logic;
51 --signal FifoCpt : integer range 0 to 1 := 0;
52
49
53 begin
50 begin
54
51
55 process (clk,reset)
52 process (clk,reset)
56 begin
53 begin
57 if(reset='0')then
54 if(reset='0')then
58 Pong_int <= '0';
55 Pong <= '0';
59 Error <= '0';
56 Error <= '0';
60 ect <= e0;
57 ect <= e0;
61
58
@@ -64,14 +61,13 begin
64 case ect is
61 case ect is
65
62
66 when e0 =>
63 when e0 =>
67 -- if(Full(FifoCpt) = '1')then
68 if(Valid = '1')then
64 if(Valid = '1')then
69 Pong_int <= not Pong_int;
65 Pong <= not Pong;
70 ect <= e1;
66 ect <= e1;
71 end if;
67 end if;
72
68
73 when e1 =>
69 when e1 =>
74 if(Acq = '0')then
70 if(Ack = '0')then
75 Error <= '1';
71 Error <= '1';
76 ect <= e1;
72 ect <= e1;
77 else
73 else
@@ -80,7 +76,7 begin
80 end if;
76 end if;
81
77
82 when others =>
78 when others =>
83 null;
79 null;
84
80
85 end case;
81 end case;
86
82
@@ -88,10 +84,6 begin
88 end process;
84 end process;
89
85
90 FifoData <= Data & Data;
86 FifoData <= Data & Data;
91 Pong <= Pong_int;
87 FifoWrite <= '1' & not Write when Pong='0' else not Write & '1';
92
93 --FifoCpt <= 0 when Pong_int='0' else 1;
94
95 FifoWrite <= '1' & not Write when Pong_int='0' else not Write & '1';
96
88
97 end architecture; No newline at end of file
89 end architecture;
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@@ -35,13 +35,11 entity MatriceSpectrale is
35
35
36 FifoIN_Full : in std_logic_vector(4 downto 0);
36 FifoIN_Full : in std_logic_vector(4 downto 0);
37 SetReUse : in std_logic_vector(4 downto 0);
37 SetReUse : in std_logic_vector(4 downto 0);
38 -- FifoOUT_Full : in std_logic_vector(1 downto 0);
39 Valid : in std_logic;
38 Valid : in std_logic;
40 Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0);
39 Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0);
41 ACQ : in std_logic;
40 ACK : in std_logic;
42 SM_Write : out std_logic;
41 SM_Write : out std_logic;
43 FlagError : out std_logic;
42 FlagError : out std_logic;
44 Pong : out std_logic;
45 Statu : out std_logic_vector(3 downto 0);
43 Statu : out std_logic_vector(3 downto 0);
46 Write : out std_logic_vector(1 downto 0);
44 Write : out std_logic_vector(1 downto 0);
47 Read : out std_logic_vector(4 downto 0);
45 Read : out std_logic_vector(4 downto 0);
@@ -78,7 +76,7 begin
78
76
79 DISP : Dispatch
77 DISP : Dispatch
80 generic map(Result_SZ)
78 generic map(Result_SZ)
81 port map(clkm,rstn,ACQ,Matrix_Result,Matrix_Write,Valid,Data_OUT,Write,Pong,FlagError);
79 port map(clkm,rstn,ACK,Matrix_Result,Matrix_Write,Valid,Data_OUT,Write,FlagError);
82
80
83 Statu <= TopSM_Statu;
81 Statu <= TopSM_Statu;
84 SM_Write <= Matrix_Write;
82 SM_Write <= Matrix_Write;
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@@ -66,13 +66,11 component MatriceSpectrale is
66
66
67 FifoIN_Full : in std_logic_vector(4 downto 0);
67 FifoIN_Full : in std_logic_vector(4 downto 0);
68 SetReUse : in std_logic_vector(4 downto 0);
68 SetReUse : in std_logic_vector(4 downto 0);
69 -- FifoOUT_Full : in std_logic_vector(1 downto 0);
70 Valid : in std_logic;
69 Valid : in std_logic;
71 Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0);
70 Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0);
72 ACQ : in std_logic;
71 ACK : in std_logic;
73 SM_Write : out std_logic;
72 SM_Write : out std_logic;
74 FlagError : out std_logic;
73 FlagError : out std_logic;
75 Pong : out std_logic;
76 Statu : out std_logic_vector(3 downto 0);
74 Statu : out std_logic_vector(3 downto 0);
77 Write : out std_logic_vector(1 downto 0);
75 Write : out std_logic_vector(1 downto 0);
78 Read : out std_logic_vector(4 downto 0);
76 Read : out std_logic_vector(4 downto 0);
@@ -199,14 +197,12 generic(
199 port(
197 port(
200 clk : in std_logic;
198 clk : in std_logic;
201 reset : in std_logic;
199 reset : in std_logic;
202 Acq : in std_logic;
200 Ack : in std_logic;
203 Data : in std_logic_vector(Data_SZ-1 downto 0);
201 Data : in std_logic_vector(Data_SZ-1 downto 0);
204 Write : in std_logic;
202 Write : in std_logic;
205 Valid : in std_logic;
203 Valid : in std_logic;
206 -- Full : in std_logic_vector(1 downto 0);
207 FifoData : out std_logic_vector(2*Data_SZ-1 downto 0);
204 FifoData : out std_logic_vector(2*Data_SZ-1 downto 0);
208 FifoWrite : out std_logic_vector(1 downto 0);
205 FifoWrite : out std_logic_vector(1 downto 0);
209 Pong : out std_logic;
210 Error : out std_logic
206 Error : out std_logic
211 );
207 );
212 end component;
208 end component;
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@@ -1,66 +1,65
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.std_logic_1164.all;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
24 use IEEE.numeric_std.all;
25 library lpp;
25 library lpp;
26 use lpp.lpp_memory.all;
26 use lpp.lpp_memory.all;
27 use lpp.iir_filter.all;
27 use lpp.iir_filter.all;
28 library techmap;
28 library techmap;
29 use techmap.gencomp.all;
29 use techmap.gencomp.all;
30
30
31 entity lppFIFOxN is
31 entity lppFIFOxN is
32 generic(
32 generic(
33 tech : integer := 0;
33 tech : integer := 0;
34 Mem_use : integer := use_RAM;
34 Mem_use : integer := use_RAM;
35 Data_sz : integer range 1 to 32 := 8;
35 Data_sz : integer range 1 to 32 := 8;
36 Addr_sz : integer range 1 to 32 := 8;
36 Addr_sz : integer range 2 to 12 := 8;
37 FifoCnt : integer := 1;
37 FifoCnt : integer := 1;
38 Enable_ReUse : std_logic := '0'
38 Enable_ReUse : std_logic := '0'
39 );
39 );
40 port(
40 port(
41 rst : in std_logic;
41 rstn : in std_logic;
42 wclk : in std_logic;
42 wclk : in std_logic;
43 rclk : in std_logic;
43 rclk : in std_logic;
44 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
44 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
45 wen : in std_logic_vector(FifoCnt-1 downto 0);
45 wen : in std_logic_vector(FifoCnt-1 downto 0);
46 ren : in std_logic_vector(FifoCnt-1 downto 0);
46 ren : in std_logic_vector(FifoCnt-1 downto 0);
47 wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
47 wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
48 rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
48 rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
49 full : out std_logic_vector(FifoCnt-1 downto 0);
49 full : out std_logic_vector(FifoCnt-1 downto 0);
50 empty : out std_logic_vector(FifoCnt-1 downto 0)
50 empty : out std_logic_vector(FifoCnt-1 downto 0)
51 );
51 );
52 end entity;
52 end entity;
53
53
54
54
55 architecture ar_lppFIFOxN of lppFIFOxN is
55 architecture ar_lppFIFOxN of lppFIFOxN is
56
56
57 begin
57 begin
58
58
59 fifos: for i in 0 to FifoCnt-1 generate
59 fifos: for i in 0 to FifoCnt-1 generate
60 FIFO0 : lpp_fifo
60 FIFO0 : lpp_fifo
61 generic map (tech,Mem_use,Enable_ReUse,Data_sz,Addr_sz)
61 generic map (tech,Mem_use,Enable_ReUse,Data_sz,Addr_sz)
62 port map(rst,ReUse(i),rclk,ren(i),rdata((i+1)*Data_sz-1 downto i*Data_sz),empty(i),open,wclk,wen(i),wdata((i+1)*Data_sz-1 downto i*Data_sz),full(i),open);
62 port map(rstn,ReUse(i),rclk,ren(i),rdata((i+1)*Data_sz-1 downto i*Data_sz),empty(i),open,wclk,wen(i),wdata((i+1)*Data_sz-1 downto i*Data_sz),full(i),open);
63 end generate;
63 end generate;
64
64
65 end architecture;
65 end architecture;
66
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@@ -34,7 +34,7 generic(
34 Mem_use : integer := use_RAM;
34 Mem_use : integer := use_RAM;
35 Enable_ReUse : std_logic := '0';
35 Enable_ReUse : std_logic := '0';
36 DataSz : integer range 1 to 32 := 8;
36 DataSz : integer range 1 to 32 := 8;
37 abits : integer range 2 to 12 := 8
37 AddrSz : integer range 2 to 12 := 8
38 );
38 );
39 port(
39 port(
40 rstn : in std_logic;
40 rstn : in std_logic;
@@ -43,12 +43,12 port(
43 ren : in std_logic;
43 ren : in std_logic;
44 rdata : out std_logic_vector(DataSz-1 downto 0);
44 rdata : out std_logic_vector(DataSz-1 downto 0);
45 empty : out std_logic;
45 empty : out std_logic;
46 raddr : out std_logic_vector(abits-1 downto 0);
46 raddr : out std_logic_vector(AddrSz-1 downto 0);
47 wclk : in std_logic;
47 wclk : in std_logic;
48 wen : in std_logic;
48 wen : in std_logic;
49 wdata : in std_logic_vector(DataSz-1 downto 0);
49 wdata : in std_logic_vector(DataSz-1 downto 0);
50 full : out std_logic;
50 full : out std_logic;
51 waddr : out std_logic_vector(abits-1 downto 0)
51 waddr : out std_logic_vector(AddrSz-1 downto 0)
52 );
52 );
53 end entity;
53 end entity;
54
54
@@ -65,10 +65,10 signal sWEN : std_logic;
65 signal sRE : std_logic;
65 signal sRE : std_logic;
66 signal sWE : std_logic;
66 signal sWE : std_logic;
67
67
68 signal Waddr_vect : std_logic_vector(abits-1 downto 0):=(others =>'0');
68 signal Waddr_vect : std_logic_vector(AddrSz-1 downto 0):=(others =>'0');
69 signal Raddr_vect : std_logic_vector(abits-1 downto 0):=(others =>'0');
69 signal Raddr_vect : std_logic_vector(AddrSz-1 downto 0):=(others =>'0');
70 signal Waddr_vect_s : std_logic_vector(abits-1 downto 0):=(others =>'0');
70 signal Waddr_vect_s : std_logic_vector(AddrSz-1 downto 0):=(others =>'0');
71 signal Raddr_vect_s : std_logic_vector(abits-1 downto 0):=(others =>'0');
71 signal Raddr_vect_s : std_logic_vector(AddrSz-1 downto 0):=(others =>'0');
72
72
73 begin
73 begin
74
74
@@ -78,13 +78,13 begin
78 --==================================================================================
78 --==================================================================================
79 memRAM : IF Mem_use = use_RAM GENERATE
79 memRAM : IF Mem_use = use_RAM GENERATE
80 SRAM : syncram_2p
80 SRAM : syncram_2p
81 generic map(tech,abits,DataSz)
81 generic map(tech,AddrSz,DataSz)
82 port map(RCLK,sRE,Raddr_vect,rdata,WCLK,sWE,Waddr_vect,wdata);
82 port map(RCLK,sRE,Raddr_vect,rdata,WCLK,sWE,Waddr_vect,wdata);
83 END GENERATE;
83 END GENERATE;
84 --==================================================================================
84 --==================================================================================
85 memCEL : IF Mem_use = use_CEL GENERATE
85 memCEL : IF Mem_use = use_CEL GENERATE
86 CRAM : RAM_CEL
86 CRAM : RAM_CEL
87 generic map(DataSz,abits)
87 generic map(DataSz,AddrSz)
88 port map(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, WCLK, rstn);
88 port map(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, WCLK, rstn);
89 END GENERATE;
89 END GENERATE;
90 --==================================================================================
90 --==================================================================================
@@ -177,4 +177,3 end architecture;
177
177
178
178
179
179
180
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@@ -1,163 +1,163
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 library grlib;
24 library grlib;
25 use grlib.amba.all;
25 use grlib.amba.all;
26 use std.textio.all;
26 use std.textio.all;
27 library lpp;
27 library lpp;
28 use lpp.lpp_amba.all;
28 use lpp.lpp_amba.all;
29 use lpp.iir_filter.all;
29 use lpp.iir_filter.all;
30 library gaisler;
30 library gaisler;
31 use gaisler.misc.all;
31 use gaisler.misc.all;
32 use gaisler.memctrl.all;
32 use gaisler.memctrl.all;
33 library techmap;
33 library techmap;
34 use techmap.gencomp.all;
34 use techmap.gencomp.all;
35
35
36 --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on
36 --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on
37
37
38 package lpp_memory is
38 package lpp_memory is
39
39
40 component APB_FIFO is
40 component APB_FIFO is
41 generic (
41 generic (
42 tech : integer := apa3;
42 tech : integer := apa3;
43 pindex : integer := 0;
43 pindex : integer := 0;
44 paddr : integer := 0;
44 paddr : integer := 0;
45 pmask : integer := 16#fff#;
45 pmask : integer := 16#fff#;
46 pirq : integer := 0;
46 pirq : integer := 0;
47 abits : integer := 8;
47 abits : integer := 8;
48 FifoCnt : integer := 2;
48 FifoCnt : integer := 2;
49 Data_sz : integer := 16;
49 Data_sz : integer := 16;
50 Addr_sz : integer := 9;
50 Addr_sz : integer := 9;
51 Enable_ReUse : std_logic := '0';
51 Enable_ReUse : std_logic := '0';
52 Mem_use : integer := use_RAM;
52 Mem_use : integer := use_RAM;
53 R : integer := 1;
53 R : integer := 1;
54 W : integer := 1
54 W : integer := 1
55 );
55 );
56 port (
56 port (
57 clk : in std_logic; --! Horloge du composant
57 clk : in std_logic; --! Horloge du composant
58 rst : in std_logic; --! Reset general du composant
58 rst : in std_logic; --! Reset general du composant
59 rclk : in std_logic;
59 rclk : in std_logic;
60 wclk : in std_logic;
60 wclk : in std_logic;
61 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
61 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
62 REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en mοΏ½moire
62 REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en mοΏ½moire
63 WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'οΏ½criture en mοΏ½moire
63 WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'οΏ½criture en mοΏ½moire
64 Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, MοΏ½moire vide
64 Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, MοΏ½moire vide
65 Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, MοΏ½moire pleine
65 Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, MοΏ½moire pleine
66 RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donnοΏ½es en entrοΏ½e
66 RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donnοΏ½es en entrοΏ½e
67 WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donnοΏ½es en sortie
67 WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donnοΏ½es en sortie
68 WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (οΏ½criture)
68 WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (οΏ½criture)
69 RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture)
69 RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture)
70 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
70 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
71 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
71 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
72 );
72 );
73 end component;
73 end component;
74
74
75
75
76 component lpp_fifo is
76 component lpp_fifo is
77 generic(
77 generic(
78 tech : integer := 0;
78 tech : integer := 0;
79 Mem_use : integer := use_RAM;
79 Mem_use : integer := use_RAM;
80 Enable_ReUse : std_logic := '0';
80 Enable_ReUse : std_logic := '0';
81 DataSz : integer range 1 to 32 := 8;
81 DataSz : integer range 1 to 32 := 8;
82 abits : integer range 2 to 12 := 8
82 AddrSz : integer range 2 to 12 := 8
83 );
83 );
84 port(
84 port(
85 rstn : in std_logic;
85 rstn : in std_logic;
86 ReUse : in std_logic; --27/01/12
86 ReUse : in std_logic; --27/01/12
87 rclk : in std_logic;
87 rclk : in std_logic;
88 ren : in std_logic;
88 ren : in std_logic;
89 rdata : out std_logic_vector(DataSz-1 downto 0);
89 rdata : out std_logic_vector(DataSz-1 downto 0);
90 empty : out std_logic;
90 empty : out std_logic;
91 raddr : out std_logic_vector(abits-1 downto 0);
91 raddr : out std_logic_vector(AddrSz-1 downto 0);
92 wclk : in std_logic;
92 wclk : in std_logic;
93 wen : in std_logic;
93 wen : in std_logic;
94 wdata : in std_logic_vector(DataSz-1 downto 0);
94 wdata : in std_logic_vector(DataSz-1 downto 0);
95 full : out std_logic;
95 full : out std_logic;
96 waddr : out std_logic_vector(abits-1 downto 0)
96 waddr : out std_logic_vector(AddrSz-1 downto 0)
97 );
97 );
98 end component;
98 end component;
99
99
100
100
101 component lppFIFOxN is
101 component lppFIFOxN is
102 generic(
102 generic(
103 tech : integer := 0;
103 tech : integer := 0;
104 Mem_use : integer := use_RAM;
104 Mem_use : integer := use_RAM;
105 Data_sz : integer range 1 to 32 := 8;
105 Data_sz : integer range 1 to 32 := 8;
106 Addr_sz : integer range 1 to 32 := 8;
106 Addr_sz : integer range 1 to 32 := 8;
107 FifoCnt : integer := 1;
107 FifoCnt : integer := 1;
108 Enable_ReUse : std_logic := '0'
108 Enable_ReUse : std_logic := '0'
109 );
109 );
110 port(
110 port(
111 rst : in std_logic;
111 rstn : in std_logic;
112 wclk : in std_logic;
112 wclk : in std_logic;
113 rclk : in std_logic;
113 rclk : in std_logic;
114 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
114 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
115 wen : in std_logic_vector(FifoCnt-1 downto 0);
115 wen : in std_logic_vector(FifoCnt-1 downto 0);
116 ren : in std_logic_vector(FifoCnt-1 downto 0);
116 ren : in std_logic_vector(FifoCnt-1 downto 0);
117 wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
117 wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
118 rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
118 rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
119 full : out std_logic_vector(FifoCnt-1 downto 0);
119 full : out std_logic_vector(FifoCnt-1 downto 0);
120 empty : out std_logic_vector(FifoCnt-1 downto 0)
120 empty : out std_logic_vector(FifoCnt-1 downto 0)
121 );
121 );
122 end component;
122 end component;
123
123
124 component FillFifo is
124 component FillFifo is
125 generic(
125 generic(
126 Data_sz : integer range 1 to 32 := 16;
126 Data_sz : integer range 1 to 32 := 16;
127 Fifo_cnt : integer range 1 to 8 := 5
127 Fifo_cnt : integer range 1 to 8 := 5
128 );
128 );
129 port(
129 port(
130 clk : in std_logic;
130 clk : in std_logic;
131 raz : in std_logic;
131 raz : in std_logic;
132 write : out std_logic_vector(Fifo_cnt-1 downto 0);
132 write : out std_logic_vector(Fifo_cnt-1 downto 0);
133 reuse : out std_logic_vector(Fifo_cnt-1 downto 0);
133 reuse : out std_logic_vector(Fifo_cnt-1 downto 0);
134 data : out std_logic_vector(Fifo_cnt*Data_sz-1 downto 0)
134 data : out std_logic_vector(Fifo_cnt*Data_sz-1 downto 0)
135 );
135 );
136 end component;
136 end component;
137
137
138 component ssram_plugin is
138 component ssram_plugin is
139 generic (tech : integer := 0);
139 generic (tech : integer := 0);
140 port
140 port
141 (
141 (
142 clk : in std_logic;
142 clk : in std_logic;
143 mem_ctrlr_o : in memory_out_type;
143 mem_ctrlr_o : in memory_out_type;
144 SSRAM_CLK : out std_logic;
144 SSRAM_CLK : out std_logic;
145 nBWa : out std_logic;
145 nBWa : out std_logic;
146 nBWb : out std_logic;
146 nBWb : out std_logic;
147 nBWc : out std_logic;
147 nBWc : out std_logic;
148 nBWd : out std_logic;
148 nBWd : out std_logic;
149 nBWE : out std_logic;
149 nBWE : out std_logic;
150 nADSC : out std_logic;
150 nADSC : out std_logic;
151 nADSP : out std_logic;
151 nADSP : out std_logic;
152 nADV : out std_logic;
152 nADV : out std_logic;
153 nGW : out std_logic;
153 nGW : out std_logic;
154 nCE1 : out std_logic;
154 nCE1 : out std_logic;
155 CE2 : out std_logic;
155 CE2 : out std_logic;
156 nCE3 : out std_logic;
156 nCE3 : out std_logic;
157 nOE : out std_logic;
157 nOE : out std_logic;
158 MODE : out std_logic;
158 MODE : out std_logic;
159 ZZ : out std_logic
159 ZZ : out std_logic
160 );
160 );
161 end component;
161 end component;
162
162
163 end;
163 end; No newline at end of file
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