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1 | ----------------------------------------------------------------------------- |
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1 | ----------------------------------------------------------------------------- | |
2 | -- LEON3 Demonstration design |
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2 | -- LEON3 Demonstration design | |
3 | -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research |
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3 | -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research | |
4 | -- |
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4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
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5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 2 of the License, or |
|
7 | -- the Free Software Foundation; either version 2 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
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9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
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10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
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11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
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14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
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16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------ |
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18 | ------------------------------------------------------------------------------ | |
19 |
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19 | |||
20 |
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20 | |||
21 | library ieee; |
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21 | library ieee; | |
22 | use ieee.std_logic_1164.all; |
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22 | use ieee.std_logic_1164.all; | |
23 | library grlib; |
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23 | library grlib; | |
24 | use grlib.amba.all; |
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24 | use grlib.amba.all; | |
25 | use grlib.stdlib.all; |
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25 | use grlib.stdlib.all; | |
26 | library techmap; |
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26 | library techmap; | |
27 | use techmap.gencomp.all; |
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27 | use techmap.gencomp.all; | |
28 | library gaisler; |
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28 | library gaisler; | |
29 | use gaisler.memctrl.all; |
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29 | use gaisler.memctrl.all; | |
30 | use gaisler.leon3.all; |
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30 | use gaisler.leon3.all; | |
31 | use gaisler.uart.all; |
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31 | use gaisler.uart.all; | |
32 | use gaisler.misc.all; |
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32 | use gaisler.misc.all; | |
33 | library esa; |
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33 | library esa; | |
34 | use esa.memoryctrl.all; |
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34 | use esa.memoryctrl.all; | |
35 | use work.config.all; |
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35 | use work.config.all; | |
36 | library lpp; |
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36 | library lpp; | |
37 | use lpp.lpp_amba.all; |
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37 | use lpp.lpp_amba.all; | |
38 | use lpp.lpp_memory.all; |
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38 | use lpp.lpp_memory.all; | |
39 | use lpp.lpp_uart.all; |
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39 | use lpp.lpp_uart.all; | |
40 | use lpp.lpp_matrix.all; |
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40 | use lpp.lpp_matrix.all; | |
41 | use lpp.lpp_delay.all; |
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41 | use lpp.lpp_delay.all; | |
42 | use lpp.lpp_fft.all; |
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42 | use lpp.lpp_fft.all; | |
43 | use lpp.fft_components.all; |
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43 | use lpp.fft_components.all; | |
44 | use lpp.lpp_ad_conv.all; |
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44 | use lpp.lpp_ad_conv.all; | |
45 | use lpp.iir_filter.all; |
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45 | use lpp.iir_filter.all; | |
46 | use lpp.general_purpose.all; |
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46 | use lpp.general_purpose.all; | |
47 | use lpp.Filtercfg.all; |
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47 | use lpp.Filtercfg.all; | |
48 |
use lpp.lpp_ |
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48 | use lpp.lpp_cna.all; | |
49 | use lpp.lpp_top_lfr_pkg.all; |
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50 | use lpp.lpp_dma_pkg.all; |
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51 | use lpp.lpp_Header.all; |
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52 |
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49 | |||
53 | entity leon3mp is |
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50 | entity leon3mp is | |
54 | generic ( |
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51 | generic ( | |
55 | fabtech : integer := CFG_FABTECH; |
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52 | fabtech : integer := CFG_FABTECH; | |
56 | memtech : integer := CFG_MEMTECH; |
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53 | memtech : integer := CFG_MEMTECH; | |
57 | padtech : integer := CFG_PADTECH; |
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54 | padtech : integer := CFG_PADTECH; | |
58 | clktech : integer := CFG_CLKTECH; |
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55 | clktech : integer := CFG_CLKTECH; | |
59 | disas : integer := CFG_DISAS; -- Enable disassembly to console |
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56 | disas : integer := CFG_DISAS; -- Enable disassembly to console | |
60 | dbguart : integer := CFG_DUART; -- Print UART on console |
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57 | dbguart : integer := CFG_DUART; -- Print UART on console | |
61 | pclow : integer := CFG_PCLOW |
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58 | pclow : integer := CFG_PCLOW | |
62 | ); |
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59 | ); | |
63 | port ( |
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60 | port ( | |
64 | clk50MHz : in std_ulogic; |
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61 | clk50MHz : in std_ulogic; | |
65 | reset : in std_ulogic; |
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62 | reset : in std_ulogic; | |
66 | ramclk : out std_logic; |
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63 | ramclk : out std_logic; | |
67 |
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64 | |||
68 | ahbrxd : in std_ulogic; -- DSU rx data |
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65 | ahbrxd : in std_ulogic; -- DSU rx data | |
69 | ahbtxd : out std_ulogic; -- DSU tx data |
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66 | ahbtxd : out std_ulogic; -- DSU tx data | |
70 | dsubre : in std_ulogic; |
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67 | dsubre : in std_ulogic; | |
71 | dsuact : out std_ulogic; |
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68 | dsuact : out std_ulogic; | |
72 | urxd1 : in std_ulogic; -- UART1 rx data |
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69 | urxd1 : in std_ulogic; -- UART1 rx data | |
73 | utxd1 : out std_ulogic; -- UART1 tx data |
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70 | utxd1 : out std_ulogic; -- UART1 tx data | |
74 | errorn : out std_ulogic; |
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71 | errorn : out std_ulogic; | |
75 |
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72 | |||
76 | address : out std_logic_vector(18 downto 0); |
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73 | address : out std_logic_vector(18 downto 0); | |
77 | data : inout std_logic_vector(31 downto 0); |
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74 | data : inout std_logic_vector(31 downto 0); | |
78 | gpio : inout std_logic_vector(6 downto 0); -- I/O port |
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75 | gpio : inout std_logic_vector(6 downto 0); -- I/O port | |
79 |
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76 | |||
80 | nBWa : out std_logic; |
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77 | nBWa : out std_logic; | |
81 | nBWb : out std_logic; |
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78 | nBWb : out std_logic; | |
82 | nBWc : out std_logic; |
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79 | nBWc : out std_logic; | |
83 | nBWd : out std_logic; |
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80 | nBWd : out std_logic; | |
84 | nBWE : out std_logic; |
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81 | nBWE : out std_logic; | |
85 | nADSC : out std_logic; |
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82 | nADSC : out std_logic; | |
86 | nADSP : out std_logic; |
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83 | nADSP : out std_logic; | |
87 | nADV : out std_logic; |
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84 | nADV : out std_logic; | |
88 | nGW : out std_logic; |
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85 | nGW : out std_logic; | |
89 | nCE1 : out std_logic; |
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86 | nCE1 : out std_logic; | |
90 | CE2 : out std_logic; |
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87 | CE2 : out std_logic; | |
91 | nCE3 : out std_logic; |
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88 | nCE3 : out std_logic; | |
92 | nOE : out std_logic; |
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89 | nOE : out std_logic; | |
93 | MODE : out std_logic; |
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90 | MODE : out std_logic; | |
94 | SSRAM_CLK : out std_logic; |
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91 | SSRAM_CLK : out std_logic; | |
95 | ZZ : out std_logic; |
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92 | ZZ : out std_logic; | |
96 | --------------------------------------------------------------------- |
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93 | --------------------------------------------------------------------- | |
97 | --- AJOUT TEST ------------------------In/Out----------------------- |
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94 | --- AJOUT TEST ------------------------In/Out----------------------- | |
98 | --------------------------------------------------------------------- |
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95 | --------------------------------------------------------------------- | |
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96 | -- DAC | |||
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97 | DAC_SYNC : out std_logic; | |||
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98 | DAC_SCLK : out std_logic; | |||
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99 | DAC_DATA : out std_logic; | |||
99 | -- UART |
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100 | -- UART | |
100 | UART_RXD : in std_logic; |
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101 | UART_RXD : in std_logic; | |
101 | UART_TXD : out std_logic; |
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102 | UART_TXD : out std_logic; | |
102 | -- ACQ |
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103 | CNV_CH1 : OUT STD_LOGIC; |
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104 | SCK_CH1 : OUT STD_LOGIC; |
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105 | SDO_CH1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
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106 | Bias_Fails : out std_logic; |
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107 | -- ADC |
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108 | -- ADC_in : in AD7688_in(4 downto 0); |
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109 | -- ADC_out : out AD7688_out; |
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110 |
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111 | -- CNA |
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112 | -- DAC_SYNC : out std_logic; |
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113 | -- DAC_SCLK : out std_logic; |
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114 | -- DAC_DATA : out std_logic; |
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115 | -- Diver |
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116 | SPW1_EN : out std_logic; |
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117 | SPW2_EN : out std_logic; |
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118 | TEST : out std_logic_vector(3 downto 0); |
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119 |
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120 | BP : in std_logic; |
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121 | --------------------------------------------------------------------- |
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103 | --------------------------------------------------------------------- | |
122 | led : out std_logic_vector(1 downto 0) |
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104 | led : out std_logic_vector(1 downto 0) | |
123 | ); |
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105 | ); | |
124 | end; |
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106 | end; | |
125 |
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107 | |||
126 | architecture Behavioral of leon3mp is |
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108 | architecture Behavioral of leon3mp is | |
127 |
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109 | |||
128 | constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+ |
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110 | constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+ | |
129 | CFG_GRETH+CFG_AHB_JTAG+1; -- +1 pour le DMA |
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111 | CFG_GRETH+CFG_AHB_JTAG; | |
130 | constant maxahbm : integer := maxahbmsp; |
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112 | constant maxahbm : integer := maxahbmsp; | |
131 |
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113 | |||
132 | --Clk & Rst gοΏ½nοΏ½ |
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114 | --Clk & Rst gοΏ½nοΏ½ | |
133 | signal vcc : std_logic_vector(4 downto 0); |
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115 | signal vcc : std_logic_vector(4 downto 0); | |
134 | signal gnd : std_logic_vector(4 downto 0); |
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116 | signal gnd : std_logic_vector(4 downto 0); | |
135 | signal resetnl : std_ulogic; |
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117 | signal resetnl : std_ulogic; | |
136 | signal clk2x : std_ulogic; |
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118 | signal clk2x : std_ulogic; | |
137 | signal lclk : std_ulogic; |
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119 | signal lclk : std_ulogic; | |
138 | signal lclk2x : std_ulogic; |
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120 | signal lclk2x : std_ulogic; | |
139 | signal clkm : std_ulogic; |
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121 | signal clkm : std_ulogic; | |
140 | signal rstn : std_ulogic; |
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122 | signal rstn : std_ulogic; | |
141 | signal rstraw : std_ulogic; |
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123 | signal rstraw : std_ulogic; | |
142 | signal pciclk : std_ulogic; |
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124 | signal pciclk : std_ulogic; | |
143 | signal sdclkl : std_ulogic; |
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125 | signal sdclkl : std_ulogic; | |
144 | signal cgi : clkgen_in_type; |
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126 | signal cgi : clkgen_in_type; | |
145 | signal cgo : clkgen_out_type; |
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127 | signal cgo : clkgen_out_type; | |
146 | --- AHB / APB |
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128 | --- AHB / APB | |
147 | signal apbi : apb_slv_in_type; |
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129 | signal apbi : apb_slv_in_type; | |
148 | signal apbo : apb_slv_out_vector := (others => apb_none); |
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130 | signal apbo : apb_slv_out_vector := (others => apb_none); | |
149 | signal ahbsi : ahb_slv_in_type; |
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131 | signal ahbsi : ahb_slv_in_type; | |
150 | signal ahbso : ahb_slv_out_vector := (others => ahbs_none); |
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132 | signal ahbso : ahb_slv_out_vector := (others => ahbs_none); | |
151 | signal ahbmi : ahb_mst_in_type; |
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133 | signal ahbmi : ahb_mst_in_type; | |
152 | signal ahbmo : ahb_mst_out_vector := (others => ahbm_none); |
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134 | signal ahbmo : ahb_mst_out_vector := (others => ahbm_none); | |
153 | --UART |
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135 | --UART | |
154 | signal ahbuarti : uart_in_type; |
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136 | signal ahbuarti : uart_in_type; | |
155 | signal ahbuarto : uart_out_type; |
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137 | signal ahbuarto : uart_out_type; | |
156 | signal apbuarti : uart_in_type; |
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138 | signal apbuarti : uart_in_type; | |
157 | signal apbuarto : uart_out_type; |
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139 | signal apbuarto : uart_out_type; | |
158 | --MEM CTRLR |
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140 | --MEM CTRLR | |
159 | signal memi : memory_in_type; |
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141 | signal memi : memory_in_type; | |
160 | signal memo : memory_out_type; |
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142 | signal memo : memory_out_type; | |
161 | signal wpo : wprot_out_type; |
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143 | signal wpo : wprot_out_type; | |
162 | signal sdo : sdram_out_type; |
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144 | signal sdo : sdram_out_type; | |
163 | --IRQ |
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145 | --IRQ | |
164 | signal irqi : irq_in_vector(0 to CFG_NCPU-1); |
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146 | signal irqi : irq_in_vector(0 to CFG_NCPU-1); | |
165 | signal irqo : irq_out_vector(0 to CFG_NCPU-1); |
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147 | signal irqo : irq_out_vector(0 to CFG_NCPU-1); | |
166 | --Timer |
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148 | --Timer | |
167 | signal gpti : gptimer_in_type; |
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149 | signal gpti : gptimer_in_type; | |
168 | signal gpto : gptimer_out_type; |
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150 | signal gpto : gptimer_out_type; | |
169 | --GPIO |
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151 | --GPIO | |
170 | signal gpioi : gpio_in_type; |
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152 | signal gpioi : gpio_in_type; | |
171 | signal gpioo : gpio_out_type; |
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153 | signal gpioo : gpio_out_type; | |
172 | --DSU |
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154 | --DSU | |
173 | signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1); |
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155 | signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1); | |
174 | signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1); |
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156 | signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1); | |
175 | signal dsui : dsu_in_type; |
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157 | signal dsui : dsu_in_type; | |
176 | signal dsuo : dsu_out_type; |
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158 | signal dsuo : dsu_out_type; | |
177 |
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159 | |||
178 | --------------------------------------------------------------------- |
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160 | --------------------------------------------------------------------- | |
179 | --- AJOUT TEST ------------------------Signaux---------------------- |
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161 | --- AJOUT TEST ------------------------Signaux---------------------- | |
180 | --------------------------------------------------------------------- |
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162 | --------------------------------------------------------------------- | |
181 | -- FIFOs |
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182 | signal FifoF0_Empty : std_logic_vector(4 downto 0); |
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183 | signal FifoF0_Data : std_logic_vector(79 downto 0); |
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184 | signal FifoF1_Empty : std_logic_vector(4 downto 0); |
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185 | signal FifoF1_Data : std_logic_vector(79 downto 0); |
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186 | signal FifoF3_Empty : std_logic_vector(4 downto 0); |
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187 | signal FifoF3_Data : std_logic_vector(79 downto 0); |
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188 |
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163 | |||
189 | signal FifoINT_Full : std_logic_vector(4 downto 0); |
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190 | signal FifoINT_Data : std_logic_vector(79 downto 0); |
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191 |
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192 | signal FifoOUT_Full : std_logic_vector(1 downto 0); |
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193 | signal FifoOUT_Empty : std_logic_vector(1 downto 0); |
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194 | signal FifoOUT_Data : std_logic_vector(63 downto 0); |
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195 |
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196 |
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197 | -- MATRICE SPECTRALE |
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198 | signal SM_FlagError : std_logic; |
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199 | signal SM_Pong : std_logic; |
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200 | signal SM_Wen : std_logic; |
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201 | signal SM_Read : std_logic_vector(4 downto 0); |
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202 | signal SM_Write : std_logic_vector(1 downto 0); |
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203 | signal SM_ReUse : std_logic_vector(4 downto 0); |
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204 | signal SM_Param : std_logic_vector(3 downto 0); |
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205 | signal SM_Data : std_logic_vector(63 downto 0); |
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206 |
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207 | --signal Dma_acq : std_logic; |
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208 | --signal Head_Valid : std_logic; |
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209 |
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210 | -- FFT |
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211 | signal FFT_Load : std_logic; |
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212 | signal FFT_Read : std_logic_vector(4 downto 0); |
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213 | signal FFT_Write : std_logic_vector(4 downto 0); |
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214 | signal FFT_ReUse : std_logic_vector(4 downto 0); |
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215 | signal FFT_Data : std_logic_vector(79 downto 0); |
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216 |
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217 | -- DEMUX |
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218 | signal DMUX_Read : std_logic_vector(14 downto 0); |
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219 | signal DMUX_Empty : std_logic_vector(4 downto 0); |
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220 | signal DMUX_Data : std_logic_vector(79 downto 0); |
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221 | signal DMUX_WorkFreq : std_logic_vector(1 downto 0); |
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222 |
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223 | -- ACQ |
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224 | signal sample_val : STD_LOGIC; |
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225 | signal sample : Samples(8-1 DOWNTO 0); |
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226 |
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227 | signal ACQ_WenF0 : STD_LOGIC_VECTOR(4 DOWNTO 0); |
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228 | signal ACQ_DataF0 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
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229 | signal ACQ_WenF1 : STD_LOGIC_VECTOR(4 DOWNTO 0); |
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230 | signal ACQ_DataF1 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
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231 | signal ACQ_WenF3 : STD_LOGIC_VECTOR(4 DOWNTO 0); |
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232 | signal ACQ_DataF3 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
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233 |
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234 | -- Header |
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235 | signal Head_Read : std_logic_vector(1 downto 0); |
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236 | signal Head_Data : std_logic_vector(31 downto 0); |
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237 | signal Head_Empty : std_logic; |
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238 | signal Head_Header : std_logic_vector(31 DOWNTO 0); |
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239 | signal Head_Valid : std_logic; |
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240 | signal Head_Val : std_logic; |
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241 |
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242 | --DMA |
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243 | signal DMA_Read : std_logic; |
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244 | signal DMA_ack : std_logic; |
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245 | --signal AHB_Master_In : AHB_Mst_In_Type; |
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246 | --signal AHB_Master_Out : AHB_Mst_Out_Type; |
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247 |
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248 |
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249 | -- ADC |
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250 | --signal SmplClk : std_logic; |
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251 | --signal ADC_DataReady : std_logic; |
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252 | --signal ADC_SmplOut : Samples_out(4 downto 0); |
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253 | --signal enableADC : std_logic; |
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254 | -- |
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255 | --signal WG_Write : std_logic_vector(4 downto 0); |
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256 | --signal WG_ReUse : std_logic_vector(4 downto 0); |
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257 | --signal WG_DATA : std_logic_vector(79 downto 0); |
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258 | --signal s_out : std_logic_vector(79 downto 0); |
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259 | -- |
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260 | --signal fuller : std_logic_vector(4 downto 0); |
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261 | --signal reader : std_logic_vector(4 downto 0); |
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262 | --signal try : std_logic_vector(1 downto 0); |
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263 | --signal TXDint : std_logic; |
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264 | -- |
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265 | ---- IIR Filter |
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266 | --signal sample_clk_out : std_logic; |
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267 | -- |
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268 | --signal Rd : std_logic_vector(0 downto 0); |
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269 | --signal Ept : std_logic_vector(4 downto 0); |
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270 | -- |
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271 | --signal Bwr : std_logic_vector(0 downto 0); |
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272 | --signal Bre : std_logic_vector(0 downto 0); |
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273 | --signal DataTMP : std_logic_vector(15 downto 0); |
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274 | --signal FullUp : std_logic_vector(0 downto 0); |
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275 | --signal EmptyUp : std_logic_vector(0 downto 0); |
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276 | --signal FullDown : std_logic_vector(0 downto 0); |
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277 | --signal EmptyDown : std_logic_vector(0 downto 0); |
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278 | --------------------------------------------------------------------- |
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164 | --------------------------------------------------------------------- | |
279 | constant IOAEN : integer := CFG_CAN; |
|
165 | constant IOAEN : integer := CFG_CAN; | |
280 | constant boardfreq : integer := 50000; |
|
166 | constant boardfreq : integer := 50000; | |
281 |
|
167 | |||
282 | begin |
|
168 | begin | |
283 |
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169 | |||
284 | --------------------------------------------------------------------- |
|
170 | --------------------------------------------------------------------- | |
285 | --- AJOUT TEST -------------------------------------IPs------------- |
|
171 | --- AJOUT TEST -------------------------------------IPs------------- | |
286 | --------------------------------------------------------------------- |
|
172 | --------------------------------------------------------------------- | |
287 | led(1 downto 0) <= gpio(1 downto 0); |
|
|||
288 |
|
||||
289 | --- COM USB --------------------------------------------------------- |
|
|||
290 | -- MemIn0 : APB_FifoWrite |
|
|||
291 | -- generic map (5,5, Data_sz => 8, Addr_sz => 8, addr_max_int => 256) |
|
|||
292 | -- port map (clkm,rstn,apbi,USB_Read,open,open,InOutData,apbo(5)); |
|
|||
293 | -- |
|
|||
294 | -- BUF0 : APB_USB |
|
|||
295 | -- generic map (6,6,DataMax => 1024) |
|
|||
296 | -- port map(clkm,rstn,flagC,flagB,ifclk,sloe,USB_Read,USB_Write,pktend,fifoadr,InOutData,apbi,apbo(6)); |
|
|||
297 | -- |
|
|||
298 | -- MemOut0 : APB_FifoRead |
|
|||
299 | -- generic map (7,7, Data_sz => 8, Addr_sz => 8, addr_max_int => 256) |
|
|||
300 | -- port map (clkm,rstn,apbi,USB_Write,open,open,InOutData,apbo(7)); |
|
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301 | -- |
|
|||
302 | --slrd <= usb_Read; |
|
|||
303 | --slwr <= usb_Write; |
|
|||
304 |
|
||||
305 | --- CNA ------------------------------------------------------------- |
|
|||
306 |
|
||||
307 | -- CONV : APB_CNA |
|
|||
308 | -- generic map (5,5) |
|
|||
309 | -- port map(clkm,rstn,apbi,apbo(5),DAC_SYNC,DAC_SCLK,DAC_DATA); |
|
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310 |
|
||||
311 | --TEST(0) <= SmplClk; |
|
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312 | --TEST(1) <= WG_Write(0); |
|
|||
313 | --TEST(2) <= Fuller(0); |
|
|||
314 | --TEST(3) <= s_out(s_out'length-1); |
|
|||
315 |
|
||||
316 |
|
||||
317 | --SPW1_EN <= '1'; |
|
|||
318 | --SPW2_EN <= '0'; |
|
|||
319 |
|
||||
320 | --- CAN ------------------------------------------------------------- |
|
|||
321 |
|
173 | |||
322 | -- Divider : Clk_divider |
|
174 | -- apbo not free : 0 1 2 3 7 11 | |
323 | -- generic map(OSC_freqHz => 24_576_000, TargetFreq_Hz => 24_576) |
|
|||
324 | -- Port map(clkm,rstn,SmplClk); |
|
|||
325 | -- |
|
|||
326 | -- ADC : AD7688_drvr |
|
|||
327 | -- generic map (ChanelCount => 5, clkkHz => 24_576) |
|
|||
328 | -- port map (clkm,rstn,enableADC,SmplClk,ADC_DataReady,ADC_SmplOut,ADC_in,ADC_out); |
|
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329 | -- |
|
|||
330 | -- WG : WriteGen_ADC |
|
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331 | -- port map (clkm,rstn,SmplClk,ADC_DataReady,Fuller,WG_ReUse,WG_Write); |
|
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332 | -- |
|
|||
333 | --enableADC <= gpio(0); |
|
|||
334 |
|
175 | |||
335 | --WG_DATA <= ADC_SmplOut(4) & ADC_SmplOut(3) & ADC_SmplOut(2) & ADC_SmplOut(1) & ADC_SmplOut(0); |
|
176 | --- DAC ------------------------------------------------------------- | |
336 | -- |
|
|||
337 | -- |
|
|||
338 | -- MemIn1 : APB_FIFO |
|
|||
339 | -- generic map (pindex => 6, paddr => 6, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) |
|
|||
340 | -- port map (clkm,rstn,clkm,clkm,WG_ReUse,(others => '1'),WG_Write,open,Fuller,open,WG_DATA,open,open,apbi,apbo(6)); |
|
|||
341 |
|
||||
342 | -- DIGITAL_acquisition : ADS7886_drvr |
|
|||
343 | -- GENERIC MAP ( |
|
|||
344 | -- ChanelCount => 8, |
|
|||
345 | -- ncycle_cnv_high => 79, |
|
|||
346 | -- ncycle_cnv => 500) |
|
|||
347 | -- PORT MAP ( |
|
|||
348 | -- cnv_clk => clk50MHz, -- |
|
|||
349 | -- cnv_rstn => rstn, -- |
|
|||
350 | -- cnv_run => '1', -- |
|
|||
351 | -- cnv => CNV_CH1, -- |
|
|||
352 | -- clk => clkm, -- |
|
|||
353 | -- rstn => rstn, -- |
|
|||
354 | -- sck => SCK_CH1, -- |
|
|||
355 | -- sdo => SDO_CH1, -- |
|
|||
356 | -- sample => sample, |
|
|||
357 | -- sample_val => sample_val); |
|
|||
358 | -- |
|
|||
359 | --TopACQ_WenF0 <= not sample_filter_v2_out_val & not sample_filter_v2_out_val & not sample_filter_v2_out_val & not sample_filter_v2_out_val & not sample_filter_v2_out_val; |
|
|||
360 | --TopACQ_DataF0 <= E & D & C & B & A; |
|
|||
361 |
|
||||
362 | -- |
|
|||
363 | --TEST(0) <= TopACQ_WenF0(1); |
|
|||
364 | --TEST(1) <= SDO_CH1(1); |
|
|||
365 | -- |
|
|||
366 | --process(clkm,rstn) |
|
|||
367 | --begin |
|
|||
368 | -- if(rstn='0')then |
|
|||
369 | -- TopACQ_WenF0a <= (others => '1'); |
|
|||
370 | -- |
|
|||
371 | -- elsif(clkm'event and clkm='1')then |
|
|||
372 | -- TopACQ_WenF0a <= not sample_val & not sample_val & not sample_val & not sample_val & not sample_val; |
|
|||
373 | -- |
|
|||
374 | -- end if; |
|
|||
375 | --end process; |
|
|||
376 |
|
||||
377 | ACQ0 : lpp_top_acq |
|
|||
378 | port map('1',CNV_CH1,SCK_CH1,SDO_CH1,clk50MHz,rstn,clkm,rstn,ACQ_WenF0,ACQ_DataF0,ACQ_WenF1,ACQ_DataF1,open,open,ACQ_WenF3,ACQ_DataF3); |
|
|||
379 |
|
177 | |||
380 | Bias_Fails <= '0'; |
|
178 | CAL0 : APB_CNA | |
381 | --------- FIFO IN ------------------------------------------------------------- |
|
179 | generic map (pindex => 4, paddr => 4) | |
382 | ---- |
|
180 | port map(clkm,rstn,apbi,apbo(4),DAC_SYNC,DAC_SCLK,DAC_DATA); | |
383 | -- Memf0 : APB_FIFO |
|
|||
384 | -- generic map (pindex => 9, paddr => 9, FifoCnt => 5, Data_sz => 16, Addr_sz => 9, Enable_ReUse => '0', R => 1, W => 0) |
|
|||
385 | -- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),ACQ_WenF0,open,open,open,ACQ_DataF0,open,open,apbi,apbo(9)); |
|
|||
386 | -- |
|
|||
387 | -- Memf1 : APB_FIFO |
|
|||
388 | -- generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) |
|
|||
389 | -- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),ACQ_WenF1,open,open,open,ACQ_DataF1,open,open,apbi,apbo(8)); |
|
|||
390 | -- |
|
|||
391 | -- Memf3 : APB_FIFO |
|
|||
392 | -- generic map (pindex => 5, paddr => 5, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) |
|
|||
393 | -- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),ACQ_WenF3,open,open,open,ACQ_DataF3,open,open,apbi,apbo(5)); |
|
|||
394 |
|
||||
395 | Memf0 : lppFIFOxN |
|
|||
396 | generic map(Data_sz => 16, Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0') |
|
|||
397 | port map(rstn,clkm,clkm,(others => '0'),ACQ_WenF0,DMUX_Read(4 downto 0),ACQ_DataF0,FifoF0_Data,open,FifoF0_Empty); |
|
|||
398 |
|
||||
399 | Memf1 : lppFIFOxN |
|
|||
400 | generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') |
|
|||
401 | port map(rstn,clkm,clkm,(others => '0'),ACQ_WenF1,DMUX_Read(9 downto 5),ACQ_DataF1,FifoF1_Data,open,FifoF1_Empty); |
|
|||
402 |
|
||||
403 | Memf3 : lppFIFOxN |
|
|||
404 | generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') |
|
|||
405 | port map(rstn,clkm,clkm,(others => '0'),ACQ_WenF3,DMUX_Read(14 downto 10),ACQ_DataF3,FifoF3_Data,open,FifoF3_Empty); |
|
|||
406 | -- |
|
|||
407 | ----- DEMUX ------------------------------------------------------------- |
|
|||
408 |
|
||||
409 | DMUX0 : DEMUX |
|
|||
410 | generic map(Data_sz => 16) |
|
|||
411 | port map(clkm,rstn,FFT_Read,FFT_Load,FifoF0_Empty,FifoF1_Empty,FifoF3_Empty,FifoF0_Data,FifoF1_Data,FifoF3_Data,DMUX_WorkFreq,DMUX_Read,DMUX_Empty,DMUX_Data); |
|
|||
412 |
|
||||
413 | ------- FFT ------------------------------------------------------------- |
|
|||
414 |
|
||||
415 | -- MemIn : APB_FIFO |
|
|||
416 | -- generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1) |
|
|||
417 | -- port map (clkm,rstn,clkm,clkm,(others => '0'),FFT_Read,(others => '1'),DMUX_Empty,open,DMUX_Data,(others => '0'),open,open,apbi,apbo(8)); |
|
|||
418 |
|
||||
419 | FFT0 : FFT |
|
|||
420 | generic map(Data_sz => 16,NbData => 256) |
|
|||
421 | port map(clkm,rstn,DMUX_Empty,DMUX_Data,FifoINT_Full,FFT_Load,FFT_Read,FFT_Write,FFT_ReUse,FFT_Data); |
|
|||
422 |
|
||||
423 | --------- LINK MEMORY ------------------------------------------------------- |
|
|||
424 |
|
||||
425 | -- MemOut : APB_FIFO |
|
|||
426 | -- generic map (pindex => 9, paddr => 9, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 0) |
|
|||
427 | -- port map (clkm,rstn,clkm,clkm,FFT_ReUse,(others =>'1'),FFT_Write,open,FifoINT_Full,open,FFT_Data,open,open,apbi,apbo(9)); |
|
|||
428 |
|
||||
429 | MemInt : lppFIFOxN |
|
|||
430 | generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '1') |
|
|||
431 | port map(rstn,clkm,clkm,SM_ReUse,FFT_Write,SM_Read,FFT_Data,FifoINT_Data,FifoINT_Full,open); |
|
|||
432 |
|
181 | |||
433 | -- MemIn : APB_FIFO |
|
|||
434 | -- generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 0, W => 1) |
|
|||
435 | -- port map (clkm,rstn,clkm,clkm,(others => '0'),SM_Read,(others => '1'),open,FifoINT_Full,FifoINT_Data,(others => '0'),open,open,apbi,apbo(8)); |
|
|||
436 |
|
||||
437 | ----- MATRICE SPECTRALE ---------------------5 FIFO Input--------------- |
|
|||
438 |
|
||||
439 | SM0 : MatriceSpectrale |
|
|||
440 | generic map(Input_SZ => 16,Result_SZ => 32) |
|
|||
441 | port map(clkm,rstn,FifoINT_Full,FFT_ReUse,Head_Valid,FifoINT_Data,DMA_ack,SM_Wen,SM_FlagError,SM_Pong,SM_Param,SM_Write,SM_Read,SM_ReUse,SM_Data); |
|
|||
442 |
|
||||
443 |
|
||||
444 | --DMA_ack <= '1'; |
|
|||
445 | --Head_Valid <= '1'; |
|
|||
446 |
|
||||
447 | -- MemOut : APB_FIFO |
|
|||
448 | -- generic map (pindex => 9, paddr => 9, FifoCnt => 2, Data_sz => 32, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) |
|
|||
449 | -- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),SM_Write,open,FifoOUT_Full,open,SM_Data,open,open,apbi,apbo(9)); |
|
|||
450 |
|
||||
451 | MemOut : lppFIFOxN |
|
|||
452 | generic map(Data_sz => 32, Addr_sz => 8, FifoCnt => 2, Enable_ReUse => '0') |
|
|||
453 | port map(rstn,clkm,clkm,(others => '0'),SM_Write,Head_Read,SM_Data,FifoOUT_Data,FifoOUT_Full,FifoOUT_Empty); |
|
|||
454 |
|
||||
455 | ----------- Header ------------------------------------------------------- |
|
|||
456 |
|
||||
457 | Head0 : HeaderBuilder |
|
|||
458 | generic map(Data_sz => 32) |
|
|||
459 | port map(clkm,rstn,SM_Pong,SM_Param,DMUX_WorkFreq,SM_Wen,Head_Valid,FifoOUT_Data,FifoOUT_Empty,Head_Read,Head_Data,Head_Empty,DMA_Read,Head_Header,Head_Val,DMA_ack); |
|
|||
460 |
|
||||
461 |
|
||||
462 | --- DMA ------------------------------------------------------- |
|
|||
463 |
|
||||
464 | DMA0 : lpp_dma |
|
|||
465 | generic map(hindex => 1,pindex => 9, paddr => 9,pirq => 14, pmask =>16#fff#,tech => CFG_FABTECH) |
|
|||
466 | port map(clkm,rstn,apbi,apbo(9),ahbmi,ahbmo(1),Head_Data,Head_Empty,DMA_Read,Head_Header,Head_Val,DMA_ack); |
|
|||
467 |
|
||||
468 |
|
||||
469 | ----- FIFO ------------------------------------------------------------- |
|
|||
470 |
|
||||
471 | -- Memtest : APB_FIFO |
|
|||
472 | -- generic map (pindex => 5, paddr => 5, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 1) |
|
|||
473 | -- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),(others => '1'),open,open,open,(others => '0'),open,open,apbi,apbo(5)); |
|
|||
474 |
|
||||
475 | --***************************************TEST DEMI-FIFO******************************************************************************** |
|
|||
476 | -- MemIn : APB_FIFO |
|
|||
477 | -- generic map (pindex => 8, paddr => 8, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1) |
|
|||
478 | -- port map (clkm,rstn,clkm,clkm,(others => '0'),Bre,(others => '1'),EmptyUp,FullUp,DataTMP,(others => '0'),open,open,apbi,apbo(8)); |
|
|||
479 | -- |
|
|||
480 | -- Pont : Bridge |
|
|||
481 | -- port map(clkm,rstn,EmptyUp(0),FullDown(0),Bwr(0),Bre(0)); |
|
|||
482 | -- |
|
|||
483 | -- MemOut : APB_FIFO |
|
|||
484 | -- generic map (pindex => 9, paddr => 9, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) |
|
|||
485 | -- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),Bwr,EmptyDown,FullDown,open,DataTMP,open,open,apbi,apbo(9)); |
|
|||
486 | --************************************************************************************************************************************* |
|
|||
487 |
|
182 | |||
488 | --- UART ------------------------------------------------------------- |
|
183 | --- UART ------------------------------------------------------------- | |
489 |
|
184 | |||
490 | COM0 : APB_UART |
|
185 | COM0 : APB_UART | |
491 |
generic map (pindex => |
|
186 | generic map (pindex => 5, paddr => 5) | |
492 |
port map (clkm,rstn,apbi,apbo( |
|
187 | port map (clkm,rstn,apbi,apbo(5),UART_TXD,UART_RXD); | |
493 |
|
188 | |||
494 | --- DELAY ------------------------------------------------------------ |
|
|||
495 |
|
||||
496 | -- Delay0 : APB_Delay |
|
|||
497 | -- generic map (pindex => 4, paddr => 4) |
|
|||
498 | -- port map (clkm,rstn,apbi,apbo(4)); |
|
|||
499 |
|
189 | |||
500 |
--- |
|
190 | --- FIFO ------------------------------------------------------------- | |
501 | --Test(0) <= sample_clk_out; |
|
191 | ||
502 | -- |
|
192 | Memtest : APB_FIFO | |
503 | -- |
|
193 | generic map (pindex => 6, paddr => 6, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 1) | |
504 | -- IIR1: APB_IIR_Filter |
|
194 | port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),(others => '1'),open,open,open,(others => '0'),open,open,apbi,apbo(6)); | |
505 | -- generic map( |
|
195 | ||
506 | -- tech => CFG_MEMTECH, |
|
|||
507 | -- pindex => 8, |
|
|||
508 | -- paddr => 8, |
|
|||
509 | -- Sample_SZ => Sample_SZ, |
|
|||
510 | -- ChanelsCount => ChanelsCount, |
|
|||
511 | -- Coef_SZ => Coef_SZ, |
|
|||
512 | -- CoefCntPerCel => CoefCntPerCel, |
|
|||
513 | -- Cels_count => Cels_count, |
|
|||
514 | -- virgPos => virgPos |
|
|||
515 | -- ) |
|
|||
516 | -- port map( |
|
|||
517 | -- rst => rstn, |
|
|||
518 | -- clk => clkm, |
|
|||
519 | -- apbi => apbi, |
|
|||
520 | -- apbo => apbo(8), |
|
|||
521 | -- sample_clk_out => sample_clk_out, |
|
|||
522 | -- GOtest => Test(1), |
|
|||
523 | -- CoefsInitVal => (others => '1') |
|
|||
524 | -- ); |
|
|||
525 | ---------------------------------------------------------------------- |
|
|||
526 |
|
196 | |||
527 | ---------------------------------------------------------------------- |
|
197 | ---------------------------------------------------------------------- | |
528 | --- Reset and Clock generation ------------------------------------- |
|
198 | --- Reset and Clock generation ------------------------------------- | |
529 | ---------------------------------------------------------------------- |
|
199 | ---------------------------------------------------------------------- | |
530 |
|
200 | |||
531 | vcc <= (others => '1'); gnd <= (others => '0'); |
|
201 | vcc <= (others => '1'); gnd <= (others => '0'); | |
532 | cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; |
|
202 | cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; | |
533 |
|
203 | |||
534 | rst0 : rstgen port map (reset, clkm, cgo.clklock, rstn, rstraw); |
|
204 | rst0 : rstgen port map (reset, clkm, cgo.clklock, rstn, rstraw); | |
535 |
|
205 | |||
536 |
|
206 | |||
537 | clk_pad : clkpad generic map (tech => padtech) port map (clk50MHz, lclk2x); |
|
207 | clk_pad : clkpad generic map (tech => padtech) port map (clk50MHz, lclk2x); | |
538 |
|
208 | |||
539 | clkgen0 : clkgen -- clock generator |
|
209 | clkgen0 : clkgen -- clock generator | |
540 | generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, |
|
210 | generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, | |
541 | CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV) |
|
211 | CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV) | |
542 | port map (lclk, lclk, clkm, open, clk2x, sdclkl, pciclk, cgi, cgo); |
|
212 | port map (lclk, lclk, clkm, open, clk2x, sdclkl, pciclk, cgi, cgo); | |
543 |
|
213 | |||
544 | ramclk <= clkm; |
|
214 | ramclk <= clkm; | |
545 | process(lclk2x) |
|
215 | process(lclk2x) | |
546 | begin |
|
216 | begin | |
547 | if lclk2x'event and lclk2x = '1' then |
|
217 | if lclk2x'event and lclk2x = '1' then | |
548 | lclk <= not lclk; |
|
218 | lclk <= not lclk; | |
549 | end if; |
|
219 | end if; | |
550 | end process; |
|
220 | end process; | |
551 |
|
221 | |||
552 | ---------------------------------------------------------------------- |
|
222 | ---------------------------------------------------------------------- | |
553 | --- LEON3 processor / DSU / IRQ ------------------------------------ |
|
223 | --- LEON3 processor / DSU / IRQ ------------------------------------ | |
554 | ---------------------------------------------------------------------- |
|
224 | ---------------------------------------------------------------------- | |
555 |
|
225 | |||
556 | l3 : if CFG_LEON3 = 1 generate |
|
226 | l3 : if CFG_LEON3 = 1 generate | |
557 | cpu : for i in 0 to CFG_NCPU-1 generate |
|
227 | cpu : for i in 0 to CFG_NCPU-1 generate | |
558 | u0 : leon3s -- LEON3 processor |
|
228 | u0 : leon3s -- LEON3 processor | |
559 | generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, |
|
229 | generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, | |
560 | 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, |
|
230 | 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, | |
561 | CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, |
|
231 | CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, | |
562 | CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, |
|
232 | CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, | |
563 | CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, |
|
233 | CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, | |
564 | CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1) |
|
234 | CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1) | |
565 | port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, |
|
235 | port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, | |
566 | irqi(i), irqo(i), dbgi(i), dbgo(i)); |
|
236 | irqi(i), irqo(i), dbgi(i), dbgo(i)); | |
567 | end generate; |
|
237 | end generate; | |
568 | errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error); |
|
238 | errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error); | |
569 |
|
239 | |||
570 | dsugen : if CFG_DSU = 1 generate |
|
240 | dsugen : if CFG_DSU = 1 generate | |
571 | dsu0 : dsu3 -- LEON3 Debug Support Unit |
|
241 | dsu0 : dsu3 -- LEON3 Debug Support Unit | |
572 | generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#, |
|
242 | generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#, | |
573 | ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) |
|
243 | ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) | |
574 | port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); |
|
244 | port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); | |
575 | -- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable); |
|
245 | -- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable); | |
576 | dsui.enable <= '1'; |
|
246 | dsui.enable <= '1'; | |
577 | dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break); |
|
247 | dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break); | |
578 | dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active); |
|
248 | dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active); | |
579 | end generate; |
|
249 | end generate; | |
580 | end generate; |
|
250 | end generate; | |
581 |
|
251 | |||
582 | nodsu : if CFG_DSU = 0 generate |
|
252 | nodsu : if CFG_DSU = 0 generate | |
583 | ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; |
|
253 | ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; | |
584 | end generate; |
|
254 | end generate; | |
585 |
|
255 | |||
586 | irqctrl : if CFG_IRQ3_ENABLE /= 0 generate |
|
256 | irqctrl : if CFG_IRQ3_ENABLE /= 0 generate | |
587 | irqctrl0 : irqmp -- interrupt controller |
|
257 | irqctrl0 : irqmp -- interrupt controller | |
588 | generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU) |
|
258 | generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU) | |
589 | port map (rstn, clkm, apbi, apbo(2), irqo, irqi); |
|
259 | port map (rstn, clkm, apbi, apbo(2), irqo, irqi); | |
590 | end generate; |
|
260 | end generate; | |
591 | irq3 : if CFG_IRQ3_ENABLE = 0 generate |
|
261 | irq3 : if CFG_IRQ3_ENABLE = 0 generate | |
592 | x : for i in 0 to CFG_NCPU-1 generate |
|
262 | x : for i in 0 to CFG_NCPU-1 generate | |
593 | irqi(i).irl <= "0000"; |
|
263 | irqi(i).irl <= "0000"; | |
594 | end generate; |
|
264 | end generate; | |
595 | apbo(2) <= apb_none; |
|
265 | apbo(2) <= apb_none; | |
596 | end generate; |
|
266 | end generate; | |
597 |
|
267 | |||
598 | ---------------------------------------------------------------------- |
|
268 | ---------------------------------------------------------------------- | |
599 | --- Memory controllers --------------------------------------------- |
|
269 | --- Memory controllers --------------------------------------------- | |
600 | ---------------------------------------------------------------------- |
|
270 | ---------------------------------------------------------------------- | |
601 |
|
271 | |||
602 | memctrlr : mctrl generic map (hindex => 0,pindex => 0, paddr => 0) |
|
272 | memctrlr : mctrl generic map (hindex => 0,pindex => 0, paddr => 0) | |
603 | port map (rstn, clkm, memi, memo, ahbsi, ahbso(0),apbi,apbo(0),wpo, sdo); |
|
273 | port map (rstn, clkm, memi, memo, ahbsi, ahbso(0),apbi,apbo(0),wpo, sdo); | |
604 |
|
274 | |||
605 | memi.brdyn <= '1'; memi.bexcn <= '1'; |
|
275 | memi.brdyn <= '1'; memi.bexcn <= '1'; | |
606 | memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10"; |
|
276 | memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10"; | |
607 |
|
277 | |||
608 | bdr : for i in 0 to 3 generate |
|
278 | bdr : for i in 0 to 3 generate | |
609 | data_pad : iopadv generic map (tech => padtech, width => 8) |
|
279 | data_pad : iopadv generic map (tech => padtech, width => 8) | |
610 | port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8), |
|
280 | port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8), | |
611 | memo.bdrive(i), memi.data(31-i*8 downto 24-i*8)); |
|
281 | memo.bdrive(i), memi.data(31-i*8 downto 24-i*8)); | |
612 | end generate; |
|
282 | end generate; | |
613 |
|
283 | |||
614 |
|
284 | |||
615 | addr_pad : outpadv generic map (width => 19, tech => padtech) |
|
285 | addr_pad : outpadv generic map (width => 19, tech => padtech) | |
616 | port map (address, memo.address(20 downto 2)); |
|
286 | port map (address, memo.address(20 downto 2)); | |
617 |
|
287 | |||
618 |
|
288 | |||
619 | SSRAM_0:entity ssram_plugin |
|
289 | SSRAM_0:entity ssram_plugin | |
620 | generic map (tech => padtech) |
|
290 | generic map (tech => padtech) | |
621 | port map |
|
291 | port map | |
622 | (lclk2x,memo,SSRAM_CLK,nBWa,nBWb,nBWc,nBWd,nBWE,nADSC,nADSP,nADV,nGW,nCE1,CE2,nCE3,nOE,MODE,ZZ); |
|
292 | (lclk2x,memo,SSRAM_CLK,nBWa,nBWb,nBWc,nBWd,nBWE,nADSC,nADSP,nADV,nGW,nCE1,CE2,nCE3,nOE,MODE,ZZ); | |
623 |
|
293 | |||
624 | ---------------------------------------------------------------------- |
|
294 | ---------------------------------------------------------------------- | |
625 | --- AHB CONTROLLER ------------------------------------------------- |
|
295 | --- AHB CONTROLLER ------------------------------------------------- | |
626 | ---------------------------------------------------------------------- |
|
296 | ---------------------------------------------------------------------- | |
627 |
|
297 | |||
628 | ahb0 : ahbctrl -- AHB arbiter/multiplexer |
|
298 | ahb0 : ahbctrl -- AHB arbiter/multiplexer | |
629 | generic map (defmast => CFG_DEFMST, split => CFG_SPLIT, |
|
299 | generic map (defmast => CFG_DEFMST, split => CFG_SPLIT, | |
630 | rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, |
|
300 | rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, | |
631 | ioen => IOAEN, nahbm => maxahbm, nahbs => 8) |
|
301 | ioen => IOAEN, nahbm => maxahbm, nahbs => 8) | |
632 | port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); |
|
302 | port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); | |
633 |
|
303 | |||
634 | ---------------------------------------------------------------------- |
|
304 | ---------------------------------------------------------------------- | |
635 | --- AHB UART ------------------------------------------------------- |
|
305 | --- AHB UART ------------------------------------------------------- | |
636 | ---------------------------------------------------------------------- |
|
306 | ---------------------------------------------------------------------- | |
637 |
|
307 | |||
638 | dcomgen : if CFG_AHB_UART = 1 generate |
|
308 | dcomgen : if CFG_AHB_UART = 1 generate | |
639 | dcom0: ahbuart -- Debug UART |
|
309 | dcom0: ahbuart -- Debug UART | |
640 |
generic map (hindex => |
|
310 | generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7) | |
641 |
port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo( |
|
311 | port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU)); | |
642 | dsurx_pad : inpad generic map (tech => padtech) port map (ahbrxd, ahbuarti.rxd); |
|
312 | dsurx_pad : inpad generic map (tech => padtech) port map (ahbrxd, ahbuarti.rxd); | |
643 | dsutx_pad : outpad generic map (tech => padtech) port map (ahbtxd, ahbuarto.txd); |
|
313 | dsutx_pad : outpad generic map (tech => padtech) port map (ahbtxd, ahbuarto.txd); | |
644 | -- led(0) <= not ahbuarti.rxd; led(1) <= not ahbuarto.txd; |
|
314 | -- led(0) <= not ahbuarti.rxd; led(1) <= not ahbuarto.txd; | |
645 | end generate; |
|
315 | end generate; | |
646 | nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate; |
|
316 | nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate; | |
647 |
|
317 | |||
648 | ---------------------------------------------------------------------- |
|
318 | ---------------------------------------------------------------------- | |
649 | --- APB Bridge ----------------------------------------------------- |
|
319 | --- APB Bridge ----------------------------------------------------- | |
650 | ---------------------------------------------------------------------- |
|
320 | ---------------------------------------------------------------------- | |
651 |
|
321 | |||
652 | apb0 : apbctrl -- AHB/APB bridge |
|
322 | apb0 : apbctrl -- AHB/APB bridge | |
653 | generic map (hindex => 1, haddr => CFG_APBADDR) |
|
323 | generic map (hindex => 1, haddr => CFG_APBADDR) | |
654 | port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo ); |
|
324 | port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo ); | |
655 |
|
325 | |||
656 | ---------------------------------------------------------------------- |
|
326 | ---------------------------------------------------------------------- | |
657 | --- GPT Timer ------------------------------------------------------ |
|
327 | --- GPT Timer ------------------------------------------------------ | |
658 | ---------------------------------------------------------------------- |
|
328 | ---------------------------------------------------------------------- | |
659 |
|
329 | |||
660 | gpt : if CFG_GPT_ENABLE /= 0 generate |
|
330 | gpt : if CFG_GPT_ENABLE /= 0 generate | |
661 | timer0 : gptimer -- timer unit |
|
331 | timer0 : gptimer -- timer unit | |
662 | generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, |
|
332 | generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, | |
663 | sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, |
|
333 | sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, | |
664 | nbits => CFG_GPT_TW) |
|
334 | nbits => CFG_GPT_TW) | |
665 | port map (rstn, clkm, apbi, apbo(3), gpti, gpto); |
|
335 | port map (rstn, clkm, apbi, apbo(3), gpti, gpto); | |
666 | gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0'; |
|
336 | gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0'; | |
667 | -- led(4) <= gpto.wdog; |
|
337 | -- led(4) <= gpto.wdog; | |
668 | end generate; |
|
338 | end generate; | |
669 | notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate; |
|
339 | notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate; | |
670 |
|
340 | |||
671 |
|
341 | |||
672 | ---------------------------------------------------------------------- |
|
342 | ---------------------------------------------------------------------- | |
673 | --- APB UART ------------------------------------------------------- |
|
343 | --- APB UART ------------------------------------------------------- | |
674 | ---------------------------------------------------------------------- |
|
344 | ---------------------------------------------------------------------- | |
675 |
|
345 | |||
676 | ua1 : if CFG_UART1_ENABLE /= 0 generate |
|
346 | ua1 : if CFG_UART1_ENABLE /= 0 generate | |
677 | uart1 : apbuart -- UART 1 |
|
347 | uart1 : apbuart -- UART 1 | |
678 | generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, |
|
348 | generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, | |
679 | fifosize => CFG_UART1_FIFO) |
|
349 | fifosize => CFG_UART1_FIFO) | |
680 | port map (rstn, clkm, apbi, apbo(1), ahbuarti, apbuarto); |
|
350 | port map (rstn, clkm, apbi, apbo(1), ahbuarti, apbuarto); | |
681 | apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd; |
|
351 | apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd; | |
682 | apbuarti.ctsn <= '0'; --rtsn1 <= apbuarto.rtsn; |
|
352 | apbuarti.ctsn <= '0'; --rtsn1 <= apbuarto.rtsn; | |
683 | -- led(0) <= not apbuarti.rxd; led(1) <= not apbuarto.txd; |
|
353 | -- led(0) <= not apbuarti.rxd; led(1) <= not apbuarto.txd; | |
684 | end generate; |
|
354 | end generate; | |
685 | noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate; |
|
355 | noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate; | |
686 |
|
356 | |||
687 | ---------------------------------------------------------------------- |
|
357 | ---------------------------------------------------------------------- | |
688 | --- GPIO ----------------------------------------------------------- |
|
358 | --- GPIO ----------------------------------------------------------- | |
689 | ---------------------------------------------------------------------- |
|
359 | ---------------------------------------------------------------------- | |
|
360 | led(0) <= gpio(0); led(1) <= gpio(1); | |||
690 |
|
361 | |||
691 | gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit |
|
362 | gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit | |
692 | grgpio0: grgpio |
|
363 | grgpio0: grgpio | |
693 | generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 7) |
|
364 | generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 7) | |
694 | port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo); |
|
365 | port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo); | |
695 |
|
366 | |||
696 | pio_pads : for i in 0 to 6 generate |
|
367 | pio_pads : for i in 0 to 6 generate | |
697 | pio_pad : iopad generic map (tech => padtech) |
|
368 | pio_pad : iopad generic map (tech => padtech) | |
698 | port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i)); |
|
369 | port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i)); | |
699 | end generate; |
|
370 | end generate; | |
700 | end generate; |
|
371 | end generate; | |
701 |
|
372 | |||
702 |
|
373 | |||
703 | end Behavioral; No newline at end of file |
|
374 | end Behavioral; |
@@ -1,188 +1,155 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------ |
|
18 | ------------------------------------------------------------------------------ | |
19 | -- Author : Martin Morlot |
|
19 | -- Author : Martin Morlot | |
20 | -- Mail : martin.morlot@lpp.polytechnique.fr |
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |
21 | ------------------------------------------------------------------------------ |
|
21 | ------------------------------------------------------------------------------ | |
22 | library IEEE; |
|
22 | library IEEE; | |
23 | use IEEE.std_logic_1164.all; |
|
23 | use IEEE.std_logic_1164.all; | |
24 | use IEEE.numeric_std.all; |
|
24 | use IEEE.numeric_std.all; | |
25 |
|
25 | |||
26 | entity HeaderBuilder is |
|
26 | entity HeaderBuilder is | |
27 | generic( |
|
27 | generic( | |
28 | Data_sz : integer := 32); |
|
28 | Data_sz : integer := 32); | |
29 | port( |
|
29 | port( | |
30 | clkm : in std_logic; |
|
30 | clkm : in std_logic; | |
31 | rstn : in std_logic; |
|
31 | rstn : in std_logic; | |
32 |
|
32 | |||
33 | pong : in std_logic; |
|
|||
34 | Statu : in std_logic_vector(3 downto 0); |
|
33 | Statu : in std_logic_vector(3 downto 0); | |
35 | Matrix_Type : in std_logic_vector(1 downto 0); |
|
34 | Matrix_Type : in std_logic_vector(1 downto 0); | |
36 | Matrix_Write : in std_logic; |
|
35 | Matrix_Write : in std_logic; | |
37 | Valid : out std_logic; |
|
36 | Valid : out std_logic; | |
38 |
|
37 | |||
39 | dataIN : in std_logic_vector((2*Data_sz)-1 downto 0); |
|
38 | dataIN : in std_logic_vector((2*Data_sz)-1 downto 0); | |
40 | emptyIN : in std_logic_vector(1 downto 0); |
|
39 | emptyIN : in std_logic_vector(1 downto 0); | |
41 | RenOUT : out std_logic_vector(1 downto 0); |
|
40 | RenOUT : out std_logic_vector(1 downto 0); | |
42 |
|
41 | |||
43 | dataOUT : out std_logic_vector(Data_sz-1 downto 0); |
|
42 | dataOUT : out std_logic_vector(Data_sz-1 downto 0); | |
44 | emptyOUT : out std_logic; |
|
43 | emptyOUT : out std_logic; | |
45 | RenIN : in std_logic; |
|
44 | RenIN : in std_logic; | |
46 |
|
45 | |||
47 | header : out std_logic_vector(Data_sz-1 DOWNTO 0); |
|
46 | header : out std_logic_vector(Data_sz-1 DOWNTO 0); | |
48 | header_val : out std_logic; |
|
47 | header_val : out std_logic; | |
49 | header_ack : in std_logic |
|
48 | header_ack : in std_logic | |
50 | ); |
|
49 | ); | |
51 | end entity; |
|
50 | end entity; | |
52 |
|
51 | |||
53 |
|
52 | |||
54 | architecture ar_HeaderBuilder of HeaderBuilder is |
|
53 | architecture ar_HeaderBuilder of HeaderBuilder is | |
55 |
|
54 | |||
56 | signal Matrix_Param : std_logic_vector(3 downto 0); |
|
55 | signal Matrix_Param : std_logic_vector(3 downto 0); | |
57 | signal Write_reg : std_logic; |
|
56 | signal Write_reg : std_logic; | |
58 | signal Data_cpt : integer; |
|
57 | signal Data_cpt : integer; | |
59 | signal MAX : integer; |
|
58 | signal MAX : integer; | |
60 | signal pong_reg : std_logic; |
|
|||
61 |
|
59 | |||
62 | type etat is (idle0,idle1,pong0,pong1); |
|
60 | type etat is (idle0,idle1,pong0,pong1); | |
63 | signal ect : etat; |
|
61 | signal ect : etat; | |
64 |
|
62 | |||
65 | begin |
|
63 | begin | |
66 |
|
64 | |||
67 | process (clkm,rstn) |
|
65 | process (clkm,rstn) | |
68 | begin |
|
66 | begin | |
69 | if(rstn='0')then |
|
67 | if(rstn='0')then | |
70 | ect <= idle0; |
|
68 | ect <= idle0; | |
71 | Valid <= '0'; |
|
69 | Valid <= '0'; | |
72 | pong_reg <= '0'; |
|
|||
73 | header_val <= '0'; |
|
70 | header_val <= '0'; | |
74 | header(5 downto 0) <= (others => '0'); |
|
71 | header(5 downto 0) <= (others => '0'); | |
75 | Write_reg <= '0'; |
|
72 | Write_reg <= '0'; | |
76 | Data_cpt <= 0; |
|
73 | Data_cpt <= 0; | |
77 | MAX <= 128; |
|
74 | MAX <= 128; | |
78 |
|
75 | |||
79 |
|
76 | |||
80 | elsif(clkm' event and clkm='1')then |
|
77 | elsif(clkm' event and clkm='1')then | |
81 | Write_reg <= Matrix_Write; |
|
78 | Write_reg <= Matrix_Write; | |
82 | pong_reg <= pong; |
|
|||
83 |
|
79 | |||
84 | if(Statu="0001" or Statu="0011" or Statu="0110" or Statu="1010" or Statu="1111")then |
|
80 | if(Statu="0001" or Statu="0011" or Statu="0110" or Statu="1010" or Statu="1111")then | |
85 | MAX <= 128; |
|
81 | MAX <= 128; | |
86 | else |
|
82 | else | |
87 | MAX <= 256; |
|
83 | MAX <= 256; | |
88 | end if; |
|
84 | end if; | |
89 |
|
85 | |||
90 | -- if(Write_reg = '0' and Matrix_Write = '1')then |
|
|||
91 | -- if(Data_cpt = MAX)then |
|
|||
92 | -- Data_cpt <= 0; |
|
|||
93 | -- Valid <= '1'; |
|
|||
94 | -- header_val <= '1'; |
|
|||
95 | -- else |
|
|||
96 | -- Data_cpt <= Data_cpt + 1; |
|
|||
97 | -- Valid <= '0'; |
|
|||
98 | -- end if; |
|
|||
99 | -- end if; |
|
|||
100 |
|
||||
101 | if(Write_reg = '0' and Matrix_Write = '1')then |
|
86 | if(Write_reg = '0' and Matrix_Write = '1')then | |
102 | Data_cpt <= Data_cpt + 1; |
|
87 | Data_cpt <= Data_cpt + 1; | |
103 | Valid <= '0'; |
|
88 | Valid <= '0'; | |
104 | elsif(Data_cpt = MAX)then |
|
89 | elsif(Data_cpt = MAX)then | |
105 | Data_cpt <= 0; |
|
90 | Data_cpt <= 0; | |
106 | Valid <= '1'; |
|
91 | Valid <= '1'; | |
107 | header_val <= '1'; |
|
92 | header_val <= '1'; | |
108 | else |
|
93 | else | |
109 | Valid <= '0'; |
|
94 | Valid <= '0'; | |
110 | end if; |
|
95 | end if; | |
111 |
|
||||
112 | -- if(header_ack = '1')then |
|
|||
113 | -- header_val <= '0'; |
|
|||
114 | -- end if; |
|
|||
115 |
|
||||
116 | -- if(emptyIN = "10")then |
|
|||
117 | -- ping <= '0'; |
|
|||
118 | -- elsif(emptyIN = "01")then |
|
|||
119 | -- ping <= '1'; |
|
|||
120 | -- else |
|
|||
121 | -- ping <= ping; |
|
|||
122 | -- end if; |
|
|||
123 |
|
|
96 | ||
124 |
|
|
97 | ||
125 |
|
|
98 | case ect is | |
126 |
|
99 | |||
127 | when idle0 => |
|
100 | when idle0 => | |
128 | if(header_ack = '1')then |
|
101 | if(header_ack = '1')then | |
129 | header_val <= '0'; |
|
102 | header_val <= '0'; | |
130 |
|
|
103 | ect <= pong0; | |
131 | ect <= pong0; |
|
|||
132 | --elsif(pong = '0')then |
|
|||
133 | --ect <= pong1; |
|
|||
134 | --end if; |
|
|||
135 | end if; |
|
104 | end if; | |
136 |
|
105 | |||
137 | when pong0 => |
|
106 | when pong0 => | |
138 | header(1 downto 0) <= Matrix_Type; |
|
107 | header(1 downto 0) <= Matrix_Type; | |
139 | header(5 downto 2) <= Matrix_Param; |
|
108 | header(5 downto 2) <= Matrix_Param; | |
140 | if(emptyIN(0) = '1')then |
|
109 | if(emptyIN(0) = '1')then | |
141 | ect <= idle1; |
|
110 | ect <= idle1; | |
142 | end if; |
|
111 | end if; | |
143 |
|
112 | |||
144 | when idle1 => |
|
113 | when idle1 => | |
145 | if(header_ack = '1')then |
|
114 | if(header_ack = '1')then | |
146 | header_val <= '0'; |
|
115 | header_val <= '0'; | |
147 | ect <= pong1; |
|
116 | ect <= pong1; | |
148 | end if; |
|
117 | end if; | |
149 |
|
118 | |||
150 | when pong1 => |
|
119 | when pong1 => | |
151 | header(1 downto 0) <= Matrix_Type; |
|
120 | header(1 downto 0) <= Matrix_Type; | |
152 | header(5 downto 2) <= Matrix_Param; |
|
121 | header(5 downto 2) <= Matrix_Param; | |
153 | if(emptyIN(1) = '1')then |
|
122 | if(emptyIN(1) = '1')then | |
154 | ect <= idle0; |
|
123 | ect <= idle0; | |
155 | end if; |
|
124 | end if; | |
156 |
|
125 | |||
157 | end case; |
|
126 | end case; | |
158 | end if; |
|
127 | end if; | |
159 | end process; |
|
128 | end process; | |
160 |
|
129 | |||
161 | Matrix_Param <= std_logic_vector(to_unsigned(to_integer(unsigned(Statu))-1,4)); |
|
130 | Matrix_Param <= std_logic_vector(to_unsigned(to_integer(unsigned(Statu))-1,4)); | |
162 |
|
131 | |||
163 | --header(1 downto 0) <= Matrix_Type; |
|
|||
164 | --header(5 downto 2) <= Matrix_Param; |
|
|||
165 | header(31 downto 6) <= (others => '0'); |
|
132 | header(31 downto 6) <= (others => '0'); | |
166 |
|
133 | |||
167 | with ect select |
|
134 | with ect select | |
168 | dataOUT <= dataIN(Data_sz-1 downto 0) when pong0, |
|
135 | dataOUT <= dataIN(Data_sz-1 downto 0) when pong0, | |
169 | dataIN(Data_sz-1 downto 0) when idle0, |
|
136 | dataIN(Data_sz-1 downto 0) when idle0, | |
170 | dataIN((2*Data_sz)-1 downto Data_sz) when pong1, |
|
137 | dataIN((2*Data_sz)-1 downto Data_sz) when pong1, | |
171 | dataIN((2*Data_sz)-1 downto Data_sz) when idle1, |
|
138 | dataIN((2*Data_sz)-1 downto Data_sz) when idle1, | |
172 | (others => '0') when others; |
|
139 | (others => '0') when others; | |
173 |
|
140 | |||
174 | with ect select |
|
141 | with ect select | |
175 | emptyOUT <= emptyIN(0) when pong0, |
|
142 | emptyOUT <= emptyIN(0) when pong0, | |
176 | emptyIN(0) when idle0, |
|
143 | emptyIN(0) when idle0, | |
177 | emptyIN(1) when pong1, |
|
144 | emptyIN(1) when pong1, | |
178 | emptyIN(1) when idle1, |
|
145 | emptyIN(1) when idle1, | |
179 | '1' when others; |
|
146 | '1' when others; | |
180 |
|
147 | |||
181 | with ect select |
|
148 | with ect select | |
182 | RenOUT <= '1' & RenIN when pong0, |
|
149 | RenOUT <= '1' & RenIN when pong0, | |
183 | '1' & RenIN when idle0, |
|
150 | '1' & RenIN when idle0, | |
184 | RenIN & '1' when pong1, |
|
151 | RenIN & '1' when pong1, | |
185 | RenIN & '1' when idle1, |
|
152 | RenIN & '1' when idle1, | |
186 | "11" when others; |
|
153 | "11" when others; | |
187 |
|
154 | |||
188 | end architecture; |
|
155 | end architecture; |
@@ -1,61 +1,60 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------ |
|
18 | ------------------------------------------------------------------------------ | |
19 | -- Author : Martin Morlot |
|
19 | -- Author : Martin Morlot | |
20 | -- Mail : martin.morlot@lpp.polytechnique.fr |
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |
21 | ------------------------------------------------------------------------------ |
|
21 | ------------------------------------------------------------------------------ | |
22 | library ieee; |
|
22 | library ieee; | |
23 | use ieee.std_logic_1164.all; |
|
23 | use ieee.std_logic_1164.all; | |
24 | library grlib; |
|
24 | library grlib; | |
25 | use grlib.amba.all; |
|
25 | use grlib.amba.all; | |
26 | use std.textio.all; |
|
26 | use std.textio.all; | |
27 | library lpp; |
|
27 | library lpp; | |
28 | use lpp.lpp_amba.all; |
|
28 | use lpp.lpp_amba.all; | |
29 |
|
29 | |||
30 | --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on |
|
30 | --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on | |
31 |
|
31 | |||
32 | package lpp_Header is |
|
32 | package lpp_Header is | |
33 |
|
33 | |||
34 | component HeaderBuilder is |
|
34 | component HeaderBuilder is | |
35 | generic( |
|
35 | generic( | |
36 | Data_sz : integer := 32); |
|
36 | Data_sz : integer := 32); | |
37 | port( |
|
37 | port( | |
38 | clkm : in std_logic; |
|
38 | clkm : in std_logic; | |
39 | rstn : in std_logic; |
|
39 | rstn : in std_logic; | |
40 |
|
40 | |||
41 | pong : in std_logic; |
|
|||
42 | Statu : in std_logic_vector(3 downto 0); |
|
41 | Statu : in std_logic_vector(3 downto 0); | |
43 | Matrix_Type : in std_logic_vector(1 downto 0); |
|
42 | Matrix_Type : in std_logic_vector(1 downto 0); | |
44 | Matrix_Write : in std_logic; |
|
43 | Matrix_Write : in std_logic; | |
45 | Valid : out std_logic; |
|
44 | Valid : out std_logic; | |
46 |
|
45 | |||
47 | dataIN : in std_logic_vector((2*Data_sz)-1 downto 0); |
|
46 | dataIN : in std_logic_vector((2*Data_sz)-1 downto 0); | |
48 | emptyIN : in std_logic_vector(1 downto 0); |
|
47 | emptyIN : in std_logic_vector(1 downto 0); | |
49 | RenOUT : out std_logic_vector(1 downto 0); |
|
48 | RenOUT : out std_logic_vector(1 downto 0); | |
50 |
|
49 | |||
51 | dataOUT : out std_logic_vector(Data_sz-1 downto 0); |
|
50 | dataOUT : out std_logic_vector(Data_sz-1 downto 0); | |
52 | emptyOUT : out std_logic; |
|
51 | emptyOUT : out std_logic; | |
53 | RenIN : in std_logic; |
|
52 | RenIN : in std_logic; | |
54 |
|
53 | |||
55 | header : out std_logic_vector(Data_sz-1 DOWNTO 0); |
|
54 | header : out std_logic_vector(Data_sz-1 DOWNTO 0); | |
56 | header_val : out std_logic; |
|
55 | header_val : out std_logic; | |
57 | header_ack : in std_logic |
|
56 | header_ack : in std_logic | |
58 | ); |
|
57 | ); | |
59 | end component; |
|
58 | end component; | |
60 |
|
59 | |||
61 | end; No newline at end of file |
|
60 | end; |
@@ -1,82 +1,82 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------ |
|
18 | ------------------------------------------------------------------------------ | |
19 | -- Author : Martin Morlot |
|
19 | -- Author : Martin Morlot | |
20 | -- Mail : martin.morlot@lpp.polytechnique.fr |
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |
21 | ------------------------------------------------------------------------------ |
|
21 | ------------------------------------------------------------------------------ | |
22 | library IEEE; |
|
22 | library IEEE; | |
23 | use IEEE.std_logic_1164.all; |
|
23 | use IEEE.std_logic_1164.all; | |
24 | use IEEE.numeric_std.all; |
|
24 | use IEEE.numeric_std.all; | |
25 | use work.Convertisseur_config.all; |
|
25 | use work.Convertisseur_config.all; | |
26 |
|
26 | |||
27 | --! Programme du Convertisseur NumοΏ½rique/Analogique |
|
27 | --! Programme du Convertisseur NumοΏ½rique/Analogique | |
28 |
|
28 | |||
29 | entity CNA_TabloC is |
|
29 | entity CNA_TabloC is | |
30 | port( |
|
30 | port( | |
31 | clock : in std_logic; --! Horloge du composant |
|
31 | clock : in std_logic; --! Horloge du composant | |
32 | rst : in std_logic; --! Reset general du composant |
|
32 | rst : in std_logic; --! Reset general du composant | |
33 | enable : in std_logic; --! Autorise ou non l'utilisation du composant |
|
33 | enable : in std_logic; --! Autorise ou non l'utilisation du composant | |
34 | Data_C : in std_logic_vector(15 downto 0); --! DonnοΏ½e NumοΏ½rique d'entrοΏ½e sur 16 bits |
|
34 | Data_C : in std_logic_vector(15 downto 0); --! DonnοΏ½e NumοΏ½rique d'entrοΏ½e sur 16 bits | |
35 | SYNC : out std_logic; --! Signal de synchronisation du convertisseur |
|
35 | SYNC : out std_logic; --! Signal de synchronisation du convertisseur | |
36 | SCLK : out std_logic; --! Horloge systeme du convertisseur |
|
36 | SCLK : out std_logic; --! Horloge systeme du convertisseur | |
37 | flag_sd : out std_logic; --! Flag, signale la fin de la sοΏ½rialisation d'une donnοΏ½e |
|
37 | flag_sd : out std_logic; --! Flag, signale la fin de la sοΏ½rialisation d'une donnοΏ½e | |
38 | Data : out std_logic --! DonnοΏ½e numοΏ½rique sοΏ½rialisοΏ½ |
|
38 | Data : out std_logic --! DonnοΏ½e numοΏ½rique sοΏ½rialisοΏ½ | |
39 | ); |
|
39 | ); | |
40 | end CNA_TabloC; |
|
40 | end CNA_TabloC; | |
41 |
|
41 | |||
42 | --! @details Un driver C va permettre de gοΏ½nerer un tableau de donnοΏ½es sur 16 bits, |
|
42 | --! @details Un driver C va permettre de gοΏ½nerer un tableau de donnοΏ½es sur 16 bits, | |
43 | --! qui seront sοΏ½rialisοΏ½ pour οΏ½tre ensuite dirigοΏ½es vers le convertisseur. |
|
43 | --! qui seront sοΏ½rialisοΏ½ pour οΏ½tre ensuite dirigοΏ½es vers le convertisseur. | |
44 |
|
44 | |||
45 | architecture ar_CNA_TabloC of CNA_TabloC is |
|
45 | architecture ar_CNA_TabloC of CNA_TabloC is | |
46 |
|
46 | |||
47 | component CLKINT |
|
47 | --component CLKINT | |
48 | port( A : in std_logic := 'U'; |
|
48 | --port( A : in std_logic := 'U'; | |
49 | Y : out std_logic); |
|
49 | -- Y : out std_logic); | |
50 | end component; |
|
50 | --end component; | |
51 |
|
51 | |||
52 | signal clk : std_logic; |
|
52 | --signal clk : std_logic; | |
53 |
|
53 | |||
54 | signal raz : std_logic; |
|
54 | --signal raz : std_logic; | |
55 | signal s_SCLK : std_logic; |
|
55 | signal s_SCLK : std_logic; | |
56 | signal OKAI_send : std_logic; |
|
56 | signal OKAI_send : std_logic; | |
57 |
|
57 | |||
58 | begin |
|
58 | begin | |
59 |
|
59 | |||
60 | CLKINT_0 : CLKINT |
|
60 | --CLKINT_0 : CLKINT | |
61 | port map(A => clock, Y => clk); |
|
61 | -- port map(A => clock, Y => clk); | |
62 |
|
62 | |||
63 | CLKINT_1 : CLKINT |
|
63 | --CLKINT_1 : CLKINT | |
64 | port map(A => rst, Y => raz); |
|
64 | -- port map(A => rst, Y => raz); | |
65 |
|
65 | |||
66 |
|
66 | |||
67 | SystemCLK : entity work.Systeme_Clock |
|
67 | SystemCLK : entity work.Systeme_Clock | |
68 | generic map (nb_serial) |
|
68 | generic map (nb_serial) | |
69 |
port map (clk,r |
|
69 | port map (clock,rst,s_SCLK); | |
70 |
|
70 | |||
71 |
|
71 | |||
72 | Signal_sync : entity work.Gene_SYNC |
|
72 | Signal_sync : entity work.Gene_SYNC | |
73 |
port map (s_SCLK,r |
|
73 | port map (s_SCLK,rst,enable,OKAI_send,SYNC); | |
74 |
|
74 | |||
75 |
|
75 | |||
76 | Serial : entity work.serialize |
|
76 | Serial : entity work.serialize | |
77 |
port map (clk,r |
|
77 | port map (clock,rst,s_SCLK,Data_C,OKAI_send,flag_sd,Data); | |
78 |
|
78 | |||
79 |
|
79 | |||
80 | SCLK <= s_SCLK; |
|
80 | SCLK <= s_SCLK; | |
81 |
|
81 | |||
82 | end ar_CNA_TabloC; No newline at end of file |
|
82 | end ar_CNA_TabloC; |
@@ -1,97 +1,89 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
19 | -- Author : Martin Morlot |
|
19 | -- Author : Martin Morlot | |
20 | -- Mail : martin.morlot@lpp.polytechnique.fr |
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |
21 | ------------------------------------------------------------------------------- |
|
21 | ------------------------------------------------------------------------------- | |
22 | library IEEE; |
|
22 | library IEEE; | |
23 | use IEEE.numeric_std.all; |
|
23 | use IEEE.numeric_std.all; | |
24 | use IEEE.std_logic_1164.all; |
|
24 | use IEEE.std_logic_1164.all; | |
25 |
|
25 | |||
26 | entity Dispatch is |
|
26 | entity Dispatch is | |
27 | generic( |
|
27 | generic( | |
28 | Data_SZ : integer := 32); |
|
28 | Data_SZ : integer := 32); | |
29 | port( |
|
29 | port( | |
30 | clk : in std_logic; |
|
30 | clk : in std_logic; | |
31 | reset : in std_logic; |
|
31 | reset : in std_logic; | |
32 |
Ac |
|
32 | Ack : in std_logic; | |
33 | Data : in std_logic_vector(Data_SZ-1 downto 0); |
|
33 | Data : in std_logic_vector(Data_SZ-1 downto 0); | |
34 | Write : in std_logic; |
|
34 | Write : in std_logic; | |
35 | Valid : in std_logic; |
|
35 | Valid : in std_logic; | |
36 | -- Full : in std_logic_vector(1 downto 0); |
|
|||
37 | FifoData : out std_logic_vector(2*Data_SZ-1 downto 0); |
|
36 | FifoData : out std_logic_vector(2*Data_SZ-1 downto 0); | |
38 | FifoWrite : out std_logic_vector(1 downto 0); |
|
37 | FifoWrite : out std_logic_vector(1 downto 0); | |
39 | Pong : out std_logic; |
|
|||
40 | Error : out std_logic |
|
38 | Error : out std_logic | |
41 | ); |
|
39 | ); | |
42 | end entity; |
|
40 | end entity; | |
43 |
|
41 | |||
44 |
|
42 | |||
45 | architecture ar_Dispatch of Dispatch is |
|
43 | architecture ar_Dispatch of Dispatch is | |
46 |
|
44 | |||
47 | type etat is (eX,e0,e1,e2); |
|
45 | type etat is (eX,e0,e1,e2); | |
48 | signal ect : etat; |
|
46 | signal ect : etat; | |
49 |
|
47 | |||
50 |
signal Pong |
|
48 | signal Pong : std_logic; | |
51 | --signal FifoCpt : integer range 0 to 1 := 0; |
|
|||
52 |
|
49 | |||
53 | begin |
|
50 | begin | |
54 |
|
51 | |||
55 | process (clk,reset) |
|
52 | process (clk,reset) | |
56 | begin |
|
53 | begin | |
57 | if(reset='0')then |
|
54 | if(reset='0')then | |
58 |
Pong |
|
55 | Pong <= '0'; | |
59 | Error <= '0'; |
|
56 | Error <= '0'; | |
60 | ect <= e0; |
|
57 | ect <= e0; | |
61 |
|
58 | |||
62 | elsif(clk' event and clk='1')then |
|
59 | elsif(clk' event and clk='1')then | |
63 |
|
60 | |||
64 | case ect is |
|
61 | case ect is | |
65 |
|
62 | |||
66 | when e0 => |
|
63 | when e0 => | |
67 | -- if(Full(FifoCpt) = '1')then |
|
|||
68 | if(Valid = '1')then |
|
64 | if(Valid = '1')then | |
69 |
Pong |
|
65 | Pong <= not Pong; | |
70 | ect <= e1; |
|
66 | ect <= e1; | |
71 | end if; |
|
67 | end if; | |
72 |
|
68 | |||
73 | when e1 => |
|
69 | when e1 => | |
74 |
if(Ac |
|
70 | if(Ack = '0')then | |
75 | Error <= '1'; |
|
71 | Error <= '1'; | |
76 | ect <= e1; |
|
72 | ect <= e1; | |
77 | else |
|
73 | else | |
78 | Error <= '0'; |
|
74 | Error <= '0'; | |
79 | ect <= e0; |
|
75 | ect <= e0; | |
80 | end if; |
|
76 | end if; | |
81 |
|
77 | |||
82 | when others => |
|
78 | when others => | |
83 |
null; |
|
79 | null; | |
84 |
|
80 | |||
85 | end case; |
|
81 | end case; | |
86 |
|
82 | |||
87 | end if; |
|
83 | end if; | |
88 | end process; |
|
84 | end process; | |
89 |
|
85 | |||
90 | FifoData <= Data & Data; |
|
86 | FifoData <= Data & Data; | |
91 | Pong <= Pong_int; |
|
87 | FifoWrite <= '1' & not Write when Pong='0' else not Write & '1'; | |
92 |
|
||||
93 | --FifoCpt <= 0 when Pong_int='0' else 1; |
|
|||
94 |
|
||||
95 | FifoWrite <= '1' & not Write when Pong_int='0' else not Write & '1'; |
|
|||
96 |
|
88 | |||
97 | end architecture; No newline at end of file |
|
89 | end architecture; |
@@ -1,87 +1,85 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------ |
|
18 | ------------------------------------------------------------------------------ | |
19 | -- Author : Martin Morlot |
|
19 | -- Author : Martin Morlot | |
20 | -- Mail : martin.morlot@lpp.polytechnique.fr |
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |
21 | ------------------------------------------------------------------------------ |
|
21 | ------------------------------------------------------------------------------ | |
22 | library IEEE; |
|
22 | library IEEE; | |
23 | use IEEE.std_logic_1164.all; |
|
23 | use IEEE.std_logic_1164.all; | |
24 | use IEEE.numeric_std.all; |
|
24 | use IEEE.numeric_std.all; | |
25 | library lpp; |
|
25 | library lpp; | |
26 | use lpp.lpp_matrix.all; |
|
26 | use lpp.lpp_matrix.all; | |
27 |
|
27 | |||
28 | entity MatriceSpectrale is |
|
28 | entity MatriceSpectrale is | |
29 | generic( |
|
29 | generic( | |
30 | Input_SZ : integer := 16; |
|
30 | Input_SZ : integer := 16; | |
31 | Result_SZ : integer := 32); |
|
31 | Result_SZ : integer := 32); | |
32 | port( |
|
32 | port( | |
33 | clkm : in std_logic; |
|
33 | clkm : in std_logic; | |
34 | rstn : in std_logic; |
|
34 | rstn : in std_logic; | |
35 |
|
35 | |||
36 | FifoIN_Full : in std_logic_vector(4 downto 0); |
|
36 | FifoIN_Full : in std_logic_vector(4 downto 0); | |
37 | SetReUse : in std_logic_vector(4 downto 0); |
|
37 | SetReUse : in std_logic_vector(4 downto 0); | |
38 | -- FifoOUT_Full : in std_logic_vector(1 downto 0); |
|
|||
39 | Valid : in std_logic; |
|
38 | Valid : in std_logic; | |
40 | Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0); |
|
39 | Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0); | |
41 |
AC |
|
40 | ACK : in std_logic; | |
42 | SM_Write : out std_logic; |
|
41 | SM_Write : out std_logic; | |
43 | FlagError : out std_logic; |
|
42 | FlagError : out std_logic; | |
44 | Pong : out std_logic; |
|
|||
45 | Statu : out std_logic_vector(3 downto 0); |
|
43 | Statu : out std_logic_vector(3 downto 0); | |
46 | Write : out std_logic_vector(1 downto 0); |
|
44 | Write : out std_logic_vector(1 downto 0); | |
47 | Read : out std_logic_vector(4 downto 0); |
|
45 | Read : out std_logic_vector(4 downto 0); | |
48 | ReUse : out std_logic_vector(4 downto 0); |
|
46 | ReUse : out std_logic_vector(4 downto 0); | |
49 | Data_OUT : out std_logic_vector((2*Result_SZ)-1 downto 0) |
|
47 | Data_OUT : out std_logic_vector((2*Result_SZ)-1 downto 0) | |
50 | ); |
|
48 | ); | |
51 | end entity; |
|
49 | end entity; | |
52 |
|
50 | |||
53 |
|
51 | |||
54 | architecture ar_MatriceSpectrale of MatriceSpectrale is |
|
52 | architecture ar_MatriceSpectrale of MatriceSpectrale is | |
55 |
|
53 | |||
56 | signal Matrix_Write : std_logic; |
|
54 | signal Matrix_Write : std_logic; | |
57 | signal Matrix_Read : std_logic_vector(1 downto 0); |
|
55 | signal Matrix_Read : std_logic_vector(1 downto 0); | |
58 | signal Matrix_Result : std_logic_vector(31 downto 0); |
|
56 | signal Matrix_Result : std_logic_vector(31 downto 0); | |
59 |
|
57 | |||
60 | signal TopSM_Start : std_logic; |
|
58 | signal TopSM_Start : std_logic; | |
61 | signal TopSM_Statu : std_logic_vector(3 downto 0); |
|
59 | signal TopSM_Statu : std_logic_vector(3 downto 0); | |
62 | signal TopSM_Data1 : std_logic_vector(15 downto 0); |
|
60 | signal TopSM_Data1 : std_logic_vector(15 downto 0); | |
63 | signal TopSM_Data2 : std_logic_vector(15 downto 0); |
|
61 | signal TopSM_Data2 : std_logic_vector(15 downto 0); | |
64 |
|
62 | |||
65 | begin |
|
63 | begin | |
66 |
|
64 | |||
67 | CTRL0 : ReUse_CTRLR |
|
65 | CTRL0 : ReUse_CTRLR | |
68 | port map(clkm,rstn,SetReUse,TopSM_Statu,ReUse); |
|
66 | port map(clkm,rstn,SetReUse,TopSM_Statu,ReUse); | |
69 |
|
67 | |||
70 |
|
68 | |||
71 | TopSM : TopSpecMatrix |
|
69 | TopSM : TopSpecMatrix | |
72 | generic map (Input_SZ) |
|
70 | generic map (Input_SZ) | |
73 | port map(clkm,rstn,Matrix_Write,Matrix_Read,FifoIN_Full,Data_IN,TopSM_Start,Read,TopSM_Statu,TopSM_Data1,TopSM_Data2); |
|
71 | port map(clkm,rstn,Matrix_Write,Matrix_Read,FifoIN_Full,Data_IN,TopSM_Start,Read,TopSM_Statu,TopSM_Data1,TopSM_Data2); | |
74 |
|
72 | |||
75 | SM : SpectralMatrix |
|
73 | SM : SpectralMatrix | |
76 | generic map (Input_SZ,Result_SZ) |
|
74 | generic map (Input_SZ,Result_SZ) | |
77 | port map(clkm,rstn,TopSM_Start,TopSM_Data1,TopSM_Data2,TopSM_Statu,Matrix_Read,Matrix_Write,Matrix_Result); |
|
75 | port map(clkm,rstn,TopSM_Start,TopSM_Data1,TopSM_Data2,TopSM_Statu,Matrix_Read,Matrix_Write,Matrix_Result); | |
78 |
|
76 | |||
79 | DISP : Dispatch |
|
77 | DISP : Dispatch | |
80 | generic map(Result_SZ) |
|
78 | generic map(Result_SZ) | |
81 |
port map(clkm,rstn,AC |
|
79 | port map(clkm,rstn,ACK,Matrix_Result,Matrix_Write,Valid,Data_OUT,Write,FlagError); | |
82 |
|
80 | |||
83 | Statu <= TopSM_Statu; |
|
81 | Statu <= TopSM_Statu; | |
84 | SM_Write <= Matrix_Write; |
|
82 | SM_Write <= Matrix_Write; | |
85 |
|
83 | |||
86 | end architecture; |
|
84 | end architecture; | |
87 |
|
85 |
@@ -1,269 +1,265 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------ |
|
18 | ------------------------------------------------------------------------------ | |
19 | -- Author : Martin Morlot |
|
19 | -- Author : Martin Morlot | |
20 | -- Mail : martin.morlot@lpp.polytechnique.fr |
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |
21 | ------------------------------------------------------------------------------ |
|
21 | ------------------------------------------------------------------------------ | |
22 | library ieee; |
|
22 | library ieee; | |
23 | use ieee.std_logic_1164.all; |
|
23 | use ieee.std_logic_1164.all; | |
24 | library grlib; |
|
24 | library grlib; | |
25 | use grlib.amba.all; |
|
25 | use grlib.amba.all; | |
26 | use std.textio.all; |
|
26 | use std.textio.all; | |
27 | library lpp; |
|
27 | library lpp; | |
28 | use lpp.lpp_amba.all; |
|
28 | use lpp.lpp_amba.all; | |
29 |
|
29 | |||
30 | --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on |
|
30 | --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on | |
31 |
|
31 | |||
32 | package lpp_matrix is |
|
32 | package lpp_matrix is | |
33 |
|
33 | |||
34 | component APB_Matrix is |
|
34 | component APB_Matrix is | |
35 | generic ( |
|
35 | generic ( | |
36 | pindex : integer := 0; |
|
36 | pindex : integer := 0; | |
37 | paddr : integer := 0; |
|
37 | paddr : integer := 0; | |
38 | pmask : integer := 16#fff#; |
|
38 | pmask : integer := 16#fff#; | |
39 | pirq : integer := 0; |
|
39 | pirq : integer := 0; | |
40 | abits : integer := 8; |
|
40 | abits : integer := 8; | |
41 | Input_SZ : integer := 16; |
|
41 | Input_SZ : integer := 16; | |
42 | Result_SZ : integer := 32); |
|
42 | Result_SZ : integer := 32); | |
43 | port ( |
|
43 | port ( | |
44 | clk : in std_logic; |
|
44 | clk : in std_logic; | |
45 | rst : in std_logic; |
|
45 | rst : in std_logic; | |
46 | FIFO1 : in std_logic_vector(Input_SZ-1 downto 0); |
|
46 | FIFO1 : in std_logic_vector(Input_SZ-1 downto 0); | |
47 | FIFO2 : in std_logic_vector(Input_SZ-1 downto 0); |
|
47 | FIFO2 : in std_logic_vector(Input_SZ-1 downto 0); | |
48 | Full : in std_logic_vector(1 downto 0); |
|
48 | Full : in std_logic_vector(1 downto 0); | |
49 | Empty : in std_logic_vector(1 downto 0); |
|
49 | Empty : in std_logic_vector(1 downto 0); | |
50 | ReadFIFO : out std_logic_vector(1 downto 0); |
|
50 | ReadFIFO : out std_logic_vector(1 downto 0); | |
51 | FullFIFO : in std_logic; |
|
51 | FullFIFO : in std_logic; | |
52 | WriteFIFO : out std_logic; |
|
52 | WriteFIFO : out std_logic; | |
53 | Result : out std_logic_vector(Result_SZ-1 downto 0); |
|
53 | Result : out std_logic_vector(Result_SZ-1 downto 0); | |
54 | apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus |
|
54 | apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus | |
55 | apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus |
|
55 | apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus | |
56 | ); |
|
56 | ); | |
57 | end component; |
|
57 | end component; | |
58 |
|
58 | |||
59 | component MatriceSpectrale is |
|
59 | component MatriceSpectrale is | |
60 | generic( |
|
60 | generic( | |
61 | Input_SZ : integer := 16; |
|
61 | Input_SZ : integer := 16; | |
62 | Result_SZ : integer := 32); |
|
62 | Result_SZ : integer := 32); | |
63 | port( |
|
63 | port( | |
64 | clkm : in std_logic; |
|
64 | clkm : in std_logic; | |
65 | rstn : in std_logic; |
|
65 | rstn : in std_logic; | |
66 |
|
66 | |||
67 | FifoIN_Full : in std_logic_vector(4 downto 0); |
|
67 | FifoIN_Full : in std_logic_vector(4 downto 0); | |
68 | SetReUse : in std_logic_vector(4 downto 0); |
|
68 | SetReUse : in std_logic_vector(4 downto 0); | |
69 | -- FifoOUT_Full : in std_logic_vector(1 downto 0); |
|
|||
70 | Valid : in std_logic; |
|
69 | Valid : in std_logic; | |
71 | Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0); |
|
70 | Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0); | |
72 |
AC |
|
71 | ACK : in std_logic; | |
73 | SM_Write : out std_logic; |
|
72 | SM_Write : out std_logic; | |
74 | FlagError : out std_logic; |
|
73 | FlagError : out std_logic; | |
75 | Pong : out std_logic; |
|
|||
76 | Statu : out std_logic_vector(3 downto 0); |
|
74 | Statu : out std_logic_vector(3 downto 0); | |
77 | Write : out std_logic_vector(1 downto 0); |
|
75 | Write : out std_logic_vector(1 downto 0); | |
78 | Read : out std_logic_vector(4 downto 0); |
|
76 | Read : out std_logic_vector(4 downto 0); | |
79 | ReUse : out std_logic_vector(4 downto 0); |
|
77 | ReUse : out std_logic_vector(4 downto 0); | |
80 | Data_OUT : out std_logic_vector((2*Result_SZ)-1 downto 0) |
|
78 | Data_OUT : out std_logic_vector((2*Result_SZ)-1 downto 0) | |
81 | ); |
|
79 | ); | |
82 | end component; |
|
80 | end component; | |
83 |
|
81 | |||
84 |
|
82 | |||
85 | component TopSpecMatrix is |
|
83 | component TopSpecMatrix is | |
86 | generic( |
|
84 | generic( | |
87 | Input_SZ : integer := 16); |
|
85 | Input_SZ : integer := 16); | |
88 | port( |
|
86 | port( | |
89 | clk : in std_logic; |
|
87 | clk : in std_logic; | |
90 | rstn : in std_logic; |
|
88 | rstn : in std_logic; | |
91 | Write : in std_logic; |
|
89 | Write : in std_logic; | |
92 | ReadIn : in std_logic_vector(1 downto 0); |
|
90 | ReadIn : in std_logic_vector(1 downto 0); | |
93 | Full : in std_logic_vector(4 downto 0); |
|
91 | Full : in std_logic_vector(4 downto 0); | |
94 | Data : in std_logic_vector((5*Input_SZ)-1 downto 0); |
|
92 | Data : in std_logic_vector((5*Input_SZ)-1 downto 0); | |
95 | Start : out std_logic; |
|
93 | Start : out std_logic; | |
96 | ReadOut : out std_logic_vector(4 downto 0); |
|
94 | ReadOut : out std_logic_vector(4 downto 0); | |
97 | Statu : out std_logic_vector(3 downto 0); |
|
95 | Statu : out std_logic_vector(3 downto 0); | |
98 | DATA1 : out std_logic_vector(Input_SZ-1 downto 0); |
|
96 | DATA1 : out std_logic_vector(Input_SZ-1 downto 0); | |
99 | DATA2 : out std_logic_vector(Input_SZ-1 downto 0) |
|
97 | DATA2 : out std_logic_vector(Input_SZ-1 downto 0) | |
100 | ); |
|
98 | ); | |
101 | end component; |
|
99 | end component; | |
102 |
|
100 | |||
103 |
|
101 | |||
104 | component Top_MatrixSpec is |
|
102 | component Top_MatrixSpec is | |
105 | generic( |
|
103 | generic( | |
106 | Input_SZ : integer := 16; |
|
104 | Input_SZ : integer := 16; | |
107 | Result_SZ : integer := 32); |
|
105 | Result_SZ : integer := 32); | |
108 | port( |
|
106 | port( | |
109 | clk : in std_logic; |
|
107 | clk : in std_logic; | |
110 | reset : in std_logic; |
|
108 | reset : in std_logic; | |
111 | Statu : in std_logic_vector(3 downto 0); |
|
109 | Statu : in std_logic_vector(3 downto 0); | |
112 | FIFO1 : in std_logic_vector(Input_SZ-1 downto 0); |
|
110 | FIFO1 : in std_logic_vector(Input_SZ-1 downto 0); | |
113 | FIFO2 : in std_logic_vector(Input_SZ-1 downto 0); |
|
111 | FIFO2 : in std_logic_vector(Input_SZ-1 downto 0); | |
114 | Full : in std_logic_vector(1 downto 0); |
|
112 | Full : in std_logic_vector(1 downto 0); | |
115 | Empty : in std_logic_vector(1 downto 0); |
|
113 | Empty : in std_logic_vector(1 downto 0); | |
116 | ReadFIFO : out std_logic_vector(1 downto 0); |
|
114 | ReadFIFO : out std_logic_vector(1 downto 0); | |
117 | FullFIFO : in std_logic; |
|
115 | FullFIFO : in std_logic; | |
118 | WriteFIFO : out std_logic; |
|
116 | WriteFIFO : out std_logic; | |
119 | Result : out std_logic_vector(Result_SZ-1 downto 0) |
|
117 | Result : out std_logic_vector(Result_SZ-1 downto 0) | |
120 | ); |
|
118 | ); | |
121 | end component; |
|
119 | end component; | |
122 |
|
120 | |||
123 | component SpectralMatrix is |
|
121 | component SpectralMatrix is | |
124 | generic( |
|
122 | generic( | |
125 | Input_SZ : integer := 16; |
|
123 | Input_SZ : integer := 16; | |
126 | Result_SZ : integer := 32); |
|
124 | Result_SZ : integer := 32); | |
127 | port( |
|
125 | port( | |
128 | clk : in std_logic; |
|
126 | clk : in std_logic; | |
129 | reset : in std_logic; |
|
127 | reset : in std_logic; | |
130 | Start : in std_logic; |
|
128 | Start : in std_logic; | |
131 | FIFO1 : in std_logic_vector(Input_SZ-1 downto 0); |
|
129 | FIFO1 : in std_logic_vector(Input_SZ-1 downto 0); | |
132 | FIFO2 : in std_logic_vector(Input_SZ-1 downto 0); |
|
130 | FIFO2 : in std_logic_vector(Input_SZ-1 downto 0); | |
133 | Statu : in std_logic_vector(3 downto 0); |
|
131 | Statu : in std_logic_vector(3 downto 0); | |
134 | -- FullFIFO : in std_logic; |
|
132 | -- FullFIFO : in std_logic; | |
135 | ReadFIFO : out std_logic_vector(1 downto 0); |
|
133 | ReadFIFO : out std_logic_vector(1 downto 0); | |
136 | WriteFIFO : out std_logic; |
|
134 | WriteFIFO : out std_logic; | |
137 | Result : out std_logic_vector(Result_SZ-1 downto 0) |
|
135 | Result : out std_logic_vector(Result_SZ-1 downto 0) | |
138 | ); |
|
136 | ); | |
139 | end component; |
|
137 | end component; | |
140 |
|
138 | |||
141 |
|
139 | |||
142 | component Matrix is |
|
140 | component Matrix is | |
143 | generic( |
|
141 | generic( | |
144 | Input_SZ : integer := 16); |
|
142 | Input_SZ : integer := 16); | |
145 | port( |
|
143 | port( | |
146 | clk : in std_logic; |
|
144 | clk : in std_logic; | |
147 | raz : in std_logic; |
|
145 | raz : in std_logic; | |
148 | IN1 : in std_logic_vector(Input_SZ-1 downto 0); |
|
146 | IN1 : in std_logic_vector(Input_SZ-1 downto 0); | |
149 | IN2 : in std_logic_vector(Input_SZ-1 downto 0); |
|
147 | IN2 : in std_logic_vector(Input_SZ-1 downto 0); | |
150 | Take : in std_logic; |
|
148 | Take : in std_logic; | |
151 | Received : in std_logic; |
|
149 | Received : in std_logic; | |
152 | Conjugate : in std_logic; |
|
150 | Conjugate : in std_logic; | |
153 | Valid : out std_logic; |
|
151 | Valid : out std_logic; | |
154 | Read : out std_logic; |
|
152 | Read : out std_logic; | |
155 | Result : out std_logic_vector(2*Input_SZ-1 downto 0) |
|
153 | Result : out std_logic_vector(2*Input_SZ-1 downto 0) | |
156 | ); |
|
154 | ); | |
157 | end component; |
|
155 | end component; | |
158 |
|
156 | |||
159 | component GetResult is |
|
157 | component GetResult is | |
160 | generic( |
|
158 | generic( | |
161 | Result_SZ : integer := 32); |
|
159 | Result_SZ : integer := 32); | |
162 | port( |
|
160 | port( | |
163 | clk : in std_logic; |
|
161 | clk : in std_logic; | |
164 | raz : in std_logic; |
|
162 | raz : in std_logic; | |
165 | Valid : in std_logic; |
|
163 | Valid : in std_logic; | |
166 | Conjugate : in std_logic; |
|
164 | Conjugate : in std_logic; | |
167 | Res : in std_logic_vector(Result_SZ-1 downto 0); |
|
165 | Res : in std_logic_vector(Result_SZ-1 downto 0); | |
168 | -- Full : in std_logic; |
|
166 | -- Full : in std_logic; | |
169 | WriteFIFO : out std_logic; |
|
167 | WriteFIFO : out std_logic; | |
170 | Received : out std_logic; |
|
168 | Received : out std_logic; | |
171 | Result : out std_logic_vector(Result_SZ-1 downto 0) |
|
169 | Result : out std_logic_vector(Result_SZ-1 downto 0) | |
172 | ); |
|
170 | ); | |
173 | end component; |
|
171 | end component; | |
174 |
|
172 | |||
175 |
|
173 | |||
176 | component TopMatrix_PDR is |
|
174 | component TopMatrix_PDR is | |
177 | generic( |
|
175 | generic( | |
178 | Input_SZ : integer := 16; |
|
176 | Input_SZ : integer := 16; | |
179 | Result_SZ : integer := 32); |
|
177 | Result_SZ : integer := 32); | |
180 | port( |
|
178 | port( | |
181 | clk : in std_logic; |
|
179 | clk : in std_logic; | |
182 | reset : in std_logic; |
|
180 | reset : in std_logic; | |
183 | Data : in std_logic_vector((5*Input_SZ)-1 downto 0); |
|
181 | Data : in std_logic_vector((5*Input_SZ)-1 downto 0); | |
184 | FULLin : in std_logic_vector(4 downto 0); |
|
182 | FULLin : in std_logic_vector(4 downto 0); | |
185 | READin : in std_logic_vector(1 downto 0); |
|
183 | READin : in std_logic_vector(1 downto 0); | |
186 | WRITEin : in std_logic; |
|
184 | WRITEin : in std_logic; | |
187 | FIFO1 : out std_logic_vector(Input_SZ-1 downto 0); |
|
185 | FIFO1 : out std_logic_vector(Input_SZ-1 downto 0); | |
188 | FIFO2 : out std_logic_vector(Input_SZ-1 downto 0); |
|
186 | FIFO2 : out std_logic_vector(Input_SZ-1 downto 0); | |
189 | Start : out std_logic; |
|
187 | Start : out std_logic; | |
190 | Read : out std_logic_vector(4 downto 0); |
|
188 | Read : out std_logic_vector(4 downto 0); | |
191 | Statu : out std_logic_vector(3 downto 0) |
|
189 | Statu : out std_logic_vector(3 downto 0) | |
192 | ); |
|
190 | ); | |
193 | end component; |
|
191 | end component; | |
194 |
|
192 | |||
195 |
|
193 | |||
196 | component Dispatch is |
|
194 | component Dispatch is | |
197 | generic( |
|
195 | generic( | |
198 | Data_SZ : integer := 32); |
|
196 | Data_SZ : integer := 32); | |
199 | port( |
|
197 | port( | |
200 | clk : in std_logic; |
|
198 | clk : in std_logic; | |
201 | reset : in std_logic; |
|
199 | reset : in std_logic; | |
202 |
Ac |
|
200 | Ack : in std_logic; | |
203 | Data : in std_logic_vector(Data_SZ-1 downto 0); |
|
201 | Data : in std_logic_vector(Data_SZ-1 downto 0); | |
204 | Write : in std_logic; |
|
202 | Write : in std_logic; | |
205 | Valid : in std_logic; |
|
203 | Valid : in std_logic; | |
206 | -- Full : in std_logic_vector(1 downto 0); |
|
|||
207 | FifoData : out std_logic_vector(2*Data_SZ-1 downto 0); |
|
204 | FifoData : out std_logic_vector(2*Data_SZ-1 downto 0); | |
208 | FifoWrite : out std_logic_vector(1 downto 0); |
|
205 | FifoWrite : out std_logic_vector(1 downto 0); | |
209 | Pong : out std_logic; |
|
|||
210 | Error : out std_logic |
|
206 | Error : out std_logic | |
211 | ); |
|
207 | ); | |
212 | end component; |
|
208 | end component; | |
213 |
|
209 | |||
214 |
|
210 | |||
215 | component DriveInputs is |
|
211 | component DriveInputs is | |
216 | port( |
|
212 | port( | |
217 | clk : in std_logic; |
|
213 | clk : in std_logic; | |
218 | raz : in std_logic; |
|
214 | raz : in std_logic; | |
219 | Read : in std_logic; |
|
215 | Read : in std_logic; | |
220 | Conjugate : in std_logic; |
|
216 | Conjugate : in std_logic; | |
221 | Take : out std_logic; |
|
217 | Take : out std_logic; | |
222 | ReadFIFO : out std_logic_vector(1 downto 0) |
|
218 | ReadFIFO : out std_logic_vector(1 downto 0) | |
223 | ); |
|
219 | ); | |
224 | end component; |
|
220 | end component; | |
225 |
|
221 | |||
226 | component Starter is |
|
222 | component Starter is | |
227 | port( |
|
223 | port( | |
228 | clk : in std_logic; |
|
224 | clk : in std_logic; | |
229 | raz : in std_logic; |
|
225 | raz : in std_logic; | |
230 | Full : in std_logic_vector(1 downto 0); |
|
226 | Full : in std_logic_vector(1 downto 0); | |
231 | Empty : in std_logic_vector(1 downto 0); |
|
227 | Empty : in std_logic_vector(1 downto 0); | |
232 | Statu : in std_logic_vector(3 downto 0); |
|
228 | Statu : in std_logic_vector(3 downto 0); | |
233 | Write : in std_logic; |
|
229 | Write : in std_logic; | |
234 | Start : out std_logic |
|
230 | Start : out std_logic | |
235 | ); |
|
231 | ); | |
236 | end component; |
|
232 | end component; | |
237 |
|
233 | |||
238 | component ALU_Driver is |
|
234 | component ALU_Driver is | |
239 | generic( |
|
235 | generic( | |
240 | Input_SZ_1 : integer := 16; |
|
236 | Input_SZ_1 : integer := 16; | |
241 | Input_SZ_2 : integer := 16); |
|
237 | Input_SZ_2 : integer := 16); | |
242 | port( |
|
238 | port( | |
243 | clk : in std_logic; |
|
239 | clk : in std_logic; | |
244 | reset : in std_logic; |
|
240 | reset : in std_logic; | |
245 | IN1 : in std_logic_vector(Input_SZ_1-1 downto 0); |
|
241 | IN1 : in std_logic_vector(Input_SZ_1-1 downto 0); | |
246 | IN2 : in std_logic_vector(Input_SZ_2-1 downto 0); |
|
242 | IN2 : in std_logic_vector(Input_SZ_2-1 downto 0); | |
247 | Take : in std_logic; |
|
243 | Take : in std_logic; | |
248 | Received : in std_logic; |
|
244 | Received : in std_logic; | |
249 | Conjugate : in std_logic; |
|
245 | Conjugate : in std_logic; | |
250 | Valid : out std_logic; |
|
246 | Valid : out std_logic; | |
251 | Read : out std_logic; |
|
247 | Read : out std_logic; | |
252 | CTRL : out std_logic_vector(2 downto 0); |
|
248 | CTRL : out std_logic_vector(2 downto 0); | |
253 | COMP : out std_logic_vector(1 downto 0); |
|
249 | COMP : out std_logic_vector(1 downto 0); | |
254 | OP1 : out std_logic_vector(Input_SZ_1-1 downto 0); |
|
250 | OP1 : out std_logic_vector(Input_SZ_1-1 downto 0); | |
255 | OP2 : out std_logic_vector(Input_SZ_2-1 downto 0) |
|
251 | OP2 : out std_logic_vector(Input_SZ_2-1 downto 0) | |
256 | ); |
|
252 | ); | |
257 | end component; |
|
253 | end component; | |
258 |
|
254 | |||
259 | component ReUse_CTRLR is |
|
255 | component ReUse_CTRLR is | |
260 | port( |
|
256 | port( | |
261 | clk : in std_logic; |
|
257 | clk : in std_logic; | |
262 | reset : in std_logic; |
|
258 | reset : in std_logic; | |
263 | SetReUse : in std_logic_vector(4 downto 0); |
|
259 | SetReUse : in std_logic_vector(4 downto 0); | |
264 | Statu : in std_logic_vector(3 downto 0); |
|
260 | Statu : in std_logic_vector(3 downto 0); | |
265 | ReUse : out std_logic_vector(4 downto 0) |
|
261 | ReUse : out std_logic_vector(4 downto 0) | |
266 | ); |
|
262 | ); | |
267 | end component; |
|
263 | end component; | |
268 |
|
264 | |||
269 | end; No newline at end of file |
|
265 | end; |
@@ -1,66 +1,65 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------ |
|
18 | ------------------------------------------------------------------------------ | |
19 | -- Author : Martin Morlot |
|
19 | -- Author : Martin Morlot | |
20 | -- Mail : martin.morlot@lpp.polytechnique.fr |
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |
21 | ------------------------------------------------------------------------------ |
|
21 | ------------------------------------------------------------------------------ | |
22 | library IEEE; |
|
22 | library IEEE; | |
23 | use IEEE.std_logic_1164.all; |
|
23 | use IEEE.std_logic_1164.all; | |
24 | use IEEE.numeric_std.all; |
|
24 | use IEEE.numeric_std.all; | |
25 | library lpp; |
|
25 | library lpp; | |
26 | use lpp.lpp_memory.all; |
|
26 | use lpp.lpp_memory.all; | |
27 | use lpp.iir_filter.all; |
|
27 | use lpp.iir_filter.all; | |
28 | library techmap; |
|
28 | library techmap; | |
29 | use techmap.gencomp.all; |
|
29 | use techmap.gencomp.all; | |
30 |
|
30 | |||
31 | entity lppFIFOxN is |
|
31 | entity lppFIFOxN is | |
32 | generic( |
|
32 | generic( | |
33 | tech : integer := 0; |
|
33 | tech : integer := 0; | |
34 | Mem_use : integer := use_RAM; |
|
34 | Mem_use : integer := use_RAM; | |
35 | Data_sz : integer range 1 to 32 := 8; |
|
35 | Data_sz : integer range 1 to 32 := 8; | |
36 |
Addr_sz : integer range |
|
36 | Addr_sz : integer range 2 to 12 := 8; | |
37 | FifoCnt : integer := 1; |
|
37 | FifoCnt : integer := 1; | |
38 | Enable_ReUse : std_logic := '0' |
|
38 | Enable_ReUse : std_logic := '0' | |
39 | ); |
|
39 | ); | |
40 | port( |
|
40 | port( | |
41 | rst : in std_logic; |
|
41 | rstn : in std_logic; | |
42 | wclk : in std_logic; |
|
42 | wclk : in std_logic; | |
43 | rclk : in std_logic; |
|
43 | rclk : in std_logic; | |
44 | ReUse : in std_logic_vector(FifoCnt-1 downto 0); |
|
44 | ReUse : in std_logic_vector(FifoCnt-1 downto 0); | |
45 | wen : in std_logic_vector(FifoCnt-1 downto 0); |
|
45 | wen : in std_logic_vector(FifoCnt-1 downto 0); | |
46 | ren : in std_logic_vector(FifoCnt-1 downto 0); |
|
46 | ren : in std_logic_vector(FifoCnt-1 downto 0); | |
47 | wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); |
|
47 | wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); | |
48 | rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); |
|
48 | rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); | |
49 | full : out std_logic_vector(FifoCnt-1 downto 0); |
|
49 | full : out std_logic_vector(FifoCnt-1 downto 0); | |
50 | empty : out std_logic_vector(FifoCnt-1 downto 0) |
|
50 | empty : out std_logic_vector(FifoCnt-1 downto 0) | |
51 | ); |
|
51 | ); | |
52 | end entity; |
|
52 | end entity; | |
53 |
|
53 | |||
54 |
|
54 | |||
55 | architecture ar_lppFIFOxN of lppFIFOxN is |
|
55 | architecture ar_lppFIFOxN of lppFIFOxN is | |
56 |
|
56 | |||
57 | begin |
|
57 | begin | |
58 |
|
58 | |||
59 | fifos: for i in 0 to FifoCnt-1 generate |
|
59 | fifos: for i in 0 to FifoCnt-1 generate | |
60 | FIFO0 : lpp_fifo |
|
60 | FIFO0 : lpp_fifo | |
61 | generic map (tech,Mem_use,Enable_ReUse,Data_sz,Addr_sz) |
|
61 | generic map (tech,Mem_use,Enable_ReUse,Data_sz,Addr_sz) | |
62 | port map(rst,ReUse(i),rclk,ren(i),rdata((i+1)*Data_sz-1 downto i*Data_sz),empty(i),open,wclk,wen(i),wdata((i+1)*Data_sz-1 downto i*Data_sz),full(i),open); |
|
62 | port map(rstn,ReUse(i),rclk,ren(i),rdata((i+1)*Data_sz-1 downto i*Data_sz),empty(i),open,wclk,wen(i),wdata((i+1)*Data_sz-1 downto i*Data_sz),full(i),open); | |
63 | end generate; |
|
63 | end generate; | |
64 |
|
64 | |||
65 | end architecture; |
|
65 | end architecture; | |
66 |
|
@@ -1,180 +1,179 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------ |
|
18 | ------------------------------------------------------------------------------ | |
19 | -- Author : Martin Morlot |
|
19 | -- Author : Martin Morlot | |
20 | -- Mail : martin.morlot@lpp.polytechnique.fr |
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |
21 | ------------------------------------------------------------------------------ |
|
21 | ------------------------------------------------------------------------------ | |
22 | library IEEE; |
|
22 | library IEEE; | |
23 | use IEEE.std_logic_1164.all; |
|
23 | use IEEE.std_logic_1164.all; | |
24 | use IEEE.numeric_std.all; |
|
24 | use IEEE.numeric_std.all; | |
25 | library lpp; |
|
25 | library lpp; | |
26 | use lpp.lpp_memory.all; |
|
26 | use lpp.lpp_memory.all; | |
27 | use lpp.iir_filter.all; |
|
27 | use lpp.iir_filter.all; | |
28 | library techmap; |
|
28 | library techmap; | |
29 | use techmap.gencomp.all; |
|
29 | use techmap.gencomp.all; | |
30 |
|
30 | |||
31 | entity lpp_fifo is |
|
31 | entity lpp_fifo is | |
32 | generic( |
|
32 | generic( | |
33 | tech : integer := 0; |
|
33 | tech : integer := 0; | |
34 | Mem_use : integer := use_RAM; |
|
34 | Mem_use : integer := use_RAM; | |
35 | Enable_ReUse : std_logic := '0'; |
|
35 | Enable_ReUse : std_logic := '0'; | |
36 | DataSz : integer range 1 to 32 := 8; |
|
36 | DataSz : integer range 1 to 32 := 8; | |
37 |
|
|
37 | AddrSz : integer range 2 to 12 := 8 | |
38 | ); |
|
38 | ); | |
39 | port( |
|
39 | port( | |
40 | rstn : in std_logic; |
|
40 | rstn : in std_logic; | |
41 | ReUse : in std_logic; |
|
41 | ReUse : in std_logic; | |
42 | rclk : in std_logic; |
|
42 | rclk : in std_logic; | |
43 | ren : in std_logic; |
|
43 | ren : in std_logic; | |
44 | rdata : out std_logic_vector(DataSz-1 downto 0); |
|
44 | rdata : out std_logic_vector(DataSz-1 downto 0); | |
45 | empty : out std_logic; |
|
45 | empty : out std_logic; | |
46 |
raddr : out std_logic_vector( |
|
46 | raddr : out std_logic_vector(AddrSz-1 downto 0); | |
47 | wclk : in std_logic; |
|
47 | wclk : in std_logic; | |
48 | wen : in std_logic; |
|
48 | wen : in std_logic; | |
49 | wdata : in std_logic_vector(DataSz-1 downto 0); |
|
49 | wdata : in std_logic_vector(DataSz-1 downto 0); | |
50 | full : out std_logic; |
|
50 | full : out std_logic; | |
51 |
waddr : out std_logic_vector( |
|
51 | waddr : out std_logic_vector(AddrSz-1 downto 0) | |
52 | ); |
|
52 | ); | |
53 | end entity; |
|
53 | end entity; | |
54 |
|
54 | |||
55 |
|
55 | |||
56 | architecture ar_lpp_fifo of lpp_fifo is |
|
56 | architecture ar_lpp_fifo of lpp_fifo is | |
57 |
|
57 | |||
58 | signal sFull : std_logic; |
|
58 | signal sFull : std_logic; | |
59 | signal sFull_s : std_logic; |
|
59 | signal sFull_s : std_logic; | |
60 | signal sEmpty_s : std_logic; |
|
60 | signal sEmpty_s : std_logic; | |
61 |
|
61 | |||
62 | signal sEmpty : std_logic; |
|
62 | signal sEmpty : std_logic; | |
63 | signal sREN : std_logic; |
|
63 | signal sREN : std_logic; | |
64 | signal sWEN : std_logic; |
|
64 | signal sWEN : std_logic; | |
65 | signal sRE : std_logic; |
|
65 | signal sRE : std_logic; | |
66 | signal sWE : std_logic; |
|
66 | signal sWE : std_logic; | |
67 |
|
67 | |||
68 |
signal Waddr_vect : std_logic_vector( |
|
68 | signal Waddr_vect : std_logic_vector(AddrSz-1 downto 0):=(others =>'0'); | |
69 |
signal Raddr_vect : std_logic_vector( |
|
69 | signal Raddr_vect : std_logic_vector(AddrSz-1 downto 0):=(others =>'0'); | |
70 |
signal Waddr_vect_s : std_logic_vector( |
|
70 | signal Waddr_vect_s : std_logic_vector(AddrSz-1 downto 0):=(others =>'0'); | |
71 |
signal Raddr_vect_s : std_logic_vector( |
|
71 | signal Raddr_vect_s : std_logic_vector(AddrSz-1 downto 0):=(others =>'0'); | |
72 |
|
72 | |||
73 | begin |
|
73 | begin | |
74 |
|
74 | |||
75 | --================================================================================== |
|
75 | --================================================================================== | |
76 | -- /!\ syncram_2p Write et Read actif a l'οΏ½tat haut /!\ |
|
76 | -- /!\ syncram_2p Write et Read actif a l'οΏ½tat haut /!\ | |
77 | -- A l'inverse de RAM_CEL !!! |
|
77 | -- A l'inverse de RAM_CEL !!! | |
78 | --================================================================================== |
|
78 | --================================================================================== | |
79 | memRAM : IF Mem_use = use_RAM GENERATE |
|
79 | memRAM : IF Mem_use = use_RAM GENERATE | |
80 | SRAM : syncram_2p |
|
80 | SRAM : syncram_2p | |
81 |
generic map(tech, |
|
81 | generic map(tech,AddrSz,DataSz) | |
82 | port map(RCLK,sRE,Raddr_vect,rdata,WCLK,sWE,Waddr_vect,wdata); |
|
82 | port map(RCLK,sRE,Raddr_vect,rdata,WCLK,sWE,Waddr_vect,wdata); | |
83 | END GENERATE; |
|
83 | END GENERATE; | |
84 | --================================================================================== |
|
84 | --================================================================================== | |
85 | memCEL : IF Mem_use = use_CEL GENERATE |
|
85 | memCEL : IF Mem_use = use_CEL GENERATE | |
86 | CRAM : RAM_CEL |
|
86 | CRAM : RAM_CEL | |
87 |
generic map(DataSz, |
|
87 | generic map(DataSz,AddrSz) | |
88 | port map(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, WCLK, rstn); |
|
88 | port map(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, WCLK, rstn); | |
89 | END GENERATE; |
|
89 | END GENERATE; | |
90 | --================================================================================== |
|
90 | --================================================================================== | |
91 |
|
91 | |||
92 | --============================= |
|
92 | --============================= | |
93 | -- Read section |
|
93 | -- Read section | |
94 | --============================= |
|
94 | --============================= | |
95 | sREN <= REN or sEmpty; |
|
95 | sREN <= REN or sEmpty; | |
96 | sRE <= not sREN; |
|
96 | sRE <= not sREN; | |
97 |
|
97 | |||
98 | sEmpty_s <= '0' when ReUse = '1' and Enable_ReUse='1' else |
|
98 | sEmpty_s <= '0' when ReUse = '1' and Enable_ReUse='1' else | |
99 | '1' when sEmpty = '1' and Wen = '1' else |
|
99 | '1' when sEmpty = '1' and Wen = '1' else | |
100 | '1' when sEmpty = '0' and (Wen = '1' and Ren = '0' and Raddr_vect_s = Waddr_vect) else |
|
100 | '1' when sEmpty = '0' and (Wen = '1' and Ren = '0' and Raddr_vect_s = Waddr_vect) else | |
101 | '0'; |
|
101 | '0'; | |
102 |
|
102 | |||
103 | Raddr_vect_s <= std_logic_vector(unsigned(Raddr_vect) +1); |
|
103 | Raddr_vect_s <= std_logic_vector(unsigned(Raddr_vect) +1); | |
104 |
|
104 | |||
105 | process (rclk,rstn) |
|
105 | process (rclk,rstn) | |
106 | begin |
|
106 | begin | |
107 | if(rstn='0')then |
|
107 | if(rstn='0')then | |
108 | Raddr_vect <= (others =>'0'); |
|
108 | Raddr_vect <= (others =>'0'); | |
109 | sempty <= '1'; |
|
109 | sempty <= '1'; | |
110 | elsif(rclk'event and rclk='1')then |
|
110 | elsif(rclk'event and rclk='1')then | |
111 | sEmpty <= sempty_s; |
|
111 | sEmpty <= sempty_s; | |
112 |
|
112 | |||
113 | if(sREN='0' and sempty = '0')then |
|
113 | if(sREN='0' and sempty = '0')then | |
114 | Raddr_vect <= Raddr_vect_s; |
|
114 | Raddr_vect <= Raddr_vect_s; | |
115 | end if; |
|
115 | end if; | |
116 |
|
116 | |||
117 | end if; |
|
117 | end if; | |
118 | end process; |
|
118 | end process; | |
119 |
|
119 | |||
120 | --============================= |
|
120 | --============================= | |
121 | -- Write section |
|
121 | -- Write section | |
122 | --============================= |
|
122 | --============================= | |
123 | sWEN <= WEN or sFull; |
|
123 | sWEN <= WEN or sFull; | |
124 | sWE <= not sWEN; |
|
124 | sWE <= not sWEN; | |
125 |
|
125 | |||
126 | sFull_s <= '1' when ReUse = '1' and Enable_ReUse='1' else |
|
126 | sFull_s <= '1' when ReUse = '1' and Enable_ReUse='1' else | |
127 | '1' when Waddr_vect_s = Raddr_vect and REN = '1' and WEN = '0' else |
|
127 | '1' when Waddr_vect_s = Raddr_vect and REN = '1' and WEN = '0' else | |
128 | '1' when sFull = '1' and REN = '1' else |
|
128 | '1' when sFull = '1' and REN = '1' else | |
129 | '0'; |
|
129 | '0'; | |
130 |
|
130 | |||
131 | Waddr_vect_s <= std_logic_vector(unsigned(Waddr_vect) +1); |
|
131 | Waddr_vect_s <= std_logic_vector(unsigned(Waddr_vect) +1); | |
132 |
|
132 | |||
133 | process (wclk,rstn) |
|
133 | process (wclk,rstn) | |
134 | begin |
|
134 | begin | |
135 | if(rstn='0')then |
|
135 | if(rstn='0')then | |
136 | Waddr_vect <= (others =>'0'); |
|
136 | Waddr_vect <= (others =>'0'); | |
137 | sfull <= '0'; |
|
137 | sfull <= '0'; | |
138 | elsif(wclk'event and wclk='1')then |
|
138 | elsif(wclk'event and wclk='1')then | |
139 | sfull <= sfull_s; |
|
139 | sfull <= sfull_s; | |
140 |
|
140 | |||
141 | if(sWEN='0' and sfull='0')then |
|
141 | if(sWEN='0' and sfull='0')then | |
142 | Waddr_vect <= Waddr_vect_s; |
|
142 | Waddr_vect <= Waddr_vect_s; | |
143 | end if; |
|
143 | end if; | |
144 |
|
144 | |||
145 | end if; |
|
145 | end if; | |
146 | end process; |
|
146 | end process; | |
147 |
|
147 | |||
148 |
|
148 | |||
149 | full <= sFull_s; |
|
149 | full <= sFull_s; | |
150 | empty <= sEmpty_s; |
|
150 | empty <= sEmpty_s; | |
151 | waddr <= Waddr_vect; |
|
151 | waddr <= Waddr_vect; | |
152 | raddr <= Raddr_vect; |
|
152 | raddr <= Raddr_vect; | |
153 |
|
153 | |||
154 | end architecture; |
|
154 | end architecture; | |
155 |
|
155 | |||
156 |
|
156 | |||
157 |
|
157 | |||
158 |
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158 | |||
159 |
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159 | |||
160 |
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160 | |||
161 |
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161 | |||
162 |
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162 | |||
163 |
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163 | |||
164 |
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164 | |||
165 |
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165 | |||
166 |
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166 | |||
167 |
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167 | |||
168 |
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168 | |||
169 |
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169 | |||
170 |
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170 | |||
171 |
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171 | |||
172 |
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172 | |||
173 |
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173 | |||
174 |
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174 | |||
175 |
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175 | |||
176 |
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177 |
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178 |
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179 |
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179 | |||
180 |
|
@@ -1,163 +1,163 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------ |
|
18 | ------------------------------------------------------------------------------ | |
19 | -- Author : Martin Morlot |
|
19 | -- Author : Martin Morlot | |
20 | -- Mail : martin.morlot@lpp.polytechnique.fr |
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |
21 | ------------------------------------------------------------------------------ |
|
21 | ------------------------------------------------------------------------------ | |
22 | library ieee; |
|
22 | library ieee; | |
23 | use ieee.std_logic_1164.all; |
|
23 | use ieee.std_logic_1164.all; | |
24 | library grlib; |
|
24 | library grlib; | |
25 | use grlib.amba.all; |
|
25 | use grlib.amba.all; | |
26 | use std.textio.all; |
|
26 | use std.textio.all; | |
27 | library lpp; |
|
27 | library lpp; | |
28 | use lpp.lpp_amba.all; |
|
28 | use lpp.lpp_amba.all; | |
29 | use lpp.iir_filter.all; |
|
29 | use lpp.iir_filter.all; | |
30 | library gaisler; |
|
30 | library gaisler; | |
31 | use gaisler.misc.all; |
|
31 | use gaisler.misc.all; | |
32 | use gaisler.memctrl.all; |
|
32 | use gaisler.memctrl.all; | |
33 | library techmap; |
|
33 | library techmap; | |
34 | use techmap.gencomp.all; |
|
34 | use techmap.gencomp.all; | |
35 |
|
35 | |||
36 | --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on |
|
36 | --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on | |
37 |
|
37 | |||
38 | package lpp_memory is |
|
38 | package lpp_memory is | |
39 |
|
39 | |||
40 | component APB_FIFO is |
|
40 | component APB_FIFO is | |
41 | generic ( |
|
41 | generic ( | |
42 | tech : integer := apa3; |
|
42 | tech : integer := apa3; | |
43 | pindex : integer := 0; |
|
43 | pindex : integer := 0; | |
44 | paddr : integer := 0; |
|
44 | paddr : integer := 0; | |
45 | pmask : integer := 16#fff#; |
|
45 | pmask : integer := 16#fff#; | |
46 | pirq : integer := 0; |
|
46 | pirq : integer := 0; | |
47 | abits : integer := 8; |
|
47 | abits : integer := 8; | |
48 | FifoCnt : integer := 2; |
|
48 | FifoCnt : integer := 2; | |
49 | Data_sz : integer := 16; |
|
49 | Data_sz : integer := 16; | |
50 | Addr_sz : integer := 9; |
|
50 | Addr_sz : integer := 9; | |
51 | Enable_ReUse : std_logic := '0'; |
|
51 | Enable_ReUse : std_logic := '0'; | |
52 | Mem_use : integer := use_RAM; |
|
52 | Mem_use : integer := use_RAM; | |
53 | R : integer := 1; |
|
53 | R : integer := 1; | |
54 | W : integer := 1 |
|
54 | W : integer := 1 | |
55 | ); |
|
55 | ); | |
56 | port ( |
|
56 | port ( | |
57 | clk : in std_logic; --! Horloge du composant |
|
57 | clk : in std_logic; --! Horloge du composant | |
58 | rst : in std_logic; --! Reset general du composant |
|
58 | rst : in std_logic; --! Reset general du composant | |
59 | rclk : in std_logic; |
|
59 | rclk : in std_logic; | |
60 | wclk : in std_logic; |
|
60 | wclk : in std_logic; | |
61 | ReUse : in std_logic_vector(FifoCnt-1 downto 0); |
|
61 | ReUse : in std_logic_vector(FifoCnt-1 downto 0); | |
62 | REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en mοΏ½moire |
|
62 | REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en mοΏ½moire | |
63 | WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'οΏ½criture en mοΏ½moire |
|
63 | WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'οΏ½criture en mοΏ½moire | |
64 | Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, MοΏ½moire vide |
|
64 | Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, MοΏ½moire vide | |
65 | Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, MοΏ½moire pleine |
|
65 | Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, MοΏ½moire pleine | |
66 | RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donnοΏ½es en entrοΏ½e |
|
66 | RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donnοΏ½es en entrοΏ½e | |
67 | WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donnοΏ½es en sortie |
|
67 | WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donnοΏ½es en sortie | |
68 | WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (οΏ½criture) |
|
68 | WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (οΏ½criture) | |
69 | RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture) |
|
69 | RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture) | |
70 | apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus |
|
70 | apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus | |
71 | apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus |
|
71 | apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus | |
72 | ); |
|
72 | ); | |
73 | end component; |
|
73 | end component; | |
74 |
|
74 | |||
75 |
|
75 | |||
76 | component lpp_fifo is |
|
76 | component lpp_fifo is | |
77 | generic( |
|
77 | generic( | |
78 | tech : integer := 0; |
|
78 | tech : integer := 0; | |
79 | Mem_use : integer := use_RAM; |
|
79 | Mem_use : integer := use_RAM; | |
80 | Enable_ReUse : std_logic := '0'; |
|
80 | Enable_ReUse : std_logic := '0'; | |
81 | DataSz : integer range 1 to 32 := 8; |
|
81 | DataSz : integer range 1 to 32 := 8; | |
82 |
|
|
82 | AddrSz : integer range 2 to 12 := 8 | |
83 | ); |
|
83 | ); | |
84 | port( |
|
84 | port( | |
85 | rstn : in std_logic; |
|
85 | rstn : in std_logic; | |
86 | ReUse : in std_logic; --27/01/12 |
|
86 | ReUse : in std_logic; --27/01/12 | |
87 | rclk : in std_logic; |
|
87 | rclk : in std_logic; | |
88 | ren : in std_logic; |
|
88 | ren : in std_logic; | |
89 | rdata : out std_logic_vector(DataSz-1 downto 0); |
|
89 | rdata : out std_logic_vector(DataSz-1 downto 0); | |
90 | empty : out std_logic; |
|
90 | empty : out std_logic; | |
91 |
raddr : out std_logic_vector( |
|
91 | raddr : out std_logic_vector(AddrSz-1 downto 0); | |
92 | wclk : in std_logic; |
|
92 | wclk : in std_logic; | |
93 | wen : in std_logic; |
|
93 | wen : in std_logic; | |
94 | wdata : in std_logic_vector(DataSz-1 downto 0); |
|
94 | wdata : in std_logic_vector(DataSz-1 downto 0); | |
95 | full : out std_logic; |
|
95 | full : out std_logic; | |
96 |
waddr : out std_logic_vector( |
|
96 | waddr : out std_logic_vector(AddrSz-1 downto 0) | |
97 | ); |
|
97 | ); | |
98 | end component; |
|
98 | end component; | |
99 |
|
99 | |||
100 |
|
100 | |||
101 | component lppFIFOxN is |
|
101 | component lppFIFOxN is | |
102 | generic( |
|
102 | generic( | |
103 | tech : integer := 0; |
|
103 | tech : integer := 0; | |
104 | Mem_use : integer := use_RAM; |
|
104 | Mem_use : integer := use_RAM; | |
105 | Data_sz : integer range 1 to 32 := 8; |
|
105 | Data_sz : integer range 1 to 32 := 8; | |
106 | Addr_sz : integer range 1 to 32 := 8; |
|
106 | Addr_sz : integer range 1 to 32 := 8; | |
107 | FifoCnt : integer := 1; |
|
107 | FifoCnt : integer := 1; | |
108 | Enable_ReUse : std_logic := '0' |
|
108 | Enable_ReUse : std_logic := '0' | |
109 | ); |
|
109 | ); | |
110 | port( |
|
110 | port( | |
111 | rst : in std_logic; |
|
111 | rstn : in std_logic; | |
112 | wclk : in std_logic; |
|
112 | wclk : in std_logic; | |
113 | rclk : in std_logic; |
|
113 | rclk : in std_logic; | |
114 | ReUse : in std_logic_vector(FifoCnt-1 downto 0); |
|
114 | ReUse : in std_logic_vector(FifoCnt-1 downto 0); | |
115 | wen : in std_logic_vector(FifoCnt-1 downto 0); |
|
115 | wen : in std_logic_vector(FifoCnt-1 downto 0); | |
116 | ren : in std_logic_vector(FifoCnt-1 downto 0); |
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116 | ren : in std_logic_vector(FifoCnt-1 downto 0); | |
117 | wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); |
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117 | wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); | |
118 | rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); |
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118 | rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); | |
119 | full : out std_logic_vector(FifoCnt-1 downto 0); |
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119 | full : out std_logic_vector(FifoCnt-1 downto 0); | |
120 | empty : out std_logic_vector(FifoCnt-1 downto 0) |
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120 | empty : out std_logic_vector(FifoCnt-1 downto 0) | |
121 | ); |
|
121 | ); | |
122 | end component; |
|
122 | end component; | |
123 |
|
123 | |||
124 | component FillFifo is |
|
124 | component FillFifo is | |
125 | generic( |
|
125 | generic( | |
126 | Data_sz : integer range 1 to 32 := 16; |
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126 | Data_sz : integer range 1 to 32 := 16; | |
127 | Fifo_cnt : integer range 1 to 8 := 5 |
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127 | Fifo_cnt : integer range 1 to 8 := 5 | |
128 | ); |
|
128 | ); | |
129 | port( |
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129 | port( | |
130 | clk : in std_logic; |
|
130 | clk : in std_logic; | |
131 | raz : in std_logic; |
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131 | raz : in std_logic; | |
132 | write : out std_logic_vector(Fifo_cnt-1 downto 0); |
|
132 | write : out std_logic_vector(Fifo_cnt-1 downto 0); | |
133 | reuse : out std_logic_vector(Fifo_cnt-1 downto 0); |
|
133 | reuse : out std_logic_vector(Fifo_cnt-1 downto 0); | |
134 | data : out std_logic_vector(Fifo_cnt*Data_sz-1 downto 0) |
|
134 | data : out std_logic_vector(Fifo_cnt*Data_sz-1 downto 0) | |
135 | ); |
|
135 | ); | |
136 | end component; |
|
136 | end component; | |
137 |
|
137 | |||
138 | component ssram_plugin is |
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138 | component ssram_plugin is | |
139 | generic (tech : integer := 0); |
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139 | generic (tech : integer := 0); | |
140 | port |
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140 | port | |
141 | ( |
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141 | ( | |
142 | clk : in std_logic; |
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142 | clk : in std_logic; | |
143 | mem_ctrlr_o : in memory_out_type; |
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143 | mem_ctrlr_o : in memory_out_type; | |
144 | SSRAM_CLK : out std_logic; |
|
144 | SSRAM_CLK : out std_logic; | |
145 | nBWa : out std_logic; |
|
145 | nBWa : out std_logic; | |
146 | nBWb : out std_logic; |
|
146 | nBWb : out std_logic; | |
147 | nBWc : out std_logic; |
|
147 | nBWc : out std_logic; | |
148 | nBWd : out std_logic; |
|
148 | nBWd : out std_logic; | |
149 | nBWE : out std_logic; |
|
149 | nBWE : out std_logic; | |
150 | nADSC : out std_logic; |
|
150 | nADSC : out std_logic; | |
151 | nADSP : out std_logic; |
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151 | nADSP : out std_logic; | |
152 | nADV : out std_logic; |
|
152 | nADV : out std_logic; | |
153 | nGW : out std_logic; |
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153 | nGW : out std_logic; | |
154 | nCE1 : out std_logic; |
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154 | nCE1 : out std_logic; | |
155 | CE2 : out std_logic; |
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155 | CE2 : out std_logic; | |
156 | nCE3 : out std_logic; |
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156 | nCE3 : out std_logic; | |
157 | nOE : out std_logic; |
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157 | nOE : out std_logic; | |
158 | MODE : out std_logic; |
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158 | MODE : out std_logic; | |
159 | ZZ : out std_logic |
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159 | ZZ : out std_logic | |
160 | ); |
|
160 | ); | |
161 | end component; |
|
161 | end component; | |
162 |
|
162 | |||
163 |
end; |
|
163 | end; No newline at end of file |
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