diff --git a/lib/lpp/leon3mp.vhd b/lib/lpp/leon3mp.vhd --- a/lib/lpp/leon3mp.vhd +++ b/lib/lpp/leon3mp.vhd @@ -45,10 +45,7 @@ use lpp.lpp_ad_conv.all; use lpp.iir_filter.all; use lpp.general_purpose.all; use lpp.Filtercfg.all; -use lpp.lpp_demux.all; -use lpp.lpp_top_lfr_pkg.all; -use lpp.lpp_dma_pkg.all; -use lpp.lpp_Header.all; +use lpp.lpp_cna.all; entity leon3mp is generic ( @@ -96,28 +93,13 @@ entity leon3mp is --------------------------------------------------------------------- --- AJOUT TEST ------------------------In/Out----------------------- --------------------------------------------------------------------- +-- DAC + DAC_SYNC : out std_logic; + DAC_SCLK : out std_logic; + DAC_DATA : out std_logic; -- UART UART_RXD : in std_logic; UART_TXD : out std_logic; --- ACQ - CNV_CH1 : OUT STD_LOGIC; - SCK_CH1 : OUT STD_LOGIC; - SDO_CH1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - Bias_Fails : out std_logic; --- ADC --- ADC_in : in AD7688_in(4 downto 0); --- ADC_out : out AD7688_out; - --- CNA --- DAC_SYNC : out std_logic; --- DAC_SCLK : out std_logic; --- DAC_DATA : out std_logic; --- Diver - SPW1_EN : out std_logic; - SPW2_EN : out std_logic; - TEST : out std_logic_vector(3 downto 0); - - BP : in std_logic; --------------------------------------------------------------------- led : out std_logic_vector(1 downto 0) ); @@ -126,7 +108,7 @@ end; architecture Behavioral of leon3mp is constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+ - CFG_GRETH+CFG_AHB_JTAG+1; -- +1 pour le DMA + CFG_GRETH+CFG_AHB_JTAG; constant maxahbm : integer := maxahbmsp; --Clk & Rst géné @@ -178,103 +160,7 @@ signal dsuo : dsu_out_type; --------------------------------------------------------------------- --- AJOUT TEST ------------------------Signaux---------------------- --------------------------------------------------------------------- --- FIFOs -signal FifoF0_Empty : std_logic_vector(4 downto 0); -signal FifoF0_Data : std_logic_vector(79 downto 0); -signal FifoF1_Empty : std_logic_vector(4 downto 0); -signal FifoF1_Data : std_logic_vector(79 downto 0); -signal FifoF3_Empty : std_logic_vector(4 downto 0); -signal FifoF3_Data : std_logic_vector(79 downto 0); -signal FifoINT_Full : std_logic_vector(4 downto 0); -signal FifoINT_Data : std_logic_vector(79 downto 0); - -signal FifoOUT_Full : std_logic_vector(1 downto 0); -signal FifoOUT_Empty : std_logic_vector(1 downto 0); -signal FifoOUT_Data : std_logic_vector(63 downto 0); - - --- MATRICE SPECTRALE -signal SM_FlagError : std_logic; -signal SM_Pong : std_logic; -signal SM_Wen : std_logic; -signal SM_Read : std_logic_vector(4 downto 0); -signal SM_Write : std_logic_vector(1 downto 0); -signal SM_ReUse : std_logic_vector(4 downto 0); -signal SM_Param : std_logic_vector(3 downto 0); -signal SM_Data : std_logic_vector(63 downto 0); - ---signal Dma_acq : std_logic; ---signal Head_Valid : std_logic; - --- FFT -signal FFT_Load : std_logic; -signal FFT_Read : std_logic_vector(4 downto 0); -signal FFT_Write : std_logic_vector(4 downto 0); -signal FFT_ReUse : std_logic_vector(4 downto 0); -signal FFT_Data : std_logic_vector(79 downto 0); - --- DEMUX -signal DMUX_Read : std_logic_vector(14 downto 0); -signal DMUX_Empty : std_logic_vector(4 downto 0); -signal DMUX_Data : std_logic_vector(79 downto 0); -signal DMUX_WorkFreq : std_logic_vector(1 downto 0); - --- ACQ -signal sample_val : STD_LOGIC; -signal sample : Samples(8-1 DOWNTO 0); - -signal ACQ_WenF0 : STD_LOGIC_VECTOR(4 DOWNTO 0); -signal ACQ_DataF0 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); -signal ACQ_WenF1 : STD_LOGIC_VECTOR(4 DOWNTO 0); -signal ACQ_DataF1 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); -signal ACQ_WenF3 : STD_LOGIC_VECTOR(4 DOWNTO 0); -signal ACQ_DataF3 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - --- Header -signal Head_Read : std_logic_vector(1 downto 0); -signal Head_Data : std_logic_vector(31 downto 0); -signal Head_Empty : std_logic; -signal Head_Header : std_logic_vector(31 DOWNTO 0); -signal Head_Valid : std_logic; -signal Head_Val : std_logic; - ---DMA -signal DMA_Read : std_logic; -signal DMA_ack : std_logic; ---signal AHB_Master_In : AHB_Mst_In_Type; ---signal AHB_Master_Out : AHB_Mst_Out_Type; - - --- ADC ---signal SmplClk : std_logic; ---signal ADC_DataReady : std_logic; ---signal ADC_SmplOut : Samples_out(4 downto 0); ---signal enableADC : std_logic; --- ---signal WG_Write : std_logic_vector(4 downto 0); ---signal WG_ReUse : std_logic_vector(4 downto 0); ---signal WG_DATA : std_logic_vector(79 downto 0); ---signal s_out : std_logic_vector(79 downto 0); --- ---signal fuller : std_logic_vector(4 downto 0); ---signal reader : std_logic_vector(4 downto 0); ---signal try : std_logic_vector(1 downto 0); ---signal TXDint : std_logic; --- ----- IIR Filter ---signal sample_clk_out : std_logic; --- ---signal Rd : std_logic_vector(0 downto 0); ---signal Ept : std_logic_vector(4 downto 0); --- ---signal Bwr : std_logic_vector(0 downto 0); ---signal Bre : std_logic_vector(0 downto 0); ---signal DataTMP : std_logic_vector(15 downto 0); ---signal FullUp : std_logic_vector(0 downto 0); ---signal EmptyUp : std_logic_vector(0 downto 0); ---signal FullDown : std_logic_vector(0 downto 0); ---signal EmptyDown : std_logic_vector(0 downto 0); --------------------------------------------------------------------- constant IOAEN : integer := CFG_CAN; constant boardfreq : integer := 50000; @@ -284,245 +170,29 @@ begin --------------------------------------------------------------------- --- AJOUT TEST -------------------------------------IPs------------- --------------------------------------------------------------------- -led(1 downto 0) <= gpio(1 downto 0); - ---- COM USB --------------------------------------------------------- --- MemIn0 : APB_FifoWrite --- generic map (5,5, Data_sz => 8, Addr_sz => 8, addr_max_int => 256) --- port map (clkm,rstn,apbi,USB_Read,open,open,InOutData,apbo(5)); --- --- BUF0 : APB_USB --- generic map (6,6,DataMax => 1024) --- port map(clkm,rstn,flagC,flagB,ifclk,sloe,USB_Read,USB_Write,pktend,fifoadr,InOutData,apbi,apbo(6)); --- --- MemOut0 : APB_FifoRead --- generic map (7,7, Data_sz => 8, Addr_sz => 8, addr_max_int => 256) --- port map (clkm,rstn,apbi,USB_Write,open,open,InOutData,apbo(7)); --- ---slrd <= usb_Read; ---slwr <= usb_Write; - ---- CNA ------------------------------------------------------------- - --- CONV : APB_CNA --- generic map (5,5) --- port map(clkm,rstn,apbi,apbo(5),DAC_SYNC,DAC_SCLK,DAC_DATA); - ---TEST(0) <= SmplClk; ---TEST(1) <= WG_Write(0); ---TEST(2) <= Fuller(0); ---TEST(3) <= s_out(s_out'length-1); - - ---SPW1_EN <= '1'; ---SPW2_EN <= '0'; - ---- CAN ------------------------------------------------------------- --- Divider : Clk_divider --- generic map(OSC_freqHz => 24_576_000, TargetFreq_Hz => 24_576) --- Port map(clkm,rstn,SmplClk); --- --- ADC : AD7688_drvr --- generic map (ChanelCount => 5, clkkHz => 24_576) --- port map (clkm,rstn,enableADC,SmplClk,ADC_DataReady,ADC_SmplOut,ADC_in,ADC_out); --- --- WG : WriteGen_ADC --- port map (clkm,rstn,SmplClk,ADC_DataReady,Fuller,WG_ReUse,WG_Write); --- ---enableADC <= gpio(0); +-- apbo not free : 0 1 2 3 7 11 ---WG_DATA <= ADC_SmplOut(4) & ADC_SmplOut(3) & ADC_SmplOut(2) & ADC_SmplOut(1) & ADC_SmplOut(0); --- --- --- MemIn1 : APB_FIFO --- generic map (pindex => 6, paddr => 6, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) --- port map (clkm,rstn,clkm,clkm,WG_ReUse,(others => '1'),WG_Write,open,Fuller,open,WG_DATA,open,open,apbi,apbo(6)); - --- DIGITAL_acquisition : ADS7886_drvr --- GENERIC MAP ( --- ChanelCount => 8, --- ncycle_cnv_high => 79, --- ncycle_cnv => 500) --- PORT MAP ( --- cnv_clk => clk50MHz, -- --- cnv_rstn => rstn, -- --- cnv_run => '1', -- --- cnv => CNV_CH1, -- --- clk => clkm, -- --- rstn => rstn, -- --- sck => SCK_CH1, -- --- sdo => SDO_CH1, -- --- sample => sample, --- sample_val => sample_val); --- ---TopACQ_WenF0 <= not sample_filter_v2_out_val & not sample_filter_v2_out_val & not sample_filter_v2_out_val & not sample_filter_v2_out_val & not sample_filter_v2_out_val; ---TopACQ_DataF0 <= E & D & C & B & A; - --- ---TEST(0) <= TopACQ_WenF0(1); ---TEST(1) <= SDO_CH1(1); --- ---process(clkm,rstn) ---begin --- if(rstn='0')then --- TopACQ_WenF0a <= (others => '1'); --- --- elsif(clkm'event and clkm='1')then --- TopACQ_WenF0a <= not sample_val & not sample_val & not sample_val & not sample_val & not sample_val; --- --- end if; ---end process; - - ACQ0 : lpp_top_acq - port map('1',CNV_CH1,SCK_CH1,SDO_CH1,clk50MHz,rstn,clkm,rstn,ACQ_WenF0,ACQ_DataF0,ACQ_WenF1,ACQ_DataF1,open,open,ACQ_WenF3,ACQ_DataF3); +--- DAC ------------------------------------------------------------- -Bias_Fails <= '0'; ---------- FIFO IN ------------------------------------------------------------- ----- --- Memf0 : APB_FIFO --- generic map (pindex => 9, paddr => 9, FifoCnt => 5, Data_sz => 16, Addr_sz => 9, Enable_ReUse => '0', R => 1, W => 0) --- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),ACQ_WenF0,open,open,open,ACQ_DataF0,open,open,apbi,apbo(9)); --- --- Memf1 : APB_FIFO --- generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) --- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),ACQ_WenF1,open,open,open,ACQ_DataF1,open,open,apbi,apbo(8)); --- --- Memf3 : APB_FIFO --- generic map (pindex => 5, paddr => 5, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) --- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),ACQ_WenF3,open,open,open,ACQ_DataF3,open,open,apbi,apbo(5)); - - Memf0 : lppFIFOxN - generic map(Data_sz => 16, Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0') - port map(rstn,clkm,clkm,(others => '0'),ACQ_WenF0,DMUX_Read(4 downto 0),ACQ_DataF0,FifoF0_Data,open,FifoF0_Empty); - - Memf1 : lppFIFOxN - generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') - port map(rstn,clkm,clkm,(others => '0'),ACQ_WenF1,DMUX_Read(9 downto 5),ACQ_DataF1,FifoF1_Data,open,FifoF1_Empty); - - Memf3 : lppFIFOxN - generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') - port map(rstn,clkm,clkm,(others => '0'),ACQ_WenF3,DMUX_Read(14 downto 10),ACQ_DataF3,FifoF3_Data,open,FifoF3_Empty); --- ------ DEMUX ------------------------------------------------------------- - - DMUX0 : DEMUX - generic map(Data_sz => 16) - port map(clkm,rstn,FFT_Read,FFT_Load,FifoF0_Empty,FifoF1_Empty,FifoF3_Empty,FifoF0_Data,FifoF1_Data,FifoF3_Data,DMUX_WorkFreq,DMUX_Read,DMUX_Empty,DMUX_Data); - -------- FFT ------------------------------------------------------------- - --- MemIn : APB_FIFO --- generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1) --- port map (clkm,rstn,clkm,clkm,(others => '0'),FFT_Read,(others => '1'),DMUX_Empty,open,DMUX_Data,(others => '0'),open,open,apbi,apbo(8)); - - FFT0 : FFT - generic map(Data_sz => 16,NbData => 256) - port map(clkm,rstn,DMUX_Empty,DMUX_Data,FifoINT_Full,FFT_Load,FFT_Read,FFT_Write,FFT_ReUse,FFT_Data); - ---------- LINK MEMORY ------------------------------------------------------- - --- MemOut : APB_FIFO --- generic map (pindex => 9, paddr => 9, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 0) --- port map (clkm,rstn,clkm,clkm,FFT_ReUse,(others =>'1'),FFT_Write,open,FifoINT_Full,open,FFT_Data,open,open,apbi,apbo(9)); - - MemInt : lppFIFOxN - generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '1') - port map(rstn,clkm,clkm,SM_ReUse,FFT_Write,SM_Read,FFT_Data,FifoINT_Data,FifoINT_Full,open); + CAL0 : APB_CNA + generic map (pindex => 4, paddr => 4) + port map(clkm,rstn,apbi,apbo(4),DAC_SYNC,DAC_SCLK,DAC_DATA); --- MemIn : APB_FIFO --- generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 0, W => 1) --- port map (clkm,rstn,clkm,clkm,(others => '0'),SM_Read,(others => '1'),open,FifoINT_Full,FifoINT_Data,(others => '0'),open,open,apbi,apbo(8)); - ------ MATRICE SPECTRALE ---------------------5 FIFO Input--------------- - - SM0 : MatriceSpectrale - generic map(Input_SZ => 16,Result_SZ => 32) - port map(clkm,rstn,FifoINT_Full,FFT_ReUse,Head_Valid,FifoINT_Data,DMA_ack,SM_Wen,SM_FlagError,SM_Pong,SM_Param,SM_Write,SM_Read,SM_ReUse,SM_Data); - - ---DMA_ack <= '1'; ---Head_Valid <= '1'; - --- MemOut : APB_FIFO --- generic map (pindex => 9, paddr => 9, FifoCnt => 2, Data_sz => 32, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) --- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),SM_Write,open,FifoOUT_Full,open,SM_Data,open,open,apbi,apbo(9)); - - MemOut : lppFIFOxN - generic map(Data_sz => 32, Addr_sz => 8, FifoCnt => 2, Enable_ReUse => '0') - port map(rstn,clkm,clkm,(others => '0'),SM_Write,Head_Read,SM_Data,FifoOUT_Data,FifoOUT_Full,FifoOUT_Empty); - ------------ Header ------------------------------------------------------- - - Head0 : HeaderBuilder - generic map(Data_sz => 32) - port map(clkm,rstn,SM_Pong,SM_Param,DMUX_WorkFreq,SM_Wen,Head_Valid,FifoOUT_Data,FifoOUT_Empty,Head_Read,Head_Data,Head_Empty,DMA_Read,Head_Header,Head_Val,DMA_ack); - - ---- DMA ------------------------------------------------------- - - DMA0 : lpp_dma - generic map(hindex => 1,pindex => 9, paddr => 9,pirq => 14, pmask =>16#fff#,tech => CFG_FABTECH) - port map(clkm,rstn,apbi,apbo(9),ahbmi,ahbmo(1),Head_Data,Head_Empty,DMA_Read,Head_Header,Head_Val,DMA_ack); - - ------ FIFO ------------------------------------------------------------- - --- Memtest : APB_FIFO --- generic map (pindex => 5, paddr => 5, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 1) --- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),(others => '1'),open,open,open,(others => '0'),open,open,apbi,apbo(5)); - ---***************************************TEST DEMI-FIFO******************************************************************************** --- MemIn : APB_FIFO --- generic map (pindex => 8, paddr => 8, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1) --- port map (clkm,rstn,clkm,clkm,(others => '0'),Bre,(others => '1'),EmptyUp,FullUp,DataTMP,(others => '0'),open,open,apbi,apbo(8)); --- --- Pont : Bridge --- port map(clkm,rstn,EmptyUp(0),FullDown(0),Bwr(0),Bre(0)); --- --- MemOut : APB_FIFO --- generic map (pindex => 9, paddr => 9, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) --- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),Bwr,EmptyDown,FullDown,open,DataTMP,open,open,apbi,apbo(9)); ---************************************************************************************************************************************* --- UART ------------------------------------------------------------- COM0 : APB_UART - generic map (pindex => 4, paddr => 4) - port map (clkm,rstn,apbi,apbo(4),UART_TXD,UART_RXD); + generic map (pindex => 5, paddr => 5) + port map (clkm,rstn,apbi,apbo(5),UART_TXD,UART_RXD); ---- DELAY ------------------------------------------------------------ - --- Delay0 : APB_Delay --- generic map (pindex => 4, paddr => 4) --- port map (clkm,rstn,apbi,apbo(4)); ---- IIR Filter ------------------------------------------------------- ---Test(0) <= sample_clk_out; --- --- --- IIR1: APB_IIR_Filter --- generic map( --- tech => CFG_MEMTECH, --- pindex => 8, --- paddr => 8, --- Sample_SZ => Sample_SZ, --- ChanelsCount => ChanelsCount, --- Coef_SZ => Coef_SZ, --- CoefCntPerCel => CoefCntPerCel, --- Cels_count => Cels_count, --- virgPos => virgPos --- ) --- port map( --- rst => rstn, --- clk => clkm, --- apbi => apbi, --- apbo => apbo(8), --- sample_clk_out => sample_clk_out, --- GOtest => Test(1), --- CoefsInitVal => (others => '1') --- ); ----------------------------------------------------------------------- +--- FIFO ------------------------------------------------------------- + + Memtest : APB_FIFO + generic map (pindex => 6, paddr => 6, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 1) + port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),(others => '1'),open,open,open,(others => '0'),open,open,apbi,apbo(6)); + ---------------------------------------------------------------------- --- Reset and Clock generation ------------------------------------- @@ -637,8 +307,8 @@ end process; dcomgen : if CFG_AHB_UART = 1 generate dcom0: ahbuart -- Debug UART - generic map (hindex => 2, pindex => 7, paddr => 7) - port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(2)); + generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7) + port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU)); dsurx_pad : inpad generic map (tech => padtech) port map (ahbrxd, ahbuarti.rxd); dsutx_pad : outpad generic map (tech => padtech) port map (ahbtxd, ahbuarto.txd); -- led(0) <= not ahbuarti.rxd; led(1) <= not ahbuarto.txd; @@ -687,6 +357,7 @@ end process; ---------------------------------------------------------------------- --- GPIO ----------------------------------------------------------- ---------------------------------------------------------------------- +led(0) <= gpio(0); led(1) <= gpio(1); gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit grgpio0: grgpio diff --git a/lib/lpp/lpp_Header/HeaderBuilder.vhd b/lib/lpp/lpp_Header/HeaderBuilder.vhd --- a/lib/lpp/lpp_Header/HeaderBuilder.vhd +++ b/lib/lpp/lpp_Header/HeaderBuilder.vhd @@ -30,7 +30,6 @@ entity HeaderBuilder is clkm : in std_logic; rstn : in std_logic; - pong : in std_logic; Statu : in std_logic_vector(3 downto 0); Matrix_Type : in std_logic_vector(1 downto 0); Matrix_Write : in std_logic; @@ -57,7 +56,6 @@ signal Matrix_Param : std_logic_vect signal Write_reg : std_logic; signal Data_cpt : integer; signal MAX : integer; -signal pong_reg : std_logic; type etat is (idle0,idle1,pong0,pong1); signal ect : etat; @@ -69,7 +67,6 @@ begin if(rstn='0')then ect <= idle0; Valid <= '0'; - pong_reg <= '0'; header_val <= '0'; header(5 downto 0) <= (others => '0'); Write_reg <= '0'; @@ -79,7 +76,6 @@ begin elsif(clkm' event and clkm='1')then Write_reg <= Matrix_Write; - pong_reg <= pong; if(Statu="0001" or Statu="0011" or Statu="0110" or Statu="1010" or Statu="1111")then MAX <= 128; @@ -87,17 +83,6 @@ begin MAX <= 256; end if; --- if(Write_reg = '0' and Matrix_Write = '1')then --- if(Data_cpt = MAX)then --- Data_cpt <= 0; --- Valid <= '1'; --- header_val <= '1'; --- else --- Data_cpt <= Data_cpt + 1; --- Valid <= '0'; --- end if; --- end if; - if(Write_reg = '0' and Matrix_Write = '1')then Data_cpt <= Data_cpt + 1; Valid <= '0'; @@ -107,19 +92,7 @@ begin header_val <= '1'; else Valid <= '0'; - end if; - --- if(header_ack = '1')then --- header_val <= '0'; --- end if; - --- if(emptyIN = "10")then --- ping <= '0'; --- elsif(emptyIN = "01")then --- ping <= '1'; --- else --- ping <= ping; --- end if; + end if; case ect is @@ -127,11 +100,7 @@ begin when idle0 => if(header_ack = '1')then header_val <= '0'; - --if(pong = '1')then - ect <= pong0; - --elsif(pong = '0')then - --ect <= pong1; - --end if; + ect <= pong0; end if; when pong0 => @@ -160,8 +129,6 @@ begin Matrix_Param <= std_logic_vector(to_unsigned(to_integer(unsigned(Statu))-1,4)); ---header(1 downto 0) <= Matrix_Type; ---header(5 downto 2) <= Matrix_Param; header(31 downto 6) <= (others => '0'); with ect select diff --git a/lib/lpp/lpp_Header/lpp_Header.vhd b/lib/lpp/lpp_Header/lpp_Header.vhd --- a/lib/lpp/lpp_Header/lpp_Header.vhd +++ b/lib/lpp/lpp_Header/lpp_Header.vhd @@ -38,7 +38,6 @@ component HeaderBuilder is clkm : in std_logic; rstn : in std_logic; - pong : in std_logic; Statu : in std_logic_vector(3 downto 0); Matrix_Type : in std_logic_vector(1 downto 0); Matrix_Write : in std_logic; diff --git a/lib/lpp/lpp_cna/CNA_TabloC.vhd b/lib/lpp/lpp_cna/CNA_TabloC.vhd --- a/lib/lpp/lpp_cna/CNA_TabloC.vhd +++ b/lib/lpp/lpp_cna/CNA_TabloC.vhd @@ -44,37 +44,37 @@ end CNA_TabloC; architecture ar_CNA_TabloC of CNA_TabloC is -component CLKINT -port( A : in std_logic := 'U'; - Y : out std_logic); -end component; +--component CLKINT +--port( A : in std_logic := 'U'; +-- Y : out std_logic); +--end component; -signal clk : std_logic; +--signal clk : std_logic; -signal raz : std_logic; +--signal raz : std_logic; signal s_SCLK : std_logic; signal OKAI_send : std_logic; begin -CLKINT_0 : CLKINT - port map(A => clock, Y => clk); +--CLKINT_0 : CLKINT +-- port map(A => clock, Y => clk); -CLKINT_1 : CLKINT - port map(A => rst, Y => raz); +--CLKINT_1 : CLKINT +-- port map(A => rst, Y => raz); SystemCLK : entity work.Systeme_Clock generic map (nb_serial) - port map (clk,raz,s_SCLK); + port map (clock,rst,s_SCLK); Signal_sync : entity work.Gene_SYNC - port map (s_SCLK,raz,enable,OKAI_send,SYNC); + port map (s_SCLK,rst,enable,OKAI_send,SYNC); Serial : entity work.serialize - port map (clk,raz,s_SCLK,Data_C,OKAI_send,flag_sd,Data); + port map (clock,rst,s_SCLK,Data_C,OKAI_send,flag_sd,Data); SCLK <= s_SCLK; diff --git a/lib/lpp/lpp_matrix/Dispatch.vhd b/lib/lpp/lpp_matrix/Dispatch.vhd --- a/lib/lpp/lpp_matrix/Dispatch.vhd +++ b/lib/lpp/lpp_matrix/Dispatch.vhd @@ -29,14 +29,12 @@ generic( port( clk : in std_logic; reset : in std_logic; - Acq : in std_logic; + Ack : in std_logic; Data : in std_logic_vector(Data_SZ-1 downto 0); Write : in std_logic; Valid : in std_logic; --- Full : in std_logic_vector(1 downto 0); FifoData : out std_logic_vector(2*Data_SZ-1 downto 0); FifoWrite : out std_logic_vector(1 downto 0); - Pong : out std_logic; Error : out std_logic ); end entity; @@ -47,15 +45,14 @@ architecture ar_Dispatch of Dispatch is type etat is (eX,e0,e1,e2); signal ect : etat; -signal Pong_int : std_logic; ---signal FifoCpt : integer range 0 to 1 := 0; +signal Pong : std_logic; begin process (clk,reset) begin if(reset='0')then - Pong_int <= '0'; + Pong <= '0'; Error <= '0'; ect <= e0; @@ -64,14 +61,13 @@ begin case ect is when e0 => --- if(Full(FifoCpt) = '1')then if(Valid = '1')then - Pong_int <= not Pong_int; + Pong <= not Pong; ect <= e1; end if; when e1 => - if(Acq = '0')then + if(Ack = '0')then Error <= '1'; ect <= e1; else @@ -80,7 +76,7 @@ begin end if; when others => - null; + null; end case; @@ -88,10 +84,6 @@ begin end process; FifoData <= Data & Data; -Pong <= Pong_int; - ---FifoCpt <= 0 when Pong_int='0' else 1; - -FifoWrite <= '1' & not Write when Pong_int='0' else not Write & '1'; +FifoWrite <= '1' & not Write when Pong='0' else not Write & '1'; end architecture; \ No newline at end of file diff --git a/lib/lpp/lpp_matrix/MatriceSpectrale.vhd b/lib/lpp/lpp_matrix/MatriceSpectrale.vhd --- a/lib/lpp/lpp_matrix/MatriceSpectrale.vhd +++ b/lib/lpp/lpp_matrix/MatriceSpectrale.vhd @@ -35,13 +35,11 @@ entity MatriceSpectrale is FifoIN_Full : in std_logic_vector(4 downto 0); SetReUse : in std_logic_vector(4 downto 0); --- FifoOUT_Full : in std_logic_vector(1 downto 0); Valid : in std_logic; Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0); - ACQ : in std_logic; + ACK : in std_logic; SM_Write : out std_logic; FlagError : out std_logic; - Pong : out std_logic; Statu : out std_logic_vector(3 downto 0); Write : out std_logic_vector(1 downto 0); Read : out std_logic_vector(4 downto 0); @@ -78,7 +76,7 @@ begin DISP : Dispatch generic map(Result_SZ) - port map(clkm,rstn,ACQ,Matrix_Result,Matrix_Write,Valid,Data_OUT,Write,Pong,FlagError); + port map(clkm,rstn,ACK,Matrix_Result,Matrix_Write,Valid,Data_OUT,Write,FlagError); Statu <= TopSM_Statu; SM_Write <= Matrix_Write; diff --git a/lib/lpp/lpp_matrix/lpp_matrix.vhd b/lib/lpp/lpp_matrix/lpp_matrix.vhd --- a/lib/lpp/lpp_matrix/lpp_matrix.vhd +++ b/lib/lpp/lpp_matrix/lpp_matrix.vhd @@ -66,13 +66,11 @@ component MatriceSpectrale is FifoIN_Full : in std_logic_vector(4 downto 0); SetReUse : in std_logic_vector(4 downto 0); --- FifoOUT_Full : in std_logic_vector(1 downto 0); Valid : in std_logic; Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0); - ACQ : in std_logic; + ACK : in std_logic; SM_Write : out std_logic; FlagError : out std_logic; - Pong : out std_logic; Statu : out std_logic_vector(3 downto 0); Write : out std_logic_vector(1 downto 0); Read : out std_logic_vector(4 downto 0); @@ -199,14 +197,12 @@ generic( port( clk : in std_logic; reset : in std_logic; - Acq : in std_logic; + Ack : in std_logic; Data : in std_logic_vector(Data_SZ-1 downto 0); Write : in std_logic; Valid : in std_logic; --- Full : in std_logic_vector(1 downto 0); FifoData : out std_logic_vector(2*Data_SZ-1 downto 0); FifoWrite : out std_logic_vector(1 downto 0); - Pong : out std_logic; Error : out std_logic ); end component; diff --git a/lib/lpp/lpp_memory/lppFIFOxN.vhd b/lib/lpp/lpp_memory/lppFIFOxN.vhd --- a/lib/lpp/lpp_memory/lppFIFOxN.vhd +++ b/lib/lpp/lpp_memory/lppFIFOxN.vhd @@ -1,66 +1,65 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- --- Author : Martin Morlot --- Mail : martin.morlot@lpp.polytechnique.fr ------------------------------------------------------------------------------- -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -library lpp; -use lpp.lpp_memory.all; -use lpp.iir_filter.all; -library techmap; -use techmap.gencomp.all; - -entity lppFIFOxN is -generic( - tech : integer := 0; - Mem_use : integer := use_RAM; - Data_sz : integer range 1 to 32 := 8; - Addr_sz : integer range 1 to 32 := 8; - FifoCnt : integer := 1; - Enable_ReUse : std_logic := '0' - ); -port( - rst : in std_logic; - wclk : in std_logic; - rclk : in std_logic; - ReUse : in std_logic_vector(FifoCnt-1 downto 0); - wen : in std_logic_vector(FifoCnt-1 downto 0); - ren : in std_logic_vector(FifoCnt-1 downto 0); - wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); - rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); - full : out std_logic_vector(FifoCnt-1 downto 0); - empty : out std_logic_vector(FifoCnt-1 downto 0) -); -end entity; - - -architecture ar_lppFIFOxN of lppFIFOxN is - -begin - -fifos: for i in 0 to FifoCnt-1 generate - FIFO0 : lpp_fifo - generic map (tech,Mem_use,Enable_ReUse,Data_sz,Addr_sz) - port map(rst,ReUse(i),rclk,ren(i),rdata((i+1)*Data_sz-1 downto i*Data_sz),empty(i),open,wclk,wen(i),wdata((i+1)*Data_sz-1 downto i*Data_sz),full(i),open); -end generate; - -end architecture; - +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +library lpp; +use lpp.lpp_memory.all; +use lpp.iir_filter.all; +library techmap; +use techmap.gencomp.all; + +entity lppFIFOxN is +generic( + tech : integer := 0; + Mem_use : integer := use_RAM; + Data_sz : integer range 1 to 32 := 8; + Addr_sz : integer range 2 to 12 := 8; + FifoCnt : integer := 1; + Enable_ReUse : std_logic := '0' + ); +port( + rstn : in std_logic; + wclk : in std_logic; + rclk : in std_logic; + ReUse : in std_logic_vector(FifoCnt-1 downto 0); + wen : in std_logic_vector(FifoCnt-1 downto 0); + ren : in std_logic_vector(FifoCnt-1 downto 0); + wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); + rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); + full : out std_logic_vector(FifoCnt-1 downto 0); + empty : out std_logic_vector(FifoCnt-1 downto 0) +); +end entity; + + +architecture ar_lppFIFOxN of lppFIFOxN is + +begin + +fifos: for i in 0 to FifoCnt-1 generate + FIFO0 : lpp_fifo + generic map (tech,Mem_use,Enable_ReUse,Data_sz,Addr_sz) + port map(rstn,ReUse(i),rclk,ren(i),rdata((i+1)*Data_sz-1 downto i*Data_sz),empty(i),open,wclk,wen(i),wdata((i+1)*Data_sz-1 downto i*Data_sz),full(i),open); +end generate; + +end architecture; diff --git a/lib/lpp/lpp_memory/lpp_FIFO.vhd b/lib/lpp/lpp_memory/lpp_FIFO.vhd --- a/lib/lpp/lpp_memory/lpp_FIFO.vhd +++ b/lib/lpp/lpp_memory/lpp_FIFO.vhd @@ -34,7 +34,7 @@ generic( Mem_use : integer := use_RAM; Enable_ReUse : std_logic := '0'; DataSz : integer range 1 to 32 := 8; - abits : integer range 2 to 12 := 8 + AddrSz : integer range 2 to 12 := 8 ); port( rstn : in std_logic; @@ -43,12 +43,12 @@ port( ren : in std_logic; rdata : out std_logic_vector(DataSz-1 downto 0); empty : out std_logic; - raddr : out std_logic_vector(abits-1 downto 0); + raddr : out std_logic_vector(AddrSz-1 downto 0); wclk : in std_logic; wen : in std_logic; wdata : in std_logic_vector(DataSz-1 downto 0); full : out std_logic; - waddr : out std_logic_vector(abits-1 downto 0) + waddr : out std_logic_vector(AddrSz-1 downto 0) ); end entity; @@ -65,10 +65,10 @@ signal sWEN : std_logic; signal sRE : std_logic; signal sWE : std_logic; -signal Waddr_vect : std_logic_vector(abits-1 downto 0):=(others =>'0'); -signal Raddr_vect : std_logic_vector(abits-1 downto 0):=(others =>'0'); -signal Waddr_vect_s : std_logic_vector(abits-1 downto 0):=(others =>'0'); -signal Raddr_vect_s : std_logic_vector(abits-1 downto 0):=(others =>'0'); +signal Waddr_vect : std_logic_vector(AddrSz-1 downto 0):=(others =>'0'); +signal Raddr_vect : std_logic_vector(AddrSz-1 downto 0):=(others =>'0'); +signal Waddr_vect_s : std_logic_vector(AddrSz-1 downto 0):=(others =>'0'); +signal Raddr_vect_s : std_logic_vector(AddrSz-1 downto 0):=(others =>'0'); begin @@ -78,13 +78,13 @@ begin --================================================================================== memRAM : IF Mem_use = use_RAM GENERATE SRAM : syncram_2p - generic map(tech,abits,DataSz) + generic map(tech,AddrSz,DataSz) port map(RCLK,sRE,Raddr_vect,rdata,WCLK,sWE,Waddr_vect,wdata); END GENERATE; --================================================================================== memCEL : IF Mem_use = use_CEL GENERATE CRAM : RAM_CEL - generic map(DataSz,abits) + generic map(DataSz,AddrSz) port map(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, WCLK, rstn); END GENERATE; --================================================================================== @@ -177,4 +177,3 @@ end architecture; - diff --git a/lib/lpp/lpp_memory/lpp_memory.vhd b/lib/lpp/lpp_memory/lpp_memory.vhd --- a/lib/lpp/lpp_memory/lpp_memory.vhd +++ b/lib/lpp/lpp_memory/lpp_memory.vhd @@ -1,163 +1,163 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- --- Author : Martin Morlot --- Mail : martin.morlot@lpp.polytechnique.fr ------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -library grlib; -use grlib.amba.all; -use std.textio.all; -library lpp; -use lpp.lpp_amba.all; -use lpp.iir_filter.all; -library gaisler; -use gaisler.misc.all; -use gaisler.memctrl.all; -library techmap; -use techmap.gencomp.all; - ---! Package contenant tous les programmes qui forment le composant intégré dans le léon - -package lpp_memory is - -component APB_FIFO is -generic ( - tech : integer := apa3; - pindex : integer := 0; - paddr : integer := 0; - pmask : integer := 16#fff#; - pirq : integer := 0; - abits : integer := 8; - FifoCnt : integer := 2; - Data_sz : integer := 16; - Addr_sz : integer := 9; - Enable_ReUse : std_logic := '0'; - Mem_use : integer := use_RAM; - R : integer := 1; - W : integer := 1 - ); - port ( - clk : in std_logic; --! Horloge du composant - rst : in std_logic; --! Reset general du composant - rclk : in std_logic; - wclk : in std_logic; - ReUse : in std_logic_vector(FifoCnt-1 downto 0); - REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en mémoire - WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'écriture en mémoire - Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, Mémoire vide - Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, Mémoire pleine - RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de données en entrée - WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de données en sortie - WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (écriture) - RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture) - apbi : in apb_slv_in_type; --! Registre de gestion des entrées du bus - apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus - ); -end component; - - -component lpp_fifo is -generic( - tech : integer := 0; - Mem_use : integer := use_RAM; - Enable_ReUse : std_logic := '0'; - DataSz : integer range 1 to 32 := 8; - abits : integer range 2 to 12 := 8 - ); -port( - rstn : in std_logic; - ReUse : in std_logic; --27/01/12 - rclk : in std_logic; - ren : in std_logic; - rdata : out std_logic_vector(DataSz-1 downto 0); - empty : out std_logic; - raddr : out std_logic_vector(abits-1 downto 0); - wclk : in std_logic; - wen : in std_logic; - wdata : in std_logic_vector(DataSz-1 downto 0); - full : out std_logic; - waddr : out std_logic_vector(abits-1 downto 0) -); -end component; - - -component lppFIFOxN is -generic( - tech : integer := 0; - Mem_use : integer := use_RAM; - Data_sz : integer range 1 to 32 := 8; - Addr_sz : integer range 1 to 32 := 8; - FifoCnt : integer := 1; - Enable_ReUse : std_logic := '0' - ); -port( - rst : in std_logic; - wclk : in std_logic; - rclk : in std_logic; - ReUse : in std_logic_vector(FifoCnt-1 downto 0); - wen : in std_logic_vector(FifoCnt-1 downto 0); - ren : in std_logic_vector(FifoCnt-1 downto 0); - wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); - rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); - full : out std_logic_vector(FifoCnt-1 downto 0); - empty : out std_logic_vector(FifoCnt-1 downto 0) -); -end component; - -component FillFifo is -generic( - Data_sz : integer range 1 to 32 := 16; - Fifo_cnt : integer range 1 to 8 := 5 - ); -port( - clk : in std_logic; - raz : in std_logic; - write : out std_logic_vector(Fifo_cnt-1 downto 0); - reuse : out std_logic_vector(Fifo_cnt-1 downto 0); - data : out std_logic_vector(Fifo_cnt*Data_sz-1 downto 0) -); -end component; - -component ssram_plugin is -generic (tech : integer := 0); -port -( - clk : in std_logic; - mem_ctrlr_o : in memory_out_type; - SSRAM_CLK : out std_logic; - nBWa : out std_logic; - nBWb : out std_logic; - nBWc : out std_logic; - nBWd : out std_logic; - nBWE : out std_logic; - nADSC : out std_logic; - nADSP : out std_logic; - nADV : out std_logic; - nGW : out std_logic; - nCE1 : out std_logic; - CE2 : out std_logic; - nCE3 : out std_logic; - nOE : out std_logic; - MODE : out std_logic; - ZZ : out std_logic -); -end component; - -end; +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------ +library ieee; +use ieee.std_logic_1164.all; +library grlib; +use grlib.amba.all; +use std.textio.all; +library lpp; +use lpp.lpp_amba.all; +use lpp.iir_filter.all; +library gaisler; +use gaisler.misc.all; +use gaisler.memctrl.all; +library techmap; +use techmap.gencomp.all; + +--! Package contenant tous les programmes qui forment le composant intégré dans le léon + +package lpp_memory is + +component APB_FIFO is +generic ( + tech : integer := apa3; + pindex : integer := 0; + paddr : integer := 0; + pmask : integer := 16#fff#; + pirq : integer := 0; + abits : integer := 8; + FifoCnt : integer := 2; + Data_sz : integer := 16; + Addr_sz : integer := 9; + Enable_ReUse : std_logic := '0'; + Mem_use : integer := use_RAM; + R : integer := 1; + W : integer := 1 + ); + port ( + clk : in std_logic; --! Horloge du composant + rst : in std_logic; --! Reset general du composant + rclk : in std_logic; + wclk : in std_logic; + ReUse : in std_logic_vector(FifoCnt-1 downto 0); + REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en mémoire + WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'écriture en mémoire + Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, Mémoire vide + Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, Mémoire pleine + RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de données en entrée + WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de données en sortie + WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (écriture) + RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture) + apbi : in apb_slv_in_type; --! Registre de gestion des entrées du bus + apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus + ); +end component; + + +component lpp_fifo is +generic( + tech : integer := 0; + Mem_use : integer := use_RAM; + Enable_ReUse : std_logic := '0'; + DataSz : integer range 1 to 32 := 8; + AddrSz : integer range 2 to 12 := 8 + ); +port( + rstn : in std_logic; + ReUse : in std_logic; --27/01/12 + rclk : in std_logic; + ren : in std_logic; + rdata : out std_logic_vector(DataSz-1 downto 0); + empty : out std_logic; + raddr : out std_logic_vector(AddrSz-1 downto 0); + wclk : in std_logic; + wen : in std_logic; + wdata : in std_logic_vector(DataSz-1 downto 0); + full : out std_logic; + waddr : out std_logic_vector(AddrSz-1 downto 0) +); +end component; + + +component lppFIFOxN is +generic( + tech : integer := 0; + Mem_use : integer := use_RAM; + Data_sz : integer range 1 to 32 := 8; + Addr_sz : integer range 1 to 32 := 8; + FifoCnt : integer := 1; + Enable_ReUse : std_logic := '0' + ); +port( + rstn : in std_logic; + wclk : in std_logic; + rclk : in std_logic; + ReUse : in std_logic_vector(FifoCnt-1 downto 0); + wen : in std_logic_vector(FifoCnt-1 downto 0); + ren : in std_logic_vector(FifoCnt-1 downto 0); + wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); + rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); + full : out std_logic_vector(FifoCnt-1 downto 0); + empty : out std_logic_vector(FifoCnt-1 downto 0) +); +end component; + +component FillFifo is +generic( + Data_sz : integer range 1 to 32 := 16; + Fifo_cnt : integer range 1 to 8 := 5 + ); +port( + clk : in std_logic; + raz : in std_logic; + write : out std_logic_vector(Fifo_cnt-1 downto 0); + reuse : out std_logic_vector(Fifo_cnt-1 downto 0); + data : out std_logic_vector(Fifo_cnt*Data_sz-1 downto 0) +); +end component; + +component ssram_plugin is +generic (tech : integer := 0); +port +( + clk : in std_logic; + mem_ctrlr_o : in memory_out_type; + SSRAM_CLK : out std_logic; + nBWa : out std_logic; + nBWb : out std_logic; + nBWc : out std_logic; + nBWd : out std_logic; + nBWE : out std_logic; + nADSC : out std_logic; + nADSP : out std_logic; + nADV : out std_logic; + nGW : out std_logic; + nCE1 : out std_logic; + CE2 : out std_logic; + nCE3 : out std_logic; + nOE : out std_logic; + MODE : out std_logic; + ZZ : out std_logic +); +end component; + +end; \ No newline at end of file