@@ -45,10 +45,7 use lpp.lpp_ad_conv.all; | |||
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45 | 45 | use lpp.iir_filter.all; |
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46 | 46 | use lpp.general_purpose.all; |
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47 | 47 | use lpp.Filtercfg.all; |
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48 |
use lpp.lpp_ |
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49 | use lpp.lpp_top_lfr_pkg.all; | |
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50 | use lpp.lpp_dma_pkg.all; | |
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51 | use lpp.lpp_Header.all; | |
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48 | use lpp.lpp_cna.all; | |
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52 | 49 | |
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53 | 50 | entity leon3mp is |
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54 | 51 | generic ( |
@@ -96,28 +93,13 entity leon3mp is | |||
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96 | 93 | --------------------------------------------------------------------- |
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97 | 94 | --- AJOUT TEST ------------------------In/Out----------------------- |
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98 | 95 | --------------------------------------------------------------------- |
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96 | -- DAC | |
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97 | DAC_SYNC : out std_logic; | |
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98 | DAC_SCLK : out std_logic; | |
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99 | DAC_DATA : out std_logic; | |
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99 | 100 | -- UART |
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100 | 101 | UART_RXD : in std_logic; |
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101 | 102 | UART_TXD : out std_logic; |
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102 | -- ACQ | |
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103 | CNV_CH1 : OUT STD_LOGIC; | |
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104 | SCK_CH1 : OUT STD_LOGIC; | |
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105 | SDO_CH1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |
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106 | Bias_Fails : out std_logic; | |
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107 | -- ADC | |
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108 | -- ADC_in : in AD7688_in(4 downto 0); | |
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109 | -- ADC_out : out AD7688_out; | |
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110 | ||
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111 | -- CNA | |
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112 | -- DAC_SYNC : out std_logic; | |
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113 | -- DAC_SCLK : out std_logic; | |
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114 | -- DAC_DATA : out std_logic; | |
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115 | -- Diver | |
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116 | SPW1_EN : out std_logic; | |
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117 | SPW2_EN : out std_logic; | |
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118 | TEST : out std_logic_vector(3 downto 0); | |
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119 | ||
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120 | BP : in std_logic; | |
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121 | 103 | --------------------------------------------------------------------- |
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122 | 104 | led : out std_logic_vector(1 downto 0) |
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123 | 105 | ); |
@@ -126,7 +108,7 end; | |||
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126 | 108 | architecture Behavioral of leon3mp is |
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127 | 109 | |
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128 | 110 | constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+ |
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129 | CFG_GRETH+CFG_AHB_JTAG+1; -- +1 pour le DMA | |
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111 | CFG_GRETH+CFG_AHB_JTAG; | |
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130 | 112 | constant maxahbm : integer := maxahbmsp; |
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131 | 113 | |
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132 | 114 | --Clk & Rst gοΏ½nοΏ½ |
@@ -178,103 +160,7 signal dsuo : dsu_out_type; | |||
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178 | 160 | --------------------------------------------------------------------- |
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179 | 161 | --- AJOUT TEST ------------------------Signaux---------------------- |
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180 | 162 | --------------------------------------------------------------------- |
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181 | -- FIFOs | |
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182 | signal FifoF0_Empty : std_logic_vector(4 downto 0); | |
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183 | signal FifoF0_Data : std_logic_vector(79 downto 0); | |
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184 | signal FifoF1_Empty : std_logic_vector(4 downto 0); | |
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185 | signal FifoF1_Data : std_logic_vector(79 downto 0); | |
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186 | signal FifoF3_Empty : std_logic_vector(4 downto 0); | |
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187 | signal FifoF3_Data : std_logic_vector(79 downto 0); | |
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188 | 163 | |
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189 | signal FifoINT_Full : std_logic_vector(4 downto 0); | |
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190 | signal FifoINT_Data : std_logic_vector(79 downto 0); | |
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191 | ||
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192 | signal FifoOUT_Full : std_logic_vector(1 downto 0); | |
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193 | signal FifoOUT_Empty : std_logic_vector(1 downto 0); | |
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194 | signal FifoOUT_Data : std_logic_vector(63 downto 0); | |
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195 | ||
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196 | ||
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197 | -- MATRICE SPECTRALE | |
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198 | signal SM_FlagError : std_logic; | |
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199 | signal SM_Pong : std_logic; | |
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200 | signal SM_Wen : std_logic; | |
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201 | signal SM_Read : std_logic_vector(4 downto 0); | |
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202 | signal SM_Write : std_logic_vector(1 downto 0); | |
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203 | signal SM_ReUse : std_logic_vector(4 downto 0); | |
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204 | signal SM_Param : std_logic_vector(3 downto 0); | |
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205 | signal SM_Data : std_logic_vector(63 downto 0); | |
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206 | ||
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207 | --signal Dma_acq : std_logic; | |
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208 | --signal Head_Valid : std_logic; | |
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209 | ||
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210 | -- FFT | |
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211 | signal FFT_Load : std_logic; | |
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212 | signal FFT_Read : std_logic_vector(4 downto 0); | |
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213 | signal FFT_Write : std_logic_vector(4 downto 0); | |
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214 | signal FFT_ReUse : std_logic_vector(4 downto 0); | |
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215 | signal FFT_Data : std_logic_vector(79 downto 0); | |
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216 | ||
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217 | -- DEMUX | |
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218 | signal DMUX_Read : std_logic_vector(14 downto 0); | |
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219 | signal DMUX_Empty : std_logic_vector(4 downto 0); | |
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220 | signal DMUX_Data : std_logic_vector(79 downto 0); | |
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221 | signal DMUX_WorkFreq : std_logic_vector(1 downto 0); | |
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222 | ||
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223 | -- ACQ | |
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224 | signal sample_val : STD_LOGIC; | |
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225 | signal sample : Samples(8-1 DOWNTO 0); | |
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226 | ||
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227 | signal ACQ_WenF0 : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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228 | signal ACQ_DataF0 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
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229 | signal ACQ_WenF1 : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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230 | signal ACQ_DataF1 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
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231 | signal ACQ_WenF3 : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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232 | signal ACQ_DataF3 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
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233 | ||
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234 | -- Header | |
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235 | signal Head_Read : std_logic_vector(1 downto 0); | |
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236 | signal Head_Data : std_logic_vector(31 downto 0); | |
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237 | signal Head_Empty : std_logic; | |
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238 | signal Head_Header : std_logic_vector(31 DOWNTO 0); | |
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239 | signal Head_Valid : std_logic; | |
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240 | signal Head_Val : std_logic; | |
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241 | ||
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242 | --DMA | |
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243 | signal DMA_Read : std_logic; | |
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244 | signal DMA_ack : std_logic; | |
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245 | --signal AHB_Master_In : AHB_Mst_In_Type; | |
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246 | --signal AHB_Master_Out : AHB_Mst_Out_Type; | |
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247 | ||
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248 | ||
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249 | -- ADC | |
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250 | --signal SmplClk : std_logic; | |
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251 | --signal ADC_DataReady : std_logic; | |
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252 | --signal ADC_SmplOut : Samples_out(4 downto 0); | |
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253 | --signal enableADC : std_logic; | |
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254 | -- | |
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255 | --signal WG_Write : std_logic_vector(4 downto 0); | |
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256 | --signal WG_ReUse : std_logic_vector(4 downto 0); | |
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257 | --signal WG_DATA : std_logic_vector(79 downto 0); | |
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258 | --signal s_out : std_logic_vector(79 downto 0); | |
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259 | -- | |
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260 | --signal fuller : std_logic_vector(4 downto 0); | |
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261 | --signal reader : std_logic_vector(4 downto 0); | |
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262 | --signal try : std_logic_vector(1 downto 0); | |
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263 | --signal TXDint : std_logic; | |
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264 | -- | |
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265 | ---- IIR Filter | |
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266 | --signal sample_clk_out : std_logic; | |
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267 | -- | |
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268 | --signal Rd : std_logic_vector(0 downto 0); | |
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269 | --signal Ept : std_logic_vector(4 downto 0); | |
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270 | -- | |
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271 | --signal Bwr : std_logic_vector(0 downto 0); | |
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272 | --signal Bre : std_logic_vector(0 downto 0); | |
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273 | --signal DataTMP : std_logic_vector(15 downto 0); | |
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274 | --signal FullUp : std_logic_vector(0 downto 0); | |
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275 | --signal EmptyUp : std_logic_vector(0 downto 0); | |
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276 | --signal FullDown : std_logic_vector(0 downto 0); | |
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277 | --signal EmptyDown : std_logic_vector(0 downto 0); | |
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278 | 164 | --------------------------------------------------------------------- |
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279 | 165 | constant IOAEN : integer := CFG_CAN; |
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280 | 166 | constant boardfreq : integer := 50000; |
@@ -284,245 +170,29 begin | |||
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284 | 170 | --------------------------------------------------------------------- |
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285 | 171 | --- AJOUT TEST -------------------------------------IPs------------- |
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286 | 172 | --------------------------------------------------------------------- |
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287 | led(1 downto 0) <= gpio(1 downto 0); | |
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288 | ||
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289 | --- COM USB --------------------------------------------------------- | |
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290 | -- MemIn0 : APB_FifoWrite | |
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291 | -- generic map (5,5, Data_sz => 8, Addr_sz => 8, addr_max_int => 256) | |
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292 | -- port map (clkm,rstn,apbi,USB_Read,open,open,InOutData,apbo(5)); | |
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293 | -- | |
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294 | -- BUF0 : APB_USB | |
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295 | -- generic map (6,6,DataMax => 1024) | |
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296 | -- port map(clkm,rstn,flagC,flagB,ifclk,sloe,USB_Read,USB_Write,pktend,fifoadr,InOutData,apbi,apbo(6)); | |
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297 | -- | |
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298 | -- MemOut0 : APB_FifoRead | |
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299 | -- generic map (7,7, Data_sz => 8, Addr_sz => 8, addr_max_int => 256) | |
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300 | -- port map (clkm,rstn,apbi,USB_Write,open,open,InOutData,apbo(7)); | |
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301 | -- | |
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302 | --slrd <= usb_Read; | |
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303 | --slwr <= usb_Write; | |
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304 | ||
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305 | --- CNA ------------------------------------------------------------- | |
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306 | ||
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307 | -- CONV : APB_CNA | |
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308 | -- generic map (5,5) | |
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309 | -- port map(clkm,rstn,apbi,apbo(5),DAC_SYNC,DAC_SCLK,DAC_DATA); | |
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310 | ||
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311 | --TEST(0) <= SmplClk; | |
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312 | --TEST(1) <= WG_Write(0); | |
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313 | --TEST(2) <= Fuller(0); | |
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314 | --TEST(3) <= s_out(s_out'length-1); | |
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315 | ||
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316 | ||
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317 | --SPW1_EN <= '1'; | |
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318 | --SPW2_EN <= '0'; | |
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319 | ||
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320 | --- CAN ------------------------------------------------------------- | |
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321 | 173 | |
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322 | -- Divider : Clk_divider | |
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323 | -- generic map(OSC_freqHz => 24_576_000, TargetFreq_Hz => 24_576) | |
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324 | -- Port map(clkm,rstn,SmplClk); | |
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325 | -- | |
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326 | -- ADC : AD7688_drvr | |
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327 | -- generic map (ChanelCount => 5, clkkHz => 24_576) | |
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328 | -- port map (clkm,rstn,enableADC,SmplClk,ADC_DataReady,ADC_SmplOut,ADC_in,ADC_out); | |
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329 | -- | |
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330 | -- WG : WriteGen_ADC | |
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331 | -- port map (clkm,rstn,SmplClk,ADC_DataReady,Fuller,WG_ReUse,WG_Write); | |
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332 | -- | |
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333 | --enableADC <= gpio(0); | |
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174 | -- apbo not free : 0 1 2 3 7 11 | |
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334 | 175 | |
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335 | --WG_DATA <= ADC_SmplOut(4) & ADC_SmplOut(3) & ADC_SmplOut(2) & ADC_SmplOut(1) & ADC_SmplOut(0); | |
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336 | -- | |
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337 | -- | |
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338 | -- MemIn1 : APB_FIFO | |
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339 | -- generic map (pindex => 6, paddr => 6, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) | |
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340 | -- port map (clkm,rstn,clkm,clkm,WG_ReUse,(others => '1'),WG_Write,open,Fuller,open,WG_DATA,open,open,apbi,apbo(6)); | |
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341 | ||
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342 | -- DIGITAL_acquisition : ADS7886_drvr | |
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343 | -- GENERIC MAP ( | |
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344 | -- ChanelCount => 8, | |
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345 | -- ncycle_cnv_high => 79, | |
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346 | -- ncycle_cnv => 500) | |
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347 | -- PORT MAP ( | |
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348 | -- cnv_clk => clk50MHz, -- | |
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349 | -- cnv_rstn => rstn, -- | |
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350 | -- cnv_run => '1', -- | |
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351 | -- cnv => CNV_CH1, -- | |
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352 | -- clk => clkm, -- | |
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353 | -- rstn => rstn, -- | |
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354 | -- sck => SCK_CH1, -- | |
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355 | -- sdo => SDO_CH1, -- | |
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356 | -- sample => sample, | |
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357 | -- sample_val => sample_val); | |
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358 | -- | |
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359 | --TopACQ_WenF0 <= not sample_filter_v2_out_val & not sample_filter_v2_out_val & not sample_filter_v2_out_val & not sample_filter_v2_out_val & not sample_filter_v2_out_val; | |
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360 | --TopACQ_DataF0 <= E & D & C & B & A; | |
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361 | ||
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362 | -- | |
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363 | --TEST(0) <= TopACQ_WenF0(1); | |
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364 | --TEST(1) <= SDO_CH1(1); | |
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365 | -- | |
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366 | --process(clkm,rstn) | |
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367 | --begin | |
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368 | -- if(rstn='0')then | |
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369 | -- TopACQ_WenF0a <= (others => '1'); | |
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370 | -- | |
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371 | -- elsif(clkm'event and clkm='1')then | |
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372 | -- TopACQ_WenF0a <= not sample_val & not sample_val & not sample_val & not sample_val & not sample_val; | |
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373 | -- | |
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374 | -- end if; | |
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375 | --end process; | |
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376 | ||
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377 | ACQ0 : lpp_top_acq | |
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378 | port map('1',CNV_CH1,SCK_CH1,SDO_CH1,clk50MHz,rstn,clkm,rstn,ACQ_WenF0,ACQ_DataF0,ACQ_WenF1,ACQ_DataF1,open,open,ACQ_WenF3,ACQ_DataF3); | |
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176 | --- DAC ------------------------------------------------------------- | |
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379 | 177 | |
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380 | Bias_Fails <= '0'; | |
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381 | --------- FIFO IN ------------------------------------------------------------- | |
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382 | ---- | |
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383 | -- Memf0 : APB_FIFO | |
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384 | -- generic map (pindex => 9, paddr => 9, FifoCnt => 5, Data_sz => 16, Addr_sz => 9, Enable_ReUse => '0', R => 1, W => 0) | |
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385 | -- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),ACQ_WenF0,open,open,open,ACQ_DataF0,open,open,apbi,apbo(9)); | |
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386 | -- | |
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387 | -- Memf1 : APB_FIFO | |
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388 | -- generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) | |
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389 | -- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),ACQ_WenF1,open,open,open,ACQ_DataF1,open,open,apbi,apbo(8)); | |
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390 | -- | |
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391 | -- Memf3 : APB_FIFO | |
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392 | -- generic map (pindex => 5, paddr => 5, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) | |
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393 | -- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),ACQ_WenF3,open,open,open,ACQ_DataF3,open,open,apbi,apbo(5)); | |
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394 | ||
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395 | Memf0 : lppFIFOxN | |
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396 | generic map(Data_sz => 16, Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0') | |
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397 | port map(rstn,clkm,clkm,(others => '0'),ACQ_WenF0,DMUX_Read(4 downto 0),ACQ_DataF0,FifoF0_Data,open,FifoF0_Empty); | |
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398 | ||
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399 | Memf1 : lppFIFOxN | |
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400 | generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') | |
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401 | port map(rstn,clkm,clkm,(others => '0'),ACQ_WenF1,DMUX_Read(9 downto 5),ACQ_DataF1,FifoF1_Data,open,FifoF1_Empty); | |
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402 | ||
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403 | Memf3 : lppFIFOxN | |
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404 | generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') | |
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405 | port map(rstn,clkm,clkm,(others => '0'),ACQ_WenF3,DMUX_Read(14 downto 10),ACQ_DataF3,FifoF3_Data,open,FifoF3_Empty); | |
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406 | -- | |
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407 | ----- DEMUX ------------------------------------------------------------- | |
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408 | ||
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409 | DMUX0 : DEMUX | |
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410 | generic map(Data_sz => 16) | |
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411 | port map(clkm,rstn,FFT_Read,FFT_Load,FifoF0_Empty,FifoF1_Empty,FifoF3_Empty,FifoF0_Data,FifoF1_Data,FifoF3_Data,DMUX_WorkFreq,DMUX_Read,DMUX_Empty,DMUX_Data); | |
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412 | ||
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413 | ------- FFT ------------------------------------------------------------- | |
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414 | ||
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415 | -- MemIn : APB_FIFO | |
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416 | -- generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1) | |
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417 | -- port map (clkm,rstn,clkm,clkm,(others => '0'),FFT_Read,(others => '1'),DMUX_Empty,open,DMUX_Data,(others => '0'),open,open,apbi,apbo(8)); | |
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418 | ||
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419 | FFT0 : FFT | |
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420 | generic map(Data_sz => 16,NbData => 256) | |
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421 | port map(clkm,rstn,DMUX_Empty,DMUX_Data,FifoINT_Full,FFT_Load,FFT_Read,FFT_Write,FFT_ReUse,FFT_Data); | |
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422 | ||
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423 | --------- LINK MEMORY ------------------------------------------------------- | |
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424 | ||
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425 | -- MemOut : APB_FIFO | |
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426 | -- generic map (pindex => 9, paddr => 9, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 0) | |
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427 | -- port map (clkm,rstn,clkm,clkm,FFT_ReUse,(others =>'1'),FFT_Write,open,FifoINT_Full,open,FFT_Data,open,open,apbi,apbo(9)); | |
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428 | ||
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429 | MemInt : lppFIFOxN | |
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430 | generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '1') | |
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431 | port map(rstn,clkm,clkm,SM_ReUse,FFT_Write,SM_Read,FFT_Data,FifoINT_Data,FifoINT_Full,open); | |
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178 | CAL0 : APB_CNA | |
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179 | generic map (pindex => 4, paddr => 4) | |
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180 | port map(clkm,rstn,apbi,apbo(4),DAC_SYNC,DAC_SCLK,DAC_DATA); | |
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432 | 181 | |
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433 | -- MemIn : APB_FIFO | |
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434 | -- generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 0, W => 1) | |
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435 | -- port map (clkm,rstn,clkm,clkm,(others => '0'),SM_Read,(others => '1'),open,FifoINT_Full,FifoINT_Data,(others => '0'),open,open,apbi,apbo(8)); | |
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436 | ||
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437 | ----- MATRICE SPECTRALE ---------------------5 FIFO Input--------------- | |
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438 | ||
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439 | SM0 : MatriceSpectrale | |
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440 | generic map(Input_SZ => 16,Result_SZ => 32) | |
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441 | port map(clkm,rstn,FifoINT_Full,FFT_ReUse,Head_Valid,FifoINT_Data,DMA_ack,SM_Wen,SM_FlagError,SM_Pong,SM_Param,SM_Write,SM_Read,SM_ReUse,SM_Data); | |
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442 | ||
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443 | ||
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444 | --DMA_ack <= '1'; | |
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445 | --Head_Valid <= '1'; | |
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446 | ||
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447 | -- MemOut : APB_FIFO | |
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448 | -- generic map (pindex => 9, paddr => 9, FifoCnt => 2, Data_sz => 32, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) | |
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449 | -- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),SM_Write,open,FifoOUT_Full,open,SM_Data,open,open,apbi,apbo(9)); | |
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450 | ||
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451 | MemOut : lppFIFOxN | |
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452 | generic map(Data_sz => 32, Addr_sz => 8, FifoCnt => 2, Enable_ReUse => '0') | |
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453 | port map(rstn,clkm,clkm,(others => '0'),SM_Write,Head_Read,SM_Data,FifoOUT_Data,FifoOUT_Full,FifoOUT_Empty); | |
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454 | ||
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455 | ----------- Header ------------------------------------------------------- | |
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456 | ||
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457 | Head0 : HeaderBuilder | |
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458 | generic map(Data_sz => 32) | |
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459 | port map(clkm,rstn,SM_Pong,SM_Param,DMUX_WorkFreq,SM_Wen,Head_Valid,FifoOUT_Data,FifoOUT_Empty,Head_Read,Head_Data,Head_Empty,DMA_Read,Head_Header,Head_Val,DMA_ack); | |
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460 | ||
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461 | ||
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462 | --- DMA ------------------------------------------------------- | |
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463 | ||
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464 | DMA0 : lpp_dma | |
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465 | generic map(hindex => 1,pindex => 9, paddr => 9,pirq => 14, pmask =>16#fff#,tech => CFG_FABTECH) | |
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466 | port map(clkm,rstn,apbi,apbo(9),ahbmi,ahbmo(1),Head_Data,Head_Empty,DMA_Read,Head_Header,Head_Val,DMA_ack); | |
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467 | ||
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468 | ||
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469 | ----- FIFO ------------------------------------------------------------- | |
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470 | ||
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471 | -- Memtest : APB_FIFO | |
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472 | -- generic map (pindex => 5, paddr => 5, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 1) | |
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473 | -- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),(others => '1'),open,open,open,(others => '0'),open,open,apbi,apbo(5)); | |
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474 | ||
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475 | --***************************************TEST DEMI-FIFO******************************************************************************** | |
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476 | -- MemIn : APB_FIFO | |
|
477 | -- generic map (pindex => 8, paddr => 8, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1) | |
|
478 | -- port map (clkm,rstn,clkm,clkm,(others => '0'),Bre,(others => '1'),EmptyUp,FullUp,DataTMP,(others => '0'),open,open,apbi,apbo(8)); | |
|
479 | -- | |
|
480 | -- Pont : Bridge | |
|
481 | -- port map(clkm,rstn,EmptyUp(0),FullDown(0),Bwr(0),Bre(0)); | |
|
482 | -- | |
|
483 | -- MemOut : APB_FIFO | |
|
484 | -- generic map (pindex => 9, paddr => 9, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) | |
|
485 | -- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),Bwr,EmptyDown,FullDown,open,DataTMP,open,open,apbi,apbo(9)); | |
|
486 | --************************************************************************************************************************************* | |
|
487 | 182 | |
|
488 | 183 | --- UART ------------------------------------------------------------- |
|
489 | 184 | |
|
490 | 185 | COM0 : APB_UART |
|
491 |
generic map (pindex => |
|
|
492 |
port map (clkm,rstn,apbi,apbo( |
|
|
186 | generic map (pindex => 5, paddr => 5) | |
|
187 | port map (clkm,rstn,apbi,apbo(5),UART_TXD,UART_RXD); | |
|
493 | 188 | |
|
494 | --- DELAY ------------------------------------------------------------ | |
|
495 | ||
|
496 | -- Delay0 : APB_Delay | |
|
497 | -- generic map (pindex => 4, paddr => 4) | |
|
498 | -- port map (clkm,rstn,apbi,apbo(4)); | |
|
499 | 189 | |
|
500 |
--- |
|
|
501 | --Test(0) <= sample_clk_out; | |
|
502 | -- | |
|
503 | -- | |
|
504 | -- IIR1: APB_IIR_Filter | |
|
505 | -- generic map( | |
|
506 | -- tech => CFG_MEMTECH, | |
|
507 | -- pindex => 8, | |
|
508 | -- paddr => 8, | |
|
509 | -- Sample_SZ => Sample_SZ, | |
|
510 | -- ChanelsCount => ChanelsCount, | |
|
511 | -- Coef_SZ => Coef_SZ, | |
|
512 | -- CoefCntPerCel => CoefCntPerCel, | |
|
513 | -- Cels_count => Cels_count, | |
|
514 | -- virgPos => virgPos | |
|
515 | -- ) | |
|
516 | -- port map( | |
|
517 | -- rst => rstn, | |
|
518 | -- clk => clkm, | |
|
519 | -- apbi => apbi, | |
|
520 | -- apbo => apbo(8), | |
|
521 | -- sample_clk_out => sample_clk_out, | |
|
522 | -- GOtest => Test(1), | |
|
523 | -- CoefsInitVal => (others => '1') | |
|
524 | -- ); | |
|
525 | ---------------------------------------------------------------------- | |
|
190 | --- FIFO ------------------------------------------------------------- | |
|
191 | ||
|
192 | Memtest : APB_FIFO | |
|
193 | generic map (pindex => 6, paddr => 6, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 1) | |
|
194 | port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),(others => '1'),open,open,open,(others => '0'),open,open,apbi,apbo(6)); | |
|
195 | ||
|
526 | 196 | |
|
527 | 197 | ---------------------------------------------------------------------- |
|
528 | 198 | --- Reset and Clock generation ------------------------------------- |
@@ -637,8 +307,8 end process; | |||
|
637 | 307 | |
|
638 | 308 | dcomgen : if CFG_AHB_UART = 1 generate |
|
639 | 309 | dcom0: ahbuart -- Debug UART |
|
640 |
generic map (hindex => |
|
|
641 |
port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo( |
|
|
310 | generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7) | |
|
311 | port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU)); | |
|
642 | 312 | dsurx_pad : inpad generic map (tech => padtech) port map (ahbrxd, ahbuarti.rxd); |
|
643 | 313 | dsutx_pad : outpad generic map (tech => padtech) port map (ahbtxd, ahbuarto.txd); |
|
644 | 314 | -- led(0) <= not ahbuarti.rxd; led(1) <= not ahbuarto.txd; |
@@ -687,6 +357,7 end process; | |||
|
687 | 357 | ---------------------------------------------------------------------- |
|
688 | 358 | --- GPIO ----------------------------------------------------------- |
|
689 | 359 | ---------------------------------------------------------------------- |
|
360 | led(0) <= gpio(0); led(1) <= gpio(1); | |
|
690 | 361 | |
|
691 | 362 | gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit |
|
692 | 363 | grgpio0: grgpio |
@@ -30,7 +30,6 entity HeaderBuilder is | |||
|
30 | 30 | clkm : in std_logic; |
|
31 | 31 | rstn : in std_logic; |
|
32 | 32 | |
|
33 | pong : in std_logic; | |
|
34 | 33 | Statu : in std_logic_vector(3 downto 0); |
|
35 | 34 | Matrix_Type : in std_logic_vector(1 downto 0); |
|
36 | 35 | Matrix_Write : in std_logic; |
@@ -57,7 +56,6 signal Matrix_Param : std_logic_vect | |||
|
57 | 56 | signal Write_reg : std_logic; |
|
58 | 57 | signal Data_cpt : integer; |
|
59 | 58 | signal MAX : integer; |
|
60 | signal pong_reg : std_logic; | |
|
61 | 59 | |
|
62 | 60 | type etat is (idle0,idle1,pong0,pong1); |
|
63 | 61 | signal ect : etat; |
@@ -69,7 +67,6 begin | |||
|
69 | 67 | if(rstn='0')then |
|
70 | 68 | ect <= idle0; |
|
71 | 69 | Valid <= '0'; |
|
72 | pong_reg <= '0'; | |
|
73 | 70 | header_val <= '0'; |
|
74 | 71 | header(5 downto 0) <= (others => '0'); |
|
75 | 72 | Write_reg <= '0'; |
@@ -79,7 +76,6 begin | |||
|
79 | 76 | |
|
80 | 77 | elsif(clkm' event and clkm='1')then |
|
81 | 78 | Write_reg <= Matrix_Write; |
|
82 | pong_reg <= pong; | |
|
83 | 79 | |
|
84 | 80 | if(Statu="0001" or Statu="0011" or Statu="0110" or Statu="1010" or Statu="1111")then |
|
85 | 81 | MAX <= 128; |
@@ -87,17 +83,6 begin | |||
|
87 | 83 | MAX <= 256; |
|
88 | 84 | end if; |
|
89 | 85 | |
|
90 | -- if(Write_reg = '0' and Matrix_Write = '1')then | |
|
91 | -- if(Data_cpt = MAX)then | |
|
92 | -- Data_cpt <= 0; | |
|
93 | -- Valid <= '1'; | |
|
94 | -- header_val <= '1'; | |
|
95 | -- else | |
|
96 | -- Data_cpt <= Data_cpt + 1; | |
|
97 | -- Valid <= '0'; | |
|
98 | -- end if; | |
|
99 | -- end if; | |
|
100 | ||
|
101 | 86 | if(Write_reg = '0' and Matrix_Write = '1')then |
|
102 | 87 | Data_cpt <= Data_cpt + 1; |
|
103 | 88 | Valid <= '0'; |
@@ -107,19 +92,7 begin | |||
|
107 | 92 | header_val <= '1'; |
|
108 | 93 | else |
|
109 | 94 | Valid <= '0'; |
|
110 | end if; | |
|
111 | ||
|
112 | -- if(header_ack = '1')then | |
|
113 | -- header_val <= '0'; | |
|
114 | -- end if; | |
|
115 | ||
|
116 | -- if(emptyIN = "10")then | |
|
117 | -- ping <= '0'; | |
|
118 | -- elsif(emptyIN = "01")then | |
|
119 | -- ping <= '1'; | |
|
120 | -- else | |
|
121 | -- ping <= ping; | |
|
122 | -- end if; | |
|
95 | end if; | |
|
123 | 96 |
|
|
124 | 97 |
|
|
125 | 98 |
|
@@ -127,11 +100,7 begin | |||
|
127 | 100 | when idle0 => |
|
128 | 101 | if(header_ack = '1')then |
|
129 | 102 | header_val <= '0'; |
|
130 |
|
|
|
131 | ect <= pong0; | |
|
132 | --elsif(pong = '0')then | |
|
133 | --ect <= pong1; | |
|
134 | --end if; | |
|
103 | ect <= pong0; | |
|
135 | 104 | end if; |
|
136 | 105 | |
|
137 | 106 | when pong0 => |
@@ -160,8 +129,6 begin | |||
|
160 | 129 | |
|
161 | 130 | Matrix_Param <= std_logic_vector(to_unsigned(to_integer(unsigned(Statu))-1,4)); |
|
162 | 131 | |
|
163 | --header(1 downto 0) <= Matrix_Type; | |
|
164 | --header(5 downto 2) <= Matrix_Param; | |
|
165 | 132 | header(31 downto 6) <= (others => '0'); |
|
166 | 133 | |
|
167 | 134 | with ect select |
@@ -38,7 +38,6 component HeaderBuilder is | |||
|
38 | 38 | clkm : in std_logic; |
|
39 | 39 | rstn : in std_logic; |
|
40 | 40 | |
|
41 | pong : in std_logic; | |
|
42 | 41 | Statu : in std_logic_vector(3 downto 0); |
|
43 | 42 | Matrix_Type : in std_logic_vector(1 downto 0); |
|
44 | 43 | Matrix_Write : in std_logic; |
@@ -44,37 +44,37 end CNA_TabloC; | |||
|
44 | 44 | |
|
45 | 45 | architecture ar_CNA_TabloC of CNA_TabloC is |
|
46 | 46 | |
|
47 | component CLKINT | |
|
48 | port( A : in std_logic := 'U'; | |
|
49 | Y : out std_logic); | |
|
50 | end component; | |
|
47 | --component CLKINT | |
|
48 | --port( A : in std_logic := 'U'; | |
|
49 | -- Y : out std_logic); | |
|
50 | --end component; | |
|
51 | 51 | |
|
52 | signal clk : std_logic; | |
|
52 | --signal clk : std_logic; | |
|
53 | 53 | |
|
54 | signal raz : std_logic; | |
|
54 | --signal raz : std_logic; | |
|
55 | 55 | signal s_SCLK : std_logic; |
|
56 | 56 | signal OKAI_send : std_logic; |
|
57 | 57 | |
|
58 | 58 | begin |
|
59 | 59 | |
|
60 | CLKINT_0 : CLKINT | |
|
61 | port map(A => clock, Y => clk); | |
|
60 | --CLKINT_0 : CLKINT | |
|
61 | -- port map(A => clock, Y => clk); | |
|
62 | 62 | |
|
63 | CLKINT_1 : CLKINT | |
|
64 | port map(A => rst, Y => raz); | |
|
63 | --CLKINT_1 : CLKINT | |
|
64 | -- port map(A => rst, Y => raz); | |
|
65 | 65 | |
|
66 | 66 | |
|
67 | 67 | SystemCLK : entity work.Systeme_Clock |
|
68 | 68 | generic map (nb_serial) |
|
69 |
port map (clk,r |
|
|
69 | port map (clock,rst,s_SCLK); | |
|
70 | 70 | |
|
71 | 71 | |
|
72 | 72 | Signal_sync : entity work.Gene_SYNC |
|
73 |
port map (s_SCLK,r |
|
|
73 | port map (s_SCLK,rst,enable,OKAI_send,SYNC); | |
|
74 | 74 | |
|
75 | 75 | |
|
76 | 76 | Serial : entity work.serialize |
|
77 |
port map (clk,r |
|
|
77 | port map (clock,rst,s_SCLK,Data_C,OKAI_send,flag_sd,Data); | |
|
78 | 78 | |
|
79 | 79 | |
|
80 | 80 | SCLK <= s_SCLK; |
@@ -29,14 +29,12 generic( | |||
|
29 | 29 | port( |
|
30 | 30 | clk : in std_logic; |
|
31 | 31 | reset : in std_logic; |
|
32 |
Ac |
|
|
32 | Ack : in std_logic; | |
|
33 | 33 | Data : in std_logic_vector(Data_SZ-1 downto 0); |
|
34 | 34 | Write : in std_logic; |
|
35 | 35 | Valid : in std_logic; |
|
36 | -- Full : in std_logic_vector(1 downto 0); | |
|
37 | 36 | FifoData : out std_logic_vector(2*Data_SZ-1 downto 0); |
|
38 | 37 | FifoWrite : out std_logic_vector(1 downto 0); |
|
39 | Pong : out std_logic; | |
|
40 | 38 | Error : out std_logic |
|
41 | 39 | ); |
|
42 | 40 | end entity; |
@@ -47,15 +45,14 architecture ar_Dispatch of Dispatch is | |||
|
47 | 45 | type etat is (eX,e0,e1,e2); |
|
48 | 46 | signal ect : etat; |
|
49 | 47 | |
|
50 |
signal Pong |
|
|
51 | --signal FifoCpt : integer range 0 to 1 := 0; | |
|
48 | signal Pong : std_logic; | |
|
52 | 49 | |
|
53 | 50 | begin |
|
54 | 51 | |
|
55 | 52 | process (clk,reset) |
|
56 | 53 | begin |
|
57 | 54 | if(reset='0')then |
|
58 |
Pong |
|
|
55 | Pong <= '0'; | |
|
59 | 56 | Error <= '0'; |
|
60 | 57 | ect <= e0; |
|
61 | 58 | |
@@ -64,14 +61,13 begin | |||
|
64 | 61 | case ect is |
|
65 | 62 | |
|
66 | 63 | when e0 => |
|
67 | -- if(Full(FifoCpt) = '1')then | |
|
68 | 64 | if(Valid = '1')then |
|
69 |
Pong |
|
|
65 | Pong <= not Pong; | |
|
70 | 66 | ect <= e1; |
|
71 | 67 | end if; |
|
72 | 68 | |
|
73 | 69 | when e1 => |
|
74 |
if(Ac |
|
|
70 | if(Ack = '0')then | |
|
75 | 71 | Error <= '1'; |
|
76 | 72 | ect <= e1; |
|
77 | 73 | else |
@@ -80,7 +76,7 begin | |||
|
80 | 76 | end if; |
|
81 | 77 | |
|
82 | 78 | when others => |
|
83 |
null; |
|
|
79 | null; | |
|
84 | 80 | |
|
85 | 81 | end case; |
|
86 | 82 | |
@@ -88,10 +84,6 begin | |||
|
88 | 84 | end process; |
|
89 | 85 | |
|
90 | 86 | FifoData <= Data & Data; |
|
91 | Pong <= Pong_int; | |
|
92 | ||
|
93 | --FifoCpt <= 0 when Pong_int='0' else 1; | |
|
94 | ||
|
95 | FifoWrite <= '1' & not Write when Pong_int='0' else not Write & '1'; | |
|
87 | FifoWrite <= '1' & not Write when Pong='0' else not Write & '1'; | |
|
96 | 88 | |
|
97 | 89 | end architecture; No newline at end of file |
@@ -35,13 +35,11 entity MatriceSpectrale is | |||
|
35 | 35 | |
|
36 | 36 | FifoIN_Full : in std_logic_vector(4 downto 0); |
|
37 | 37 | SetReUse : in std_logic_vector(4 downto 0); |
|
38 | -- FifoOUT_Full : in std_logic_vector(1 downto 0); | |
|
39 | 38 | Valid : in std_logic; |
|
40 | 39 | Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0); |
|
41 |
AC |
|
|
40 | ACK : in std_logic; | |
|
42 | 41 | SM_Write : out std_logic; |
|
43 | 42 | FlagError : out std_logic; |
|
44 | Pong : out std_logic; | |
|
45 | 43 | Statu : out std_logic_vector(3 downto 0); |
|
46 | 44 | Write : out std_logic_vector(1 downto 0); |
|
47 | 45 | Read : out std_logic_vector(4 downto 0); |
@@ -78,7 +76,7 begin | |||
|
78 | 76 | |
|
79 | 77 | DISP : Dispatch |
|
80 | 78 | generic map(Result_SZ) |
|
81 |
port map(clkm,rstn,AC |
|
|
79 | port map(clkm,rstn,ACK,Matrix_Result,Matrix_Write,Valid,Data_OUT,Write,FlagError); | |
|
82 | 80 | |
|
83 | 81 | Statu <= TopSM_Statu; |
|
84 | 82 | SM_Write <= Matrix_Write; |
@@ -66,13 +66,11 component MatriceSpectrale is | |||
|
66 | 66 | |
|
67 | 67 | FifoIN_Full : in std_logic_vector(4 downto 0); |
|
68 | 68 | SetReUse : in std_logic_vector(4 downto 0); |
|
69 | -- FifoOUT_Full : in std_logic_vector(1 downto 0); | |
|
70 | 69 | Valid : in std_logic; |
|
71 | 70 | Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0); |
|
72 |
AC |
|
|
71 | ACK : in std_logic; | |
|
73 | 72 | SM_Write : out std_logic; |
|
74 | 73 | FlagError : out std_logic; |
|
75 | Pong : out std_logic; | |
|
76 | 74 | Statu : out std_logic_vector(3 downto 0); |
|
77 | 75 | Write : out std_logic_vector(1 downto 0); |
|
78 | 76 | Read : out std_logic_vector(4 downto 0); |
@@ -199,14 +197,12 generic( | |||
|
199 | 197 | port( |
|
200 | 198 | clk : in std_logic; |
|
201 | 199 | reset : in std_logic; |
|
202 |
Ac |
|
|
200 | Ack : in std_logic; | |
|
203 | 201 | Data : in std_logic_vector(Data_SZ-1 downto 0); |
|
204 | 202 | Write : in std_logic; |
|
205 | 203 | Valid : in std_logic; |
|
206 | -- Full : in std_logic_vector(1 downto 0); | |
|
207 | 204 | FifoData : out std_logic_vector(2*Data_SZ-1 downto 0); |
|
208 | 205 | FifoWrite : out std_logic_vector(1 downto 0); |
|
209 | Pong : out std_logic; | |
|
210 | 206 | Error : out std_logic |
|
211 | 207 | ); |
|
212 | 208 | end component; |
@@ -1,66 +1,65 | |||
|
1 | ------------------------------------------------------------------------------ | |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
|
3 | -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS | |
|
4 | -- | |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
|
6 | -- it under the terms of the GNU General Public License as published by | |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
|
8 | -- (at your option) any later version. | |
|
9 | -- | |
|
10 | -- This program is distributed in the hope that it will be useful, | |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
|
13 | -- GNU General Public License for more details. | |
|
14 | -- | |
|
15 | -- You should have received a copy of the GNU General Public License | |
|
16 | -- along with this program; if not, write to the Free Software | |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
|
18 | ------------------------------------------------------------------------------ | |
|
19 | -- Author : Martin Morlot | |
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |
|
21 | ------------------------------------------------------------------------------ | |
|
22 | library IEEE; | |
|
23 | use IEEE.std_logic_1164.all; | |
|
24 | use IEEE.numeric_std.all; | |
|
25 | library lpp; | |
|
26 | use lpp.lpp_memory.all; | |
|
27 | use lpp.iir_filter.all; | |
|
28 | library techmap; | |
|
29 | use techmap.gencomp.all; | |
|
30 | ||
|
31 | entity lppFIFOxN is | |
|
32 | generic( | |
|
33 | tech : integer := 0; | |
|
34 | Mem_use : integer := use_RAM; | |
|
35 | Data_sz : integer range 1 to 32 := 8; | |
|
36 |
Addr_sz : integer range |
|
|
37 | FifoCnt : integer := 1; | |
|
38 | Enable_ReUse : std_logic := '0' | |
|
39 | ); | |
|
40 | port( | |
|
41 | rst : in std_logic; | |
|
42 | wclk : in std_logic; | |
|
43 | rclk : in std_logic; | |
|
44 | ReUse : in std_logic_vector(FifoCnt-1 downto 0); | |
|
45 | wen : in std_logic_vector(FifoCnt-1 downto 0); | |
|
46 | ren : in std_logic_vector(FifoCnt-1 downto 0); | |
|
47 | wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); | |
|
48 | rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); | |
|
49 | full : out std_logic_vector(FifoCnt-1 downto 0); | |
|
50 | empty : out std_logic_vector(FifoCnt-1 downto 0) | |
|
51 | ); | |
|
52 | end entity; | |
|
53 | ||
|
54 | ||
|
55 | architecture ar_lppFIFOxN of lppFIFOxN is | |
|
56 | ||
|
57 | begin | |
|
58 | ||
|
59 | fifos: for i in 0 to FifoCnt-1 generate | |
|
60 | FIFO0 : lpp_fifo | |
|
61 | generic map (tech,Mem_use,Enable_ReUse,Data_sz,Addr_sz) | |
|
62 | port map(rst,ReUse(i),rclk,ren(i),rdata((i+1)*Data_sz-1 downto i*Data_sz),empty(i),open,wclk,wen(i),wdata((i+1)*Data_sz-1 downto i*Data_sz),full(i),open); | |
|
63 | end generate; | |
|
64 | ||
|
65 | end architecture; | |
|
66 | ||
|
1 | ------------------------------------------------------------------------------ | |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
|
3 | -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS | |
|
4 | -- | |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
|
6 | -- it under the terms of the GNU General Public License as published by | |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
|
8 | -- (at your option) any later version. | |
|
9 | -- | |
|
10 | -- This program is distributed in the hope that it will be useful, | |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
|
13 | -- GNU General Public License for more details. | |
|
14 | -- | |
|
15 | -- You should have received a copy of the GNU General Public License | |
|
16 | -- along with this program; if not, write to the Free Software | |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
|
18 | ------------------------------------------------------------------------------ | |
|
19 | -- Author : Martin Morlot | |
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |
|
21 | ------------------------------------------------------------------------------ | |
|
22 | library IEEE; | |
|
23 | use IEEE.std_logic_1164.all; | |
|
24 | use IEEE.numeric_std.all; | |
|
25 | library lpp; | |
|
26 | use lpp.lpp_memory.all; | |
|
27 | use lpp.iir_filter.all; | |
|
28 | library techmap; | |
|
29 | use techmap.gencomp.all; | |
|
30 | ||
|
31 | entity lppFIFOxN is | |
|
32 | generic( | |
|
33 | tech : integer := 0; | |
|
34 | Mem_use : integer := use_RAM; | |
|
35 | Data_sz : integer range 1 to 32 := 8; | |
|
36 | Addr_sz : integer range 2 to 12 := 8; | |
|
37 | FifoCnt : integer := 1; | |
|
38 | Enable_ReUse : std_logic := '0' | |
|
39 | ); | |
|
40 | port( | |
|
41 | rstn : in std_logic; | |
|
42 | wclk : in std_logic; | |
|
43 | rclk : in std_logic; | |
|
44 | ReUse : in std_logic_vector(FifoCnt-1 downto 0); | |
|
45 | wen : in std_logic_vector(FifoCnt-1 downto 0); | |
|
46 | ren : in std_logic_vector(FifoCnt-1 downto 0); | |
|
47 | wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); | |
|
48 | rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); | |
|
49 | full : out std_logic_vector(FifoCnt-1 downto 0); | |
|
50 | empty : out std_logic_vector(FifoCnt-1 downto 0) | |
|
51 | ); | |
|
52 | end entity; | |
|
53 | ||
|
54 | ||
|
55 | architecture ar_lppFIFOxN of lppFIFOxN is | |
|
56 | ||
|
57 | begin | |
|
58 | ||
|
59 | fifos: for i in 0 to FifoCnt-1 generate | |
|
60 | FIFO0 : lpp_fifo | |
|
61 | generic map (tech,Mem_use,Enable_ReUse,Data_sz,Addr_sz) | |
|
62 | port map(rstn,ReUse(i),rclk,ren(i),rdata((i+1)*Data_sz-1 downto i*Data_sz),empty(i),open,wclk,wen(i),wdata((i+1)*Data_sz-1 downto i*Data_sz),full(i),open); | |
|
63 | end generate; | |
|
64 | ||
|
65 | end architecture; |
@@ -34,7 +34,7 generic( | |||
|
34 | 34 | Mem_use : integer := use_RAM; |
|
35 | 35 | Enable_ReUse : std_logic := '0'; |
|
36 | 36 | DataSz : integer range 1 to 32 := 8; |
|
37 |
|
|
|
37 | AddrSz : integer range 2 to 12 := 8 | |
|
38 | 38 | ); |
|
39 | 39 | port( |
|
40 | 40 | rstn : in std_logic; |
@@ -43,12 +43,12 port( | |||
|
43 | 43 | ren : in std_logic; |
|
44 | 44 | rdata : out std_logic_vector(DataSz-1 downto 0); |
|
45 | 45 | empty : out std_logic; |
|
46 |
raddr : out std_logic_vector( |
|
|
46 | raddr : out std_logic_vector(AddrSz-1 downto 0); | |
|
47 | 47 | wclk : in std_logic; |
|
48 | 48 | wen : in std_logic; |
|
49 | 49 | wdata : in std_logic_vector(DataSz-1 downto 0); |
|
50 | 50 | full : out std_logic; |
|
51 |
waddr : out std_logic_vector( |
|
|
51 | waddr : out std_logic_vector(AddrSz-1 downto 0) | |
|
52 | 52 | ); |
|
53 | 53 | end entity; |
|
54 | 54 | |
@@ -65,10 +65,10 signal sWEN : std_logic; | |||
|
65 | 65 | signal sRE : std_logic; |
|
66 | 66 | signal sWE : std_logic; |
|
67 | 67 | |
|
68 |
signal Waddr_vect : std_logic_vector( |
|
|
69 |
signal Raddr_vect : std_logic_vector( |
|
|
70 |
signal Waddr_vect_s : std_logic_vector( |
|
|
71 |
signal Raddr_vect_s : std_logic_vector( |
|
|
68 | signal Waddr_vect : std_logic_vector(AddrSz-1 downto 0):=(others =>'0'); | |
|
69 | signal Raddr_vect : std_logic_vector(AddrSz-1 downto 0):=(others =>'0'); | |
|
70 | signal Waddr_vect_s : std_logic_vector(AddrSz-1 downto 0):=(others =>'0'); | |
|
71 | signal Raddr_vect_s : std_logic_vector(AddrSz-1 downto 0):=(others =>'0'); | |
|
72 | 72 | |
|
73 | 73 | begin |
|
74 | 74 | |
@@ -78,13 +78,13 begin | |||
|
78 | 78 | --================================================================================== |
|
79 | 79 | memRAM : IF Mem_use = use_RAM GENERATE |
|
80 | 80 | SRAM : syncram_2p |
|
81 |
generic map(tech, |
|
|
81 | generic map(tech,AddrSz,DataSz) | |
|
82 | 82 | port map(RCLK,sRE,Raddr_vect,rdata,WCLK,sWE,Waddr_vect,wdata); |
|
83 | 83 | END GENERATE; |
|
84 | 84 | --================================================================================== |
|
85 | 85 | memCEL : IF Mem_use = use_CEL GENERATE |
|
86 | 86 | CRAM : RAM_CEL |
|
87 |
generic map(DataSz, |
|
|
87 | generic map(DataSz,AddrSz) | |
|
88 | 88 | port map(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, WCLK, rstn); |
|
89 | 89 | END GENERATE; |
|
90 | 90 | --================================================================================== |
@@ -177,4 +177,3 end architecture; | |||
|
177 | 177 | |
|
178 | 178 | |
|
179 | 179 | |
|
180 |
@@ -1,163 +1,163 | |||
|
1 | ------------------------------------------------------------------------------ | |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
|
4 | -- | |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
|
6 | -- it under the terms of the GNU General Public License as published by | |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
|
8 | -- (at your option) any later version. | |
|
9 | -- | |
|
10 | -- This program is distributed in the hope that it will be useful, | |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
|
13 | -- GNU General Public License for more details. | |
|
14 | -- | |
|
15 | -- You should have received a copy of the GNU General Public License | |
|
16 | -- along with this program; if not, write to the Free Software | |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
|
18 | ------------------------------------------------------------------------------ | |
|
19 | -- Author : Martin Morlot | |
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |
|
21 | ------------------------------------------------------------------------------ | |
|
22 | library ieee; | |
|
23 | use ieee.std_logic_1164.all; | |
|
24 | library grlib; | |
|
25 | use grlib.amba.all; | |
|
26 | use std.textio.all; | |
|
27 | library lpp; | |
|
28 | use lpp.lpp_amba.all; | |
|
29 | use lpp.iir_filter.all; | |
|
30 | library gaisler; | |
|
31 | use gaisler.misc.all; | |
|
32 | use gaisler.memctrl.all; | |
|
33 | library techmap; | |
|
34 | use techmap.gencomp.all; | |
|
35 | ||
|
36 | --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on | |
|
37 | ||
|
38 | package lpp_memory is | |
|
39 | ||
|
40 | component APB_FIFO is | |
|
41 | generic ( | |
|
42 | tech : integer := apa3; | |
|
43 | pindex : integer := 0; | |
|
44 | paddr : integer := 0; | |
|
45 | pmask : integer := 16#fff#; | |
|
46 | pirq : integer := 0; | |
|
47 | abits : integer := 8; | |
|
48 | FifoCnt : integer := 2; | |
|
49 | Data_sz : integer := 16; | |
|
50 | Addr_sz : integer := 9; | |
|
51 | Enable_ReUse : std_logic := '0'; | |
|
52 | Mem_use : integer := use_RAM; | |
|
53 | R : integer := 1; | |
|
54 | W : integer := 1 | |
|
55 | ); | |
|
56 | port ( | |
|
57 | clk : in std_logic; --! Horloge du composant | |
|
58 | rst : in std_logic; --! Reset general du composant | |
|
59 | rclk : in std_logic; | |
|
60 | wclk : in std_logic; | |
|
61 | ReUse : in std_logic_vector(FifoCnt-1 downto 0); | |
|
62 | REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en mοΏ½moire | |
|
63 | WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'οΏ½criture en mοΏ½moire | |
|
64 | Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, MοΏ½moire vide | |
|
65 | Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, MοΏ½moire pleine | |
|
66 | RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donnοΏ½es en entrοΏ½e | |
|
67 | WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donnοΏ½es en sortie | |
|
68 | WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (οΏ½criture) | |
|
69 | RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture) | |
|
70 | apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus | |
|
71 | apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus | |
|
72 | ); | |
|
73 | end component; | |
|
74 | ||
|
75 | ||
|
76 | component lpp_fifo is | |
|
77 | generic( | |
|
78 | tech : integer := 0; | |
|
79 | Mem_use : integer := use_RAM; | |
|
80 | Enable_ReUse : std_logic := '0'; | |
|
81 | DataSz : integer range 1 to 32 := 8; | |
|
82 |
|
|
|
83 | ); | |
|
84 | port( | |
|
85 | rstn : in std_logic; | |
|
86 | ReUse : in std_logic; --27/01/12 | |
|
87 | rclk : in std_logic; | |
|
88 | ren : in std_logic; | |
|
89 | rdata : out std_logic_vector(DataSz-1 downto 0); | |
|
90 | empty : out std_logic; | |
|
91 |
raddr : out std_logic_vector( |
|
|
92 | wclk : in std_logic; | |
|
93 | wen : in std_logic; | |
|
94 | wdata : in std_logic_vector(DataSz-1 downto 0); | |
|
95 | full : out std_logic; | |
|
96 |
waddr : out std_logic_vector( |
|
|
97 | ); | |
|
98 | end component; | |
|
99 | ||
|
100 | ||
|
101 | component lppFIFOxN is | |
|
102 | generic( | |
|
103 | tech : integer := 0; | |
|
104 | Mem_use : integer := use_RAM; | |
|
105 | Data_sz : integer range 1 to 32 := 8; | |
|
106 | Addr_sz : integer range 1 to 32 := 8; | |
|
107 | FifoCnt : integer := 1; | |
|
108 | Enable_ReUse : std_logic := '0' | |
|
109 | ); | |
|
110 | port( | |
|
111 | rst : in std_logic; | |
|
112 | wclk : in std_logic; | |
|
113 | rclk : in std_logic; | |
|
114 | ReUse : in std_logic_vector(FifoCnt-1 downto 0); | |
|
115 | wen : in std_logic_vector(FifoCnt-1 downto 0); | |
|
116 | ren : in std_logic_vector(FifoCnt-1 downto 0); | |
|
117 | wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); | |
|
118 | rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); | |
|
119 | full : out std_logic_vector(FifoCnt-1 downto 0); | |
|
120 | empty : out std_logic_vector(FifoCnt-1 downto 0) | |
|
121 | ); | |
|
122 | end component; | |
|
123 | ||
|
124 | component FillFifo is | |
|
125 | generic( | |
|
126 | Data_sz : integer range 1 to 32 := 16; | |
|
127 | Fifo_cnt : integer range 1 to 8 := 5 | |
|
128 | ); | |
|
129 | port( | |
|
130 | clk : in std_logic; | |
|
131 | raz : in std_logic; | |
|
132 | write : out std_logic_vector(Fifo_cnt-1 downto 0); | |
|
133 | reuse : out std_logic_vector(Fifo_cnt-1 downto 0); | |
|
134 | data : out std_logic_vector(Fifo_cnt*Data_sz-1 downto 0) | |
|
135 | ); | |
|
136 | end component; | |
|
137 | ||
|
138 | component ssram_plugin is | |
|
139 | generic (tech : integer := 0); | |
|
140 | port | |
|
141 | ( | |
|
142 | clk : in std_logic; | |
|
143 | mem_ctrlr_o : in memory_out_type; | |
|
144 | SSRAM_CLK : out std_logic; | |
|
145 | nBWa : out std_logic; | |
|
146 | nBWb : out std_logic; | |
|
147 | nBWc : out std_logic; | |
|
148 | nBWd : out std_logic; | |
|
149 | nBWE : out std_logic; | |
|
150 | nADSC : out std_logic; | |
|
151 | nADSP : out std_logic; | |
|
152 | nADV : out std_logic; | |
|
153 | nGW : out std_logic; | |
|
154 | nCE1 : out std_logic; | |
|
155 | CE2 : out std_logic; | |
|
156 | nCE3 : out std_logic; | |
|
157 | nOE : out std_logic; | |
|
158 | MODE : out std_logic; | |
|
159 | ZZ : out std_logic | |
|
160 | ); | |
|
161 | end component; | |
|
162 | ||
|
163 |
end; |
|
|
1 | ------------------------------------------------------------------------------ | |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
|
4 | -- | |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
|
6 | -- it under the terms of the GNU General Public License as published by | |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
|
8 | -- (at your option) any later version. | |
|
9 | -- | |
|
10 | -- This program is distributed in the hope that it will be useful, | |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
|
13 | -- GNU General Public License for more details. | |
|
14 | -- | |
|
15 | -- You should have received a copy of the GNU General Public License | |
|
16 | -- along with this program; if not, write to the Free Software | |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
|
18 | ------------------------------------------------------------------------------ | |
|
19 | -- Author : Martin Morlot | |
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |
|
21 | ------------------------------------------------------------------------------ | |
|
22 | library ieee; | |
|
23 | use ieee.std_logic_1164.all; | |
|
24 | library grlib; | |
|
25 | use grlib.amba.all; | |
|
26 | use std.textio.all; | |
|
27 | library lpp; | |
|
28 | use lpp.lpp_amba.all; | |
|
29 | use lpp.iir_filter.all; | |
|
30 | library gaisler; | |
|
31 | use gaisler.misc.all; | |
|
32 | use gaisler.memctrl.all; | |
|
33 | library techmap; | |
|
34 | use techmap.gencomp.all; | |
|
35 | ||
|
36 | --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on | |
|
37 | ||
|
38 | package lpp_memory is | |
|
39 | ||
|
40 | component APB_FIFO is | |
|
41 | generic ( | |
|
42 | tech : integer := apa3; | |
|
43 | pindex : integer := 0; | |
|
44 | paddr : integer := 0; | |
|
45 | pmask : integer := 16#fff#; | |
|
46 | pirq : integer := 0; | |
|
47 | abits : integer := 8; | |
|
48 | FifoCnt : integer := 2; | |
|
49 | Data_sz : integer := 16; | |
|
50 | Addr_sz : integer := 9; | |
|
51 | Enable_ReUse : std_logic := '0'; | |
|
52 | Mem_use : integer := use_RAM; | |
|
53 | R : integer := 1; | |
|
54 | W : integer := 1 | |
|
55 | ); | |
|
56 | port ( | |
|
57 | clk : in std_logic; --! Horloge du composant | |
|
58 | rst : in std_logic; --! Reset general du composant | |
|
59 | rclk : in std_logic; | |
|
60 | wclk : in std_logic; | |
|
61 | ReUse : in std_logic_vector(FifoCnt-1 downto 0); | |
|
62 | REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en mοΏ½moire | |
|
63 | WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'οΏ½criture en mοΏ½moire | |
|
64 | Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, MοΏ½moire vide | |
|
65 | Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, MοΏ½moire pleine | |
|
66 | RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donnοΏ½es en entrοΏ½e | |
|
67 | WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donnοΏ½es en sortie | |
|
68 | WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (οΏ½criture) | |
|
69 | RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture) | |
|
70 | apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus | |
|
71 | apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus | |
|
72 | ); | |
|
73 | end component; | |
|
74 | ||
|
75 | ||
|
76 | component lpp_fifo is | |
|
77 | generic( | |
|
78 | tech : integer := 0; | |
|
79 | Mem_use : integer := use_RAM; | |
|
80 | Enable_ReUse : std_logic := '0'; | |
|
81 | DataSz : integer range 1 to 32 := 8; | |
|
82 | AddrSz : integer range 2 to 12 := 8 | |
|
83 | ); | |
|
84 | port( | |
|
85 | rstn : in std_logic; | |
|
86 | ReUse : in std_logic; --27/01/12 | |
|
87 | rclk : in std_logic; | |
|
88 | ren : in std_logic; | |
|
89 | rdata : out std_logic_vector(DataSz-1 downto 0); | |
|
90 | empty : out std_logic; | |
|
91 | raddr : out std_logic_vector(AddrSz-1 downto 0); | |
|
92 | wclk : in std_logic; | |
|
93 | wen : in std_logic; | |
|
94 | wdata : in std_logic_vector(DataSz-1 downto 0); | |
|
95 | full : out std_logic; | |
|
96 | waddr : out std_logic_vector(AddrSz-1 downto 0) | |
|
97 | ); | |
|
98 | end component; | |
|
99 | ||
|
100 | ||
|
101 | component lppFIFOxN is | |
|
102 | generic( | |
|
103 | tech : integer := 0; | |
|
104 | Mem_use : integer := use_RAM; | |
|
105 | Data_sz : integer range 1 to 32 := 8; | |
|
106 | Addr_sz : integer range 1 to 32 := 8; | |
|
107 | FifoCnt : integer := 1; | |
|
108 | Enable_ReUse : std_logic := '0' | |
|
109 | ); | |
|
110 | port( | |
|
111 | rstn : in std_logic; | |
|
112 | wclk : in std_logic; | |
|
113 | rclk : in std_logic; | |
|
114 | ReUse : in std_logic_vector(FifoCnt-1 downto 0); | |
|
115 | wen : in std_logic_vector(FifoCnt-1 downto 0); | |
|
116 | ren : in std_logic_vector(FifoCnt-1 downto 0); | |
|
117 | wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); | |
|
118 | rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); | |
|
119 | full : out std_logic_vector(FifoCnt-1 downto 0); | |
|
120 | empty : out std_logic_vector(FifoCnt-1 downto 0) | |
|
121 | ); | |
|
122 | end component; | |
|
123 | ||
|
124 | component FillFifo is | |
|
125 | generic( | |
|
126 | Data_sz : integer range 1 to 32 := 16; | |
|
127 | Fifo_cnt : integer range 1 to 8 := 5 | |
|
128 | ); | |
|
129 | port( | |
|
130 | clk : in std_logic; | |
|
131 | raz : in std_logic; | |
|
132 | write : out std_logic_vector(Fifo_cnt-1 downto 0); | |
|
133 | reuse : out std_logic_vector(Fifo_cnt-1 downto 0); | |
|
134 | data : out std_logic_vector(Fifo_cnt*Data_sz-1 downto 0) | |
|
135 | ); | |
|
136 | end component; | |
|
137 | ||
|
138 | component ssram_plugin is | |
|
139 | generic (tech : integer := 0); | |
|
140 | port | |
|
141 | ( | |
|
142 | clk : in std_logic; | |
|
143 | mem_ctrlr_o : in memory_out_type; | |
|
144 | SSRAM_CLK : out std_logic; | |
|
145 | nBWa : out std_logic; | |
|
146 | nBWb : out std_logic; | |
|
147 | nBWc : out std_logic; | |
|
148 | nBWd : out std_logic; | |
|
149 | nBWE : out std_logic; | |
|
150 | nADSC : out std_logic; | |
|
151 | nADSP : out std_logic; | |
|
152 | nADV : out std_logic; | |
|
153 | nGW : out std_logic; | |
|
154 | nCE1 : out std_logic; | |
|
155 | CE2 : out std_logic; | |
|
156 | nCE3 : out std_logic; | |
|
157 | nOE : out std_logic; | |
|
158 | MODE : out std_logic; | |
|
159 | ZZ : out std_logic | |
|
160 | ); | |
|
161 | end component; | |
|
162 | ||
|
163 | end; No newline at end of file |
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