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Improved testbench for LFR's F0 IIR Filter, now processed input is read from...
Jeandet Alexis -
r642:d1feb5a41a44 default draft
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@@ -0,0 +1,60
1 {
2 "cells": [
3 {
4 "cell_type": "code",
5 "execution_count": 8,
6 "metadata": {
7 "collapsed": true
8 },
9 "outputs": [],
10 "source": [
11 "import numpy as np\n",
12 "import matplotlib.pyplot as plt\n",
13 "import random"
14 ]
15 },
16 {
17 "cell_type": "code",
18 "execution_count": 32,
19 "metadata": {
20 "collapsed": false
21 },
22 "outputs": [],
23 "source": [
24 "W,H=8,1000\n",
25 "test = np.ones((H,W))*[(random.random()*65535)-32768 for col in range(W)]\n",
26 "np.savetxt(\"input.txt\", test,fmt=\"%d\", delimiter=\" \")"
27 ]
28 },
29 {
30 "cell_type": "code",
31 "execution_count": 28,
32 "metadata": {
33 "collapsed": false
34 },
35 "outputs": [],
36 "source": []
37 }
38 ],
39 "metadata": {
40 "kernelspec": {
41 "display_name": "Python 3",
42 "language": "python",
43 "name": "python3"
44 },
45 "language_info": {
46 "codemirror_mode": {
47 "name": "ipython",
48 "version": 3
49 },
50 "file_extension": ".py",
51 "mimetype": "text/x-python",
52 "name": "python",
53 "nbconvert_exporter": "python",
54 "pygments_lexer": "ipython3",
55 "version": "3.5.2"
56 }
57 },
58 "nbformat": 4,
59 "nbformat_minor": 1
60 }
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@@ -0,0 +1,53
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
4
5 LIBRARY std;
6 USE std.textio.ALL;
7
8 LIBRARY lpp;
9 USE lpp.data_type_pkg.ALL;
10
11 ENTITY sig_reader IS
12 GENERIC(
13 FNAME : STRING := "input.txt";
14 WIDTH : INTEGER := 1;
15 RESOLUTION : INTEGER := 8;
16 GAIN : REAL := 1.0
17 );
18 PORT(
19 clk : IN std_logic;
20 end_of_simu : out std_logic;
21 out_signal : out sample_vector(0 to WIDTH-1,RESOLUTION-1 downto 0)
22 );
23 END sig_reader;
24
25 ARCHITECTURE beh OF sig_reader IS
26 FILE input_file : TEXT OPEN read_mode IS FNAME;
27 SIGNAL out_signal_reg : sample_vector(0 to WIDTH-1,RESOLUTION-1 downto 0):=(others=>(others=>'0'));
28 SIGNAL end_of_simu_reg : std_logic:='0';
29 BEGIN
30 out_signal <= out_signal_reg;
31 end_of_simu <= end_of_simu_reg;
32 PROCESS
33 VARIABLE line_var : LINE;
34 VARIABLE value : INTEGER;
35 VARIABLE cell : STD_LOGIC_VECTOR(RESOLUTION-1 downto 0);
36 BEGIN
37 WAIT UNTIL clk = '1';
38 IF endfile(input_file) THEN
39 end_of_simu_reg <= '1';
40 ELSE
41 end_of_simu_reg <= '0';
42 readline(input_file,line_var);
43 FOR COL IN 0 TO WIDTH-1 LOOP
44 read(line_var, value);
45 cell := std_logic_vector(to_signed(INTEGER(GAIN*REAL(value)) , RESOLUTION));
46 FOR bit_idx IN RESOLUTION-1 downto 0 LOOP
47 out_signal_reg(COL,bit_idx) <= cell(bit_idx);
48 END LOOP;
49 END LOOP;
50 END IF;
51 END PROCESS;
52
53 END beh;
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@@ -12,8 +12,8 EFFORT=high
12 XSTOPT=
12 XSTOPT=
13 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
13 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
15 VHDLSYNFILES= IIR_CEL_TEST.vhd tb.vhd IIR_CEL_TEST_v3.vhd generator.vhd
15 VHDLSYNFILES= IIR_CEL_TEST.vhd tb.vhd IIR_CEL_TEST_v3.vhd generator.vhd sig_reader.vhd
16 VHDLSIMFILES= tb.vhd
16 VHDLSIMFILES= tb.vhd sig_reader.vhd
17 SIMTOP=testbench
17 SIMTOP=testbench
18 #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
18 #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
19 PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_RTAX.pdc
19 PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_RTAX.pdc
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@@ -31,7 +31,8 ENTITY generator IS
31
31
32 GENERIC (
32 GENERIC (
33 AMPLITUDE : INTEGER := 100;
33 AMPLITUDE : INTEGER := 100;
34 NB_BITS : INTEGER := 16);
34 NB_BITS : INTEGER := 16
35 );
35
36
36 PORT (
37 PORT (
37 clk : IN STD_LOGIC;
38 clk : IN STD_LOGIC;
@@ -50,7 +51,6 ARCHITECTURE beh OF generator IS
50 SIGNAL reg : STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0);
51 SIGNAL reg : STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0);
51 BEGIN -- beh
52 BEGIN -- beh
52
53
53
54 PROCESS (clk, rstn)
54 PROCESS (clk, rstn)
55 variable seed1, seed2: positive; -- seed values for random generator
55 variable seed1, seed2: positive; -- seed values for random generator
56 variable rand: real; -- random real-number value in range 0 to 1.0
56 variable rand: real; -- random real-number value in range 0 to 1.0
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@@ -23,8 +23,8 USE lpp.general_purpose.ALL;
23
23
24 ENTITY testbench IS
24 ENTITY testbench IS
25 GENERIC(
25 GENERIC(
26 tech : INTEGER := 0; --axcel,
26 tech : INTEGER := 0; --axcel,0
27 Mem_use : INTEGER := use_CEL --use_RAM
27 Mem_use : INTEGER := use_CEL --use_RAM,use_CEL
28 );
28 );
29 END;
29 END;
30
30
@@ -52,8 +52,7 ARCHITECTURE behav OF testbench IS
52 SIGNAL clk_24k_r : STD_LOGIC := '0';
52 SIGNAL clk_24k_r : STD_LOGIC := '0';
53 SIGNAL rstn : STD_LOGIC;
53 SIGNAL rstn : STD_LOGIC;
54
54
55 SIGNAL signal_gen : Samples(7 DOWNTO 0);
55 SIGNAL signal_gen : sample_vector(0 to ChanelCount-1,17 downto 0);
56 SIGNAL offset_gen : Samples(7 DOWNTO 0);
57
56
58 --SIGNAL sample_fx_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
57 --SIGNAL sample_fx_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
59
58
@@ -75,10 +74,24 ARCHITECTURE behav OF testbench IS
75 data : OUT STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0)
74 data : OUT STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0)
76 );
75 );
77 END COMPONENT;
76 END COMPONENT;
77
78 COMPONENT sig_reader IS
79 GENERIC(
80 FNAME : STRING := "input.txt";
81 WIDTH : INTEGER := 1;
82 RESOLUTION : INTEGER := 8;
83 GAIN : REAL := 1.0
84 );
85 PORT(
86 clk : IN std_logic;
87 end_of_simu : out std_logic;
88 out_signal : out sample_vector(0 to WIDTH-1,RESOLUTION-1 downto 0)
89 );
90 END COMPONENT;
78
91
79
92
80 FILE log_input : TEXT OPEN write_mode IS "log_input.txt";
93 FILE input : TEXT OPEN read_mode IS "input.txt";
81 FILE log_output_fx : TEXT OPEN write_mode IS "log_output_fx.txt";
94 FILE output_fx : TEXT OPEN write_mode IS "output_fx.txt";
82
95
83 SIGNAL end_of_simu : STD_LOGIC := '0';
96 SIGNAL end_of_simu : STD_LOGIC := '0';
84
97
@@ -87,18 +100,16 BEGIN
87 -----------------------------------------------------------------------------
100 -----------------------------------------------------------------------------
88 -- CLOCK and RESET
101 -- CLOCK and RESET
89 -----------------------------------------------------------------------------
102 -----------------------------------------------------------------------------
90 clk <= NOT clk AFTER 5 ns;
103 clk <= NOT clk AFTER 20 ns;
91 PROCESS
104 PROCESS
92 BEGIN -- PROCESS
105 BEGIN -- PROCESS
93 end_of_simu <= '0';
94 WAIT UNTIL clk = '1';
106 WAIT UNTIL clk = '1';
95 rstn <= '0';
107 rstn <= '0';
96 WAIT UNTIL clk = '1';
108 WAIT UNTIL clk = '1';
97 WAIT UNTIL clk = '1';
109 WAIT UNTIL clk = '1';
98 WAIT UNTIL clk = '1';
110 WAIT UNTIL clk = '1';
99 rstn <= '1';
111 rstn <= '1';
100 WAIT FOR 2000 ms;
112 WAIT UNTIL end_of_simu = '1';
101 end_of_simu <= '1';
102 WAIT UNTIL clk = '1';
113 WAIT UNTIL clk = '1';
103 REPORT "*** END simulation ***" SEVERITY failure;
114 REPORT "*** END simulation ***" SEVERITY failure;
104 WAIT;
115 WAIT;
@@ -133,7 +144,7 BEGIN
133 Coef_sel_SZ => 5,
144 Coef_sel_SZ => 5,
134 Cels_count => Cels_count,
145 Cels_count => Cels_count,
135 ChanelsCount => ChanelCount,
146 ChanelsCount => ChanelCount,
136 FILENAME => "RAM.txt")
147 FILENAME => "")
137 PORT MAP (
148 PORT MAP (
138 rstn => rstn,
149 rstn => rstn,
139 clk => clk,
150 clk => clk,
@@ -167,49 +178,39 BEGIN
167 END IF;
178 END IF;
168 END PROCESS;
179 END PROCESS;
169 -----------------------------------------------------------------------------
180 -----------------------------------------------------------------------------
170 generators : FOR I IN 0 TO 7 GENERATE
171 gen1 : generator
172 GENERIC MAP (
173 AMPLITUDE => 100,
174 NB_BITS => 16)
175 PORT MAP (
176 clk => clk,
177 rstn => rstn,
178 run => '1',
179 data_ack => sample_val,
180 offset => offset_gen(I),
181 data => signal_gen(I)
182 );
183 offset_gen(I) <= STD_LOGIC_VECTOR(to_signed((I*200), 16));
184 END GENERATE generators;
185
181
186 ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
182 ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
187 SampleLoop : FOR j IN 0 TO 15 GENERATE
183 SampleLoop : FOR j IN 0 TO 15 GENERATE
188 sample(i,j) <= signal_gen(i)(j);
189 sample_fx_wdata(i)(j) <= sample_fx(i,j);
184 sample_fx_wdata(i)(j) <= sample_fx(i,j);
185 sample(i,j) <= signal_gen(i,j);
190 END GENERATE;
186 END GENERATE;
191
187 sample(i,16) <= signal_gen(i,16);
192 sample(i, 16) <= signal_gen(i)(15);
188 sample(i,17) <= signal_gen(i,17);
193 sample(i, 17) <= signal_gen(i)(15);
194 END GENERATE;
189 END GENERATE;
195
190
196
191
197
192
198 -----------------------------------------------------------------------------
193 -----------------------------------------------------------------------------
199 -- RECORD SIGNALS
194 -- READ INPUT SIGNALS
200 -----------------------------------------------------------------------------
195 -----------------------------------------------------------------------------
201
196
202 -- PROCESS(sample_val)
197 gen: sig_reader
203 -- VARIABLE line_var : LINE;
198 GENERIC MAP(
204 -- BEGIN
199 FNAME => "input.txt",
205 -- IF sample_val'EVENT AND sample_val = '1' THEN
200 WIDTH => ChanelCount,
206 -- write(line_var, INTEGER'IMAGE(TSTAMP));
201 RESOLUTION => 18,
207 -- FOR I IN 0 TO 7 LOOP
202 GAIN => 1.0
208 -- write(line_var, " " & INTEGER'IMAGE(to_integer(SIGNED(signal_gen(I)))));
203 )
209 -- END LOOP;
204 PORT MAP(
210 -- writeline(log_input, line_var);
205 clk => sample_val,
211 -- END IF;
206 end_of_simu => end_of_simu,
212 -- END PROCESS;
207 out_signal => signal_gen
208 );
209
210
211 -----------------------------------------------------------------------------
212 -- RECORD OUTPUT SIGNALS
213 -----------------------------------------------------------------------------
213
214
214 PROCESS(sample_fx_val,end_of_simu)
215 PROCESS(sample_fx_val,end_of_simu)
215 VARIABLE line_var : LINE;
216 VARIABLE line_var : LINE;
@@ -219,10 +220,10 BEGIN
219 FOR I IN 0 TO 5 LOOP
220 FOR I IN 0 TO 5 LOOP
220 write(line_var, " " & INTEGER'IMAGE(to_integer(SIGNED(sample_fx_wdata(I)))));
221 write(line_var, " " & INTEGER'IMAGE(to_integer(SIGNED(sample_fx_wdata(I)))));
221 END LOOP;
222 END LOOP;
222 writeline(log_output_fx, line_var);
223 writeline(output_fx, line_var);
223 END IF;
224 END IF;
224 IF end_of_simu = '1' THEN
225 IF end_of_simu = '1' THEN
225 file_close(log_output_fx);
226 file_close(output_fx);
226 END IF;
227 END IF;
227 END PROCESS;
228 END PROCESS;
228
229
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@@ -79,8 +79,10 ARCHITECTURE ar_RAM_CEL OF RAM_CEL IS
79 variable Result : RAMarrayT := (others => (others => '0'));
79 variable Result : RAMarrayT := (others => (others => '0'));
80 begin
80 begin
81 if FileName'length /= 0 then
81 if FileName'length /= 0 then
82 report "initialysing RAM CEL From file "& FileName;
82 Result := ReadMemFile(FileName);
83 Result := ReadMemFile(FileName);
83 end if;
84 end if;
85 report "initialysing RAM CEL To 0";
84 return Result;
86 return Result;
85 end function;
87 end function;
86
88
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