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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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USE IEEE.std_logic_signed.ALL;
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USE IEEE.MATH_real.ALL;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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LIBRARY std;
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USE std.textio.ALL;
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LIBRARY lpp;
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USE lpp.iir_filter.ALL;
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USE lpp.lpp_ad_conv.ALL;
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USE lpp.FILTERcfg.ALL;
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USE lpp.lpp_lfr_filter_coeff.ALL;
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USE lpp.general_purpose.ALL;
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USE lpp.data_type_pkg.ALL;
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USE lpp.lpp_lfr_pkg.ALL;
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USE lpp.general_purpose.ALL;
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ENTITY testbench IS
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GENERIC(
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tech : INTEGER := 0; --axcel,
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Mem_use : INTEGER := use_CEL --use_RAM
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);
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END;
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ARCHITECTURE behav OF testbench IS
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CONSTANT ChanelCount : INTEGER := 8;
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CONSTANT Coef_SZ : INTEGER := 9;
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CONSTANT CoefCntPerCel : INTEGER := 6;
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CONSTANT CoefPerCel : INTEGER := 5;
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CONSTANT Cels_count : INTEGER := 5;
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SIGNAL sample : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
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SIGNAL sample_val : STD_LOGIC;
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SIGNAL sample_fx : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
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SIGNAL sample_fx_val : STD_LOGIC;
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SIGNAL TSTAMP : INTEGER := 0;
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SIGNAL clk : STD_LOGIC := '0';
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SIGNAL clk_24k : STD_LOGIC := '0';
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SIGNAL clk_24k_r : STD_LOGIC := '0';
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SIGNAL rstn : STD_LOGIC;
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SIGNAL signal_gen : Samples(7 DOWNTO 0);
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SIGNAL offset_gen : Samples(7 DOWNTO 0);
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--SIGNAL sample_fx_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
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SIGNAL sample_fx_wdata : Samples(ChanelCount-1 DOWNTO 0);
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COMPONENT generator IS
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GENERIC (
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AMPLITUDE : INTEGER := 100;
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NB_BITS : INTEGER := 16);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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run : IN STD_LOGIC;
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data_ack : IN STD_LOGIC;
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offset : IN STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0);
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data : OUT STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0)
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);
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END COMPONENT;
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FILE log_input : TEXT OPEN write_mode IS "log_input.txt";
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FILE log_output_fx : TEXT OPEN write_mode IS "log_output_fx.txt";
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SIGNAL end_of_simu : STD_LOGIC := '0';
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BEGIN
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-----------------------------------------------------------------------------
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-- CLOCK and RESET
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-----------------------------------------------------------------------------
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clk <= NOT clk AFTER 5 ns;
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PROCESS
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BEGIN -- PROCESS
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end_of_simu <= '0';
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WAIT UNTIL clk = '1';
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rstn <= '0';
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WAIT UNTIL clk = '1';
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WAIT UNTIL clk = '1';
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WAIT UNTIL clk = '1';
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rstn <= '1';
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WAIT FOR 2000 ms;
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end_of_simu <= '1';
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WAIT UNTIL clk = '1';
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REPORT "*** END simulation ***" SEVERITY failure;
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WAIT;
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END PROCESS;
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- COMMON TIMESTAMPS
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-----------------------------------------------------------------------------
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PROCESS(clk)
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BEGIN
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IF clk'EVENT AND clk = '1' THEN
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TSTAMP <= TSTAMP+1;
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END IF;
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END PROCESS;
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- LPP_LFR_FILTER f0
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-----------------------------------------------------------------------------
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IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
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GENERIC MAP (
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tech => tech,
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Mem_use => use_RAM,
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Sample_SZ => 18,
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Coef_SZ => Coef_SZ,
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Coef_Nb => 25,
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Coef_sel_SZ => 5,
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Cels_count => Cels_count,
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ChanelsCount => ChanelCount,
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FILENAME => "RAM.txt")
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PORT MAP (
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rstn => rstn,
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clk => clk,
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virg_pos => 7,
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coefs => CoefsInitValCst_v2,
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sample_in_val => sample_val,
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sample_in => sample,
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sample_out_val => sample_fx_val,
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sample_out => sample_fx);
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- SAMPLE GENERATION
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-----------------------------------------------------------------------------
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clk_24k <= NOT clk_24k AFTER 20345 ns;
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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sample_val <= '0';
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clk_24k_r <= '0';
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ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
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clk_24k_r <= clk_24k;
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IF clk_24k = '1' AND clk_24k_r = '0' THEN
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sample_val <= '1';
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ELSE
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sample_val <= '0';
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END IF;
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END IF;
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END PROCESS;
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-----------------------------------------------------------------------------
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generators : FOR I IN 0 TO 7 GENERATE
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gen1 : generator
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GENERIC MAP (
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AMPLITUDE => 100,
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NB_BITS => 16)
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PORT MAP (
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clk => clk,
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rstn => rstn,
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run => '1',
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data_ack => sample_val,
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offset => offset_gen(I),
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data => signal_gen(I)
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);
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offset_gen(I) <= STD_LOGIC_VECTOR(to_signed((I*200), 16));
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END GENERATE generators;
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ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
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SampleLoop : FOR j IN 0 TO 15 GENERATE
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sample(i,j) <= signal_gen(i)(j);
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sample_fx_wdata(i)(j) <= sample_fx(i,j);
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END GENERATE;
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sample(i, 16) <= signal_gen(i)(15);
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sample(i, 17) <= signal_gen(i)(15);
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END GENERATE;
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-----------------------------------------------------------------------------
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-- RECORD SIGNALS
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-----------------------------------------------------------------------------
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-- PROCESS(sample_val)
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-- VARIABLE line_var : LINE;
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-- BEGIN
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-- IF sample_val'EVENT AND sample_val = '1' THEN
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-- write(line_var, INTEGER'IMAGE(TSTAMP));
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-- FOR I IN 0 TO 7 LOOP
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-- write(line_var, " " & INTEGER'IMAGE(to_integer(SIGNED(signal_gen(I)))));
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-- END LOOP;
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-- writeline(log_input, line_var);
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-- END IF;
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-- END PROCESS;
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PROCESS(sample_fx_val,end_of_simu)
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VARIABLE line_var : LINE;
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BEGIN
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IF sample_fx_val'EVENT AND sample_fx_val = '1' THEN
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write(line_var, INTEGER'IMAGE(TSTAMP));
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FOR I IN 0 TO 5 LOOP
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write(line_var, " " & INTEGER'IMAGE(to_integer(SIGNED(sample_fx_wdata(I)))));
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END LOOP;
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writeline(log_output_fx, line_var);
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END IF;
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IF end_of_simu = '1' THEN
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file_close(log_output_fx);
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END IF;
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END PROCESS;
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END;
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