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Added file init for RAM_CEL IP.[Need tests]...
Jeandet Alexis -
r641:0dc1942211a7 default draft
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@@ -26,8 +26,9 TECHLIBS = axcelerator
26 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
26 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
27 tmtc openchip hynix ihp gleichmann micron usbhc opencores
27 tmtc openchip hynix ihp gleichmann micron usbhc opencores
28
28
29 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
29 DIRSKIP = b1553 pcif leon2 leon3v3 leon2ft crypto satcan ddr usb ata i2c \
30 pci grusbhc haps slink ascs can pwm greth coremp7 spi ac97 \
30 pci grusbhc haps slink ascs can pwm greth coremp7 spi ac97 \
31 ./dsp/lpp_fft_rtax \
31 ./amba_lcd_16x2_ctrlr \
32 ./amba_lcd_16x2_ctrlr \
32 ./general_purpose/lpp_AMR \
33 ./general_purpose/lpp_AMR \
33 ./general_purpose/lpp_balise \
34 ./general_purpose/lpp_balise \
@@ -40,14 +41,18 DIRSKIP = b1553 pcif leon2 leon2ft crypt
40 ./lpp_uart \
41 ./lpp_uart \
41 ./lpp_usb \
42 ./lpp_usb \
42 ./dsp/lpp_fft \
43 ./dsp/lpp_fft \
44 ./lpp_leon3_soc \
45 ./lpp_debug_lfr
43
46
44 FILESKIP = i2cmst.vhd \
47 FILESKIP = i2cmst.vhd \
45 APB_MULTI_DIODE.vhd \
48 APB_MULTI_DIODE.vhd \
46 APB_MULTI_DIODE.vhd \
49 APB_MULTI_DIODE.vhd \
47 Top_MatrixSpec.vhd \
50 Top_MatrixSpec.vhd \
48 APB_FFT.vhd \
51 APB_FFT.vhd \
52 lpp_lfr_ms_FFT.vhd \
49 lpp_lfr_apbreg.vhd \
53 lpp_lfr_apbreg.vhd \
50 CoreFFT.vhd
54 CoreFFT.vhd \
55 lpp_lfr_ms.vhd
51
56
52 include $(GRLIB)/bin/Makefile
57 include $(GRLIB)/bin/Makefile
53 include $(GRLIB)/software/leon3/Makefile
58 include $(GRLIB)/software/leon3/Makefile
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@@ -22,6 +22,10 USE lpp.lpp_lfr_pkg.ALL;
22 USE lpp.general_purpose.ALL;
22 USE lpp.general_purpose.ALL;
23
23
24 ENTITY testbench IS
24 ENTITY testbench IS
25 GENERIC(
26 tech : INTEGER := 0; --axcel,
27 Mem_use : INTEGER := use_CEL --use_RAM
28 );
25 END;
29 END;
26
30
27 ARCHITECTURE behav OF testbench IS
31 ARCHITECTURE behav OF testbench IS
@@ -121,14 +125,15 BEGIN
121
125
122 IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
126 IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
123 GENERIC MAP (
127 GENERIC MAP (
124 tech => axcel,
128 tech => tech,
125 Mem_use => use_RAM,
129 Mem_use => use_RAM,
126 Sample_SZ => 18,
130 Sample_SZ => 18,
127 Coef_SZ => Coef_SZ,
131 Coef_SZ => Coef_SZ,
128 Coef_Nb => 25,
132 Coef_Nb => 25,
129 Coef_sel_SZ => 5,
133 Coef_sel_SZ => 5,
130 Cels_count => Cels_count,
134 Cels_count => Cels_count,
131 ChanelsCount => ChanelCount)
135 ChanelsCount => ChanelCount,
136 FILENAME => "RAM.txt")
132 PORT MAP (
137 PORT MAP (
133 rstn => rstn,
138 rstn => rstn,
134 clk => clk,
139 clk => clk,
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@@ -40,7 +40,8 ENTITY IIR_CEL_CTRLR_v2 IS
40 Coef_Nb : INTEGER := 25;
40 Coef_Nb : INTEGER := 25;
41 Coef_sel_SZ : INTEGER := 5;
41 Coef_sel_SZ : INTEGER := 5;
42 Cels_count : INTEGER := 5;
42 Cels_count : INTEGER := 5;
43 ChanelsCount : INTEGER := 8);
43 ChanelsCount : INTEGER := 8;
44 FILENAME : STRING := "");
44 PORT (
45 PORT (
45 rstn : IN STD_LOGIC;
46 rstn : IN STD_LOGIC;
46 clk : IN STD_LOGIC;
47 clk : IN STD_LOGIC;
@@ -64,7 +65,8 ARCHITECTURE ar_IIR_CEL_CTRLR_v2 OF IIR_
64 Sample_SZ : INTEGER;
65 Sample_SZ : INTEGER;
65 Coef_SZ : INTEGER;
66 Coef_SZ : INTEGER;
66 Coef_Nb : INTEGER;
67 Coef_Nb : INTEGER;
67 Coef_sel_SZ : INTEGER);
68 Coef_sel_SZ : INTEGER;
69 FILENAME : STRING);
68 PORT (
70 PORT (
69 rstn : IN STD_LOGIC;
71 rstn : IN STD_LOGIC;
70 clk : IN STD_LOGIC;
72 clk : IN STD_LOGIC;
@@ -143,7 +145,8 BEGIN
143 Sample_SZ => Sample_SZ,
145 Sample_SZ => Sample_SZ,
144 Coef_SZ => Coef_SZ,
146 Coef_SZ => Coef_SZ,
145 Coef_Nb => Coef_Nb,
147 Coef_Nb => Coef_Nb,
146 Coef_sel_SZ => Coef_sel_SZ)
148 Coef_sel_SZ => Coef_sel_SZ,
149 FILENAME => FILENAME)
147 PORT MAP (
150 PORT MAP (
148 rstn => rstn,
151 rstn => rstn,
149 clk => clk,
152 clk => clk,
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@@ -35,7 +35,8 ENTITY IIR_CEL_CTRLR_v2_DATAFLOW IS
35 Sample_SZ : INTEGER := 16;
35 Sample_SZ : INTEGER := 16;
36 Coef_SZ : INTEGER := 9;
36 Coef_SZ : INTEGER := 9;
37 Coef_Nb : INTEGER := 30;
37 Coef_Nb : INTEGER := 30;
38 Coef_sel_SZ : INTEGER := 5
38 Coef_sel_SZ : INTEGER := 5;
39 FILENAME : STRING:= ""
39 );
40 );
40 PORT(
41 PORT(
41 rstn : IN STD_LOGIC;
42 rstn : IN STD_LOGIC;
@@ -70,7 +71,8 ARCHITECTURE ar_IIR_CEL_CTRLR_v2_DATAFLO
70 GENERIC (
71 GENERIC (
71 tech : INTEGER;
72 tech : INTEGER;
72 Input_SZ_1 : INTEGER;
73 Input_SZ_1 : INTEGER;
73 Mem_use : INTEGER);
74 Mem_use : INTEGER;
75 FILENAME : STRING);
74 PORT (
76 PORT (
75 rstn : IN STD_LOGIC;
77 rstn : IN STD_LOGIC;
76 clk : IN STD_LOGIC;
78 clk : IN STD_LOGIC;
@@ -129,7 +131,8 BEGIN
129 GENERIC MAP (
131 GENERIC MAP (
130 tech => tech,
132 tech => tech,
131 Input_SZ_1 => Sample_SZ,
133 Input_SZ_1 => Sample_SZ,
132 Mem_use => Mem_use)
134 Mem_use => Mem_use,
135 FILENAME => FILENAME)
133 PORT MAP (
136 PORT MAP (
134 clk => clk,
137 clk => clk,
135 rstn => rstn,
138 rstn => rstn,
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@@ -21,12 +21,18
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 LIBRARY ieee;
22 LIBRARY ieee;
23 USE ieee.std_logic_1164.ALL;
23 USE ieee.std_logic_1164.ALL;
24 USE ieee.std_logic_textio.ALL;
24 USE IEEE.numeric_std.ALL;
25 USE IEEE.numeric_std.ALL;
26 LIBRARY std;
27 USE std.textio.ALL;
28
25
29
26 ENTITY RAM_CEL IS
30 ENTITY RAM_CEL IS
27 GENERIC(
31 GENERIC(
28 DataSz : INTEGER RANGE 1 TO 32 := 8;
32 DataSz : INTEGER RANGE 1 TO 32 := 8;
29 abits : INTEGER RANGE 2 TO 12 := 8);
33 abits : INTEGER RANGE 2 TO 12 := 8;
34 FILENAME : string:= ""
35 );
30 PORT(
36 PORT(
31 WD : IN STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
37 WD : IN STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
32 RD : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
38 RD : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
@@ -46,28 +52,53 ARCHITECTURE ar_RAM_CEL OF RAM_CEL IS
46
52
47 TYPE RAMarrayT IS ARRAY (0 TO MAX-1) OF STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
53 TYPE RAMarrayT IS ARRAY (0 TO MAX-1) OF STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
48
54
49 SIGNAL RAMarray : RAMarrayT := (OTHERS => VectInit);
50 SIGNAL RD_int : STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
55 SIGNAL RD_int : STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
51
56
52 SIGNAL RADDR_reg : STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
57 SIGNAL RADDR_reg : STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
58
59
60 -- Read a *.hex file
61 impure function ReadMemFile(FileName : STRING) return RAMarrayT is
62 file FileHandle : TEXT open READ_MODE is FileName;
63 variable CurrentLine : LINE;
64 variable TempWord : STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
65 variable Result : RAMarrayT := (others => (others => '0'));
53
66
67 begin
68 for i in 0 to MAX - 1 loop
69 exit when endfile(FileHandle);
70 readline(FileHandle, CurrentLine);
71 hread(CurrentLine, TempWord);
72 Result(i) := TempWord;
73 end loop;
74
75 return Result;
76 end function;
77
78 impure function InitMem(FileName : STRING) return RAMarrayT is
79 variable Result : RAMarrayT := (others => (others => '0'));
80 begin
81 if FileName'length /= 0 then
82 Result := ReadMemFile(FileName);
83 end if;
84 return Result;
85 end function;
86
87 SIGNAL RAMarray : RAMarrayT := InitMem(FILENAME);
54 BEGIN
88 BEGIN
55
89
56 RD_int <= RAMarray(to_integer(UNSIGNED(RADDR)));
90 RD_int <= RAMarray(to_integer(UNSIGNED(RADDR)));
57
91
58
59 PROCESS(RWclk, reset)
92 PROCESS(RWclk, reset)
60 BEGIN
93 BEGIN
61 IF reset = '0' THEN
94 IF reset = '0' THEN
62 RD <= VectInit;
95 RD <= VectInit;
63 rst : FOR i IN 0 TO MAX-1 LOOP
96 -- rst : FOR i IN 0 TO MAX-1 LOOP
64 RAMarray(i) <= (OTHERS => '0');
97 -- RAMarray(i) <= (OTHERS => '0');
65 END LOOP;
98 -- END LOOP;
66
99
67 ELSIF RWclk'EVENT AND RWclk = '1' THEN
100 ELSIF RWclk'EVENT AND RWclk = '1' THEN
68 -- IF REN = '0' THEN
69 RD <= RD_int;
101 RD <= RD_int;
70 -- END IF;
71 IF REN = '0' THEN
102 IF REN = '0' THEN
72 RADDR_reg <= RADDR;
103 RADDR_reg <= RADDR;
73 END IF;
104 END IF;
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@@ -33,7 +33,8 ENTITY RAM_CTRLR_v2 IS
33 GENERIC(
33 GENERIC(
34 tech : INTEGER := 0;
34 tech : INTEGER := 0;
35 Input_SZ_1 : INTEGER := 16;
35 Input_SZ_1 : INTEGER := 16;
36 Mem_use : INTEGER := use_RAM
36 Mem_use : INTEGER := use_RAM;
37 FILENAME : STRING:= ""
37 );
38 );
38 PORT(
39 PORT(
39 rstn : IN STD_LOGIC;
40 rstn : IN STD_LOGIC;
@@ -81,7 +82,7 BEGIN
81 WEN <= NOT ram_write_s;
82 WEN <= NOT ram_write_s;
82 REN <= NOT ram_read;
83 REN <= NOT ram_read;
83 RAMblk : RAM_CEL
84 RAMblk : RAM_CEL
84 GENERIC MAP(Input_SZ_1, 8)
85 GENERIC MAP(Input_SZ_1, 8,FILENAME)
85 PORT MAP(
86 PORT MAP(
86 WD => WD,
87 WD => WD,
87 RD => RD,
88 RD => RD,
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@@ -128,7 +128,8 PACKAGE iir_filter IS
128 Coef_Nb : INTEGER;
128 Coef_Nb : INTEGER;
129 Coef_sel_SZ : INTEGER;
129 Coef_sel_SZ : INTEGER;
130 Cels_count : INTEGER;
130 Cels_count : INTEGER;
131 ChanelsCount : INTEGER);
131 ChanelsCount : INTEGER;
132 FILENAME : STRING);
132 PORT (
133 PORT (
133 rstn : IN STD_LOGIC;
134 rstn : IN STD_LOGIC;
134 clk : IN STD_LOGIC;
135 clk : IN STD_LOGIC;
@@ -232,7 +233,8 PACKAGE iir_filter IS
232
233
233 COMPONENT RAM_CEL is
234 COMPONENT RAM_CEL is
234 generic(DataSz : integer range 1 to 32 := 8;
235 generic(DataSz : integer range 1 to 32 := 8;
235 abits : integer range 2 to 12 := 8);
236 abits : integer range 2 to 12 := 8;
237 FILENAME : STRING:="");
236 port( WD : in std_logic_vector(DataSz-1 downto 0); RD : out
238 port( WD : in std_logic_vector(DataSz-1 downto 0); RD : out
237 std_logic_vector(DataSz-1 downto 0);WEN, REN : in std_logic;
239 std_logic_vector(DataSz-1 downto 0);WEN, REN : in std_logic;
238 WADDR : in std_logic_vector(abits-1 downto 0); RADDR : in
240 WADDR : in std_logic_vector(abits-1 downto 0); RADDR : in
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