diff --git a/designs/Validation_IIR_f0_LFR/Makefile b/designs/Validation_IIR_f0_LFR/Makefile --- a/designs/Validation_IIR_f0_LFR/Makefile +++ b/designs/Validation_IIR_f0_LFR/Makefile @@ -26,8 +26,9 @@ TECHLIBS = axcelerator LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ tmtc openchip hynix ihp gleichmann micron usbhc opencores -DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ +DIRSKIP = b1553 pcif leon2 leon3v3 leon2ft crypto satcan ddr usb ata i2c \ pci grusbhc haps slink ascs can pwm greth coremp7 spi ac97 \ + ./dsp/lpp_fft_rtax \ ./amba_lcd_16x2_ctrlr \ ./general_purpose/lpp_AMR \ ./general_purpose/lpp_balise \ @@ -40,14 +41,18 @@ DIRSKIP = b1553 pcif leon2 leon2ft crypt ./lpp_uart \ ./lpp_usb \ ./dsp/lpp_fft \ + ./lpp_leon3_soc \ + ./lpp_debug_lfr FILESKIP = i2cmst.vhd \ APB_MULTI_DIODE.vhd \ APB_MULTI_DIODE.vhd \ Top_MatrixSpec.vhd \ APB_FFT.vhd \ + lpp_lfr_ms_FFT.vhd \ lpp_lfr_apbreg.vhd \ - CoreFFT.vhd + CoreFFT.vhd \ + lpp_lfr_ms.vhd include $(GRLIB)/bin/Makefile include $(GRLIB)/software/leon3/Makefile diff --git a/designs/Validation_IIR_f0_LFR/tb.vhd b/designs/Validation_IIR_f0_LFR/tb.vhd --- a/designs/Validation_IIR_f0_LFR/tb.vhd +++ b/designs/Validation_IIR_f0_LFR/tb.vhd @@ -22,6 +22,10 @@ USE lpp.lpp_lfr_pkg.ALL; USE lpp.general_purpose.ALL; ENTITY testbench IS +GENERIC( + tech : INTEGER := 0; --axcel, + Mem_use : INTEGER := use_CEL --use_RAM +); END; ARCHITECTURE behav OF testbench IS @@ -121,14 +125,15 @@ BEGIN IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 GENERIC MAP ( - tech => axcel, + tech => tech, Mem_use => use_RAM, Sample_SZ => 18, Coef_SZ => Coef_SZ, Coef_Nb => 25, Coef_sel_SZ => 5, Cels_count => Cels_count, - ChanelsCount => ChanelCount) + ChanelsCount => ChanelCount, + FILENAME => "RAM.txt") PORT MAP ( rstn => rstn, clk => clk, diff --git a/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd b/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd --- a/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd +++ b/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd @@ -40,7 +40,8 @@ ENTITY IIR_CEL_CTRLR_v2 IS Coef_Nb : INTEGER := 25; Coef_sel_SZ : INTEGER := 5; Cels_count : INTEGER := 5; - ChanelsCount : INTEGER := 8); + ChanelsCount : INTEGER := 8; + FILENAME : STRING := ""); PORT ( rstn : IN STD_LOGIC; clk : IN STD_LOGIC; @@ -64,7 +65,8 @@ ARCHITECTURE ar_IIR_CEL_CTRLR_v2 OF IIR_ Sample_SZ : INTEGER; Coef_SZ : INTEGER; Coef_Nb : INTEGER; - Coef_sel_SZ : INTEGER); + Coef_sel_SZ : INTEGER; + FILENAME : STRING); PORT ( rstn : IN STD_LOGIC; clk : IN STD_LOGIC; @@ -143,7 +145,8 @@ BEGIN Sample_SZ => Sample_SZ, Coef_SZ => Coef_SZ, Coef_Nb => Coef_Nb, - Coef_sel_SZ => Coef_sel_SZ) + Coef_sel_SZ => Coef_sel_SZ, + FILENAME => FILENAME) PORT MAP ( rstn => rstn, clk => clk, diff --git a/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd b/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd --- a/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd +++ b/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd @@ -35,7 +35,8 @@ ENTITY IIR_CEL_CTRLR_v2_DATAFLOW IS Sample_SZ : INTEGER := 16; Coef_SZ : INTEGER := 9; Coef_Nb : INTEGER := 30; - Coef_sel_SZ : INTEGER := 5 + Coef_sel_SZ : INTEGER := 5; + FILENAME : STRING:= "" ); PORT( rstn : IN STD_LOGIC; @@ -70,7 +71,8 @@ ARCHITECTURE ar_IIR_CEL_CTRLR_v2_DATAFLO GENERIC ( tech : INTEGER; Input_SZ_1 : INTEGER; - Mem_use : INTEGER); + Mem_use : INTEGER; + FILENAME : STRING); PORT ( rstn : IN STD_LOGIC; clk : IN STD_LOGIC; @@ -129,7 +131,8 @@ BEGIN GENERIC MAP ( tech => tech, Input_SZ_1 => Sample_SZ, - Mem_use => Mem_use) + Mem_use => Mem_use, + FILENAME => FILENAME) PORT MAP ( clk => clk, rstn => rstn, diff --git a/lib/lpp/dsp/iir_filter/RAM_CEL.vhd b/lib/lpp/dsp/iir_filter/RAM_CEL.vhd --- a/lib/lpp/dsp/iir_filter/RAM_CEL.vhd +++ b/lib/lpp/dsp/iir_filter/RAM_CEL.vhd @@ -21,12 +21,18 @@ ------------------------------------------------------------------------------ LIBRARY ieee; USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_textio.ALL; USE IEEE.numeric_std.ALL; +LIBRARY std; +USE std.textio.ALL; + ENTITY RAM_CEL IS GENERIC( DataSz : INTEGER RANGE 1 TO 32 := 8; - abits : INTEGER RANGE 2 TO 12 := 8); + abits : INTEGER RANGE 2 TO 12 := 8; + FILENAME : string:= "" + ); PORT( WD : IN STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0); RD : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0); @@ -46,28 +52,53 @@ ARCHITECTURE ar_RAM_CEL OF RAM_CEL IS TYPE RAMarrayT IS ARRAY (0 TO MAX-1) OF STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0); - SIGNAL RAMarray : RAMarrayT := (OTHERS => VectInit); SIGNAL RD_int : STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0); SIGNAL RADDR_reg : STD_LOGIC_VECTOR(abits-1 DOWNTO 0); + + + -- Read a *.hex file + impure function ReadMemFile(FileName : STRING) return RAMarrayT is + file FileHandle : TEXT open READ_MODE is FileName; + variable CurrentLine : LINE; + variable TempWord : STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0); + variable Result : RAMarrayT := (others => (others => '0')); + begin + for i in 0 to MAX - 1 loop + exit when endfile(FileHandle); + readline(FileHandle, CurrentLine); + hread(CurrentLine, TempWord); + Result(i) := TempWord; + end loop; + + return Result; + end function; + + impure function InitMem(FileName : STRING) return RAMarrayT is + variable Result : RAMarrayT := (others => (others => '0')); + begin + if FileName'length /= 0 then + Result := ReadMemFile(FileName); + end if; + return Result; + end function; + + SIGNAL RAMarray : RAMarrayT := InitMem(FILENAME); BEGIN RD_int <= RAMarray(to_integer(UNSIGNED(RADDR))); - PROCESS(RWclk, reset) BEGIN IF reset = '0' THEN RD <= VectInit; - rst : FOR i IN 0 TO MAX-1 LOOP - RAMarray(i) <= (OTHERS => '0'); - END LOOP; +-- rst : FOR i IN 0 TO MAX-1 LOOP +-- RAMarray(i) <= (OTHERS => '0'); +-- END LOOP; ELSIF RWclk'EVENT AND RWclk = '1' THEN --- IF REN = '0' THEN RD <= RD_int; --- END IF; IF REN = '0' THEN RADDR_reg <= RADDR; END IF; diff --git a/lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd b/lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd --- a/lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd +++ b/lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd @@ -33,7 +33,8 @@ ENTITY RAM_CTRLR_v2 IS GENERIC( tech : INTEGER := 0; Input_SZ_1 : INTEGER := 16; - Mem_use : INTEGER := use_RAM + Mem_use : INTEGER := use_RAM; + FILENAME : STRING:= "" ); PORT( rstn : IN STD_LOGIC; @@ -81,7 +82,7 @@ BEGIN WEN <= NOT ram_write_s; REN <= NOT ram_read; RAMblk : RAM_CEL - GENERIC MAP(Input_SZ_1, 8) + GENERIC MAP(Input_SZ_1, 8,FILENAME) PORT MAP( WD => WD, RD => RD, diff --git a/lib/lpp/dsp/iir_filter/iir_filter.vhd b/lib/lpp/dsp/iir_filter/iir_filter.vhd --- a/lib/lpp/dsp/iir_filter/iir_filter.vhd +++ b/lib/lpp/dsp/iir_filter/iir_filter.vhd @@ -128,7 +128,8 @@ PACKAGE iir_filter IS Coef_Nb : INTEGER; Coef_sel_SZ : INTEGER; Cels_count : INTEGER; - ChanelsCount : INTEGER); + ChanelsCount : INTEGER; + FILENAME : STRING); PORT ( rstn : IN STD_LOGIC; clk : IN STD_LOGIC; @@ -232,7 +233,8 @@ PACKAGE iir_filter IS COMPONENT RAM_CEL is generic(DataSz : integer range 1 to 32 := 8; - abits : integer range 2 to 12 := 8); + abits : integer range 2 to 12 := 8; + FILENAME : STRING:=""); port( WD : in std_logic_vector(DataSz-1 downto 0); RD : out std_logic_vector(DataSz-1 downto 0);WEN, REN : in std_logic; WADDR : in std_logic_vector(abits-1 downto 0); RADDR : in