diff --git a/designs/Validation_IIR_f0_LFR/Makefile b/designs/Validation_IIR_f0_LFR/Makefile
--- a/designs/Validation_IIR_f0_LFR/Makefile
+++ b/designs/Validation_IIR_f0_LFR/Makefile
@@ -12,8 +12,8 @@ EFFORT=high
 XSTOPT=
 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
-VHDLSYNFILES= IIR_CEL_TEST.vhd tb.vhd IIR_CEL_TEST_v3.vhd generator.vhd
-VHDLSIMFILES= tb.vhd
+VHDLSYNFILES= IIR_CEL_TEST.vhd tb.vhd IIR_CEL_TEST_v3.vhd generator.vhd sig_reader.vhd
+VHDLSIMFILES= tb.vhd sig_reader.vhd
 SIMTOP=testbench
 #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
 PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_RTAX.pdc
diff --git a/designs/Validation_IIR_f0_LFR/generator.vhd b/designs/Validation_IIR_f0_LFR/generator.vhd
--- a/designs/Validation_IIR_f0_LFR/generator.vhd
+++ b/designs/Validation_IIR_f0_LFR/generator.vhd
@@ -31,7 +31,8 @@ ENTITY generator IS
   
   GENERIC (
     AMPLITUDE            : INTEGER := 100;
-    NB_BITS              : INTEGER := 16);
+    NB_BITS              : INTEGER := 16
+    );
 
   PORT (
     clk      : IN  STD_LOGIC;
@@ -50,7 +51,6 @@ ARCHITECTURE beh OF generator IS
   SIGNAL reg : STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0);
 BEGIN  -- beh
 
-  
   PROCESS (clk, rstn)
     variable seed1, seed2: positive; -- seed values for random generator
     variable rand: real; -- random real-number value in range 0 to 1.0  
diff --git a/designs/Validation_IIR_f0_LFR/make_signals.ipynb b/designs/Validation_IIR_f0_LFR/make_signals.ipynb
new file mode 100644
--- /dev/null
+++ b/designs/Validation_IIR_f0_LFR/make_signals.ipynb
@@ -0,0 +1,60 @@
+{
+ "cells": [
+  {
+   "cell_type": "code",
+   "execution_count": 8,
+   "metadata": {
+    "collapsed": true
+   },
+   "outputs": [],
+   "source": [
+    "import numpy as np\n",
+    "import matplotlib.pyplot as plt\n",
+    "import random"
+   ]
+  },
+  {
+   "cell_type": "code",
+   "execution_count": 32,
+   "metadata": {
+    "collapsed": false
+   },
+   "outputs": [],
+   "source": [
+    "W,H=8,1000\n",
+    "test = np.ones((H,W))*[(random.random()*65535)-32768 for col in range(W)]\n",
+    "np.savetxt(\"input.txt\", test,fmt=\"%d\", delimiter=\" \")"
+   ]
+  },
+  {
+   "cell_type": "code",
+   "execution_count": 28,
+   "metadata": {
+    "collapsed": false
+   },
+   "outputs": [],
+   "source": []
+  }
+ ],
+ "metadata": {
+  "kernelspec": {
+   "display_name": "Python 3",
+   "language": "python",
+   "name": "python3"
+  },
+  "language_info": {
+   "codemirror_mode": {
+    "name": "ipython",
+    "version": 3
+   },
+   "file_extension": ".py",
+   "mimetype": "text/x-python",
+   "name": "python",
+   "nbconvert_exporter": "python",
+   "pygments_lexer": "ipython3",
+   "version": "3.5.2"
+  }
+ },
+ "nbformat": 4,
+ "nbformat_minor": 1
+}
diff --git a/designs/Validation_IIR_f0_LFR/sig_reader.vhd b/designs/Validation_IIR_f0_LFR/sig_reader.vhd
new file mode 100644
--- /dev/null
+++ b/designs/Validation_IIR_f0_LFR/sig_reader.vhd
@@ -0,0 +1,53 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+LIBRARY std;
+USE std.textio.ALL;
+
+LIBRARY lpp;
+USE lpp.data_type_pkg.ALL;
+
+ENTITY sig_reader IS
+GENERIC(
+    FNAME       : STRING  := "input.txt";
+    WIDTH       : INTEGER := 1;
+    RESOLUTION  : INTEGER := 8;
+    GAIN        : REAL    := 1.0
+);
+PORT(
+    clk             : IN std_logic;
+    end_of_simu     : out std_logic;
+    out_signal      : out sample_vector(0 to WIDTH-1,RESOLUTION-1 downto 0)
+);
+END sig_reader;
+
+ARCHITECTURE beh OF sig_reader IS
+  FILE input_file    : TEXT OPEN read_mode IS FNAME;
+  SIGNAL out_signal_reg  :  sample_vector(0 to WIDTH-1,RESOLUTION-1 downto 0):=(others=>(others=>'0'));
+  SIGNAL end_of_simu_reg     :  std_logic:='0';
+BEGIN 
+    out_signal <= out_signal_reg;
+    end_of_simu <= end_of_simu_reg;
+    PROCESS
+        VARIABLE line_var : LINE;
+        VARIABLE value    : INTEGER;
+        VARIABLE cell     : STD_LOGIC_VECTOR(RESOLUTION-1 downto 0);
+    BEGIN
+        WAIT UNTIL clk = '1';
+        IF endfile(input_file) THEN
+            end_of_simu_reg <= '1';
+        ELSE
+            end_of_simu_reg <= '0';
+            readline(input_file,line_var);
+            FOR COL IN 0 TO WIDTH-1 LOOP
+                read(line_var, value);
+                cell := std_logic_vector(to_signed(INTEGER(GAIN*REAL(value)) , RESOLUTION));
+                FOR bit_idx IN RESOLUTION-1 downto 0 LOOP
+                    out_signal_reg(COL,bit_idx) <= cell(bit_idx);
+                END LOOP;
+            END LOOP;
+        END IF;
+    END PROCESS;
+
+END beh;
diff --git a/designs/Validation_IIR_f0_LFR/tb.vhd b/designs/Validation_IIR_f0_LFR/tb.vhd
--- a/designs/Validation_IIR_f0_LFR/tb.vhd
+++ b/designs/Validation_IIR_f0_LFR/tb.vhd
@@ -23,8 +23,8 @@ USE lpp.general_purpose.ALL;
 
 ENTITY testbench IS
 GENERIC(
-    tech          : INTEGER := 0; --axcel,
-    Mem_use       : INTEGER := use_CEL --use_RAM
+    tech          : INTEGER := 0; --axcel,0
+    Mem_use       : INTEGER := use_CEL --use_RAM,use_CEL
 );
 END;
 
@@ -52,8 +52,7 @@ ARCHITECTURE behav OF testbench IS
   SIGNAL clk_24k_r : STD_LOGIC := '0';
   SIGNAL rstn      : STD_LOGIC;
 
-  SIGNAL signal_gen : Samples(7 DOWNTO 0);
-  SIGNAL offset_gen : Samples(7 DOWNTO 0);
+  SIGNAL signal_gen : sample_vector(0 to ChanelCount-1,17 downto 0);
 
   --SIGNAL sample_fx_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
 
@@ -75,10 +74,24 @@ ARCHITECTURE behav OF testbench IS
       data     : OUT STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0)
       );
   END COMPONENT;
+  
+  COMPONENT sig_reader IS
+    GENERIC(
+        FNAME       : STRING  := "input.txt";
+        WIDTH       : INTEGER := 1;
+        RESOLUTION  : INTEGER := 8;
+        GAIN        : REAL    := 1.0
+    );
+    PORT(
+        clk             : IN std_logic;
+        end_of_simu     : out std_logic;
+        out_signal      : out sample_vector(0 to WIDTH-1,RESOLUTION-1 downto 0)
+    );
+  END COMPONENT;
 
 
-  FILE log_input     : TEXT OPEN write_mode IS "log_input.txt";
-  FILE log_output_fx : TEXT OPEN write_mode IS "log_output_fx.txt";
+  FILE input     : TEXT OPEN read_mode IS "input.txt";
+  FILE output_fx : TEXT OPEN write_mode IS "output_fx.txt";
 
   SIGNAL end_of_simu : STD_LOGIC := '0';
 
@@ -87,18 +100,16 @@ BEGIN
   -----------------------------------------------------------------------------
   -- CLOCK and RESET
   -----------------------------------------------------------------------------
-  clk <= NOT clk AFTER 5 ns;
+  clk <= NOT clk AFTER 20 ns;
   PROCESS
   BEGIN  -- PROCESS
-    end_of_simu <= '0';
     WAIT UNTIL clk = '1';
     rstn <= '0';
     WAIT UNTIL clk = '1';
     WAIT UNTIL clk = '1';
     WAIT UNTIL clk = '1';
     rstn <= '1';
-    WAIT FOR 2000 ms;
-    end_of_simu <= '1';
+    WAIT UNTIL end_of_simu = '1';
     WAIT UNTIL clk = '1';    
     REPORT "*** END simulation ***" SEVERITY failure;
     WAIT;
@@ -133,7 +144,7 @@ BEGIN
       Coef_sel_SZ  => 5,
       Cels_count   => Cels_count,
       ChanelsCount => ChanelCount,
-      FILENAME     => "RAM.txt")
+      FILENAME     => "")
     PORT MAP (
       rstn     => rstn,
       clk      => clk,
@@ -167,49 +178,39 @@ BEGIN
     END IF;
   END PROCESS;
   -----------------------------------------------------------------------------
-  generators : FOR I IN 0 TO 7 GENERATE
-    gen1 : generator
-      GENERIC MAP (
-        AMPLITUDE => 100,
-        NB_BITS   => 16)
-      PORT MAP (
-        clk      => clk,
-        rstn     => rstn,
-        run      => '1',
-        data_ack => sample_val,
-        offset   => offset_gen(I),
-        data     => signal_gen(I)
-        );
-    offset_gen(I) <= STD_LOGIC_VECTOR(to_signed((I*200), 16));
-  END GENERATE generators;
 
   ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
     SampleLoop : FOR j IN 0 TO 15 GENERATE
-      sample(i,j) <= signal_gen(i)(j);
       sample_fx_wdata(i)(j) <= sample_fx(i,j);
+      sample(i,j) <= signal_gen(i,j);
     END GENERATE;
-
-    sample(i, 16) <= signal_gen(i)(15);
-    sample(i, 17) <= signal_gen(i)(15);
+      sample(i,16) <= signal_gen(i,16);
+      sample(i,17) <= signal_gen(i,17);
   END GENERATE;
 
   
     
   -----------------------------------------------------------------------------
-  --  RECORD SIGNALS
+  --  READ INPUT SIGNALS
   -----------------------------------------------------------------------------
 
-  -- PROCESS(sample_val)
-  --   VARIABLE line_var : LINE;
-  -- BEGIN
-  --   IF sample_val'EVENT AND sample_val = '1' THEN
-  --     write(line_var, INTEGER'IMAGE(TSTAMP));
-  --     FOR I IN 0 TO 7 LOOP
-  --       write(line_var, "  " & INTEGER'IMAGE(to_integer(SIGNED(signal_gen(I)))));
-  --     END LOOP;
-  --     writeline(log_input, line_var);
-  --   END IF;
-  --  END PROCESS;
+  gen: sig_reader
+  GENERIC MAP(
+        FNAME       => "input.txt",
+        WIDTH       => ChanelCount,
+        RESOLUTION  => 18,
+        GAIN        => 1.0
+    )
+    PORT MAP(
+        clk             => sample_val,
+        end_of_simu     => end_of_simu,
+        out_signal      => signal_gen
+    );
+    
+  
+  -----------------------------------------------------------------------------
+  --  RECORD OUTPUT SIGNALS
+  -----------------------------------------------------------------------------
 
   PROCESS(sample_fx_val,end_of_simu)
     VARIABLE line_var : LINE;
@@ -219,10 +220,10 @@ BEGIN
       FOR I IN 0 TO 5 LOOP
         write(line_var, "  " & INTEGER'IMAGE(to_integer(SIGNED(sample_fx_wdata(I)))));
       END LOOP;
-      writeline(log_output_fx, line_var);
+      writeline(output_fx, line_var);
     END IF;
     IF end_of_simu = '1' THEN
-      file_close(log_output_fx);
+      file_close(output_fx);
     END IF;
   END PROCESS;
 
diff --git a/lib/lpp/dsp/iir_filter/RAM_CEL.vhd b/lib/lpp/dsp/iir_filter/RAM_CEL.vhd
--- a/lib/lpp/dsp/iir_filter/RAM_CEL.vhd
+++ b/lib/lpp/dsp/iir_filter/RAM_CEL.vhd
@@ -79,8 +79,10 @@ ARCHITECTURE ar_RAM_CEL OF RAM_CEL IS
         variable Result       : RAMarrayT    := (others => (others => '0'));
     begin
         if FileName'length /= 0 then
+            report "initialysing RAM CEL From file "& FileName;
             Result := ReadMemFile(FileName);
         end if;
+        report "initialysing RAM CEL To 0";
         return Result;
     end function;