HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · designs/Validation_IIR_f0_LFR/Makefile

Improved testbench for LFR's F0 IIR Filter, now processed input is read from...

Improved testbench for LFR's F0 IIR Filter, now processed input is read from a file.

Jeandet Alexis - - Load All Authors

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      #GRLIB=../..

      VHDLIB=../..

      SCRIPTSDIR=$(VHDLIB)/scripts/

      GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)

      TOP=testbench

      BOARD=LFR-EQM

      include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc

      DEVICE=$(PART)-$(PACKAGE)$(SPEED)

      UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf

      QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf

      EFFORT=high

      XSTOPT=

      SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"

      #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd

      VHDLSYNFILES= IIR_CEL_TEST.vhd tb.vhd IIR_CEL_TEST_v3.vhd generator.vhd sig_reader.vhd

      VHDLSIMFILES= tb.vhd sig_reader.vhd

      SIMTOP=testbench

      #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc

      PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_RTAX.pdc

      SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_altran_syn_fanout.sdc

      BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut

      CLEAN=soft-clean

      TECHLIBS = axcelerator

      LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \

      	tmtc openchip hynix ihp gleichmann micron usbhc  opencores

      DIRSKIP = b1553 pcif leon2 leon3v3 leon2ft crypto satcan ddr usb ata i2c \

      	pci grusbhc haps slink ascs can pwm greth coremp7 spi ac97 \

      	./dsp/lpp_fft_rtax \

      	./amba_lcd_16x2_ctrlr \

      	./general_purpose/lpp_AMR \

      	./general_purpose/lpp_balise \

      	./general_purpose/lpp_delay \

      	./lpp_bootloader \

      	./lfr_management \

      	./lpp_sim \

      	./lpp_sim/CY7C1061DV33 \

      	./lpp_cna \

      	./lpp_uart \

      	./lpp_usb \

      	./dsp/lpp_fft \

      	./lpp_leon3_soc \

      	./lpp_debug_lfr

      FILESKIP = i2cmst.vhd \

      	APB_MULTI_DIODE.vhd \

      	APB_MULTI_DIODE.vhd \

      	Top_MatrixSpec.vhd \

      	APB_FFT.vhd \

              lpp_lfr_ms_FFT.vhd \

      	lpp_lfr_apbreg.vhd \

      	CoreFFT.vhd \

      	lpp_lfr_ms.vhd

      include $(GRLIB)/bin/Makefile

      include $(GRLIB)/software/leon3/Makefile

      ##################  project specific targets ##########################

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				#GRLIB=../..
				VHDLIB=../..
				SCRIPTSDIR=$(VHDLIB)/scripts/
				GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
				TOP=testbench
				BOARD=LFR-EQM
				include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc
				DEVICE=$(PART)-$(PACKAGE)$(SPEED)
				UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
				QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
				EFFORT=high
				XSTOPT=
				SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
				#VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
				VHDLSYNFILES= IIR_CEL_TEST.vhd tb.vhd IIR_CEL_TEST_v3.vhd generator.vhd sig_reader.vhd
				VHDLSIMFILES= tb.vhd sig_reader.vhd
				SIMTOP=testbench
				#SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
				PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_RTAX.pdc
				SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_altran_syn_fanout.sdc
				BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
				CLEAN=soft-clean

				TECHLIBS = axcelerator

				LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
				tmtc openchip hynix ihp gleichmann micron usbhc opencores

				DIRSKIP = b1553 pcif leon2 leon3v3 leon2ft crypto satcan ddr usb ata i2c \
				pci grusbhc haps slink ascs can pwm greth coremp7 spi ac97 \
				./dsp/lpp_fft_rtax \
				./amba_lcd_16x2_ctrlr \
				./general_purpose/lpp_AMR \
				./general_purpose/lpp_balise \
				./general_purpose/lpp_delay \
				./lpp_bootloader \
				./lfr_management \
				./lpp_sim \
				./lpp_sim/CY7C1061DV33 \
				./lpp_cna \
				./lpp_uart \
				./lpp_usb \
				./dsp/lpp_fft \
				./lpp_leon3_soc \
				./lpp_debug_lfr

				FILESKIP = i2cmst.vhd \
				APB_MULTI_DIODE.vhd \
				APB_MULTI_DIODE.vhd \
				Top_MatrixSpec.vhd \
				APB_FFT.vhd \
				lpp_lfr_ms_FFT.vhd \
				lpp_lfr_apbreg.vhd \
				CoreFFT.vhd \
				lpp_lfr_ms.vhd

				include $(GRLIB)/bin/Makefile
				include $(GRLIB)/software/leon3/Makefile

				################## project specific targets ##########################