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Few fixes....
jeandet -
r682:c53e1b6b3045 default draft
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@@ -0,0 +1,52
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2017, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@member.fsf.org
21 -------------------------------------------------------------------------------
22 LIBRARY ieee;
23 USE ieee.std_logic_1164.ALL;
24 USE ieee.numeric_std.ALL;
25
26
27 PACKAGE CY7C1061DV33_pkg IS
28
29 COMPONENT CY7C1061DV33 IS
30 GENERIC
31 (ADDR_BITS : INTEGER := 20;
32 DATA_BITS : INTEGER := 16;
33 depth : INTEGER := 1048576;
34
35 MEM_ARRAY_DEBUG : INTEGER := 32;
36
37 TimingInfo : BOOLEAN := true;
38 TimingChecks : STD_LOGIC := '1'
39 );
40 PORT (
41 CE1_b : IN STD_LOGIC; -- Chip Enable CE1#
42 CE2 : IN STD_LOGIC; -- Chip Enable CE2
43 WE_b : IN STD_LOGIC; -- Write Enable WE#
44 OE_b : IN STD_LOGIC; -- Output Enable OE#
45 BHE_b : IN STD_LOGIC; -- Byte Enable High BHE#
46 BLE_b : IN STD_LOGIC; -- Byte Enable Low BLE#
47 A : IN STD_LOGIC_VECTOR(addr_bits-1 DOWNTO 0); -- Address Inputs A
48 DQ : INOUT STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0) := (OTHERS => 'Z')-- Read/Write Data IO;
49 );
50 END COMPONENT;
51
52 END CY7C1061DV33_pkg;
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@@ -0,0 +1,70
1 --****************************************************************
2 --** MODEL : package_utility **
3 --** COMPANY : Cypress Semiconductor **
4 --** REVISION: 1.0 Created new package utility model **
5 --** **
6 --****************************************************************
7 Library ieee,work;
8 Use ieee.std_logic_1164.all;
9 Use IEEE.Std_Logic_Arith.all;
10 Use IEEE.std_logic_TextIO.all;
11
12 Library Std;
13 Use STD.TextIO.all;
14
15 Package package_utility is
16
17 FUNCTION convert_string( S: in STRING) RETURN STD_LOGIC_VECTOR;
18 FUNCTION conv_integer1(S : STD_LOGIC_VECTOR) RETURN INTEGER;
19
20 End; -- package package_utility
21
22 Package body package_utility is
23
24
25 ------------------------------------------------------------------------------------------------
26 --Converts string into std_logic_vector
27 ------------------------------------------------------------------------------------------------
28
29 FUNCTION convert_string(S: in STRING) RETURN STD_LOGIC_VECTOR IS
30 VARIABLE result : STD_LOGIC_VECTOR(S'RANGE);
31 BEGIN
32 FOR i IN S'RANGE LOOP
33 IF S(i) = '0' THEN
34 result(i) := '0';
35 ELSIF S(i) = '1' THEN
36 result(i) := '1';
37 ELSIF S(i) = 'X' THEN
38 result(i) := 'X';
39 ELSE
40 result(i) := 'Z';
41 END IF;
42 END LOOP;
43 RETURN result;
44 END convert_string;
45
46 ------------------------------------------------------------------------------------------------
47 --Converts std_logic_vector into integer
48 ------------------------------------------------------------------------------------------------
49
50 FUNCTION conv_integer1(S : STD_LOGIC_VECTOR) RETURN INTEGER IS
51 VARIABLE result : INTEGER := 0;
52 BEGIN
53 FOR i IN S'RANGE LOOP
54 IF S(i) = '1' THEN
55 result := result + (2**i);
56 ELSIF S(i) = '0' THEN
57 result := result;
58 ELSE
59 result := 0;
60 END IF;
61 END LOOP;
62 RETURN result;
63 END conv_integer1;
64
65
66
67
68 end package_utility;
69
70
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@@ -39,8 +39,9 package FFT_COMPONENTS is
39 39 function to_integer( x : boolean) return integer;
40 40 function maskbar (barn, bar_enable,dma_reg_bar,dma_reg_loc : integer) return integer;
41 41 function anyfifo (bar0, bar1, bar2, bar3, bar4, bar5 : integer) return integer;
42 FUNCTION reverse (x : std_logic_vector) RETURN bit_vector;
43 FUNCTION reverseStd(x : std_logic_vector) RETURN std_logic_vector;
42 FUNCTION reverse (x :IN std_logic_vector) RETURN bit_vector;
43
44 FUNCTION reverseStd(x :IN std_logic_vector) RETURN std_logic_vector;
44 45
45 46 COMPONENT counter
46 47 GENERIC (
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@@ -1,4 +1,4
1 1 package_utility.vhd
2 2 package_timing.vhd
3 CY7C1061DV33.vhd
3 4 CY7C1061DV33_pkg.vhd
4 CY7C1061DV33.vhd
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@@ -2,7 +2,7 VHDLIB=../..
2 2 SCRIPTSDIR=$(VHDLIB)/scripts/
3 3 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 4 TOP=testbench
5 BOARD=LFR-EQM
5 BOARD=LFR-FM
6 6 include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc
7 7 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 8 UCF=
@@ -11,74 +11,43 EFFORT=high
11 11 XSTOPT=
12 12 SYNPOPT=
13 13 VHDLSYNFILES=
14 VHDLSIMFILES= tb.vhd $(VHDLIB)/boards/designs/LFR-EQM-RTAX/LFR-EQM.vhd
14 VHDLSIMFILES= $(VHDLIB)/designs/SOLO_LFR_LFR-FM/LFR-FM.vhd tb.vhd
15 15 SIMTOP=testbench
16 16 CLEAN=soft-clean
17 17
18 18 TECHLIBS = axcelerator
19 19
20 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
21 tmtc openchip hynix ihp gleichmann micron usbhc opencores fmf ftlib gsi
20
21 LIBSKIP = tmtc openchip hynix cypress ihp usbhc fmf gsi spansion eth micron
22 22
23 DIRSKIP = b1553 pcif leon2 leon3v3 leon2ft crypto satcan ddr usb ata i2c \
24 pci grusbhc haps slink ascs can pwm greth coremp7 spi ac97 srmmu atf \
25 grlfpc \
26 ./dsp/lpp_fft_rtax \
23 DIRSKIP = leon2 leon2ft crypto usb satcan ddr greth grusbhc \
24 leon4 leon4v0 l2cache iommu slink ascs pwm net spi can \
27 25 ./amba_lcd_16x2_ctrlr \
28 26 ./general_purpose/lpp_AMR \
29 27 ./general_purpose/lpp_balise \
30 28 ./general_purpose/lpp_delay \
31 29 ./lpp_bootloader \
32 ./lfr_management \
33 ./lpp_sim/CY7C1061DV33 \
34 ./lpp_cna \
35 30 ./lpp_uart \
36 31 ./lpp_usb \
37 ./dsp/lpp_fft \
38 ./lpp_leon3_soc \
39 ./lpp_debug_lfr
32 ./lpp_debug_lfr \
33 ./dsp/lpp_fft
40 34
41 35 FILESKIP = i2cmst.vhd \
42 36 APB_MULTI_DIODE.vhd \
43 37 APB_MULTI_DIODE.vhd \
44 38 Top_MatrixSpec.vhd \
45 39 APB_FFT.vhd \
46 lpp_lfr_ms_FFT.vhd \
47 lpp_lfr_apbreg.vhd \
48 CoreFFT.vhd \
49 lpp_lfr_ms.vhd \
50 lpp_lfr_sim_pkg.vhd \
51 mtie_maps.vhd \
52 ftsrctrlc.vhd \
53 ftsdctrl.vhd \
54 ftsrctrl8.vhd \
55 ftmctrl.vhd \
56 ftsdctrl64.vhd \
57 ftahbram.vhd \
58 ftahbram2.vhd \
59 sramft.vhd \
60 nandfctrlx.vhd
40 lpp_lfr_sim_pkg.vhd
61 41
62 42 include $(GRLIB)/bin/Makefile
63 43 include $(GRLIB)/software/leon3/Makefile
64
65 44 ################## project specific targets ##########################
66 45 distclean:myclean
67 vsim:cp_for_vsim
68 46
69 47 myclean:
70 48 rm -f input.txt output_fx.txt *.log
71 49 rm -rf ./2016*
72 50
73 generate :
74 python ./generate.py
75
76 cp_for_vsim: generate
77 cp ./input.txt simulation/
78
79 archivate:
80 xonsh ./archivate.xsh
81
82 test: | generate ghdl ghdl-run archivate
51 test: | ghdl ghdl-run archivate
83 52
84 53
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@@ -11,6 +11,10 USE techmap.gencomp.ALL;
11 11 LIBRARY std;
12 12 USE std.textio.ALL;
13 13
14 library opencores;
15 use opencores.spwpkg.all;
16 use opencores.spwambapkg.all;
17
14 18 LIBRARY lpp;
15 19 USE lpp.iir_filter.ALL;
16 20 USE lpp.lpp_ad_conv.ALL;
@@ -21,7 +25,7 USE lpp.data_type_pkg.ALL;
21 25 USE lpp.lpp_lfr_pkg.ALL;
22 26 USE lpp.general_purpose.ALL;
23 27 USE lpp.lpp_sim_pkg.ALL;
24 USE lpp.lpp_waveform_pkg.ALL;
28 USE lpp.CY7C1061DV33_pkg.ALL;
25 29
26 30 ENTITY testbench IS
27 31 GENERIC(
@@ -32,78 +36,151 END;
32 36
33 37 ARCHITECTURE behav OF testbench IS
34 38
35
36 COMPONENT LFR_EQM IS
37 GENERIC (
38 Mem_use : INTEGER := use_RAM;
39 USE_BOOTLOADER : INTEGER := 0;
40 USE_ADCDRIVER : INTEGER := 1;
41 tech : INTEGER := inferred;
42 tech_leon : INTEGER := inferred;
43 DEBUG_FORCE_DATA_DMA : INTEGER := 0;
44 USE_DEBUG_VECTOR : INTEGER := 0
45 );
46
47 PORT (
48 clk50MHz : IN STD_ULOGIC;
49 clk49_152MHz : IN STD_ULOGIC;
50 reset : IN STD_ULOGIC;
51
52 TAG : INOUT STD_LOGIC_VECTOR(9 DOWNTO 1);
53
54 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
55 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
56
57 nSRAM_MBE : INOUT STD_LOGIC; -- new
58 nSRAM_E1 : OUT STD_LOGIC; -- new
59 nSRAM_E2 : OUT STD_LOGIC; -- new
60 -- nSRAM_SCRUB : OUT STD_LOGIC; -- new
61 nSRAM_W : OUT STD_LOGIC; -- new
62 nSRAM_G : OUT STD_LOGIC; -- new
63 nSRAM_BUSY : IN STD_LOGIC; -- new
64 -- SPW --------------------------------------------------------------------
65 spw1_en : OUT STD_LOGIC; -- new
66 spw1_din : IN STD_LOGIC;
67 spw1_sin : IN STD_LOGIC;
68 spw1_dout : OUT STD_LOGIC;
69 spw1_sout : OUT STD_LOGIC;
70 spw2_en : OUT STD_LOGIC; -- new
71 spw2_din : IN STD_LOGIC;
72 spw2_sin : IN STD_LOGIC;
73 spw2_dout : OUT STD_LOGIC;
74 spw2_sout : OUT STD_LOGIC;
75 -- ADC --------------------------------------------------------------------
76 bias_fail_sw : OUT STD_LOGIC;
77 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
78 ADC_smpclk : OUT STD_LOGIC;
79 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
80 -- DAC --------------------------------------------------------------------
81 DAC_SDO : OUT STD_LOGIC;
82 DAC_SCK : OUT STD_LOGIC;
83 DAC_SYNC : OUT STD_LOGIC;
84 DAC_CAL_EN : OUT STD_LOGIC;
85 -- HK ---------------------------------------------------------------------
86 HK_smpclk : OUT STD_LOGIC;
87 ADC_OEB_bar_HK : OUT STD_LOGIC;
88 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
89 );
90
91 END LFR_EQM;
92
93
94 39 SIGNAL TSTAMP : INTEGER := 0;
95 40 SIGNAL clk : STD_LOGIC := '0';
96 SIGNAL clk_24576Hz : STD_LOGIC := '0';
97 SIGNAL clk_24576Hz_r : STD_LOGIC := '0';
98 SIGNAL rstn : STD_LOGIC;
99
100 SIGNAL signal_gen : sample_vector(0 to ChanelCount-1,17 downto 0);
101 SIGNAL sample_fx_wdata : Samples(ChanelCount-1 DOWNTO 0);
102 SIGNAL signal_rec : sample_vector(0 to ChanelCount-1,15 downto 0);
41 SIGNAL clk49_152MHz : STD_LOGIC := '0';
42 SIGNAL rstn,rst : STD_LOGIC;
103 43
104 44 SIGNAL end_of_simu : STD_LOGIC := '0';
105 45
106 CONSTANT half_samplig_period : time := 20345052 ps; --INTEGER( REAL(1000**4) / REAL(2.0*24576.0)) * 1 ps;
46 -----------------------------------------------------------------------------
47 -- LFR TOP WRAPPER SIGNALS
48 -----------------------------------------------------------------------------
49 SIGNAL address : STD_LOGIC_VECTOR(18 DOWNTO 0);
50 SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0);
51
52 SIGNAL nSRAM_MBE : STD_LOGIC; -- new
53 SIGNAL nSRAM_E1 : STD_LOGIC; -- new
54 SIGNAL nSRAM_E2 : STD_LOGIC; -- new
55 -- nSRAM_SCRUB : OUT STD_LOGIC; -- new
56 SIGNAL nSRAM_W : STD_LOGIC; -- new
57 SIGNAL nSRAM_G : STD_LOGIC; -- new
58 SIGNAL nSRAM_BUSY : STD_LOGIC; -- new
59 -- SPW --------------------------------------------------------------------
60 SIGNAL spw1_en : STD_LOGIC; -- new
61 SIGNAL spw1_din : STD_LOGIC;
62 SIGNAL spw1_sin : STD_LOGIC;
63 SIGNAL spw1_dout : STD_LOGIC;
64 SIGNAL spw1_sout : STD_LOGIC;
65 SIGNAL spw2_en : STD_LOGIC; -- new
66 SIGNAL spw2_din : STD_LOGIC;
67 SIGNAL spw2_sin : STD_LOGIC;
68 SIGNAL spw2_dout : STD_LOGIC;
69 SIGNAL spw2_sout : STD_LOGIC;
70 -- ADC --------------------------------------------------------------------
71 SIGNAL bias_fail_sw : STD_LOGIC;
72 SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0);
73 SIGNAL ADC_smpclk : STD_LOGIC;
74 SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0);
75 -- DAC --------------------------------------------------------------------
76 SIGNAL DAC_SDO : STD_LOGIC;
77 SIGNAL DAC_SCK : STD_LOGIC;
78 SIGNAL DAC_SYNC : STD_LOGIC;
79 SIGNAL DAC_CAL_EN : STD_LOGIC;
80 -- HK ---------------------------------------------------------------------
81 SIGNAL HK_smpclk : STD_LOGIC;
82 SIGNAL ADC_OEB_bar_HK : STD_LOGIC;
83 SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0);
84
85 SIGNAL nSRAM_CE : STD_LOGIC;
86
87
88
89
90 SIGNAL autostart: std_logic := '1';
91
92 -- Enables link start once the Ready state is reached.
93 -- Without autostart or linkstart, the link remains in state Ready.
94 SIGNAL linkstart: std_logic :='1';
95
96 -- Do not start link (overrides linkstart and autostart) and/or
97 -- disconnect a running link.
98 SIGNAL linkdis: std_logic := '0';
99
100 -- Control bits of the TimeCode to be sent. Must be valid while tick_in is high.
101 SIGNAL ctrl_in: std_logic_vector(1 downto 0) :=(others => '0');
102
103 -- Counter value of the TimeCode to be sent. Must be valid while tick_in is high.
104 SIGNAL time_in: std_logic_vector(5 downto 0):=(others => '0');
105
106 -- Pulled high by the application to write an N-Char to the transmit
107 -- queue. If "txwrite" and "txrdy" are both high on the rising edge
108 -- of "clk", a character is added to the transmit queue.
109 -- This signal has no effect if "txrdy" is low.
110 SIGNAL txwrite: std_logic := '0';
111
112 -- Control flag to be sent with the next N_Char.
113 -- Must be valid while txwrite is high.
114 SIGNAL txflag: std_logic :='0';
115
116 -- Byte to be sent, or "00000000" for EOP or "00000001" for EEP.
117 -- Must be valid while txwrite is high.
118 SIGNAL txdata: std_logic_vector(7 downto 0):=(others => '0');
119
120 -- High if the entity is ready to accept an N-Char for transmission.
121 SIGNAL txrdy: std_logic;
122
123 -- High if the transmission queue is at least half full.
124 SIGNAL txhalff: std_logic;
125
126 -- High for one clock cycle if a TimeCode was just received.
127 SIGNAL tick_out: std_logic;
128
129 -- Control bits of the last received TimeCode.
130 SIGNAL ctrl_out: std_logic_vector(1 downto 0);
131
132 -- Counter value of the last received TimeCode.
133 SIGNAL time_out: std_logic_vector(5 downto 0);
134
135 -- High if "rxflag" and "rxdata" contain valid data.
136 -- This signal is high unless the receive FIFO is empty.
137 SIGNAL rxvalid: std_logic;
138
139 -- High if the receive FIFO is at least half full.
140 SIGNAL rxhalff: std_logic;
141
142 -- High if the received character is EOP or EEP; low if the received
143 -- character is a data byte. Valid if "rxvalid" is high.
144 SIGNAL rxflag: std_logic;
145
146 -- Received byte, or "00000000" for EOP or "00000001" for EEP.
147 -- Valid if "rxvalid" is high.
148 SIGNAL rxdata: std_logic_vector(7 downto 0);
149
150 -- Pulled high by the application to accept a received character.
151 -- If "rxvalid" and "rxread" are both high on the rising edge of "clk",
152 -- a character is removed from the receive FIFO and "rxvalid", "rxflag"
153 -- and "rxdata" are updated.
154 -- This signal has no effect if "rxvalid" is low.
155 SIGNAL rxread: std_logic:='0';
156
157 -- High if the link state machine is currently in the Started state.
158 SIGNAL started: std_logic;
159
160 -- High if the link state machine is currently in the Connecting state.
161 SIGNAL connecting: std_logic;
162
163 -- High if the link state machine is currently in the Run state, indicating
164 -- that the link is fully operational. If none of started, connecting or running
165 -- is high, the link is in an initial state and the transmitter is not yet enabled.
166 SIGNAL running: std_logic;
167
168 -- Disconnect detected in state Run. Triggers a reset and reconnect of the link.
169 -- This indication is auto-clearing.
170 SIGNAL errdisc: std_logic;
171
172 -- Parity error detected in state Run. Triggers a reset and reconnect of the link.
173 -- This indication is auto-clearing.
174 SIGNAL errpar: std_logic;
175
176 -- Invalid escape sequence detected in state Run. Triggers a reset and reconnect of
177 -- the link. This indication is auto-clearing.
178 SIGNAL erresc: std_logic;
179
180 -- Credit error detected. Triggers a reset and reconnect of the link.
181 -- This indication is auto-clearing.
182 SIGNAL errcred: std_logic;
183
107 184
108 185 BEGIN
109 186
@@ -114,10 +191,12 BEGIN
114 191 BEGIN -- PROCESS
115 192 WAIT UNTIL clk = '1';
116 193 rstn <= '0';
194 rst <= '1';
117 195 WAIT UNTIL clk = '1';
118 196 WAIT UNTIL clk = '1';
119 197 WAIT UNTIL clk = '1';
120 198 rstn <= '1';
199 rst <= '0';
121 200 WAIT UNTIL end_of_simu = '1';
122 201 WAIT FOR 10 ps;
123 202 assert false report "end of test" severity note;
@@ -127,11 +206,11 BEGIN
127 206 -----------------------------------------------------------------------------
128 207
129 208
130 clk_24576Hz_gen:PROCESS
209 clk49_152MHz_gen:PROCESS
131 210 BEGIN
132 211 IF end_of_simu /= '1' THEN
133 clk_24576Hz <= NOT clk_24576Hz;
134 WAIT FOR half_samplig_period;
212 clk49_152MHz <= NOT clk49_152MHz;
213 WAIT FOR 10173 ps;
135 214 ELSE
136 215 WAIT FOR 10 ps;
137 216 assert false report "end of test" severity note;
@@ -139,12 +218,12 BEGIN
139 218 END IF;
140 219 END PROCESS;
141 220
142 clk_25M_gen:PROCESS
221 clk_50M_gen:PROCESS
143 222 BEGIN
144 223 IF end_of_simu /= '1' THEN
145 224 clk <= NOT clk;
146 225 TSTAMP <= TSTAMP+20;
147 WAIT FOR 20 ns;
226 WAIT FOR 10 ns;
148 227 ELSE
149 228 WAIT FOR 10 ps;
150 229 assert false report "end of test" severity note;
@@ -153,102 +232,241 BEGIN
153 232 END PROCESS;
154 233
155 234
156 -----------------------------------------------------------------------------
157 -- LPP_LFR_FILTER f1
158 -----------------------------------------------------------------------------
235 LFR: ENTITY work.LFR_FM
236 GENERIC MAP(
237 Mem_use => use_RAM,
238 USE_BOOTLOADER => 0,
239 USE_ADCDRIVER => 1,
240 tech => inferred,
241 tech_leon => inferred,
242 DEBUG_FORCE_DATA_DMA => 0,
243 USE_DEBUG_VECTOR => 0
244 )
245
246 PORT MAP(
247 clk50MHz => clk,
248 clk49_152MHz => clk49_152MHz,
249 reset => rstn,
250
251 TAG => OPEN,
252
253 address => address,
254 data => data,
159 255
160 IIR_CEL_f0_to_f1 : IIR_CEL_CTRLR_v2
161 GENERIC MAP (
162 tech => tech,
163 Mem_use => Mem_use, -- use_RAM
164 Sample_SZ => 18,
165 Coef_SZ => f0_to_f1_COEFFICIENT_SIZE,
166 Coef_Nb => f0_to_f1_CEL_NUMBER*5,
167 Coef_sel_SZ => 5,
168 Cels_count => f0_to_f1_CEL_NUMBER,
169 ChanelsCount => ChanelCount,
170 FILENAME => ""
171 )
172 PORT MAP (
173 rstn => rstn,
174 clk => clk,
175 virg_pos => f0_to_f1_POINT_POSITION,
176 coefs => coefs_iir_cel_f0_to_f1,
177
178 sample_in_val => sample_val,
179 sample_in => sample,
180 sample_out_val => sample_fx_val,
181 sample_out => sample_fx);
182
183 -----------------------------------------------------------------------------
256 nSRAM_MBE => nSRAM_MBE,
257 nSRAM_E1 => nSRAM_E1,
258 nSRAM_E2 => nSRAM_E2,
259 -- nSRAM_SCRUB : OUT STD_LOGIC; -- new
260 nSRAM_W => nSRAM_W,
261 nSRAM_G => nSRAM_G,
262 nSRAM_BUSY => nSRAM_BUSY,
263 -- SPW --------------------------------------------------------------------
264 spw1_en => spw1_en,
265 spw1_din => spw1_din,
266 spw1_sin => spw1_sin,
267 spw1_dout => spw1_dout,
268 spw1_sout => spw1_sout,
269 spw2_en => spw2_en,
270 spw2_din => spw2_din,
271 spw2_sin => spw2_sin,
272 spw2_dout => spw2_dout,
273 spw2_sout => spw2_sout,
274 -- ADC --------------------------------------------------------------------
275 bias_fail_sw => bias_fail_sw,
276 ADC_OEB_bar_CH => ADC_OEB_bar_CH,
277 ADC_smpclk => ADC_smpclk,
278 ADC_data => ADC_data,
279 -- DAC --------------------------------------------------------------------
280 DAC_SDO => DAC_SDO,
281 DAC_SCK => DAC_SCK,
282 DAC_SYNC => DAC_SYNC,
283 DAC_CAL_EN => DAC_CAL_EN,
284 -- HK ---------------------------------------------------------------------
285 HK_smpclk => HK_smpclk,
286 ADC_OEB_bar_HK => ADC_OEB_bar_HK,
287 HK_SEL => HK_SEL
288 );
184 289
185 290
291 spw2_din <= '1';
292 spw2_sin <= '1';
186 293 -----------------------------------------------------------------------------
187 -- SAMPLE GENERATION
294 -- SRAMS Same as EM, we don't have UT8ER1M32 models
188 295 -----------------------------------------------------------------------------
296 nSRAM_BUSY <= '1'; -- TODO emulate scrubbing
297
298 nSRAM_CE <= not nSRAM_E1;
299
300 async_1Mx16_0: CY7C1061DV33
301 GENERIC MAP (
302 ADDR_BITS => 19,
303 DATA_BITS => 16,
304 depth => 1048576,
305 MEM_ARRAY_DEBUG => 32,
306 TimingInfo => TRUE,
307 TimingChecks => '1')
308 PORT MAP (
309 CE1_b => '0',
310 CE2 => nSRAM_CE,
311 WE_b => nSRAM_W,
312 OE_b => nSRAM_G,
313 BHE_b => '0',
314 BLE_b => '0',
315 A => address,
316 DQ => data(15 DOWNTO 0));
317
318 async_1Mx16_1: CY7C1061DV33
319 GENERIC MAP (
320 ADDR_BITS => 19,
321 DATA_BITS => 16,
322 depth => 1048576,
323 MEM_ARRAY_DEBUG => 32,
324 TimingInfo => TRUE,
325 TimingChecks => '1')
326 PORT MAP (
327 CE1_b => '0',
328 CE2 => nSRAM_CE,
329 WE_b => nSRAM_W,
330 OE_b => nSRAM_G,
331 BHE_b => '0',
332 BLE_b => '0',
333 A => address,
334 DQ => data(31 DOWNTO 16));
189 335
190 336
191 PROCESS (clk, rstn)
192 BEGIN -- PROCESS
193 IF rstn = '0' THEN -- asynchronous reset (active low)
194 sample_val <= '0';
195 clk_24576Hz_r <= '0';
196 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
197 clk_24576Hz_r <= clk_24576Hz;
198 IF clk_24576Hz = '1' AND clk_24576Hz_r = '0' THEN
199 sample_val <= '1';
200 ELSE
201 sample_val <= '0';
202 END IF;
203 END IF;
204 END PROCESS;
205 -----------------------------------------------------------------------------
206
207 ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
208 SampleLoop : FOR j IN 0 TO 15 GENERATE
209 sample_fx_wdata(i)(j) <= sample_fx(i,j);
210 signal_rec(i,j) <= sample_fx_wdata(i)(j);
211 sample(i,j) <= signal_gen(i,j);
212 END GENERATE;
213 sample(i,16) <= signal_gen(i,16);
214 sample(i,17) <= signal_gen(i,17);
215 END GENERATE;
216 337
217 338
218 339
219 -----------------------------------------------------------------------------
220 -- READ INPUT SIGNALS
221 -----------------------------------------------------------------------------
340 SPW: spwstream
341
342 generic map(
343 sysfreq => 50.0e6,
344 txclkfreq => 50.0e6,
345 rximpl => impl_generic,
346 rxchunk => 1,
347 tximpl => impl_generic,
348 rxfifosize_bits => 11,
349 txfifosize_bits => 11
350 )
351
352 port map(
353 -- System clock.
354 clk => clk,
355 rxclk => clk,
356 txclk => clk,
357 rst => rst,
358 autostart => autostart,
359 linkstart => linkstart,
360 linkdis => linkdis,
361 txdivcnt => X"00",
362 tick_in => '0',
363
364 -- Control bits of the TimeCode to be sent. Must be valid while tick_in is high.
365 ctrl_in => ctrl_in,
366
367 -- Counter value of the TimeCode to be sent. Must be valid while tick_in is high.
368 time_in => time_in,
369
370 -- Pulled high by the application to write an N-Char to the transmit
371 -- queue. If "txwrite" and "txrdy" are both high on the rising edge
372 -- of "clk", a character is added to the transmit queue.
373 -- This signal has no effect if "txrdy" is low.
374 txwrite => txwrite,
375
376 -- Control flag to be sent with the next N_Char.
377 -- Must be valid while txwrite is high.
378 txflag => txflag,
379
380 -- Byte to be sent, or "00000000" for EOP or "00000001" for EEP.
381 -- Must be valid while txwrite is high.
382 txdata => txdata,
383
384 -- High if the entity is ready to accept an N-Char for transmission.
385 txrdy => txrdy,
386
387 -- High if the transmission queue is at least half full.
388 txhalff => txhalff,
389
390 -- High for one clock cycle if a TimeCode was just received.
391 tick_out => tick_out,
392
393 -- Control bits of the last received TimeCode.
394 ctrl_out => ctrl_out,
395
396 -- Counter value of the last received TimeCode.
397 time_out => time_out,
222 398
223 gen: sig_reader
224 GENERIC MAP(
225 FNAME => "input.txt",
226 WIDTH => ChanelCount,
227 RESOLUTION => 18,
228 GAIN => 1.0
229 )
230 PORT MAP(
231 clk => sample_val,
232 end_of_simu => end_of_simu,
233 out_signal => signal_gen
399 -- High if "rxflag" and "rxdata" contain valid data.
400 -- This signal is high unless the receive FIFO is empty.
401 rxvalid => rxvalid,
402
403 -- High if the receive FIFO is at least half full.
404 rxhalff => rxhalff,
405
406 -- High if the received character is EOP or EEP; low if the received
407 -- character is a data byte. Valid if "rxvalid" is high.
408 rxflag => rxflag,
409
410 -- Received byte, or "00000000" for EOP or "00000001" for EEP.
411 -- Valid if "rxvalid" is high.
412 rxdata => rxdata,
413
414 -- Pulled high by the application to accept a received character.
415 -- If "rxvalid" and "rxread" are both high on the rising edge of "clk",
416 -- a character is removed from the receive FIFO and "rxvalid", "rxflag"
417 -- and "rxdata" are updated.
418 -- This signal has no effect if "rxvalid" is low.
419 rxread => rxread,
420
421 -- High if the link state machine is currently in the Started state.
422 started => started,
423
424 -- High if the link state machine is currently in the Connecting state.
425 connecting => connecting,
426
427 -- High if the link state machine is currently in the Run state, indicating
428 -- that the link is fully operational. If none of started, connecting or running
429 -- is high, the link is in an initial state and the transmitter is not yet enabled.
430 running => running,
431
432 -- Disconnect detected in state Run. Triggers a reset and reconnect of the link.
433 -- This indication is auto-clearing.
434 errdisc => errdisc,
435
436 -- Parity error detected in state Run. Triggers a reset and reconnect of the link.
437 -- This indication is auto-clearing.
438 errpar => errpar,
439
440 -- Invalid escape sequence detected in state Run. Triggers a reset and reconnect of
441 -- the link. This indication is auto-clearing.
442 erresc => erresc,
443
444 -- Credit error detected. Triggers a reset and reconnect of the link.
445 -- This indication is auto-clearing.
446 errcred => errcred,
447
448 -- Data In signal from SpaceWire bus.
449 spw_di => spw1_dout,
450
451 -- Strobe In signal from SpaceWire bus.
452 spw_si => spw1_sout,
453
454 -- Data Out signal to SpaceWire bus.
455 spw_do => spw1_din,
456
457 -- Strobe Out signal to SpaceWire bus.
458 spw_so => spw1_sin
234 459 );
235 460
236 461
462
463
464
465
237 466 -----------------------------------------------------------------------------
238 467 -- RECORD OUTPUT SIGNALS
239 468 -----------------------------------------------------------------------------
240 469
241 rec : sig_recorder
242 GENERIC MAP(
243 FNAME => "output_fx.txt",
244 WIDTH => ChanelCount,
245 RESOLUTION => 16
246 )
247 PORT MAP(
248 clk => sample_fx_val,
249 end_of_simu => end_of_simu,
250 timestamp => TSTAMP,
251 input_signal => signal_rec
252 );
470
253 471
254 472 END;
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