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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2017, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Alexis Jeandet
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-- Mail : alexis.jeandet@member.fsf.org
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-------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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PACKAGE CY7C1061DV33_pkg IS
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COMPONENT CY7C1061DV33 IS
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GENERIC
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(ADDR_BITS : INTEGER := 20;
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DATA_BITS : INTEGER := 16;
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depth : INTEGER := 1048576;
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MEM_ARRAY_DEBUG : INTEGER := 32;
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TimingInfo : BOOLEAN := true;
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TimingChecks : STD_LOGIC := '1'
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);
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PORT (
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CE1_b : IN STD_LOGIC; -- Chip Enable CE1#
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CE2 : IN STD_LOGIC; -- Chip Enable CE2
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WE_b : IN STD_LOGIC; -- Write Enable WE#
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OE_b : IN STD_LOGIC; -- Output Enable OE#
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BHE_b : IN STD_LOGIC; -- Byte Enable High BHE#
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BLE_b : IN STD_LOGIC; -- Byte Enable Low BLE#
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A : IN STD_LOGIC_VECTOR(addr_bits-1 DOWNTO 0); -- Address Inputs A
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DQ : INOUT STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0) := (OTHERS => 'Z')-- Read/Write Data IO;
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);
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END COMPONENT;
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END CY7C1061DV33_pkg;
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