# HG changeset patch # User Jeandet Alexis # Date 2017-01-04 23:44:54 # Node ID c53e1b6b30452ae2d4239b8e8a97c257486d7bf0 # Parent 9d85f9f8f05ac9dc36a12a33442be885db7dc2d5 Few fixes. Whole LFR simulation WIP. diff --git a/lib/lpp/dsp/lpp_fft/fft_components.vhd b/lib/lpp/dsp/lpp_fft/fft_components.vhd --- a/lib/lpp/dsp/lpp_fft/fft_components.vhd +++ b/lib/lpp/dsp/lpp_fft/fft_components.vhd @@ -39,8 +39,9 @@ package FFT_COMPONENTS is function to_integer( x : boolean) return integer; function maskbar (barn, bar_enable,dma_reg_bar,dma_reg_loc : integer) return integer; function anyfifo (bar0, bar1, bar2, bar3, bar4, bar5 : integer) return integer; - FUNCTION reverse (x : std_logic_vector) RETURN bit_vector; - FUNCTION reverseStd(x : std_logic_vector) RETURN std_logic_vector; + FUNCTION reverse (x :IN std_logic_vector) RETURN bit_vector; + + FUNCTION reverseStd(x :IN std_logic_vector) RETURN std_logic_vector; COMPONENT counter GENERIC ( diff --git a/lib/lpp/lpp_sim/CY7C1061DV33/CY7C1061DV33_pkg.vhd b/lib/lpp/lpp_sim/CY7C1061DV33/CY7C1061DV33_pkg.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_sim/CY7C1061DV33/CY7C1061DV33_pkg.vhd @@ -0,0 +1,52 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2017, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Alexis Jeandet +-- Mail : alexis.jeandet@member.fsf.org +------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + + +PACKAGE CY7C1061DV33_pkg IS + + COMPONENT CY7C1061DV33 IS + GENERIC + (ADDR_BITS : INTEGER := 20; + DATA_BITS : INTEGER := 16; + depth : INTEGER := 1048576; + + MEM_ARRAY_DEBUG : INTEGER := 32; + + TimingInfo : BOOLEAN := true; + TimingChecks : STD_LOGIC := '1' + ); + PORT ( + CE1_b : IN STD_LOGIC; -- Chip Enable CE1# + CE2 : IN STD_LOGIC; -- Chip Enable CE2 + WE_b : IN STD_LOGIC; -- Write Enable WE# + OE_b : IN STD_LOGIC; -- Output Enable OE# + BHE_b : IN STD_LOGIC; -- Byte Enable High BHE# + BLE_b : IN STD_LOGIC; -- Byte Enable Low BLE# + A : IN STD_LOGIC_VECTOR(addr_bits-1 DOWNTO 0); -- Address Inputs A + DQ : INOUT STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0) := (OTHERS => 'Z')-- Read/Write Data IO; + ); + END COMPONENT; + +END CY7C1061DV33_pkg; diff --git a/lib/lpp/lpp_sim/CY7C1061DV33/package_utility.vhd b/lib/lpp/lpp_sim/CY7C1061DV33/package_utility.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_sim/CY7C1061DV33/package_utility.vhd @@ -0,0 +1,70 @@ +--**************************************************************** +--** MODEL : package_utility ** +--** COMPANY : Cypress Semiconductor ** +--** REVISION: 1.0 Created new package utility model ** +--** ** +--**************************************************************** +Library ieee,work; + Use ieee.std_logic_1164.all; + Use IEEE.Std_Logic_Arith.all; + Use IEEE.std_logic_TextIO.all; + +Library Std; + Use STD.TextIO.all; + +Package package_utility is + +FUNCTION convert_string( S: in STRING) RETURN STD_LOGIC_VECTOR; +FUNCTION conv_integer1(S : STD_LOGIC_VECTOR) RETURN INTEGER; + +End; -- package package_utility + +Package body package_utility is + + +------------------------------------------------------------------------------------------------ +--Converts string into std_logic_vector +------------------------------------------------------------------------------------------------ + +FUNCTION convert_string(S: in STRING) RETURN STD_LOGIC_VECTOR IS + VARIABLE result : STD_LOGIC_VECTOR(S'RANGE); + BEGIN + FOR i IN S'RANGE LOOP + IF S(i) = '0' THEN + result(i) := '0'; + ELSIF S(i) = '1' THEN + result(i) := '1'; + ELSIF S(i) = 'X' THEN + result(i) := 'X'; + ELSE + result(i) := 'Z'; + END IF; + END LOOP; + RETURN result; +END convert_string; + +------------------------------------------------------------------------------------------------ +--Converts std_logic_vector into integer +------------------------------------------------------------------------------------------------ + +FUNCTION conv_integer1(S : STD_LOGIC_VECTOR) RETURN INTEGER IS + VARIABLE result : INTEGER := 0; + BEGIN + FOR i IN S'RANGE LOOP + IF S(i) = '1' THEN + result := result + (2**i); + ELSIF S(i) = '0' THEN + result := result; + ELSE + result := 0; + END IF; + END LOOP; + RETURN result; + END conv_integer1; + + + + +end package_utility; + + diff --git a/lib/lpp/lpp_sim/CY7C1061DV33/vhdlsim.txt b/lib/lpp/lpp_sim/CY7C1061DV33/vhdlsim.txt --- a/lib/lpp/lpp_sim/CY7C1061DV33/vhdlsim.txt +++ b/lib/lpp/lpp_sim/CY7C1061DV33/vhdlsim.txt @@ -1,4 +1,4 @@ package_utility.vhd package_timing.vhd +CY7C1061DV33.vhd CY7C1061DV33_pkg.vhd -CY7C1061DV33.vhd diff --git a/tests/Validation_LFR/Makefile b/tests/Validation_LFR/Makefile --- a/tests/Validation_LFR/Makefile +++ b/tests/Validation_LFR/Makefile @@ -2,7 +2,7 @@ VHDLIB=../.. SCRIPTSDIR=$(VHDLIB)/scripts/ GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) TOP=testbench -BOARD=LFR-EQM +BOARD=LFR-FM include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc DEVICE=$(PART)-$(PACKAGE)$(SPEED) UCF= @@ -11,74 +11,43 @@ EFFORT=high XSTOPT= SYNPOPT= VHDLSYNFILES= -VHDLSIMFILES= tb.vhd $(VHDLIB)/boards/designs/LFR-EQM-RTAX/LFR-EQM.vhd +VHDLSIMFILES= $(VHDLIB)/designs/SOLO_LFR_LFR-FM/LFR-FM.vhd tb.vhd SIMTOP=testbench CLEAN=soft-clean TECHLIBS = axcelerator -LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ - tmtc openchip hynix ihp gleichmann micron usbhc opencores fmf ftlib gsi + +LIBSKIP = tmtc openchip hynix cypress ihp usbhc fmf gsi spansion eth micron -DIRSKIP = b1553 pcif leon2 leon3v3 leon2ft crypto satcan ddr usb ata i2c \ - pci grusbhc haps slink ascs can pwm greth coremp7 spi ac97 srmmu atf \ - grlfpc \ - ./dsp/lpp_fft_rtax \ +DIRSKIP = leon2 leon2ft crypto usb satcan ddr greth grusbhc \ + leon4 leon4v0 l2cache iommu slink ascs pwm net spi can \ ./amba_lcd_16x2_ctrlr \ ./general_purpose/lpp_AMR \ ./general_purpose/lpp_balise \ ./general_purpose/lpp_delay \ ./lpp_bootloader \ - ./lfr_management \ - ./lpp_sim/CY7C1061DV33 \ - ./lpp_cna \ ./lpp_uart \ ./lpp_usb \ - ./dsp/lpp_fft \ - ./lpp_leon3_soc \ - ./lpp_debug_lfr + ./lpp_debug_lfr \ + ./dsp/lpp_fft FILESKIP = i2cmst.vhd \ APB_MULTI_DIODE.vhd \ APB_MULTI_DIODE.vhd \ Top_MatrixSpec.vhd \ APB_FFT.vhd \ - lpp_lfr_ms_FFT.vhd \ - lpp_lfr_apbreg.vhd \ - CoreFFT.vhd \ - lpp_lfr_ms.vhd \ - lpp_lfr_sim_pkg.vhd \ - mtie_maps.vhd \ - ftsrctrlc.vhd \ - ftsdctrl.vhd \ - ftsrctrl8.vhd \ - ftmctrl.vhd \ - ftsdctrl64.vhd \ - ftahbram.vhd \ - ftahbram2.vhd \ - sramft.vhd \ - nandfctrlx.vhd + lpp_lfr_sim_pkg.vhd include $(GRLIB)/bin/Makefile include $(GRLIB)/software/leon3/Makefile - ################## project specific targets ########################## distclean:myclean -vsim:cp_for_vsim myclean: rm -f input.txt output_fx.txt *.log rm -rf ./2016* -generate : - python ./generate.py - -cp_for_vsim: generate - cp ./input.txt simulation/ - -archivate: - xonsh ./archivate.xsh - -test: | generate ghdl ghdl-run archivate +test: | ghdl ghdl-run archivate diff --git a/tests/Validation_LFR/tb.vhd b/tests/Validation_LFR/tb.vhd --- a/tests/Validation_LFR/tb.vhd +++ b/tests/Validation_LFR/tb.vhd @@ -11,6 +11,10 @@ USE techmap.gencomp.ALL; LIBRARY std; USE std.textio.ALL; +library opencores; +use opencores.spwpkg.all; +use opencores.spwambapkg.all; + LIBRARY lpp; USE lpp.iir_filter.ALL; USE lpp.lpp_ad_conv.ALL; @@ -21,7 +25,7 @@ USE lpp.data_type_pkg.ALL; USE lpp.lpp_lfr_pkg.ALL; USE lpp.general_purpose.ALL; USE lpp.lpp_sim_pkg.ALL; -USE lpp.lpp_waveform_pkg.ALL; +USE lpp.CY7C1061DV33_pkg.ALL; ENTITY testbench IS GENERIC( @@ -32,78 +36,151 @@ END; ARCHITECTURE behav OF testbench IS - -COMPONENT LFR_EQM IS - GENERIC ( - Mem_use : INTEGER := use_RAM; - USE_BOOTLOADER : INTEGER := 0; - USE_ADCDRIVER : INTEGER := 1; - tech : INTEGER := inferred; - tech_leon : INTEGER := inferred; - DEBUG_FORCE_DATA_DMA : INTEGER := 0; - USE_DEBUG_VECTOR : INTEGER := 0 - ); - - PORT ( - clk50MHz : IN STD_ULOGIC; - clk49_152MHz : IN STD_ULOGIC; - reset : IN STD_ULOGIC; - - TAG : INOUT STD_LOGIC_VECTOR(9 DOWNTO 1); - - address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0); - data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - - nSRAM_MBE : INOUT STD_LOGIC; -- new - nSRAM_E1 : OUT STD_LOGIC; -- new - nSRAM_E2 : OUT STD_LOGIC; -- new --- nSRAM_SCRUB : OUT STD_LOGIC; -- new - nSRAM_W : OUT STD_LOGIC; -- new - nSRAM_G : OUT STD_LOGIC; -- new - nSRAM_BUSY : IN STD_LOGIC; -- new - -- SPW -------------------------------------------------------------------- - spw1_en : OUT STD_LOGIC; -- new - spw1_din : IN STD_LOGIC; - spw1_sin : IN STD_LOGIC; - spw1_dout : OUT STD_LOGIC; - spw1_sout : OUT STD_LOGIC; - spw2_en : OUT STD_LOGIC; -- new - spw2_din : IN STD_LOGIC; - spw2_sin : IN STD_LOGIC; - spw2_dout : OUT STD_LOGIC; - spw2_sout : OUT STD_LOGIC; - -- ADC -------------------------------------------------------------------- - bias_fail_sw : OUT STD_LOGIC; - ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); - ADC_smpclk : OUT STD_LOGIC; - ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0); - -- DAC -------------------------------------------------------------------- - DAC_SDO : OUT STD_LOGIC; - DAC_SCK : OUT STD_LOGIC; - DAC_SYNC : OUT STD_LOGIC; - DAC_CAL_EN : OUT STD_LOGIC; - -- HK --------------------------------------------------------------------- - HK_smpclk : OUT STD_LOGIC; - ADC_OEB_bar_HK : OUT STD_LOGIC; - HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) - ); - -END LFR_EQM; - - SIGNAL TSTAMP : INTEGER := 0; SIGNAL clk : STD_LOGIC := '0'; - SIGNAL clk_24576Hz : STD_LOGIC := '0'; - SIGNAL clk_24576Hz_r : STD_LOGIC := '0'; - SIGNAL rstn : STD_LOGIC; - - SIGNAL signal_gen : sample_vector(0 to ChanelCount-1,17 downto 0); - SIGNAL sample_fx_wdata : Samples(ChanelCount-1 DOWNTO 0); - SIGNAL signal_rec : sample_vector(0 to ChanelCount-1,15 downto 0); + SIGNAL clk49_152MHz : STD_LOGIC := '0'; + SIGNAL rstn,rst : STD_LOGIC; SIGNAL end_of_simu : STD_LOGIC := '0'; - CONSTANT half_samplig_period : time := 20345052 ps; --INTEGER( REAL(1000**4) / REAL(2.0*24576.0)) * 1 ps; + ----------------------------------------------------------------------------- + -- LFR TOP WRAPPER SIGNALS + ----------------------------------------------------------------------------- + SIGNAL address : STD_LOGIC_VECTOR(18 DOWNTO 0); + SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0); + + SIGNAL nSRAM_MBE : STD_LOGIC; -- new + SIGNAL nSRAM_E1 : STD_LOGIC; -- new + SIGNAL nSRAM_E2 : STD_LOGIC; -- new +-- nSRAM_SCRUB : OUT STD_LOGIC; -- new + SIGNAL nSRAM_W : STD_LOGIC; -- new + SIGNAL nSRAM_G : STD_LOGIC; -- new + SIGNAL nSRAM_BUSY : STD_LOGIC; -- new + -- SPW -------------------------------------------------------------------- + SIGNAL spw1_en : STD_LOGIC; -- new + SIGNAL spw1_din : STD_LOGIC; + SIGNAL spw1_sin : STD_LOGIC; + SIGNAL spw1_dout : STD_LOGIC; + SIGNAL spw1_sout : STD_LOGIC; + SIGNAL spw2_en : STD_LOGIC; -- new + SIGNAL spw2_din : STD_LOGIC; + SIGNAL spw2_sin : STD_LOGIC; + SIGNAL spw2_dout : STD_LOGIC; + SIGNAL spw2_sout : STD_LOGIC; + -- ADC -------------------------------------------------------------------- + SIGNAL bias_fail_sw : STD_LOGIC; + SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL ADC_smpclk : STD_LOGIC; + SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0); + -- DAC -------------------------------------------------------------------- + SIGNAL DAC_SDO : STD_LOGIC; + SIGNAL DAC_SCK : STD_LOGIC; + SIGNAL DAC_SYNC : STD_LOGIC; + SIGNAL DAC_CAL_EN : STD_LOGIC; + -- HK --------------------------------------------------------------------- + SIGNAL HK_smpclk : STD_LOGIC; + SIGNAL ADC_OEB_bar_HK : STD_LOGIC; + SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0); + + SIGNAL nSRAM_CE : STD_LOGIC; + + + + + SIGNAL autostart: std_logic := '1'; + + -- Enables link start once the Ready state is reached. + -- Without autostart or linkstart, the link remains in state Ready. + SIGNAL linkstart: std_logic :='1'; + + -- Do not start link (overrides linkstart and autostart) and/or + -- disconnect a running link. + SIGNAL linkdis: std_logic := '0'; + + -- Control bits of the TimeCode to be sent. Must be valid while tick_in is high. + SIGNAL ctrl_in: std_logic_vector(1 downto 0) :=(others => '0'); + + -- Counter value of the TimeCode to be sent. Must be valid while tick_in is high. + SIGNAL time_in: std_logic_vector(5 downto 0):=(others => '0'); + + -- Pulled high by the application to write an N-Char to the transmit + -- queue. If "txwrite" and "txrdy" are both high on the rising edge + -- of "clk", a character is added to the transmit queue. + -- This signal has no effect if "txrdy" is low. + SIGNAL txwrite: std_logic := '0'; + + -- Control flag to be sent with the next N_Char. + -- Must be valid while txwrite is high. + SIGNAL txflag: std_logic :='0'; + + -- Byte to be sent, or "00000000" for EOP or "00000001" for EEP. + -- Must be valid while txwrite is high. + SIGNAL txdata: std_logic_vector(7 downto 0):=(others => '0'); + + -- High if the entity is ready to accept an N-Char for transmission. + SIGNAL txrdy: std_logic; + + -- High if the transmission queue is at least half full. + SIGNAL txhalff: std_logic; + + -- High for one clock cycle if a TimeCode was just received. + SIGNAL tick_out: std_logic; + + -- Control bits of the last received TimeCode. + SIGNAL ctrl_out: std_logic_vector(1 downto 0); + + -- Counter value of the last received TimeCode. + SIGNAL time_out: std_logic_vector(5 downto 0); + + -- High if "rxflag" and "rxdata" contain valid data. + -- This signal is high unless the receive FIFO is empty. + SIGNAL rxvalid: std_logic; + + -- High if the receive FIFO is at least half full. + SIGNAL rxhalff: std_logic; + + -- High if the received character is EOP or EEP; low if the received + -- character is a data byte. Valid if "rxvalid" is high. + SIGNAL rxflag: std_logic; + + -- Received byte, or "00000000" for EOP or "00000001" for EEP. + -- Valid if "rxvalid" is high. + SIGNAL rxdata: std_logic_vector(7 downto 0); + + -- Pulled high by the application to accept a received character. + -- If "rxvalid" and "rxread" are both high on the rising edge of "clk", + -- a character is removed from the receive FIFO and "rxvalid", "rxflag" + -- and "rxdata" are updated. + -- This signal has no effect if "rxvalid" is low. + SIGNAL rxread: std_logic:='0'; + + -- High if the link state machine is currently in the Started state. + SIGNAL started: std_logic; + + -- High if the link state machine is currently in the Connecting state. + SIGNAL connecting: std_logic; + + -- High if the link state machine is currently in the Run state, indicating + -- that the link is fully operational. If none of started, connecting or running + -- is high, the link is in an initial state and the transmitter is not yet enabled. + SIGNAL running: std_logic; + + -- Disconnect detected in state Run. Triggers a reset and reconnect of the link. + -- This indication is auto-clearing. + SIGNAL errdisc: std_logic; + + -- Parity error detected in state Run. Triggers a reset and reconnect of the link. + -- This indication is auto-clearing. + SIGNAL errpar: std_logic; + + -- Invalid escape sequence detected in state Run. Triggers a reset and reconnect of + -- the link. This indication is auto-clearing. + SIGNAL erresc: std_logic; + + -- Credit error detected. Triggers a reset and reconnect of the link. + -- This indication is auto-clearing. + SIGNAL errcred: std_logic; + BEGIN @@ -114,10 +191,12 @@ BEGIN BEGIN -- PROCESS WAIT UNTIL clk = '1'; rstn <= '0'; + rst <= '1'; WAIT UNTIL clk = '1'; WAIT UNTIL clk = '1'; WAIT UNTIL clk = '1'; rstn <= '1'; + rst <= '0'; WAIT UNTIL end_of_simu = '1'; WAIT FOR 10 ps; assert false report "end of test" severity note; @@ -127,11 +206,11 @@ BEGIN ----------------------------------------------------------------------------- - clk_24576Hz_gen:PROCESS + clk49_152MHz_gen:PROCESS BEGIN IF end_of_simu /= '1' THEN - clk_24576Hz <= NOT clk_24576Hz; - WAIT FOR half_samplig_period; + clk49_152MHz <= NOT clk49_152MHz; + WAIT FOR 10173 ps; ELSE WAIT FOR 10 ps; assert false report "end of test" severity note; @@ -139,12 +218,12 @@ BEGIN END IF; END PROCESS; - clk_25M_gen:PROCESS + clk_50M_gen:PROCESS BEGIN IF end_of_simu /= '1' THEN clk <= NOT clk; TSTAMP <= TSTAMP+20; - WAIT FOR 20 ns; + WAIT FOR 10 ns; ELSE WAIT FOR 10 ps; assert false report "end of test" severity note; @@ -153,102 +232,241 @@ BEGIN END PROCESS; - ----------------------------------------------------------------------------- - -- LPP_LFR_FILTER f1 - ----------------------------------------------------------------------------- +LFR: ENTITY work.LFR_FM + GENERIC MAP( + Mem_use => use_RAM, + USE_BOOTLOADER => 0, + USE_ADCDRIVER => 1, + tech => inferred, + tech_leon => inferred, + DEBUG_FORCE_DATA_DMA => 0, + USE_DEBUG_VECTOR => 0 + ) + + PORT MAP( + clk50MHz => clk, + clk49_152MHz => clk49_152MHz, + reset => rstn, + + TAG => OPEN, + + address => address, + data => data, - IIR_CEL_f0_to_f1 : IIR_CEL_CTRLR_v2 - GENERIC MAP ( - tech => tech, - Mem_use => Mem_use, -- use_RAM - Sample_SZ => 18, - Coef_SZ => f0_to_f1_COEFFICIENT_SIZE, - Coef_Nb => f0_to_f1_CEL_NUMBER*5, - Coef_sel_SZ => 5, - Cels_count => f0_to_f1_CEL_NUMBER, - ChanelsCount => ChanelCount, - FILENAME => "" - ) - PORT MAP ( - rstn => rstn, - clk => clk, - virg_pos => f0_to_f1_POINT_POSITION, - coefs => coefs_iir_cel_f0_to_f1, - - sample_in_val => sample_val, - sample_in => sample, - sample_out_val => sample_fx_val, - sample_out => sample_fx); - - ----------------------------------------------------------------------------- + nSRAM_MBE => nSRAM_MBE, + nSRAM_E1 => nSRAM_E1, + nSRAM_E2 => nSRAM_E2, +-- nSRAM_SCRUB : OUT STD_LOGIC; -- new + nSRAM_W => nSRAM_W, + nSRAM_G => nSRAM_G, + nSRAM_BUSY => nSRAM_BUSY, + -- SPW -------------------------------------------------------------------- + spw1_en => spw1_en, + spw1_din => spw1_din, + spw1_sin => spw1_sin, + spw1_dout => spw1_dout, + spw1_sout => spw1_sout, + spw2_en => spw2_en, + spw2_din => spw2_din, + spw2_sin => spw2_sin, + spw2_dout => spw2_dout, + spw2_sout => spw2_sout, + -- ADC -------------------------------------------------------------------- + bias_fail_sw => bias_fail_sw, + ADC_OEB_bar_CH => ADC_OEB_bar_CH, + ADC_smpclk => ADC_smpclk, + ADC_data => ADC_data, + -- DAC -------------------------------------------------------------------- + DAC_SDO => DAC_SDO, + DAC_SCK => DAC_SCK, + DAC_SYNC => DAC_SYNC, + DAC_CAL_EN => DAC_CAL_EN, + -- HK --------------------------------------------------------------------- + HK_smpclk => HK_smpclk, + ADC_OEB_bar_HK => ADC_OEB_bar_HK, + HK_SEL => HK_SEL + ); +spw2_din <= '1'; +spw2_sin <= '1'; ----------------------------------------------------------------------------- - -- SAMPLE GENERATION + -- SRAMS Same as EM, we don't have UT8ER1M32 models ----------------------------------------------------------------------------- + nSRAM_BUSY <= '1'; -- TODO emulate scrubbing + + nSRAM_CE <= not nSRAM_E1; + + async_1Mx16_0: CY7C1061DV33 + GENERIC MAP ( + ADDR_BITS => 19, + DATA_BITS => 16, + depth => 1048576, + MEM_ARRAY_DEBUG => 32, + TimingInfo => TRUE, + TimingChecks => '1') + PORT MAP ( + CE1_b => '0', + CE2 => nSRAM_CE, + WE_b => nSRAM_W, + OE_b => nSRAM_G, + BHE_b => '0', + BLE_b => '0', + A => address, + DQ => data(15 DOWNTO 0)); + + async_1Mx16_1: CY7C1061DV33 + GENERIC MAP ( + ADDR_BITS => 19, + DATA_BITS => 16, + depth => 1048576, + MEM_ARRAY_DEBUG => 32, + TimingInfo => TRUE, + TimingChecks => '1') + PORT MAP ( + CE1_b => '0', + CE2 => nSRAM_CE, + WE_b => nSRAM_W, + OE_b => nSRAM_G, + BHE_b => '0', + BLE_b => '0', + A => address, + DQ => data(31 DOWNTO 16)); - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - sample_val <= '0'; - clk_24576Hz_r <= '0'; - ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge - clk_24576Hz_r <= clk_24576Hz; - IF clk_24576Hz = '1' AND clk_24576Hz_r = '0' THEN - sample_val <= '1'; - ELSE - sample_val <= '0'; - END IF; - END IF; - END PROCESS; - ----------------------------------------------------------------------------- - - ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE - SampleLoop : FOR j IN 0 TO 15 GENERATE - sample_fx_wdata(i)(j) <= sample_fx(i,j); - signal_rec(i,j) <= sample_fx_wdata(i)(j); - sample(i,j) <= signal_gen(i,j); - END GENERATE; - sample(i,16) <= signal_gen(i,16); - sample(i,17) <= signal_gen(i,17); - END GENERATE; - ----------------------------------------------------------------------------- - -- READ INPUT SIGNALS - ----------------------------------------------------------------------------- +SPW: spwstream + + generic map( + sysfreq => 50.0e6, + txclkfreq => 50.0e6, + rximpl => impl_generic, + rxchunk => 1, + tximpl => impl_generic, + rxfifosize_bits => 11, + txfifosize_bits => 11 + ) + + port map( + -- System clock. + clk => clk, + rxclk => clk, + txclk => clk, + rst => rst, + autostart => autostart, + linkstart => linkstart, + linkdis => linkdis, + txdivcnt => X"00", + tick_in => '0', + + -- Control bits of the TimeCode to be sent. Must be valid while tick_in is high. + ctrl_in => ctrl_in, + + -- Counter value of the TimeCode to be sent. Must be valid while tick_in is high. + time_in => time_in, + + -- Pulled high by the application to write an N-Char to the transmit + -- queue. If "txwrite" and "txrdy" are both high on the rising edge + -- of "clk", a character is added to the transmit queue. + -- This signal has no effect if "txrdy" is low. + txwrite => txwrite, + + -- Control flag to be sent with the next N_Char. + -- Must be valid while txwrite is high. + txflag => txflag, + + -- Byte to be sent, or "00000000" for EOP or "00000001" for EEP. + -- Must be valid while txwrite is high. + txdata => txdata, + + -- High if the entity is ready to accept an N-Char for transmission. + txrdy => txrdy, + + -- High if the transmission queue is at least half full. + txhalff => txhalff, + + -- High for one clock cycle if a TimeCode was just received. + tick_out => tick_out, + + -- Control bits of the last received TimeCode. + ctrl_out => ctrl_out, + + -- Counter value of the last received TimeCode. + time_out => time_out, - gen: sig_reader - GENERIC MAP( - FNAME => "input.txt", - WIDTH => ChanelCount, - RESOLUTION => 18, - GAIN => 1.0 - ) - PORT MAP( - clk => sample_val, - end_of_simu => end_of_simu, - out_signal => signal_gen + -- High if "rxflag" and "rxdata" contain valid data. + -- This signal is high unless the receive FIFO is empty. + rxvalid => rxvalid, + + -- High if the receive FIFO is at least half full. + rxhalff => rxhalff, + + -- High if the received character is EOP or EEP; low if the received + -- character is a data byte. Valid if "rxvalid" is high. + rxflag => rxflag, + + -- Received byte, or "00000000" for EOP or "00000001" for EEP. + -- Valid if "rxvalid" is high. + rxdata => rxdata, + + -- Pulled high by the application to accept a received character. + -- If "rxvalid" and "rxread" are both high on the rising edge of "clk", + -- a character is removed from the receive FIFO and "rxvalid", "rxflag" + -- and "rxdata" are updated. + -- This signal has no effect if "rxvalid" is low. + rxread => rxread, + + -- High if the link state machine is currently in the Started state. + started => started, + + -- High if the link state machine is currently in the Connecting state. + connecting => connecting, + + -- High if the link state machine is currently in the Run state, indicating + -- that the link is fully operational. If none of started, connecting or running + -- is high, the link is in an initial state and the transmitter is not yet enabled. + running => running, + + -- Disconnect detected in state Run. Triggers a reset and reconnect of the link. + -- This indication is auto-clearing. + errdisc => errdisc, + + -- Parity error detected in state Run. Triggers a reset and reconnect of the link. + -- This indication is auto-clearing. + errpar => errpar, + + -- Invalid escape sequence detected in state Run. Triggers a reset and reconnect of + -- the link. This indication is auto-clearing. + erresc => erresc, + + -- Credit error detected. Triggers a reset and reconnect of the link. + -- This indication is auto-clearing. + errcred => errcred, + + -- Data In signal from SpaceWire bus. + spw_di => spw1_dout, + + -- Strobe In signal from SpaceWire bus. + spw_si => spw1_sout, + + -- Data Out signal to SpaceWire bus. + spw_do => spw1_din, + + -- Strobe Out signal to SpaceWire bus. + spw_so => spw1_sin ); + + + + ----------------------------------------------------------------------------- -- RECORD OUTPUT SIGNALS ----------------------------------------------------------------------------- - rec : sig_recorder - GENERIC MAP( - FNAME => "output_fx.txt", - WIDTH => ChanelCount, - RESOLUTION => 16 - ) - PORT MAP( - clk => sample_fx_val, - end_of_simu => end_of_simu, - timestamp => TSTAMP, - input_signal => signal_rec - ); + END;