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--------------------------------------------------------------------------------
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-- Copyright 2007 Actel Corporation. All rights reserved.
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-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
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-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
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-- IN ADVANCE IN WRITING.
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-- Revision 3.0 April 30, 2007 : v3.0 CoreFFT Release
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-- Package: fft_components.vhd
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-- Description: CoreFFT
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-- Core package
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-- Rev: 0.1 8/31/2005 12:54PM VD : Pre Production
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--
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--
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--------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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USE IEEE.numeric_std.all;
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USE std.textio.all;
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USE IEEE.STD_LOGIC_TEXTIO.all;
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package FFT_COMPONENTS is
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CONSTANT gPTS : integer:=256; --Number of FFT points
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CONSTANT gLOGPTS : integer:=8; --Log2(PTS)
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CONSTANT gLOGLOGPTS : integer:=3; --Stage counter width
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-------------------------------------------------
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CONSTANT gWSIZE : integer:=16; -- FFT bit resolution; length of a re or im sample
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CONSTANT gTWIDTH : integer:=16; -- Twiddle, sin or cos bit resolution
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CONSTANT gHALFPTS : integer:=gPTS/2; -- Num of FFT points (PTS) divided by 2
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CONSTANT gDWIDTH : integer:=2*gWSIZE; -- width of a complex input word,
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CONSTANT gTDWIDTH : integer:=2*gTWIDTH; -- width of a complex twiddle factor
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CONSTANT gRND_MODE : integer:=1; -- enable product rounding
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CONSTANT gSCALE_MODE : integer:=0; -- scale mode
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CONSTANT gInBuf_RWDLY : integer:=12;
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function to_logic ( x : integer) return std_logic;
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function to_logic ( x : boolean) return std_logic;
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FUNCTION to_integer( sig : std_logic_vector) return integer;
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function to_integer( x : boolean) return integer;
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function maskbar (barn, bar_enable,dma_reg_bar,dma_reg_loc : integer) return integer;
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function anyfifo (bar0, bar1, bar2, bar3, bar4, bar5 : integer) return integer;
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FUNCTION reverse (x :IN std_logic_vector) RETURN bit_vector;
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FUNCTION reverseStd(x :IN std_logic_vector) RETURN std_logic_vector;
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COMPONENT counter
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GENERIC (
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WIDTH : integer := 7;
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TERMCOUNT : integer := 127 );
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PORT (
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clk, nGrst, rst, cntEn : IN std_logic;
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tc : OUT std_logic;
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Q : OUT std_logic_vector(WIDTH-1 DOWNTO 0));
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END COMPONENT;
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COMPONENT bcounter
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GENERIC (
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WIDTH : integer := 7);
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PORT (
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clk, nGrst, rst, cntEn : IN std_logic;
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Q : OUT std_logic_vector(WIDTH-1 DOWNTO 0) );
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END COMPONENT;
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COMPONENT edgeDetect
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GENERIC (
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INPIPE :integer := 0; --if (INPIPE==1) insert input pipeline reg
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FEDGE :integer := 0);--If FEDGE==1 detect falling edge, else-rising edge
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PORT (
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clk, clkEn, edgeIn : IN std_logic;
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edgeOut : OUT std_logic);
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END COMPONENT;
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end FFT_COMPONENTS;
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package body FFT_COMPONENTS is
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function to_logic ( x : integer) return std_logic is
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variable y : std_logic;
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begin
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if x = 0 then
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y := '0';
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else
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y := '1';
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end if;
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return y;
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end to_logic;
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function to_logic( x : boolean) return std_logic is
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variable y : std_logic;
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begin
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if x then
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y := '1';
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else
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y := '0';
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end if;
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return(y);
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end to_logic;
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-- added 081805
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function to_integer(sig : std_logic_vector) return integer is
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variable num : integer := 0; -- descending sig as integer
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begin
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for i in sig'range loop
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if sig(i)='1' then
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num := num*2+1;
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else -- use anything other than '1' as '0'
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num := num*2;
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end if;
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end loop; -- i
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return num;
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end function to_integer;
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function to_integer( x : boolean) return integer is
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variable y : integer;
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begin
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if x then
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y := 1;
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else
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y := 0;
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end if;
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return(y);
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end to_integer;
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function maskbar (barn, bar_enable,dma_reg_bar,dma_reg_loc : integer) return integer is
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begin
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if ( dma_reg_loc>= 2 and barn=dma_reg_bar) then
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return(0);
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else
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return(bar_enable);
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end if;
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end maskbar;
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function anyfifo ( bar0, bar1, bar2, bar3, bar4, bar5 : integer) return integer is
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begin
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if ( bar0=2 or bar1=2 or bar2=2 or bar3=2 or bar4=2 or bar5=2) then
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return(1);
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else
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return(0);
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end if;
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end anyfifo;
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FUNCTION reverse (x :IN std_logic_vector)
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RETURN bit_vector IS
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VARIABLE i : integer;
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VARIABLE reverse : bit_vector(x'HIGH DOWNTO x'LOW);
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BEGIN
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FOR i IN x'range LOOP
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reverse(i) := To_bit( x(x'HIGH - i));
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END LOOP;
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RETURN(reverse);
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END FUNCTION reverse;
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FUNCTION reverseStd (x :IN std_logic_vector)
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RETURN std_logic_vector IS
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VARIABLE i : integer;
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VARIABLE reverse : std_logic_vector(x'HIGH DOWNTO x'LOW);
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BEGIN
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FOR i IN x'range LOOP
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reverse(i) := x(x'HIGH - i);
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END LOOP;
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RETURN(reverse);
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END FUNCTION reverseStd;
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end FFT_COMPONENTS;
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