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Added lfr_output_save module in lpp_sim lib :...
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r688:c0c43c9d60f1 tip Simu-LFR-FM draft
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1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
4
5 LIBRARY std;
6 USE std.textio.ALL;
7
8 ENTITY lfr_output_save IS
9 GENERIC(
10 FNAME : STRING := "output.txt"
11 );
12 PORT(
13 end_of_simu : IN STD_LOGIC;
14 timestamp : IN integer;
15
16 -- DAC --------------------------------------------------------------------
17 DAC_SDO : in STD_LOGIC;
18 DAC_SCK : in STD_LOGIC;
19 DAC_SYNC : in STD_LOGIC;
20 DAC_CAL_EN : in STD_LOGIC;
21 -- BIAS_FAIL --------------------------------------------------------------
22 bias_fail_sw : in STD_LOGIC
23 );
24 END lfr_output_save;
25
26 ARCHITECTURE beh OF lfr_output_save IS
27
28 FILE output_file : TEXT OPEN write_mode IS FNAME;
29
30 SIGNAL CAL_VALUE_data_v : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
31 SIGNAL CAL_VALUE_valid_v : STD_LOGIC_VECTOR(16 DOWNTO 0) := (OTHERS => '0');
32
33 SIGNAL CAL_VALUE_data : STD_LOGIC_VECTOR(15 DOWNTO 0);
34
35 BEGIN
36
37 -----------------------------------------------------------------------------
38 -- Data orginization in the output file :
39 -----------------------------------------------------------------------------
40 -- Exemple of output.txt file :
41 -- TIME CAL_VALUE CAL_ENABLE BIAS_FAIL_VALUE
42 -- TIME CAL_VALUE CAL_ENABLE BIAS_FAIL_VALUE
43 -----------------------------------------------------------------------------
44 -- TIME : integer. Current time (in ns)
45 -- others : integer(0 to 255). Current value.
46 -----------------------------------------------------------------------------
47
48
49
50 -----------------------------------------------------------------------------
51 -- DAC : SPI to Parralel
52 PROCESS (DAC_SCK) IS
53 BEGIN -- PROCESS
54 IF DAC_SCK'event AND DAC_SCK = '1' THEN -- rising clock edge
55 CAL_VALUE_valid_v(0) <= '0';
56 CAL_VALUE_valid_v(16 DOWNTO 1) <= CAL_VALUE_valid_v(15 DOWNTO 0);
57 IF DAC_SYNC = '1' THEN
58 CAL_VALUE_valid_v(0) <= '1';
59 END IF;
60 CAL_VALUE_data_v(15 DOWNTO 0) <= CAL_VALUE_data_v(14 DOWNTO 0) & DAC_SDO;
61 END IF;
62 END PROCESS;
63
64 CAL_VALUE_data <= CAL_VALUE_data_v WHEN CAL_VALUE_valid_v(16) = '1';
65 -----------------------------------------------------------------------------
66
67
68
69 -----------------------------------------------------------------------------
70 --
71 PROCESS(end_of_simu, CAL_VALUE_data, DAC_CAL_EN, bias_fail_sw)
72 VARIABLE line_var : LINE;
73 BEGIN
74 IF end_of_simu = '1' THEN
75 file_close(output_file);
76 ELSE
77 write(line_var, INTEGER'IMAGE(timestamp));
78 write(line_var," " & INTEGER'IMAGE(to_integer(UNSIGNED(CAL_VALUE_data))));
79 write(line_var," " & STD_LOGIC'IMAGE(DAC_CAL_EN));
80 write(line_var," " & STD_LOGIC'IMAGE(bias_fail_sw));
81 writeline(output_file, line_var);
82 END IF;
83 END PROCESS;
84
85 END beh;
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1 VHDLIB=../..
2 SCRIPTSDIR=$(VHDLIB)/scripts/
3 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 TOP=testbench
5 BOARD=LFR-FM
6 include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc
7 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 UCF=
9 QSF=
10 EFFORT=high
11 XSTOPT=
12 SYNPOPT=
13 VHDLSYNFILES=
14 VHDLSIMFILES= tb.vhd
15 SIMTOP=testbench
16 CLEAN=soft-clean
17
18 TECHLIBS = axcelerator
19
20
21 LIBSKIP = tmtc openchip hynix cypress ihp usbhc fmf gsi spansion eth micron
22
23 DIRSKIP = leon2 leon2ft crypto usb satcan ddr greth grusbhc \
24 leon4 leon4v0 l2cache iommu slink ascs pwm net spi can \
25 ./amba_lcd_16x2_ctrlr \
26 ./general_purpose/lpp_AMR \
27 ./general_purpose/lpp_balise \
28 ./general_purpose/lpp_delay \
29 ./lpp_bootloader \
30 ./lpp_uart \
31 ./lpp_usb \
32 ./lpp_debug_lfr \
33 ./dsp/lpp_fft
34
35 FILESKIP = i2cmst.vhd \
36 APB_MULTI_DIODE.vhd \
37 APB_MULTI_DIODE.vhd \
38 Top_MatrixSpec.vhd \
39 APB_FFT.vhd \
40 lpp_lfr_sim_pkg.vhd
41
42 include $(GRLIB)/bin/Makefile
43 include $(GRLIB)/software/leon3/Makefile
44 ################## project specific targets ##########################
45 distclean:myclean
46
47 myclean:
48 rm -f input.txt output_fx.txt *.log
49 rm -rf ./2016*
50
51 test: | ghdl ghdl-run archivate
52
53
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321 110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
322 110 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
323 110 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1
324 110 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2
325 110 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3
326 110 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4
327 110 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5
328 110 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6
329 110 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
330 110 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8
331 110 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9
332 110 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10
333 110 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11
334 110 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12
335 110 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13
336 110 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
337 110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
338 110 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
339 110 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1
340 110 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2
341 110 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3
342 110 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4
343 110 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5
344 110 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6
345 110 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
346 110 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8
347 110 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9
348 110 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10
349 110 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11
350 110 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12
351 110 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13
352 110 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
353 110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
354 110 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
355 110 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1
356 110 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2
357 110 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3
358 110 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4
359 110 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5
360 110 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6
361 110 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
362 110 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8
363 110 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9
364 110 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10
365 110 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11
366 110 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12
367 110 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13
368 110 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
369 110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
370 110 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
371 110 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1
372 110 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2
373 110 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3
374 110 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4
375 110 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5
376 110 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6
377 110 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
378 110 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8
379 110 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9
380 110 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10
381 110 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11
382 110 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12
383 110 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13
384 110 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
385 110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
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@@ -0,0 +1,25
1 0 0 'U' 'U'
2 6340 3 'U' 'U'
3 10140 3 '0' 'U'
4 11140 3 '0' '0'
5 16340 6 '0' '0'
6 26340 9 '0' '0'
7 36340 12 '0' '0'
8 46340 15 '0' '0'
9 56340 18 '0' '0'
10 66340 21 '0' '0'
11 76340 24 '0' '0'
12 86340 27 '0' '0'
13 96340 30 '0' '0'
14 106340 33 '0' '0'
15 111140 33 '1' '0'
16 112140 33 '1' '1'
17 116340 36 '1' '1'
18 126340 39 '1' '1'
19 136340 42 '1' '1'
20 146340 45 '1' '1'
21 156340 48 '1' '1'
22 166340 51 '1' '1'
23 176340 54 '1' '1'
24 186340 57 '1' '1'
25 196340 60 '1' '1'
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@@ -0,0 +1,150
1
2 LIBRARY ieee;
3 USE ieee.std_logic_1164.ALL;
4 USE ieee.numeric_std.ALL;
5 USE IEEE.std_logic_signed.ALL;
6 USE IEEE.MATH_real.ALL;
7
8 LIBRARY techmap;
9 USE techmap.gencomp.ALL;
10
11 LIBRARY std;
12 USE std.textio.ALL;
13
14 LIBRARY opencores;
15 USE opencores.spwpkg.ALL;
16 USE opencores.spwambapkg.ALL;
17
18 LIBRARY lpp;
19 USE lpp.lpp_sim_pkg.ALL;
20 USE lpp.lpp_cna.ALL;
21
22 ENTITY testbench IS
23 END;
24
25 ARCHITECTURE behav OF testbench IS
26
27 SIGNAL TSTAMP : INTEGER := 0;
28
29 SIGNAL clk_25 : STD_LOGIC := '0';
30 SIGNAL rstn_25 : STD_LOGIC;
31
32 SIGNAL end_of_simu : STD_LOGIC := '0';
33
34 SIGNAL DATA : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
35 SIGNAL SMP_CLK : STD_LOGIC := '1';
36
37 SIGNAL DAC_SYNC : STD_LOGIC;
38 SIGNAL DAC_DOUT : STD_LOGIC;
39 SIGNAL DAC_SCLK : STD_LOGIC;
40
41 SIGNAL CAL_VALUE_data_v : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
42 SIGNAL CAL_VALUE_valid_v : STD_LOGIC_VECTOR(16 DOWNTO 0) := (OTHERS => '0');
43
44 SIGNAL CAL_VALUE_data : STD_LOGIC_VECTOR(15 DOWNTO 0);
45 SIGNAL CAL_VALUE_valid : STD_LOGIC;
46
47 SIGNAL DAC_CAL_EN : STD_LOGIC;
48 SIGNAL bias_fail_sw : STD_LOGIC;
49
50 BEGIN
51
52 -----------------------------------------------------------------------------
53 -- SIM GLOBAL RUN
54 -----------------------------------------------------------------------------
55 PROCESS IS
56 BEGIN -- PROCESS
57 WAIT FOR 200 us;
58 end_of_simu <= '1';
59 WAIT;
60 END PROCESS;
61
62 -----------------------------------------------------------------------------
63 -- CLOCK and RESET
64 -----------------------------------------------------------------------------
65 PROCESS
66 BEGIN -- PROCESS
67 WAIT UNTIL clk_25 = '1';
68 rstn_25 <= '0';
69 WAIT UNTIL clk_25 = '1';
70 WAIT UNTIL clk_25 = '1';
71 WAIT UNTIL clk_25 = '1';
72 rstn_25 <= '1';
73
74 WAIT FOR 10 us;
75 DAC_CAL_EN <= '0';
76
77 WAIT FOR 1 us;
78 bias_fail_sw <= '0';
79
80 WAIT FOR 100 us;
81 DAC_CAL_EN <= '1';
82
83 WAIT FOR 1 us;
84 bias_fail_sw <= '1';
85
86
87 WAIT UNTIL end_of_simu = '1';
88 WAIT FOR 10 ps;
89 ASSERT false REPORT "end of test" SEVERITY note;
90 -- Wait forever; this will finish the simulation.
91 WAIT;
92 END PROCESS;
93 -----------------------------------------------------------------------------
94 clk_25_gen : PROCESS
95 BEGIN
96 IF end_of_simu /= '1' THEN
97 clk_25 <= NOT clk_25;
98 TSTAMP <= TSTAMP+20;
99 WAIT FOR 20 ns;
100 ELSE
101 WAIT FOR 20 ps;
102 ASSERT false REPORT "end of test" SEVERITY note;
103 WAIT;
104 END IF;
105 END PROCESS;
106 -----------------------------------------------------------------------------
107
108 clk_SMP_gen : PROCESS
109 BEGIN
110 IF end_of_simu /= '1' THEN
111 SMP_CLK <= NOT SMP_CLK;
112 IF SMP_CLK = '0' THEN
113 DATA <= DATA + 3;
114 END IF;
115 WAIT FOR 5000101 ps;
116 ELSE
117 WAIT FOR 20 ps;
118 ASSERT false REPORT "end of test" SEVERITY note;
119 WAIT;
120 END IF;
121 END PROCESS;
122
123 SPI_DAC_DRIVER_1: SPI_DAC_DRIVER
124 GENERIC MAP (
125 datawidth => 16,
126 MSBFIRST => 1)
127 PORT MAP (
128 clk => clk_25,
129 rstn => rstn_25,
130
131 DATA => DATA,
132 SMP_CLK => SMP_CLK,
133
134 SYNC => DAC_SYNC,
135 DOUT => DAC_DOUT,
136 SCLK => DAC_SCLK);
137
138 lfr_output_save_1: lfr_output_save
139 GENERIC MAP (
140 FNAME => "lfr_output.txt")
141 PORT MAP (
142 end_of_simu => end_of_simu,
143 timestamp => TSTAMP,
144 DAC_SDO => DAC_DOUT,
145 DAC_SCK => DAC_SCLK,
146 DAC_SYNC => DAC_SYNC,
147 DAC_CAL_EN => DAC_CAL_EN,
148 bias_fail_sw => bias_fail_sw);
149
150 END;
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@@ -138,6 +138,19 PACKAGE lpp_sim_pkg IS
138 138 error_oeb : OUT STD_LOGIC;
139 139 error_hksel : OUT STD_LOGIC);
140 140 END COMPONENT lfr_input_gen;
141
142 COMPONENT lfr_output_save IS
143 GENERIC (
144 FNAME : STRING);
145 PORT (
146 end_of_simu : IN STD_LOGIC;
147 timestamp : IN integer;
148 DAC_SDO : in STD_LOGIC;
149 DAC_SCK : in STD_LOGIC;
150 DAC_SYNC : in STD_LOGIC;
151 DAC_CAL_EN : in STD_LOGIC;
152 bias_fail_sw : in STD_LOGIC);
153 END COMPONENT lfr_output_save;
141 154
142 155 END lpp_sim_pkg;
143 156
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@@ -6,3 +6,4 lpp_lfr_sim_pkg.vhd
6 6 spw_sender.vhd
7 7 spw_receiver.vhd
8 8 lfr_input_gen.vhd
9 lfr_output_save.vhd
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