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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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USE IEEE.std_logic_signed.ALL;
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USE IEEE.MATH_real.ALL;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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LIBRARY std;
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USE std.textio.ALL;
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LIBRARY opencores;
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USE opencores.spwpkg.ALL;
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USE opencores.spwambapkg.ALL;
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LIBRARY lpp;
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USE lpp.lpp_sim_pkg.ALL;
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USE lpp.lpp_cna.ALL;
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ENTITY testbench IS
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END;
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ARCHITECTURE behav OF testbench IS
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SIGNAL TSTAMP : INTEGER := 0;
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SIGNAL clk_25 : STD_LOGIC := '0';
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SIGNAL rstn_25 : STD_LOGIC;
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SIGNAL end_of_simu : STD_LOGIC := '0';
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SIGNAL DATA : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
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SIGNAL SMP_CLK : STD_LOGIC := '1';
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SIGNAL DAC_SYNC : STD_LOGIC;
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SIGNAL DAC_DOUT : STD_LOGIC;
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SIGNAL DAC_SCLK : STD_LOGIC;
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SIGNAL CAL_VALUE_data_v : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
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SIGNAL CAL_VALUE_valid_v : STD_LOGIC_VECTOR(16 DOWNTO 0) := (OTHERS => '0');
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SIGNAL CAL_VALUE_data : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL CAL_VALUE_valid : STD_LOGIC;
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SIGNAL DAC_CAL_EN : STD_LOGIC;
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SIGNAL bias_fail_sw : STD_LOGIC;
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BEGIN
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-----------------------------------------------------------------------------
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-- SIM GLOBAL RUN
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-----------------------------------------------------------------------------
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PROCESS IS
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BEGIN -- PROCESS
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WAIT FOR 200 us;
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end_of_simu <= '1';
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WAIT;
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END PROCESS;
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-----------------------------------------------------------------------------
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-- CLOCK and RESET
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-----------------------------------------------------------------------------
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PROCESS
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BEGIN -- PROCESS
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WAIT UNTIL clk_25 = '1';
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rstn_25 <= '0';
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WAIT UNTIL clk_25 = '1';
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WAIT UNTIL clk_25 = '1';
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WAIT UNTIL clk_25 = '1';
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rstn_25 <= '1';
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WAIT FOR 10 us;
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DAC_CAL_EN <= '0';
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WAIT FOR 1 us;
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bias_fail_sw <= '0';
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WAIT FOR 100 us;
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DAC_CAL_EN <= '1';
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WAIT FOR 1 us;
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bias_fail_sw <= '1';
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WAIT UNTIL end_of_simu = '1';
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WAIT FOR 10 ps;
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ASSERT false REPORT "end of test" SEVERITY note;
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-- Wait forever; this will finish the simulation.
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WAIT;
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END PROCESS;
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-----------------------------------------------------------------------------
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clk_25_gen : PROCESS
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BEGIN
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IF end_of_simu /= '1' THEN
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clk_25 <= NOT clk_25;
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TSTAMP <= TSTAMP+20;
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WAIT FOR 20 ns;
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ELSE
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WAIT FOR 20 ps;
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ASSERT false REPORT "end of test" SEVERITY note;
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WAIT;
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END IF;
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END PROCESS;
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-----------------------------------------------------------------------------
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clk_SMP_gen : PROCESS
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BEGIN
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IF end_of_simu /= '1' THEN
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SMP_CLK <= NOT SMP_CLK;
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IF SMP_CLK = '0' THEN
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DATA <= DATA + 3;
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END IF;
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WAIT FOR 5000101 ps;
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ELSE
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WAIT FOR 20 ps;
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ASSERT false REPORT "end of test" SEVERITY note;
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WAIT;
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END IF;
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END PROCESS;
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SPI_DAC_DRIVER_1: SPI_DAC_DRIVER
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GENERIC MAP (
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datawidth => 16,
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MSBFIRST => 1)
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PORT MAP (
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clk => clk_25,
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rstn => rstn_25,
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DATA => DATA,
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SMP_CLK => SMP_CLK,
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SYNC => DAC_SYNC,
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DOUT => DAC_DOUT,
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SCLK => DAC_SCLK);
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lfr_output_save_1: lfr_output_save
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GENERIC MAP (
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FNAME => "lfr_output.txt")
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PORT MAP (
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end_of_simu => end_of_simu,
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timestamp => TSTAMP,
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DAC_SDO => DAC_DOUT,
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DAC_SCK => DAC_SCLK,
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DAC_SYNC => DAC_SYNC,
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DAC_CAL_EN => DAC_CAL_EN,
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bias_fail_sw => bias_fail_sw);
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END;
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