LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE IEEE.std_logic_signed.ALL;
USE IEEE.MATH_real.ALL;

LIBRARY techmap;
USE techmap.gencomp.ALL;

LIBRARY std;
USE std.textio.ALL;

LIBRARY opencores;
USE opencores.spwpkg.ALL;
USE opencores.spwambapkg.ALL;

LIBRARY lpp;
USE lpp.lpp_sim_pkg.ALL;
USE lpp.lpp_cna.ALL;

ENTITY testbench IS
END;

ARCHITECTURE behav OF testbench IS

  SIGNAL TSTAMP : INTEGER   := 0;
  
  SIGNAL clk_25    : STD_LOGIC := '0';
  SIGNAL rstn_25    : STD_LOGIC;

  SIGNAL end_of_simu : STD_LOGIC := '0';

  SIGNAL DATA : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
  SIGNAL SMP_CLK : STD_LOGIC := '1';

  SIGNAL DAC_SYNC : STD_LOGIC;
  SIGNAL DAC_DOUT : STD_LOGIC;
  SIGNAL DAC_SCLK : STD_LOGIC;

  SIGNAL CAL_VALUE_data_v  : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
  SIGNAL CAL_VALUE_valid_v : STD_LOGIC_VECTOR(16 DOWNTO 0) := (OTHERS => '0');

  SIGNAL CAL_VALUE_data  : STD_LOGIC_VECTOR(15 DOWNTO 0);
  SIGNAL CAL_VALUE_valid : STD_LOGIC;

  SIGNAL DAC_CAL_EN  : STD_LOGIC;
  SIGNAL bias_fail_sw : STD_LOGIC;
  
BEGIN

  -----------------------------------------------------------------------------
  -- SIM GLOBAL RUN
  -----------------------------------------------------------------------------
  PROCESS IS
  BEGIN  -- PROCESS
    WAIT FOR 200 us;
    end_of_simu <= '1';
    WAIT;
  END PROCESS;
  
  -----------------------------------------------------------------------------
  -- CLOCK and RESET
  -----------------------------------------------------------------------------
  PROCESS
  BEGIN  -- PROCESS
    WAIT UNTIL clk_25 = '1';
    rstn_25 <= '0';
    WAIT UNTIL clk_25 = '1';
    WAIT UNTIL clk_25 = '1';
    WAIT UNTIL clk_25 = '1';
    rstn_25 <= '1';

    WAIT FOR 10 us;
    DAC_CAL_EN <= '0';

    WAIT FOR 1 us;
    bias_fail_sw <= '0';
    
    WAIT FOR 100 us;
    DAC_CAL_EN <= '1';

    WAIT FOR 1 us;
    bias_fail_sw <= '1';

    
    WAIT UNTIL end_of_simu = '1';
    WAIT FOR 10 ps;
    ASSERT false REPORT "end of test" SEVERITY note;
    --  Wait forever; this will finish the simulation.
    WAIT;
  END PROCESS;
  -----------------------------------------------------------------------------
  clk_25_gen : PROCESS
  BEGIN
    IF end_of_simu /= '1' THEN
      clk_25 <= NOT clk_25;
      TSTAMP <= TSTAMP+20;
      WAIT FOR 20 ns;
    ELSE
      WAIT FOR 20 ps;
      ASSERT false REPORT "end of test" SEVERITY note;
      WAIT;
    END IF;
  END PROCESS;
  -----------------------------------------------------------------------------

  clk_SMP_gen : PROCESS
  BEGIN
    IF end_of_simu /= '1' THEN
      SMP_CLK <= NOT SMP_CLK;
      IF SMP_CLK = '0' THEN
        DATA <= DATA + 3;
      END IF;
      WAIT FOR 5000101 ps;
    ELSE
      WAIT FOR 20 ps;
      ASSERT false REPORT "end of test" SEVERITY note;
      WAIT;
    END IF;
  END PROCESS;

  SPI_DAC_DRIVER_1: SPI_DAC_DRIVER
    GENERIC MAP (
      datawidth => 16,
      MSBFIRST  => 1)
    PORT MAP (
      clk     => clk_25,
      rstn    => rstn_25,

      DATA    => DATA,
      SMP_CLK => SMP_CLK,
      
      SYNC    => DAC_SYNC,
      DOUT    => DAC_DOUT,
      SCLK    => DAC_SCLK);

  lfr_output_save_1: lfr_output_save
    GENERIC MAP (
      FNAME => "lfr_output.txt")
    PORT MAP (
      end_of_simu  => end_of_simu,
      timestamp    => TSTAMP,
      DAC_SDO      => DAC_DOUT,
      DAC_SCK      => DAC_SCLK,
      DAC_SYNC     => DAC_SYNC,
      DAC_CAL_EN   => DAC_CAL_EN,
      bias_fail_sw => bias_fail_sw);
  
END;