diff --git a/lib/lpp/lpp_sim/lfr_output_save.vhd b/lib/lpp/lpp_sim/lfr_output_save.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_sim/lfr_output_save.vhd @@ -0,0 +1,85 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY std; +USE std.textio.ALL; + +ENTITY lfr_output_save IS + GENERIC( + FNAME : STRING := "output.txt" + ); + PORT( + end_of_simu : IN STD_LOGIC; + timestamp : IN integer; + + -- DAC -------------------------------------------------------------------- + DAC_SDO : in STD_LOGIC; + DAC_SCK : in STD_LOGIC; + DAC_SYNC : in STD_LOGIC; + DAC_CAL_EN : in STD_LOGIC; + -- BIAS_FAIL -------------------------------------------------------------- + bias_fail_sw : in STD_LOGIC + ); +END lfr_output_save; + +ARCHITECTURE beh OF lfr_output_save IS + + FILE output_file : TEXT OPEN write_mode IS FNAME; + + SIGNAL CAL_VALUE_data_v : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0'); + SIGNAL CAL_VALUE_valid_v : STD_LOGIC_VECTOR(16 DOWNTO 0) := (OTHERS => '0'); + + SIGNAL CAL_VALUE_data : STD_LOGIC_VECTOR(15 DOWNTO 0); + +BEGIN + + ----------------------------------------------------------------------------- + -- Data orginization in the output file : + ----------------------------------------------------------------------------- + -- Exemple of output.txt file : + -- TIME CAL_VALUE CAL_ENABLE BIAS_FAIL_VALUE + -- TIME CAL_VALUE CAL_ENABLE BIAS_FAIL_VALUE + ----------------------------------------------------------------------------- + -- TIME : integer. Current time (in ns) + -- others : integer(0 to 255). Current value. + ----------------------------------------------------------------------------- + + + + ----------------------------------------------------------------------------- + -- DAC : SPI to Parralel + PROCESS (DAC_SCK) IS + BEGIN -- PROCESS + IF DAC_SCK'event AND DAC_SCK = '1' THEN -- rising clock edge + CAL_VALUE_valid_v(0) <= '0'; + CAL_VALUE_valid_v(16 DOWNTO 1) <= CAL_VALUE_valid_v(15 DOWNTO 0); + IF DAC_SYNC = '1' THEN + CAL_VALUE_valid_v(0) <= '1'; + END IF; + CAL_VALUE_data_v(15 DOWNTO 0) <= CAL_VALUE_data_v(14 DOWNTO 0) & DAC_SDO; + END IF; + END PROCESS; + + CAL_VALUE_data <= CAL_VALUE_data_v WHEN CAL_VALUE_valid_v(16) = '1'; + ----------------------------------------------------------------------------- + + + + ----------------------------------------------------------------------------- + -- + PROCESS(end_of_simu, CAL_VALUE_data, DAC_CAL_EN, bias_fail_sw) + VARIABLE line_var : LINE; + BEGIN + IF end_of_simu = '1' THEN + file_close(output_file); + ELSE + write(line_var, INTEGER'IMAGE(timestamp)); + write(line_var," " & INTEGER'IMAGE(to_integer(UNSIGNED(CAL_VALUE_data)))); + write(line_var," " & STD_LOGIC'IMAGE(DAC_CAL_EN)); + write(line_var," " & STD_LOGIC'IMAGE(bias_fail_sw)); + writeline(output_file, line_var); + END IF; + END PROCESS; + +END beh; diff --git a/lib/lpp/lpp_sim/lpp_sim_pkg.vhd b/lib/lpp/lpp_sim/lpp_sim_pkg.vhd --- a/lib/lpp/lpp_sim/lpp_sim_pkg.vhd +++ b/lib/lpp/lpp_sim/lpp_sim_pkg.vhd @@ -138,6 +138,19 @@ PACKAGE lpp_sim_pkg IS error_oeb : OUT STD_LOGIC; error_hksel : OUT STD_LOGIC); END COMPONENT lfr_input_gen; + + COMPONENT lfr_output_save IS + GENERIC ( + FNAME : STRING); + PORT ( + end_of_simu : IN STD_LOGIC; + timestamp : IN integer; + DAC_SDO : in STD_LOGIC; + DAC_SCK : in STD_LOGIC; + DAC_SYNC : in STD_LOGIC; + DAC_CAL_EN : in STD_LOGIC; + bias_fail_sw : in STD_LOGIC); + END COMPONENT lfr_output_save; END lpp_sim_pkg; diff --git a/lib/lpp/lpp_sim/vhdlsim.txt b/lib/lpp/lpp_sim/vhdlsim.txt --- a/lib/lpp/lpp_sim/vhdlsim.txt +++ b/lib/lpp/lpp_sim/vhdlsim.txt @@ -6,3 +6,4 @@ lpp_lfr_sim_pkg.vhd spw_sender.vhd spw_receiver.vhd lfr_input_gen.vhd +lfr_output_save.vhd diff --git a/tests/Test_DAC_to_File/Makefile b/tests/Test_DAC_to_File/Makefile new file mode 100644 --- /dev/null +++ b/tests/Test_DAC_to_File/Makefile @@ -0,0 +1,53 @@ +VHDLIB=../.. +SCRIPTSDIR=$(VHDLIB)/scripts/ +GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) +TOP=testbench +BOARD=LFR-FM +include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc +DEVICE=$(PART)-$(PACKAGE)$(SPEED) +UCF= +QSF= +EFFORT=high +XSTOPT= +SYNPOPT= +VHDLSYNFILES= +VHDLSIMFILES= tb.vhd +SIMTOP=testbench +CLEAN=soft-clean + +TECHLIBS = axcelerator + + +LIBSKIP = tmtc openchip hynix cypress ihp usbhc fmf gsi spansion eth micron + +DIRSKIP = leon2 leon2ft crypto usb satcan ddr greth grusbhc \ + leon4 leon4v0 l2cache iommu slink ascs pwm net spi can \ + ./amba_lcd_16x2_ctrlr \ + ./general_purpose/lpp_AMR \ + ./general_purpose/lpp_balise \ + ./general_purpose/lpp_delay \ + ./lpp_bootloader \ + ./lpp_uart \ + ./lpp_usb \ + ./lpp_debug_lfr \ + ./dsp/lpp_fft + +FILESKIP = i2cmst.vhd \ + APB_MULTI_DIODE.vhd \ + APB_MULTI_DIODE.vhd \ + Top_MatrixSpec.vhd \ + APB_FFT.vhd \ + lpp_lfr_sim_pkg.vhd + +include $(GRLIB)/bin/Makefile +include $(GRLIB)/software/leon3/Makefile +################## project specific targets ########################## +distclean:myclean + +myclean: + rm -f input.txt output_fx.txt *.log + rm -rf ./2016* + +test: | ghdl ghdl-run archivate + + diff --git a/tests/Test_DAC_to_File/adc_input.txt b/tests/Test_DAC_to_File/adc_input.txt new file mode 100644 --- /dev/null +++ b/tests/Test_DAC_to_File/adc_input.txt @@ -0,0 +1,385 @@ +10 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +110 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 +110 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 +110 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 +110 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 +110 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 +110 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 +110 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 +110 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 +110 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 +110 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 +110 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 +110 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 +110 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 +110 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 +110 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 +110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +110 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 +110 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 +110 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 +110 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 +110 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 +110 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 +110 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 +110 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 +110 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 +110 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 +110 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 +110 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 +110 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 +110 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 +110 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 +110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +110 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 +110 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 +110 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 +110 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 +110 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 +110 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 +110 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 +110 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 +110 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 +110 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 +110 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 +110 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 +110 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 +110 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 +110 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 +110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +110 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 +110 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 +110 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 +110 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 +110 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 +110 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 +110 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 +110 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 +110 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 +110 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 +110 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 +110 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 +110 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 +110 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 +110 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 +110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +110 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 +110 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 +110 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 +110 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 +110 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 +110 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 +110 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 +110 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 +110 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 +110 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 +110 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 +110 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 +110 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 +110 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 +110 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 +110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +110 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 +110 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 +110 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 +110 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 +110 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 +110 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 +110 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 +110 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 +110 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 +110 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 +110 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 +110 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 +110 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 +110 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 +110 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 +110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +110 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 +110 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 +110 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 +110 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 +110 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 +110 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 +110 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 +110 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 +110 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 +110 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 +110 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 +110 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 +110 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 +110 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 +110 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 +110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +110 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 +110 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 +110 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 +110 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 +110 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 +110 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 +110 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 +110 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 +110 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 +110 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 +110 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 +110 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 +110 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 +110 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 +110 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 +110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +110 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 +110 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 +110 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 +110 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 +110 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 +110 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 +110 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 +110 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 +110 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 +110 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 +110 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 +110 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 +110 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 +110 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 +110 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 +110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +110 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 +110 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 +110 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 +110 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 +110 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 +110 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 +110 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 +110 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 +110 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 +110 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 +110 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 +110 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 +110 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 +110 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 +110 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 +110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +110 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 +110 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 +110 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 +110 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 +110 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 +110 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 +110 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 +110 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 +110 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 +110 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 +110 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 +110 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 +110 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 +110 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 +110 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 +110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +110 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 +110 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 +110 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 +110 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 +110 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 +110 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 +110 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 +110 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 +110 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 +110 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 +110 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 +110 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 +110 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 +110 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 +110 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 +110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +110 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 +110 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 +110 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 +110 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 +110 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 +110 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 +110 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 +110 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 +110 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 +110 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 +110 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 +110 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 +110 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 +110 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 +110 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 +110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +110 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 +110 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 +110 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 +110 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 +110 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 +110 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 +110 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 +110 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 +110 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 +110 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 +110 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 +110 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 +110 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 +110 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 +110 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 +110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +110 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 +110 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 +110 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 +110 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 +110 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 +110 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 +110 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 +110 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 +110 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 +110 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 +110 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 +110 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 +110 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 +110 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 +110 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 +110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +110 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 +110 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 +110 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 +110 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 +110 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 +110 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 +110 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 +110 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 +110 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 +110 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 +110 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 +110 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 +110 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 +110 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 +110 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 +110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +110 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 +110 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 +110 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 +110 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 +110 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 +110 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 +110 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 +110 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 +110 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 +110 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 +110 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 +110 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 +110 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 +110 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 +110 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 +110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +110 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 +110 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 +110 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 +110 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 +110 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 +110 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 +110 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 +110 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 +110 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 +110 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 +110 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 +110 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 +110 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 +110 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 +110 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 +110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +110 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 +110 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 +110 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 +110 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 +110 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 +110 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 +110 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 +110 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 +110 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 +110 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 +110 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 +110 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 +110 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 +110 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 +110 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 +110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +110 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 +110 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 +110 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 +110 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 +110 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 +110 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 +110 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 +110 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 +110 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 +110 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 +110 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 +110 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 +110 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 +110 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 +110 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 +110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +110 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 +110 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 +110 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 +110 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 +110 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 +110 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 +110 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 +110 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 +110 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 +110 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 +110 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 +110 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 +110 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 +110 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 +110 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 +110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +110 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 +110 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 +110 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 +110 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 +110 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 +110 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 +110 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 +110 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 +110 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 +110 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 +110 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 +110 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 +110 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 +110 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 +110 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 +110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +110 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 +110 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 +110 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 +110 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 +110 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 +110 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 +110 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 +110 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 +110 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 +110 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 +110 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 +110 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 +110 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 +110 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 +110 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 +110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +110 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 +110 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 +110 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 +110 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 +110 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 +110 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 +110 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 +110 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 +110 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 +110 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 +110 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 +110 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 +110 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 +110 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 +110 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 +110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 diff --git a/tests/Test_DAC_to_File/lfr_output.txt b/tests/Test_DAC_to_File/lfr_output.txt new file mode 100644 --- /dev/null +++ b/tests/Test_DAC_to_File/lfr_output.txt @@ -0,0 +1,25 @@ +0 0 'U' 'U' +6340 3 'U' 'U' +10140 3 '0' 'U' +11140 3 '0' '0' +16340 6 '0' '0' +26340 9 '0' '0' +36340 12 '0' '0' +46340 15 '0' '0' +56340 18 '0' '0' +66340 21 '0' '0' +76340 24 '0' '0' +86340 27 '0' '0' +96340 30 '0' '0' +106340 33 '0' '0' +111140 33 '1' '0' +112140 33 '1' '1' +116340 36 '1' '1' +126340 39 '1' '1' +136340 42 '1' '1' +146340 45 '1' '1' +156340 48 '1' '1' +166340 51 '1' '1' +176340 54 '1' '1' +186340 57 '1' '1' +196340 60 '1' '1' diff --git a/tests/Test_DAC_to_File/tb.vhd b/tests/Test_DAC_to_File/tb.vhd new file mode 100644 --- /dev/null +++ b/tests/Test_DAC_to_File/tb.vhd @@ -0,0 +1,150 @@ + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; +USE IEEE.std_logic_signed.ALL; +USE IEEE.MATH_real.ALL; + +LIBRARY techmap; +USE techmap.gencomp.ALL; + +LIBRARY std; +USE std.textio.ALL; + +LIBRARY opencores; +USE opencores.spwpkg.ALL; +USE opencores.spwambapkg.ALL; + +LIBRARY lpp; +USE lpp.lpp_sim_pkg.ALL; +USE lpp.lpp_cna.ALL; + +ENTITY testbench IS +END; + +ARCHITECTURE behav OF testbench IS + + SIGNAL TSTAMP : INTEGER := 0; + + SIGNAL clk_25 : STD_LOGIC := '0'; + SIGNAL rstn_25 : STD_LOGIC; + + SIGNAL end_of_simu : STD_LOGIC := '0'; + + SIGNAL DATA : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0'); + SIGNAL SMP_CLK : STD_LOGIC := '1'; + + SIGNAL DAC_SYNC : STD_LOGIC; + SIGNAL DAC_DOUT : STD_LOGIC; + SIGNAL DAC_SCLK : STD_LOGIC; + + SIGNAL CAL_VALUE_data_v : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0'); + SIGNAL CAL_VALUE_valid_v : STD_LOGIC_VECTOR(16 DOWNTO 0) := (OTHERS => '0'); + + SIGNAL CAL_VALUE_data : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL CAL_VALUE_valid : STD_LOGIC; + + SIGNAL DAC_CAL_EN : STD_LOGIC; + SIGNAL bias_fail_sw : STD_LOGIC; + +BEGIN + + ----------------------------------------------------------------------------- + -- SIM GLOBAL RUN + ----------------------------------------------------------------------------- + PROCESS IS + BEGIN -- PROCESS + WAIT FOR 200 us; + end_of_simu <= '1'; + WAIT; + END PROCESS; + + ----------------------------------------------------------------------------- + -- CLOCK and RESET + ----------------------------------------------------------------------------- + PROCESS + BEGIN -- PROCESS + WAIT UNTIL clk_25 = '1'; + rstn_25 <= '0'; + WAIT UNTIL clk_25 = '1'; + WAIT UNTIL clk_25 = '1'; + WAIT UNTIL clk_25 = '1'; + rstn_25 <= '1'; + + WAIT FOR 10 us; + DAC_CAL_EN <= '0'; + + WAIT FOR 1 us; + bias_fail_sw <= '0'; + + WAIT FOR 100 us; + DAC_CAL_EN <= '1'; + + WAIT FOR 1 us; + bias_fail_sw <= '1'; + + + WAIT UNTIL end_of_simu = '1'; + WAIT FOR 10 ps; + ASSERT false REPORT "end of test" SEVERITY note; + -- Wait forever; this will finish the simulation. + WAIT; + END PROCESS; + ----------------------------------------------------------------------------- + clk_25_gen : PROCESS + BEGIN + IF end_of_simu /= '1' THEN + clk_25 <= NOT clk_25; + TSTAMP <= TSTAMP+20; + WAIT FOR 20 ns; + ELSE + WAIT FOR 20 ps; + ASSERT false REPORT "end of test" SEVERITY note; + WAIT; + END IF; + END PROCESS; + ----------------------------------------------------------------------------- + + clk_SMP_gen : PROCESS + BEGIN + IF end_of_simu /= '1' THEN + SMP_CLK <= NOT SMP_CLK; + IF SMP_CLK = '0' THEN + DATA <= DATA + 3; + END IF; + WAIT FOR 5000101 ps; + ELSE + WAIT FOR 20 ps; + ASSERT false REPORT "end of test" SEVERITY note; + WAIT; + END IF; + END PROCESS; + + SPI_DAC_DRIVER_1: SPI_DAC_DRIVER + GENERIC MAP ( + datawidth => 16, + MSBFIRST => 1) + PORT MAP ( + clk => clk_25, + rstn => rstn_25, + + DATA => DATA, + SMP_CLK => SMP_CLK, + + SYNC => DAC_SYNC, + DOUT => DAC_DOUT, + SCLK => DAC_SCLK); + + lfr_output_save_1: lfr_output_save + GENERIC MAP ( + FNAME => "lfr_output.txt") + PORT MAP ( + end_of_simu => end_of_simu, + timestamp => TSTAMP, + DAC_SDO => DAC_DOUT, + DAC_SCK => DAC_SCLK, + DAC_SYNC => DAC_SYNC, + DAC_CAL_EN => DAC_CAL_EN, + bias_fail_sw => bias_fail_sw); + +END;