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Partially Working BeagleSynth base design, SDRAM still f****** buggy.
Jeandet Alexis -
r265:9504f3e37fb4 alexis
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1
1
2 NET "CLK" CLOCK_DEDICATED_ROUTE = FALSE;
2 NET "CLK" CLOCK_DEDICATED_ROUTE = FALSE;
3 NET "CLK" LOC = "K20";
3 NET "CLK" LOC = "K20"| slew=FAST | IOSTANDARD=LVTTL;
4 #NET "CLKM" TNM_NET = "clkm_net";
5 #TIMESPEC "TS_clkm_net" = PERIOD "clkm_net" 10 ns HIGH 50%;
4
6
5 NET "RESET" CLOCK_DEDICATED_ROUTE = FALSE;
7 NET "RESET" CLOCK_DEDICATED_ROUTE = FALSE;
6 NET "RESET" LOC = "AB11";
8 NET "RESET" LOC = "AB11" | slew=FAST | IOSTANDARD=LVTTL;
7
9
8 NET "DAC_nCLR" LOC = "R11";
10 NET "DAC_nCLR" LOC = "R11" | IOSTANDARD=LVTTL;
9 NET "DAC_nCS" LOC = "T12";
11 NET "DAC_nCS" LOC = "T12" | IOSTANDARD=LVTTL;
10 NET "CAL_IN_SCK" LOC = "R13";
12 NET "CAL_IN_SCK" LOC = "R13" | IOSTANDARD=LVTTL;
11 NET "DAC_SDI(0)" LOC = "P5";
13 NET "DAC_SDI(0)" LOC = "P5" | IOSTANDARD=LVTTL;
12 NET "DAC_SDI(1)" LOC = "M5";
14 NET "DAC_SDI(1)" LOC = "M5" | IOSTANDARD=LVTTL;
13 NET "DAC_SDI(2)" LOC = "C8";
15 NET "DAC_SDI(2)" LOC = "C8" | IOSTANDARD=LVTTL;
14 NET "DAC_SDI(3)" LOC = "M6";
16 NET "DAC_SDI(3)" LOC = "M6" | IOSTANDARD=LVTTL;
15 NET "DAC_SDI(4)" LOC = "K22";
17 NET "DAC_SDI(4)" LOC = "K22" | IOSTANDARD=LVTTL;
16 NET "DAC_SDI(5)" LOC = "L22";
18 NET "DAC_SDI(5)" LOC = "L22" | IOSTANDARD=LVTTL;
17 NET "DAC_SDI(6)" LOC = "G19";
19 NET "DAC_SDI(6)" LOC = "G19" | IOSTANDARD=LVTTL;
18 NET "DAC_SDI(7)" LOC = "F20";
20 NET "DAC_SDI(7)" LOC = "F20" | IOSTANDARD=LVTTL;
19
21
20
22
21 NET "TDX" LOC = "V22";
23 NET "TXD" LOC = "V22"| slew=FAST | IOSTANDARD=LVTTL;
22 NET "RXD" LOC = "U22";
24 NET "RXD" LOC = "U22"| slew=FAST | IOSTANDARD=LVTTL;
23 NET "LED(0)" LOC = "AB9";
25 NET "LED(0)" LOC = "AB9"| slew=FAST | IOSTANDARD=LVTTL;
24 NET "LED(1)" LOC = "AB8";
26 NET "LED(1)" LOC = "AB8"| slew=FAST | IOSTANDARD=LVTTL;
25 NET "LED(2)" LOC = "AA8";
27 NET "LED(2)" LOC = "AA8"| slew=FAST | IOSTANDARD=LVTTL;
26
28
27 NET "urxd1" LOC = "D3"; # Unused PIN
29 NET "urxd1" LOC = "D3" | IOSTANDARD=LVTTL; # Unused PIN
28 NET "utxd1" LOC = "C4"; # Unused PIN No newline at end of file
30 NET "utxd1" LOC = "C4" | IOSTANDARD=LVTTL; # Unused PIN
31
32 NET "sdcke" LOC = "B6" | slew=FAST | IOSTANDARD=LVTTL; # clk en
33 NET "sdcsn" LOC = "G20"| slew=FAST | IOSTANDARD=LVTTL; # chip sel
34 NET "sdwen" LOC = "D14"| slew=FAST | IOSTANDARD=LVTTL; # write en
35 NET "sdrasn" LOC = "H19"| slew=FAST | IOSTANDARD=LVTTL; # row addr stb
36 NET "sdcasn" LOC = "C14"| slew=FAST | IOSTANDARD=LVTTL; # col addr stb
37
38 NET "sddqm(3)" LOC = "A5" | slew=FAST | IOSTANDARD=LVTTL; # data i/o mask
39 NET "sddqm(2)" LOC = "D21"| slew=FAST | IOSTANDARD=LVTTL; # data i/o mask
40 NET "sddqm(1)" LOC = "C7" | slew=FAST | IOSTANDARD=LVTTL; # data i/o mask
41 NET "sddqm(0)" LOC = "D15"| slew=FAST | IOSTANDARD=LVTTL; # data i/o mask
42
43 NET "sdclk" CLOCK_DEDICATED_ROUTE = FALSE;
44 NET "sdclk" LOC = "A6" | slew=FAST | IOSTANDARD=LVTTL; # sdram clk output
45 NET "sdba(1)" LOC = "J20"| slew=FAST | IOSTANDARD=LVTTL; # bank select address
46 NET "sdba(0)" LOC = "G16"| slew=FAST | IOSTANDARD=LVTTL; # bank select address
47
48 NET "Address(11)" LOC = "H8"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
49 NET "Address(10)" LOC = "G7"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
50 NET "Address(9)" LOC = "K7"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
51 NET "Address(8)" LOC = "H6"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
52 NET "Address(7)" LOC = "H5"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
53 NET "Address(6)" LOC = "K8"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
54 NET "Address(5)" LOC = "G4"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
55 NET "Address(4)" LOC = "H3"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
56 NET "Address(3)" LOC = "D2"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
57 NET "Address(2)" LOC = "B3"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
58 NET "Address(1)" LOC = "A2"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
59 NET "Address(0)" LOC = "C22"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
60
61 NET "Data(31)" LOC = "C5" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
62 NET "Data(30)" LOC = "A4" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
63 NET "Data(29)" LOC = "A3" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
64 NET "Data(28)" LOC = "B2" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
65 NET "Data(27)" LOC = "B1" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
66 NET "Data(26)" LOC = "C1" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
67 NET "Data(25)" LOC = "D1" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
68 NET "Data(24)" LOC = "E1" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
69 NET "Data(23)" LOC = "J22"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
70 NET "Data(22)" LOC = "H22"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
71 NET "Data(21)" LOC = "H21"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
72 NET "Data(20)" LOC = "G22"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
73 NET "Data(19)" LOC = "F22"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
74 NET "Data(18)" LOC = "F21"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
75 NET "Data(17)" LOC = "E22"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
76 NET "Data(16)" LOC = "D22"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
77 NET "Data(15)" LOC = "A7" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
78 NET "Data(14)" LOC = "B8" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
79 NET "Data(13)" LOC = "A8" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
80 NET "Data(12)" LOC = "C9" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
81 NET "Data(11)" LOC = "A9" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
82 NET "Data(10)" LOC = "B10"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
83 NET "Data(9)" LOC = "A10"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
84 NET "Data(8)" LOC = "C11"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
85 NET "Data(7)" LOC = "A13"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
86 NET "Data(6)" LOC = "C13"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
87 NET "Data(5)" LOC = "B22"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
88 NET "Data(4)" LOC = "B21"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
89 NET "Data(3)" LOC = "B20"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
90 NET "Data(2)" LOC = "A20"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
91 NET "Data(1)" LOC = "B18"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
92 NET "Data(0)" LOC = "A18"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
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@@ -1,229 +1,251
1 library ieee;
1 library ieee;
2 use ieee.std_logic_1164.all;
2 use ieee.std_logic_1164.all;
3 use IEEE.numeric_std.all;
3 use IEEE.numeric_std.all;
4 library grlib, techmap;
4 library grlib, techmap;
5 use grlib.amba.all;
5 use grlib.amba.all;
6 use grlib.amba.all;
6 use grlib.amba.all;
7 use grlib.stdlib.all;
7 use grlib.stdlib.all;
8 use techmap.gencomp.all;
8 use techmap.gencomp.all;
9 use techmap.allclkgen.all;
9 use techmap.allclkgen.all;
10 library gaisler;
10 library gaisler;
11 use gaisler.memctrl.all;
11 use gaisler.memctrl.all;
12 use gaisler.leon3.all;
12 use gaisler.leon3.all;
13 use gaisler.uart.all;
13 use gaisler.uart.all;
14 use gaisler.misc.all;
14 use gaisler.misc.all;
15 library esa;
16 use esa.memoryctrl.all;
15 --use gaisler.sim.all;
17 --use gaisler.sim.all;
16 library lpp;
18 library lpp;
17 use lpp.lpp_ad_conv.all;
19 use lpp.lpp_ad_conv.all;
18 use lpp.lpp_amba.all;
20 use lpp.lpp_amba.all;
19 use lpp.apb_devices_list.all;
21 use lpp.apb_devices_list.all;
20 use lpp.general_purpose.all;
22 use lpp.general_purpose.all;
21
23
24 Library UNISIM;
25 use UNISIM.vcomponents.all;
26
22
27
23 use work.config.all;
28 use work.config.all;
24 --==================================================================
29 --==================================================================
25 --
30 --
26 --
31 --
27 -- FPGA FREQ = 100MHz
32 -- FPGA FREQ = 100MHz
28 --
33 --
29 --
34 --
30 --==================================================================
35 --==================================================================
31
36
32 entity BeagleSynth is
37 entity BeagleSynth is
33 generic (
38 generic (
34 fabtech : integer := CFG_FABTECH;
39 fabtech : integer := CFG_FABTECH;
35 memtech : integer := CFG_MEMTECH;
40 memtech : integer := CFG_MEMTECH;
36 padtech : integer := CFG_PADTECH;
41 padtech : integer := CFG_PADTECH;
37 clktech : integer := CFG_CLKTECH
42 clktech : integer := CFG_CLKTECH
38 );
43 );
39 port (
44 port (
40 reset : in std_ulogic;
45 reset : in std_ulogic;
41 clk : in std_ulogic;
46 clk : in std_ulogic;
42 DAC_nCLR : out std_ulogic;
47 DAC_nCLR : out std_ulogic;
43 DAC_nCS : out std_ulogic;
48 DAC_nCS : out std_ulogic;
44 CAL_IN_SCK : out std_ulogic;
49 CAL_IN_SCK : out std_ulogic;
45 DAC_SDI : out std_ulogic_vector(7 downto 0);
50 DAC_SDI : out std_ulogic_vector(7 downto 0);
46 TXD : out std_ulogic;
51 TXD : out std_ulogic;
47 RXD : in std_ulogic;
52 RXD : in std_ulogic;
48 urxd1 : in std_ulogic;
53 urxd1 : in std_ulogic;
49 utxd1 : out std_ulogic;
54 utxd1 : out std_ulogic;
50 LED : out std_ulogic_vector(2 downto 0);
55 LED : out std_ulogic_vector(2 downto 0);
51 --------------------------------------------------------
56 --------------------------------------------------------
52 ---- SDRAM
57 ---- SDRAM
53 ---- For SDRAM config have a look on leon3-altera-ep1c20
58 ---- For SDRAM config have a look on leon3-altera-ep1c20
54 ---- design from GRLIB, the IS42S32400E is similar to
59 ---- design from GRLIB, the IS42S32400E is similar to
55 ---- MT48LC4M32B2.
60 ---- MT48LC4M32B2.
56 --------------------------------------------------------
61 --------------------------------------------------------
57 sdcke : out std_logic_vector ( 1 downto 0); -- clk en
62 sdcke : out std_logic; -- clk en
58 sdcsn : out std_logic_vector ( 1 downto 0); -- chip sel
63 sdcsn : out std_logic; -- chip sel
59 sdwen : out std_logic; -- write en
64 sdwen : out std_logic; -- write en
60 sdrasn : out std_logic; -- row addr stb
65 sdrasn : out std_logic; -- row addr stb
61 sdcasn : out std_logic; -- col addr stb
66 sdcasn : out std_logic; -- col addr stb
62 sddqm : out std_logic_vector (3 downto 0); -- data i/o mask
67 sddqm : out std_logic_vector (3 downto 0); -- data i/o mask
63 sdclk : out std_logic; -- sdram clk output
68 sdclk : out std_logic; -- sdram clk output
64 sdba : out std_logic_vector (3 downto 0); -- bank select address
69 sdba : out std_logic_vector (1 downto 0); -- bank select address
65 Address : out std_logic_vector(11 downto 0); -- sdram address
70 Address : out std_logic_vector(11 downto 0); -- sdram address
66 Data : inout std_logic_vector(31 downto 0) -- optional sdram data
71 Data : inout std_logic_vector(31 downto 0) -- optional sdram data
67 );
72 );
68 end;
73 end;
69
74
70 architecture rtl of BeagleSynth is
75 architecture rtl of BeagleSynth is
71 constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
76 constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
72 CFG_GRETH+CFG_AHB_JTAG;
77 CFG_GRETH+CFG_AHB_JTAG;
73 constant maxahbm : integer := maxahbmsp;
78 constant maxahbm : integer := maxahbmsp;
74 constant IOAEN : integer := CFG_CAN;
79 constant IOAEN : integer := CFG_CAN;
75 constant boardfreq : integer := 100000;
80 constant boardfreq : integer := 100000;
76
81
77 signal clk2x : std_ulogic;
82 signal clk2x : std_ulogic;
78 signal lclk : std_ulogic;
83 signal lclk : std_ulogic;
79 signal clkm : std_ulogic;
84 signal clkm : std_ulogic;
80 signal rstn : std_ulogic;
85 signal rstn : std_ulogic;
86 signal rst : std_ulogic;
81 signal rstraw : std_ulogic;
87 signal rstraw : std_ulogic;
82 signal pciclk : std_ulogic;
88 signal pciclk : std_ulogic;
83 signal sdclkl : std_ulogic;
89 signal sdclkl : std_ulogic;
90 signal sdclkl_DDR2 : std_ulogic;
84 signal cgi : clkgen_in_type;
91 signal cgi : clkgen_in_type;
85 signal cgo : clkgen_out_type;
92 signal cgo : clkgen_out_type;
86
93
87 --- AHB / APB
94 --- AHB / APB
88 signal apbi : apb_slv_in_type;
95 signal apbi : apb_slv_in_type;
89 signal apbo : apb_slv_out_vector := (others => apb_none);
96 signal apbo : apb_slv_out_vector := (others => apb_none);
90 signal ahbsi : ahb_slv_in_type;
97 signal ahbsi : ahb_slv_in_type;
91 signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
98 signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
92 signal ahbmi : ahb_mst_in_type;
99 signal ahbmi : ahb_mst_in_type;
93 signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
100 signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
94
101
95 --- MEM CTRLR
102 --- MEM CTRLR
96 signal memi : memory_in_type;
103 signal sdi : sdctrl_in_type;
97 signal memo : memory_out_type;
104 signal sdo : sdctrl_out_type;
98 signal sdo : sdram_out_type;
99
105
100 --UART
106 --UART
101 signal ahbuarti : uart_in_type;
107 signal ahbuarti : uart_in_type;
102 signal ahbuarto : uart_out_type;
108 signal ahbuarto : uart_out_type;
103 signal apbuarti : uart_in_type;
109 signal apbuarti : uart_in_type;
104 signal apbuarto : uart_out_type;
110 signal apbuarto : uart_out_type;
105
111
106 signal led2int : std_logic;
112 signal led2int : std_logic;
107
113
108 begin
114 begin
109
115
110 DAC_nCLR <= '1';
116 DAC_nCLR <= '1';
111 DAC_nCS <= '1';
117 DAC_nCS <= '1';
112 CAL_IN_SCK <= '1';
118 CAL_IN_SCK <= '1';
113 DAC_SDI <= (others =>'1');
119 DAC_SDI <= (others =>'1');
114
120
115 rst0 : rstgen port map (reset, clkm, cgo.clklock, rstn, rstraw);
121 resetn_pad : inpad generic map (tech => padtech) port map (reset, rst);
122 rst0 : rstgen port map (rst, lclk, '1', rstn, rstraw);
123 --rstn <= reset;
124 --lclk <= clk;
125 clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk, lclk);
116
126
117 lclk <= clk;
127 cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
128 clkgen0 : clkgen -- clock generator
129 generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, CFG_CLK_NOFB, 0, 0, 0, boardfreq)
130 port map (lclk, lclk, clkm, open, open, sdclkl, open, cgi, cgo,open,open);
131
132 -- sdclk_pad : outpad generic map (tech => padtech) port map (sdclk, sdclkl_DDR2);
133 --sdclk <= sdclkl;
134 sdclk <= sdclkl_DDR2;
118
135
119 clkgen0 : clkgen -- clock generatorsa
136 ODDR2_inst : ODDR2
120 generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
137 generic map(
121 CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV)
138 DDR_ALIGNMENT => "C0", -- Sets output alignment to "NONE", "C0", "C1"
122 port map (lclk, lclk, clkm, open, clk2x, sdclkl, pciclk, cgi, cgo);
139 INIT => '0', -- Sets initial state of the Q output to '0' or '1'
123
140 SRTYPE => "ASYNC") -- Specifies "SYNC" or "ASYNC" set/reset
141 port map (
142 Q => sdclkl_DDR2, -- 1-bit output data
143 C0 => sdclkl, -- 1-bit clock input
144 C1 => not sdclkl, -- 1-bit clock input
145 CE => '1', -- 1-bit clock enable input
146 D0 => '1', -- 1-bit data input (associated with C0)
147 D1 => '0', -- 1-bit data input (associated with C1)
148 R => '0', -- 1-bit reset input
149 S => '0' -- 1-bit set input
150 );
124
151
125 ----------------------------------------------------------------------
152 ----------------------------------------------------------------------
126 --- AHB CONTROLLER -------------------------------------------------
153 --- AHB CONTROLLER -------------------------------------------------
127 ----------------------------------------------------------------------
154 ----------------------------------------------------------------------
128
155
129 ahb0 : ahbctrl -- AHB arbiter/multiplexer
156 ahb0 : ahbctrl -- AHB arbiter/multiplexer
130 generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
157 generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
131 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
158 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
132 ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
159 ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
133 port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
160 port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
134
161
135 ----------------------------------------------------------------------
162 ----------------------------------------------------------------------
136 --- AHB UART -------------------------------------------------------
163 --- AHB UART -------------------------------------------------------
137 ----------------------------------------------------------------------
164 ----------------------------------------------------------------------
138
165
139 dcomgen : if CFG_AHB_UART = 1 generate
166 dcomgen : if CFG_AHB_UART = 1 generate
140 dcom0: ahbuart -- Debug UART
167 dcom0: ahbuart -- Debug UART
141 generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
168 generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
142 port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
169 port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
143 ahbuarti.rxd <= RXD;
170 ahbuarti.rxd <= RXD;
144 TXD <= ahbuarto.txd;
171 TXD <= ahbuarto.txd;
145 led(0) <= not ahbuarti.rxd; led(1) <= not ahbuarto.txd;
172 led(0) <= ahbuarti.rxd; led(1) <= ahbuarto.txd;
146 end generate;
173 end generate;
147 nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
174 nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
148
175
149 ----------------------------------------------------------------------
176 ----------------------------------------------------------------------
150 --- APB Bridge -----------------------------------------------------
177 --- APB Bridge -----------------------------------------------------
151 ----------------------------------------------------------------------
178 ----------------------------------------------------------------------
152
179
153 apb0 : apbctrl -- AHB/APB bridge
180 apb0 : apbctrl -- AHB/APB bridge
154 generic map (hindex => 1, haddr => CFG_APBADDR)
181 generic map (hindex => 1, haddr => CFG_APBADDR)
155 port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
182 port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
156
183
157 ----------------------------------------------------------------------
184 ----------------------------------------------------------------------
158 --- APB UART -------------------------------------------------------
185 --- APB UART -------------------------------------------------------
159 ----------------------------------------------------------------------
186 ----------------------------------------------------------------------
160
187
161 ua1 : if CFG_UART1_ENABLE /= 0 generate
188 ua1 : if CFG_UART1_ENABLE /= 0 generate
162 uart1 : apbuart -- UART 1
189 uart1 : apbuart -- UART 1
163 generic map (pindex => 1, paddr => 1, pirq => 2, console => CFG_DUART,
190 generic map (pindex => 1, paddr => 1, pirq => 2, console => CFG_DUART,
164 fifosize => CFG_UART1_FIFO)
191 fifosize => CFG_UART1_FIFO)
165 port map (rstn, clkm, apbi, apbo(1), ahbuarti, apbuarto);
192 port map (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
166 apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd;
193 apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd;
167 apbuarti.ctsn <= '0';
194 apbuarti.ctsn <= '0';
168 end generate;
195 end generate;
169 noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
196 noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
170
197
171
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172
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173
200
174 --div0: Clk_divider
201 --div0: Clk_divider
175 -- generic map( 100000000,1)
202 -- generic map( 100000000,1)
176 -- Port map( clkm,rstn,LED(2));
203 -- Port map( clkm,rstn,LED(2));
177
204
178 LED(2) <= led2int;
205 LED(2) <= led2int;
179
206
180 process(clkm,rstn)
207 process(clkm,rstn)
181 begin
208 begin
182 if rstn = '0' then
209 if rstn = '0' then
183 led2int <= '0';
210 led2int <= '0';
184 elsif clkm'event and clkm='1' then
211 elsif clkm'event and clkm='1' then
185 led2int <= not led2int;
212 led2int <= not led2int;
186 end if;
213 end if;
187 end process;
214 end process;
188
215
189
216
190
217
191
218
192 mctrl0 : mctrl generic map (srbanks => 4, sden => 1)
219 sdc : sdctrl
193 port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wprot, sdo);
220 generic map (hindex => 0, haddr => 16#600#, hmask => 16#F00#,ioaddr => 1, pwron => 0,
221 invclk => 0,sdbits =>32)
222 port map (rstn, clkm, ahbsi, ahbso(0), sdi, sdo);
194
223
195 -- memory controller inputs not used in this configuration
224
196 memi.brdyn <= '1'; memi.bexcn <= '1'; memi.wrn <= "1111";
225
226 --Alternative data pad instantiation with vectored bdrive
227 sd_pad : iopadvv generic map (tech=> padtech,width => 32)
228 port map (
229 data(31 downto 0),
230 sdo.data(31 downto 0),
231 sdo.vbdrive(31 downto 0),
232 sdi.data(31 downto 0));
197
233
198 memi.sd <= Data;
234
199 -- prom width at reset
200 memi.bwidth <= "10";
201 -- I/O pads driving data memory bus data signals
202 datapads : for i in 0 to 3 generate
203 data_pad : iopadv generic map (width => 8)
204 port map (
205 pad => data(31-i*8 downto 24-i*8),
206 o => memi.data(31-i*8 downto 24-i*8),
207 en => memo.bdrive(i),
208 i => memo.data(31-i*8 downto 24-i*8)
209 );
210 end generate;
211 -- connect memory controller outputs to entity output signals
235 -- connect memory controller outputs to entity output signals
212 Address <= memo.sa(11 downto 0);
236 Address <= sdo.address(13 downto 2);
213 sdba <= memo.sa(13 downto 12);
237 sdba <= sdo.address(16 downto 15);
214 writen <= memo.writen; read <= memo.read; iosn <= memo.iosn;
238 sdcke <= sdo.sdcke(0);
215 sdcke <= sdo.sdcke;
216 sdwen <= sdo.sdwen;
239 sdwen <= sdo.sdwen;
217 sdcsn <= sdo.sdcsn;
240 sdcsn <= sdo.sdcsn(0);
218 sdrasn <= sdo.rasn;
241 sdrasn <= sdo.rasn;
219 sdcasn <= sdo.casn;
242 sdcasn <= sdo.casn;
220 sddqm <= sdo.dqm(3 downto 0);
243 sddqm <= sdo.dqm(3 downto 0);
221
244 --sdi.data(31 downto 0) <= data(31 downto 0);
222 end;
223
245
224
246
225
247
226 end rtl;
248 end rtl;
227
249
228
250
229
251
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@@ -1,46 +1,49
1 include .config
1 include .config
2
2
3 #GRLIB=$(GRLIB)
3 #GRLIB=$(GRLIB)
4 TOP=BeagleSynth
4 TOP=BeagleSynth
5 BOARD=BeagleSynth
5 BOARD=BeagleSynth
6 #BOARD=SP601
6 #BOARD=SP601
7 include ../../boards/$(BOARD)/Makefile.inc
7 include ../../boards/$(BOARD)/Makefile.inc
8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
9 #UCF=$(GRLIB)/boards/$(BOARD)/ICI3.ucf
9 #UCF=$(GRLIB)/boards/$(BOARD)/ICI3.ucf
10 UCF=../../boards/$(BOARD)/default.ucf
10 UCF=../../boards/$(BOARD)/default.ucf
11 QSF=../../boards/$(BOARD)/$(TOP).qsf
11 QSF=../../boards/$(BOARD)/$(TOP).qsf
12 EFFORT=high
12 EFFORT=high
13 ISEMAPOPT="-timing"
13 ISEMAPOPT="-timing"
14 XSTOPT=""
14 XSTOPT=""
15 SYNPOPT="set_option -maxfan 100; set_option -pipe 1; set_option -retiming 1; set_option -write_apr_constraint 0"
15 SYNPOPT="set_option -maxfan 100; set_option -pipe 1; set_option -retiming 1; set_option -write_apr_constraint 0"
16 VHDLOPTSYNFILES=
16 VHDLOPTSYNFILES=
17
17
18
18
19 VHDLSYNFILES= \
19 VHDLSYNFILES= \
20 config.vhd BeagleSynth.vhd
20 config.vhd BeagleSynth.vhd
21 #VHDLSIMFILES=testbench.vhd
21 #VHDLSIMFILES=testbench.vhd
22 #SIMTOP=testbench
22 #SIMTOP=testbench
23 #SDCFILE=$(GRLIB)/boards/$(BOARD)/default.sdc
23 #SDCFILE=$(GRLIB)/boards/$(BOARD)/default.sdc
24 SDCFILE=default.sdc
24 SDCFILE=default.sdc
25 BITGEN=../../boards/$(BOARD)/default.ut
25 BITGEN=../../boards/$(BOARD)/default.ut
26 CLEAN=soft-clean
26 CLEAN=soft-clean
27 VCOMOPT=-explicit
27 VCOMOPT=-explicit
28 TECHLIBS = secureip unisim
28 TECHLIBS = secureip unisim
29
29
30 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
30 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
31 tmtc openchip cypress ihp gleichmann gsi fmf spansion
31 tmtc openchip cypress ihp gleichmann gsi fmf spansion
32 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan pci leon3ft ambatest \
32 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan pci leon3ft ambatest \
33 leon4 leon4b64 l2cache gr1553b iommu haps ascs slink coremp7 pwm \
33 leon4 leon4b64 l2cache gr1553b iommu haps ascs slink coremp7 pwm \
34 ac97 hcan usb
34 ac97 hcan usb
35 DIRADD =
35 DIRADD =
36 FILEADD =
36 FILEADD =
37 FILESKIP = grcan.vhd ddr2.v mobile_ddr.v
37 FILESKIP = grcan.vhd ddr2.v mobile_ddr.v
38
38
39 include $(GRLIB)/bin/Makefile
39 include $(GRLIB)/bin/Makefile
40 include $(GRLIB)/software/leon3/Makefile
40 include $(GRLIB)/software/leon3/Makefile
41
41
42
42
43 ################## project specific targets ##########################
43 ################## project specific targets ##########################
44
44
45 flash:
45 flash:
46 xc3sprog -c ftdi -p 1 BeagleSynth.bit
46 xc3sprog -c ftdi -p 1 BeagleSynth.bit
47
48 ram:
49 xc3sprog -c ftdi -p 0 BeagleSynth.bit
Show file before | Show file after | Hide comments
@@ -1,77 +1,77
1
1
2
2
3
3
4 -----------------------------------------------------------------------------
4 -----------------------------------------------------------------------------
5 -- LEON3 Demonstration design test bench configuration
5 -- LEON3 Demonstration design test bench configuration
6 -- Copyright (C) 2009 Aeroflex Gaisler
6 -- Copyright (C) 2009 Aeroflex Gaisler
7 ------------------------------------------------------------------------------
7 ------------------------------------------------------------------------------
8
8
9
9
10 library techmap;
10 library techmap;
11 use techmap.gencomp.all;
11 use techmap.gencomp.all;
12 LIBRARY IEEE;
12 LIBRARY IEEE;
13 USE IEEE.numeric_std.ALL;
13 USE IEEE.numeric_std.ALL;
14 USE IEEE.std_logic_1164.ALL;
14 USE IEEE.std_logic_1164.ALL;
15
15
16
16
17 package config is
17 package config is
18 -- Technology and synthesis options
18 -- Technology and synthesis options
19 constant CFG_FABTECH : integer := spartan6;
19 constant CFG_FABTECH : integer := spartan6;
20 constant CFG_MEMTECH : integer := spartan6;
20 constant CFG_MEMTECH : integer := spartan6;
21 constant CFG_PADTECH : integer := spartan6;
21 constant CFG_PADTECH : integer := spartan6;
22
22
23 -- Clock generator
23 -- Clock generator
24 constant CFG_CLKTECH : integer := spartan6;
24 constant CFG_CLKTECH : integer := spartan6;
25 constant CFG_CLKMUL : integer := (2);
25 constant CFG_CLKMUL : integer := (2);
26 constant CFG_CLKDIV : integer := (8);
26 constant CFG_CLKDIV : integer := (8);
27 constant CFG_OCLKDIV : integer := (1);
27 constant CFG_OCLKDIV : integer := (1);
28 constant CFG_PCIDLL : integer := 0;
28 constant CFG_PCIDLL : integer := 0;
29 constant CFG_PCISYSCLK: integer := 0;
29 constant CFG_PCISYSCLK: integer := 0;
30 constant CFG_CLK_NOFB : integer := 0;
30 constant CFG_CLK_NOFB : integer := 0;
31
31
32 -- AMBA settings
32 -- AMBA settings
33 constant CFG_DEFMST : integer := (0);
33 constant CFG_DEFMST : integer := (0);
34 constant CFG_RROBIN : integer := 1;
34 constant CFG_RROBIN : integer := 1;
35 constant CFG_SPLIT : integer := 0;
35 constant CFG_SPLIT : integer := 0;
36 constant CFG_AHBIO : integer := 16#FFF#;
36 constant CFG_AHBIO : integer := 16#FFF#;
37 constant CFG_APBADDR : integer := 16#800#;
37 constant CFG_APBADDR : integer := 16#800#;
38 constant CFG_AHB_MON : integer := 0;
38 constant CFG_AHB_MON : integer := 0;
39 constant CFG_AHB_MONERR : integer := 0;
39 constant CFG_AHB_MONERR : integer := 0;
40 constant CFG_AHB_MONWAR : integer := 0;
40 constant CFG_AHB_MONWAR : integer := 0;
41
41
42 -- LEON3 processor core
42 -- LEON3 processor core
43 constant CFG_LEON3 : integer := 0;
43 constant CFG_LEON3 : integer := 0;
44 constant CFG_NCPU : integer := (0);
44 constant CFG_NCPU : integer := (0);
45
45
46 -- DSU UART
46 -- DSU UART
47 constant CFG_AHB_UART : integer := 1;
47 constant CFG_AHB_UART : integer := 1;
48
48
49 -- JTAG based DSU interface
49 -- JTAG based DSU interface
50 constant CFG_AHB_JTAG : integer := 0;
50 constant CFG_AHB_JTAG : integer := 0;
51
51
52 -- UART 1
52 -- UART 1
53 constant CFG_UART1_ENABLE : integer := 1;
53 constant CFG_UART1_ENABLE : integer := 1;
54 constant CFG_UART1_FIFO : integer := 1;
54 constant CFG_UART1_FIFO : integer := 1;
55
55
56 -- GRLIB debugging
56 -- GRLIB debugging
57 constant CFG_DUART : integer := 0;
57 constant CFG_DUART : integer := 0;
58
58
59 -- LEON2 memory controller
59 -- LEON2 memory controller
60 constant CFG_MCTRL_LEON2 : integer := 1;
60 constant CFG_MCTRL_LEON2 : integer := 1;
61 constant CFG_MCTRL_RAM8BIT : integer := 0;
61 constant CFG_MCTRL_RAM8BIT : integer := 1;
62 constant CFG_MCTRL_RAM16BIT : integer := 0;
62 constant CFG_MCTRL_RAM16BIT : integer := 0;
63 constant CFG_MCTRL_5CS : integer := 0;
63 constant CFG_MCTRL_5CS : integer := 0;
64 constant CFG_MCTRL_SDEN : integer := 0;
64 constant CFG_MCTRL_SDEN : integer := 1;
65 constant CFG_MCTRL_SEPBUS : integer := 0;
65 constant CFG_MCTRL_SEPBUS : integer := 0;
66 constant CFG_MCTRL_INVCLK : integer := 0;
66 constant CFG_MCTRL_INVCLK : integer := 0;
67 constant CFG_MCTRL_SD64 : integer := 0;
67 constant CFG_MCTRL_SD64 : integer := 0;
68 constant CFG_MCTRL_PAGE : integer := 0 + 0;
68 constant CFG_MCTRL_PAGE : integer := 1 + 0;
69
69
70 -- Gaisler Ethernet core
70 -- Gaisler Ethernet core
71 constant CFG_GRETH : integer := 0;
71 constant CFG_GRETH : integer := 0;
72
72
73 -- CAN 2.0 interface
73 -- CAN 2.0 interface
74 constant CFG_CAN : integer := 0;
74 constant CFG_CAN : integer := 0;
75
75
76
76
77 end;
77 end;
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