# HG changeset patch # User Jeandet Alexis # Date 2013-12-04 22:21:47 # Node ID 9504f3e37fb4a3c7925f385ee39a468080669b5c # Parent 9bf9890b50e7de97b2366e19fc25ad0730787624 Partially Working BeagleSynth base design, SDRAM still f****** buggy. diff --git a/boards/BeagleSynth/default.ucf b/boards/BeagleSynth/default.ucf --- a/boards/BeagleSynth/default.ucf +++ b/boards/BeagleSynth/default.ucf @@ -1,28 +1,109 @@ NET "CLK" CLOCK_DEDICATED_ROUTE = FALSE; -NET "CLK" LOC = "K20"; +NET "CLK" LOC = "K20"| slew=FAST | IOSTANDARD=LVTTL; +#NET "CLKM" TNM_NET = "clkm_net"; +#TIMESPEC "TS_clkm_net" = PERIOD "clkm_net" 10 ns HIGH 50%; NET "RESET" CLOCK_DEDICATED_ROUTE = FALSE; -NET "RESET" LOC = "AB11"; +NET "RESET" LOC = "AB11" | slew=FAST | IOSTANDARD=LVTTL; -NET "DAC_nCLR" LOC = "R11"; -NET "DAC_nCS" LOC = "T12"; -NET "CAL_IN_SCK" LOC = "R13"; -NET "DAC_SDI(0)" LOC = "P5"; -NET "DAC_SDI(1)" LOC = "M5"; -NET "DAC_SDI(2)" LOC = "C8"; -NET "DAC_SDI(3)" LOC = "M6"; -NET "DAC_SDI(4)" LOC = "K22"; -NET "DAC_SDI(5)" LOC = "L22"; -NET "DAC_SDI(6)" LOC = "G19"; -NET "DAC_SDI(7)" LOC = "F20"; +NET "DAC_nCLR" LOC = "R11" | IOSTANDARD=LVTTL; +NET "DAC_nCS" LOC = "T12" | IOSTANDARD=LVTTL; +NET "CAL_IN_SCK" LOC = "R13" | IOSTANDARD=LVTTL; +NET "DAC_SDI(0)" LOC = "P5" | IOSTANDARD=LVTTL; +NET "DAC_SDI(1)" LOC = "M5" | IOSTANDARD=LVTTL; +NET "DAC_SDI(2)" LOC = "C8" | IOSTANDARD=LVTTL; +NET "DAC_SDI(3)" LOC = "M6" | IOSTANDARD=LVTTL; +NET "DAC_SDI(4)" LOC = "K22" | IOSTANDARD=LVTTL; +NET "DAC_SDI(5)" LOC = "L22" | IOSTANDARD=LVTTL; +NET "DAC_SDI(6)" LOC = "G19" | IOSTANDARD=LVTTL; +NET "DAC_SDI(7)" LOC = "F20" | IOSTANDARD=LVTTL; -NET "TDX" LOC = "V22"; -NET "RXD" LOC = "U22"; -NET "LED(0)" LOC = "AB9"; -NET "LED(1)" LOC = "AB8"; -NET "LED(2)" LOC = "AA8"; +NET "TXD" LOC = "V22"| slew=FAST | IOSTANDARD=LVTTL; +NET "RXD" LOC = "U22"| slew=FAST | IOSTANDARD=LVTTL; +NET "LED(0)" LOC = "AB9"| slew=FAST | IOSTANDARD=LVTTL; +NET "LED(1)" LOC = "AB8"| slew=FAST | IOSTANDARD=LVTTL; +NET "LED(2)" LOC = "AA8"| slew=FAST | IOSTANDARD=LVTTL; -NET "urxd1" LOC = "D3"; # Unused PIN -NET "utxd1" LOC = "C4"; # Unused PIN \ No newline at end of file +NET "urxd1" LOC = "D3" | IOSTANDARD=LVTTL; # Unused PIN +NET "utxd1" LOC = "C4" | IOSTANDARD=LVTTL; # Unused PIN + +NET "sdcke" LOC = "B6" | slew=FAST | IOSTANDARD=LVTTL; # clk en +NET "sdcsn" LOC = "G20"| slew=FAST | IOSTANDARD=LVTTL; # chip sel +NET "sdwen" LOC = "D14"| slew=FAST | IOSTANDARD=LVTTL; # write en +NET "sdrasn" LOC = "H19"| slew=FAST | IOSTANDARD=LVTTL; # row addr stb +NET "sdcasn" LOC = "C14"| slew=FAST | IOSTANDARD=LVTTL; # col addr stb + +NET "sddqm(3)" LOC = "A5" | slew=FAST | IOSTANDARD=LVTTL; # data i/o mask +NET "sddqm(2)" LOC = "D21"| slew=FAST | IOSTANDARD=LVTTL; # data i/o mask +NET "sddqm(1)" LOC = "C7" | slew=FAST | IOSTANDARD=LVTTL; # data i/o mask +NET "sddqm(0)" LOC = "D15"| slew=FAST | IOSTANDARD=LVTTL; # data i/o mask + +NET "sdclk" CLOCK_DEDICATED_ROUTE = FALSE; +NET "sdclk" LOC = "A6" | slew=FAST | IOSTANDARD=LVTTL; # sdram clk output +NET "sdba(1)" LOC = "J20"| slew=FAST | IOSTANDARD=LVTTL; # bank select address +NET "sdba(0)" LOC = "G16"| slew=FAST | IOSTANDARD=LVTTL; # bank select address + +NET "Address(11)" LOC = "H8"| slew=FAST | IOSTANDARD=LVTTL; # sdram address +NET "Address(10)" LOC = "G7"| slew=FAST | IOSTANDARD=LVTTL; # sdram address +NET "Address(9)" LOC = "K7"| slew=FAST | IOSTANDARD=LVTTL; # sdram address +NET "Address(8)" LOC = "H6"| slew=FAST | IOSTANDARD=LVTTL; # sdram address +NET "Address(7)" LOC = "H5"| slew=FAST | IOSTANDARD=LVTTL; # sdram address +NET "Address(6)" LOC = "K8"| slew=FAST | IOSTANDARD=LVTTL; # sdram address +NET "Address(5)" LOC = "G4"| slew=FAST | IOSTANDARD=LVTTL; # sdram address +NET "Address(4)" LOC = "H3"| slew=FAST | IOSTANDARD=LVTTL; # sdram address +NET "Address(3)" LOC = "D2"| slew=FAST | IOSTANDARD=LVTTL; # sdram address +NET "Address(2)" LOC = "B3"| slew=FAST | IOSTANDARD=LVTTL; # sdram address +NET "Address(1)" LOC = "A2"| slew=FAST | IOSTANDARD=LVTTL; # sdram address +NET "Address(0)" LOC = "C22"| slew=FAST | IOSTANDARD=LVTTL; # sdram address + +NET "Data(31)" LOC = "C5" | slew=FAST | IOSTANDARD=LVTTL; # sdram data +NET "Data(30)" LOC = "A4" | slew=FAST | IOSTANDARD=LVTTL; # sdram data +NET "Data(29)" LOC = "A3" | slew=FAST | IOSTANDARD=LVTTL; # sdram data +NET "Data(28)" LOC = "B2" | slew=FAST | IOSTANDARD=LVTTL; # sdram data +NET "Data(27)" LOC = "B1" | slew=FAST | IOSTANDARD=LVTTL; # sdram data +NET "Data(26)" LOC = "C1" | slew=FAST | IOSTANDARD=LVTTL; # sdram data +NET "Data(25)" LOC = "D1" | slew=FAST | IOSTANDARD=LVTTL; # sdram data +NET "Data(24)" LOC = "E1" | slew=FAST | IOSTANDARD=LVTTL; # sdram data +NET "Data(23)" LOC = "J22"| slew=FAST | IOSTANDARD=LVTTL; # sdram data +NET "Data(22)" LOC = "H22"| slew=FAST | IOSTANDARD=LVTTL; # sdram data +NET "Data(21)" LOC = "H21"| slew=FAST | IOSTANDARD=LVTTL; # sdram data +NET "Data(20)" LOC = "G22"| slew=FAST | IOSTANDARD=LVTTL; # sdram data +NET "Data(19)" LOC = "F22"| slew=FAST | IOSTANDARD=LVTTL; # sdram data +NET "Data(18)" LOC = "F21"| slew=FAST | IOSTANDARD=LVTTL; # sdram data +NET "Data(17)" LOC = "E22"| slew=FAST | IOSTANDARD=LVTTL; # sdram data +NET "Data(16)" LOC = "D22"| slew=FAST | IOSTANDARD=LVTTL; # sdram data +NET "Data(15)" LOC = "A7" | slew=FAST | IOSTANDARD=LVTTL; # sdram data +NET "Data(14)" LOC = "B8" | slew=FAST | IOSTANDARD=LVTTL; # sdram data +NET "Data(13)" LOC = "A8" | slew=FAST | IOSTANDARD=LVTTL; # sdram data +NET "Data(12)" LOC = "C9" | slew=FAST | IOSTANDARD=LVTTL; # sdram data +NET "Data(11)" LOC = "A9" | slew=FAST | IOSTANDARD=LVTTL; # sdram data +NET "Data(10)" LOC = "B10"| slew=FAST | IOSTANDARD=LVTTL; # sdram data +NET "Data(9)" LOC = "A10"| slew=FAST | IOSTANDARD=LVTTL; # sdram data +NET "Data(8)" LOC = "C11"| slew=FAST | IOSTANDARD=LVTTL; # sdram data +NET "Data(7)" LOC = "A13"| slew=FAST | IOSTANDARD=LVTTL; # sdram data +NET "Data(6)" LOC = "C13"| slew=FAST | IOSTANDARD=LVTTL; # sdram data +NET "Data(5)" LOC = "B22"| slew=FAST | IOSTANDARD=LVTTL; # sdram data +NET "Data(4)" LOC = "B21"| slew=FAST | IOSTANDARD=LVTTL; # sdram data +NET "Data(3)" LOC = "B20"| slew=FAST | IOSTANDARD=LVTTL; # sdram data +NET "Data(2)" LOC = "A20"| slew=FAST | IOSTANDARD=LVTTL; # sdram data +NET "Data(1)" LOC = "B18"| slew=FAST | IOSTANDARD=LVTTL; # sdram data +NET "Data(0)" LOC = "A18"| slew=FAST | IOSTANDARD=LVTTL; # sdram data + + + + + + + + + + + + + + + + + diff --git a/designs/BeagleSynth/BeagleSynth.vhd b/designs/BeagleSynth/BeagleSynth.vhd --- a/designs/BeagleSynth/BeagleSynth.vhd +++ b/designs/BeagleSynth/BeagleSynth.vhd @@ -12,6 +12,8 @@ use gaisler.memctrl.all; use gaisler.leon3.all; use gaisler.uart.all; use gaisler.misc.all; +library esa; +use esa.memoryctrl.all; --use gaisler.sim.all; library lpp; use lpp.lpp_ad_conv.all; @@ -19,6 +21,9 @@ use lpp.lpp_amba.all; use lpp.apb_devices_list.all; use lpp.general_purpose.all; +Library UNISIM; +use UNISIM.vcomponents.all; + use work.config.all; --================================================================== @@ -54,14 +59,14 @@ entity BeagleSynth is ---- design from GRLIB, the IS42S32400E is similar to ---- MT48LC4M32B2. -------------------------------------------------------- - sdcke : out std_logic_vector ( 1 downto 0); -- clk en - sdcsn : out std_logic_vector ( 1 downto 0); -- chip sel + sdcke : out std_logic; -- clk en + sdcsn : out std_logic; -- chip sel sdwen : out std_logic; -- write en sdrasn : out std_logic; -- row addr stb sdcasn : out std_logic; -- col addr stb sddqm : out std_logic_vector (3 downto 0); -- data i/o mask sdclk : out std_logic; -- sdram clk output - sdba : out std_logic_vector (3 downto 0); -- bank select address + sdba : out std_logic_vector (1 downto 0); -- bank select address Address : out std_logic_vector(11 downto 0); -- sdram address Data : inout std_logic_vector(31 downto 0) -- optional sdram data ); @@ -78,9 +83,11 @@ signal clk2x : std_ulogic; signal lclk : std_ulogic; signal clkm : std_ulogic; signal rstn : std_ulogic; +signal rst : std_ulogic; signal rstraw : std_ulogic; signal pciclk : std_ulogic; signal sdclkl : std_ulogic; +signal sdclkl_DDR2 : std_ulogic; signal cgi : clkgen_in_type; signal cgo : clkgen_out_type; @@ -93,9 +100,8 @@ signal ahbmi : ahb_mst_in_type; signal ahbmo : ahb_mst_out_vector := (others => ahbm_none); --- MEM CTRLR -signal memi : memory_in_type; -signal memo : memory_out_type; -signal sdo : sdram_out_type; +signal sdi : sdctrl_in_type; +signal sdo : sdctrl_out_type; --UART signal ahbuarti : uart_in_type; @@ -112,15 +118,36 @@ DAC_nCS <= '1'; CAL_IN_SCK <= '1'; DAC_SDI <= (others =>'1'); - rst0 : rstgen port map (reset, clkm, cgo.clklock, rstn, rstraw); +resetn_pad : inpad generic map (tech => padtech) port map (reset, rst); + rst0 : rstgen port map (rst, lclk, '1', rstn, rstraw); + --rstn <= reset; + --lclk <= clk; + clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk, lclk); - lclk <= clk; + cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; + clkgen0 : clkgen -- clock generator + generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, CFG_CLK_NOFB, 0, 0, 0, boardfreq) + port map (lclk, lclk, clkm, open, open, sdclkl, open, cgi, cgo,open,open); + +-- sdclk_pad : outpad generic map (tech => padtech) port map (sdclk, sdclkl_DDR2); +--sdclk <= sdclkl; +sdclk <= sdclkl_DDR2; - clkgen0 : clkgen -- clock generatorsa - generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, - CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV) - port map (lclk, lclk, clkm, open, clk2x, sdclkl, pciclk, cgi, cgo); - +ODDR2_inst : ODDR2 + generic map( + DDR_ALIGNMENT => "C0", -- Sets output alignment to "NONE", "C0", "C1" + INIT => '0', -- Sets initial state of the Q output to '0' or '1' + SRTYPE => "ASYNC") -- Specifies "SYNC" or "ASYNC" set/reset + port map ( + Q => sdclkl_DDR2, -- 1-bit output data + C0 => sdclkl, -- 1-bit clock input + C1 => not sdclkl, -- 1-bit clock input + CE => '1', -- 1-bit clock enable input + D0 => '1', -- 1-bit data input (associated with C0) + D1 => '0', -- 1-bit data input (associated with C1) + R => '0', -- 1-bit reset input + S => '0' -- 1-bit set input + ); ---------------------------------------------------------------------- --- AHB CONTROLLER ------------------------------------------------- @@ -142,7 +169,7 @@ DAC_SDI <= (others =>'1'); port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU)); ahbuarti.rxd <= RXD; TXD <= ahbuarto.txd; - led(0) <= not ahbuarti.rxd; led(1) <= not ahbuarto.txd; + led(0) <= ahbuarti.rxd; led(1) <= ahbuarto.txd; end generate; nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate; @@ -162,7 +189,7 @@ DAC_SDI <= (others =>'1'); uart1 : apbuart -- UART 1 generic map (pindex => 1, paddr => 1, pirq => 2, console => CFG_DUART, fifosize => CFG_UART1_FIFO) - port map (rstn, clkm, apbi, apbo(1), ahbuarti, apbuarto); + port map (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto); apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd; apbuarti.ctsn <= '0'; end generate; @@ -189,37 +216,32 @@ end process; -mctrl0 : mctrl generic map (srbanks => 4, sden => 1) - port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wprot, sdo); +sdc : sdctrl + generic map (hindex => 0, haddr => 16#600#, hmask => 16#F00#,ioaddr => 1, pwron => 0, + invclk => 0,sdbits =>32) + port map (rstn, clkm, ahbsi, ahbso(0), sdi, sdo); --- memory controller inputs not used in this configuration -memi.brdyn <= '1'; memi.bexcn <= '1'; memi.wrn <= "1111"; + + +--Alternative data pad instantiation with vectored bdrive +sd_pad : iopadvv generic map (tech=> padtech,width => 32) +port map ( + data(31 downto 0), + sdo.data(31 downto 0), + sdo.vbdrive(31 downto 0), + sdi.data(31 downto 0)); -memi.sd <= Data; --- prom width at reset -memi.bwidth <= "10"; --- I/O pads driving data memory bus data signals -datapads : for i in 0 to 3 generate - data_pad : iopadv generic map (width => 8) - port map ( - pad => data(31-i*8 downto 24-i*8), - o => memi.data(31-i*8 downto 24-i*8), - en => memo.bdrive(i), - i => memo.data(31-i*8 downto 24-i*8) - ); -end generate; + -- connect memory controller outputs to entity output signals -Address <= memo.sa(11 downto 0); -sdba <= memo.sa(13 downto 12); -writen <= memo.writen; read <= memo.read; iosn <= memo.iosn; -sdcke <= sdo.sdcke; +Address <= sdo.address(13 downto 2); +sdba <= sdo.address(16 downto 15); +sdcke <= sdo.sdcke(0); sdwen <= sdo.sdwen; -sdcsn <= sdo.sdcsn; +sdcsn <= sdo.sdcsn(0); sdrasn <= sdo.rasn; sdcasn <= sdo.casn; sddqm <= sdo.dqm(3 downto 0); - -end; +--sdi.data(31 downto 0) <= data(31 downto 0); diff --git a/designs/BeagleSynth/Makefile b/designs/BeagleSynth/Makefile --- a/designs/BeagleSynth/Makefile +++ b/designs/BeagleSynth/Makefile @@ -44,3 +44,6 @@ include $(GRLIB)/software/leon3/Makefile flash: xc3sprog -c ftdi -p 1 BeagleSynth.bit + +ram: + xc3sprog -c ftdi -p 0 BeagleSynth.bit diff --git a/designs/BeagleSynth/config.vhd b/designs/BeagleSynth/config.vhd --- a/designs/BeagleSynth/config.vhd +++ b/designs/BeagleSynth/config.vhd @@ -58,14 +58,14 @@ package config is -- LEON2 memory controller constant CFG_MCTRL_LEON2 : integer := 1; - constant CFG_MCTRL_RAM8BIT : integer := 0; + constant CFG_MCTRL_RAM8BIT : integer := 1; constant CFG_MCTRL_RAM16BIT : integer := 0; constant CFG_MCTRL_5CS : integer := 0; - constant CFG_MCTRL_SDEN : integer := 0; + constant CFG_MCTRL_SDEN : integer := 1; constant CFG_MCTRL_SEPBUS : integer := 0; constant CFG_MCTRL_INVCLK : integer := 0; constant CFG_MCTRL_SD64 : integer := 0; - constant CFG_MCTRL_PAGE : integer := 0 + 0; + constant CFG_MCTRL_PAGE : integer := 1 + 0; -- Gaisler Ethernet core constant CFG_GRETH : integer := 0;