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library ieee;
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use ieee.std_logic_1164.all;
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use IEEE.numeric_std.all;
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library grlib, techmap;
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use grlib.amba.all;
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use grlib.amba.all;
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use grlib.stdlib.all;
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use techmap.gencomp.all;
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use techmap.allclkgen.all;
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library gaisler;
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use gaisler.memctrl.all;
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use gaisler.leon3.all;
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use gaisler.uart.all;
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use gaisler.misc.all;
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--use gaisler.sim.all;
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library lpp;
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use lpp.lpp_ad_conv.all;
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use lpp.lpp_amba.all;
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use lpp.apb_devices_list.all;
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use lpp.general_purpose.all;
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use work.config.all;
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--==================================================================
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--
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--
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-- FPGA FREQ = 100MHz
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--
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--
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--==================================================================
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entity BeagleSynth is
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generic (
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fabtech : integer := CFG_FABTECH;
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memtech : integer := CFG_MEMTECH;
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padtech : integer := CFG_PADTECH;
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clktech : integer := CFG_CLKTECH
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);
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port (
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reset : in std_ulogic;
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clk : in std_ulogic;
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DAC_nCLR : out std_ulogic;
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DAC_nCS : out std_ulogic;
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CAL_IN_SCK : out std_ulogic;
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DAC_SDI : out std_ulogic_vector(7 downto 0);
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TXD : out std_ulogic;
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RXD : in std_ulogic;
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urxd1 : in std_ulogic;
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utxd1 : out std_ulogic;
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LED : out std_ulogic_vector(2 downto 0);
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--------------------------------------------------------
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---- SDRAM
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---- For SDRAM config have a look on leon3-altera-ep1c20
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---- design from GRLIB, the IS42S32400E is similar to
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---- MT48LC4M32B2.
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--------------------------------------------------------
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sdcke : out std_logic_vector ( 1 downto 0); -- clk en
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sdcsn : out std_logic_vector ( 1 downto 0); -- chip sel
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sdwen : out std_logic; -- write en
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sdrasn : out std_logic; -- row addr stb
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sdcasn : out std_logic; -- col addr stb
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sddqm : out std_logic_vector (3 downto 0); -- data i/o mask
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sdclk : out std_logic; -- sdram clk output
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sdba : out std_logic_vector (3 downto 0); -- bank select address
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Address : out std_logic_vector(11 downto 0); -- sdram address
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Data : inout std_logic_vector(31 downto 0) -- optional sdram data
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);
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end;
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architecture rtl of BeagleSynth is
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constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
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CFG_GRETH+CFG_AHB_JTAG;
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constant maxahbm : integer := maxahbmsp;
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constant IOAEN : integer := CFG_CAN;
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constant boardfreq : integer := 100000;
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signal clk2x : std_ulogic;
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signal lclk : std_ulogic;
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signal clkm : std_ulogic;
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signal rstn : std_ulogic;
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signal rstraw : std_ulogic;
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signal pciclk : std_ulogic;
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signal sdclkl : std_ulogic;
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signal cgi : clkgen_in_type;
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signal cgo : clkgen_out_type;
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--- AHB / APB
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signal apbi : apb_slv_in_type;
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signal apbo : apb_slv_out_vector := (others => apb_none);
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signal ahbsi : ahb_slv_in_type;
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signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
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signal ahbmi : ahb_mst_in_type;
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signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
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--- MEM CTRLR
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signal memi : memory_in_type;
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signal memo : memory_out_type;
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signal sdo : sdram_out_type;
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--UART
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signal ahbuarti : uart_in_type;
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signal ahbuarto : uart_out_type;
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signal apbuarti : uart_in_type;
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signal apbuarto : uart_out_type;
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signal led2int : std_logic;
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begin
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DAC_nCLR <= '1';
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DAC_nCS <= '1';
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CAL_IN_SCK <= '1';
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DAC_SDI <= (others =>'1');
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rst0 : rstgen port map (reset, clkm, cgo.clklock, rstn, rstraw);
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lclk <= clk;
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clkgen0 : clkgen -- clock generatorsa
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generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
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CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV)
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port map (lclk, lclk, clkm, open, clk2x, sdclkl, pciclk, cgi, cgo);
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----------------------------------------------------------------------
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--- AHB CONTROLLER -------------------------------------------------
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----------------------------------------------------------------------
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ahb0 : ahbctrl -- AHB arbiter/multiplexer
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generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
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rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
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ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
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port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
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----------------------------------------------------------------------
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--- AHB UART -------------------------------------------------------
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----------------------------------------------------------------------
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dcomgen : if CFG_AHB_UART = 1 generate
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dcom0: ahbuart -- Debug UART
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generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
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port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
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ahbuarti.rxd <= RXD;
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TXD <= ahbuarto.txd;
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led(0) <= not ahbuarti.rxd; led(1) <= not ahbuarto.txd;
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end generate;
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nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
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----------------------------------------------------------------------
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--- APB Bridge -----------------------------------------------------
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----------------------------------------------------------------------
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apb0 : apbctrl -- AHB/APB bridge
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generic map (hindex => 1, haddr => CFG_APBADDR)
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port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
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----------------------------------------------------------------------
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--- APB UART -------------------------------------------------------
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----------------------------------------------------------------------
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ua1 : if CFG_UART1_ENABLE /= 0 generate
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uart1 : apbuart -- UART 1
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generic map (pindex => 1, paddr => 1, pirq => 2, console => CFG_DUART,
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fifosize => CFG_UART1_FIFO)
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port map (rstn, clkm, apbi, apbo(1), ahbuarti, apbuarto);
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apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd;
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apbuarti.ctsn <= '0';
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end generate;
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noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
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--div0: Clk_divider
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-- generic map( 100000000,1)
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-- Port map( clkm,rstn,LED(2));
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LED(2) <= led2int;
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process(clkm,rstn)
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begin
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if rstn = '0' then
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led2int <= '0';
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elsif clkm'event and clkm='1' then
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led2int <= not led2int;
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end if;
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end process;
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mctrl0 : mctrl generic map (srbanks => 4, sden => 1)
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port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wprot, sdo);
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-- memory controller inputs not used in this configuration
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memi.brdyn <= '1'; memi.bexcn <= '1'; memi.wrn <= "1111";
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memi.sd <= Data;
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-- prom width at reset
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memi.bwidth <= "10";
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-- I/O pads driving data memory bus data signals
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datapads : for i in 0 to 3 generate
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data_pad : iopadv generic map (width => 8)
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port map (
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pad => data(31-i*8 downto 24-i*8),
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o => memi.data(31-i*8 downto 24-i*8),
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en => memo.bdrive(i),
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i => memo.data(31-i*8 downto 24-i*8)
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);
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end generate;
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-- connect memory controller outputs to entity output signals
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Address <= memo.sa(11 downto 0);
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sdba <= memo.sa(13 downto 12);
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writen <= memo.writen; read <= memo.read; iosn <= memo.iosn;
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sdcke <= sdo.sdcke;
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sdwen <= sdo.sdwen;
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sdcsn <= sdo.sdcsn;
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sdrasn <= sdo.rasn;
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sdcasn <= sdo.casn;
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sddqm <= sdo.dqm(3 downto 0);
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end;
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end rtl;
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