BeagleSynth.vhd
229 lines
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| text/x-vhdl
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VhdlLexer
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r255 | library ieee; | ||
use ieee.std_logic_1164.all; | ||||
use IEEE.numeric_std.all; | ||||
library grlib, techmap; | ||||
use grlib.amba.all; | ||||
use grlib.amba.all; | ||||
use grlib.stdlib.all; | ||||
use techmap.gencomp.all; | ||||
use techmap.allclkgen.all; | ||||
library gaisler; | ||||
use gaisler.memctrl.all; | ||||
use gaisler.leon3.all; | ||||
use gaisler.uart.all; | ||||
use gaisler.misc.all; | ||||
--use gaisler.sim.all; | ||||
library lpp; | ||||
use lpp.lpp_ad_conv.all; | ||||
use lpp.lpp_amba.all; | ||||
use lpp.apb_devices_list.all; | ||||
use lpp.general_purpose.all; | ||||
use work.config.all; | ||||
--================================================================== | ||||
-- | ||||
-- | ||||
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r263 | -- FPGA FREQ = 100MHz | ||
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r255 | -- | ||
-- | ||||
--================================================================== | ||||
entity BeagleSynth is | ||||
generic ( | ||||
fabtech : integer := CFG_FABTECH; | ||||
memtech : integer := CFG_MEMTECH; | ||||
padtech : integer := CFG_PADTECH; | ||||
clktech : integer := CFG_CLKTECH | ||||
); | ||||
port ( | ||||
reset : in std_ulogic; | ||||
clk : in std_ulogic; | ||||
DAC_nCLR : out std_ulogic; | ||||
DAC_nCS : out std_ulogic; | ||||
CAL_IN_SCK : out std_ulogic; | ||||
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r263 | DAC_SDI : out std_ulogic_vector(7 downto 0); | ||
TXD : out std_ulogic; | ||||
RXD : in std_ulogic; | ||||
urxd1 : in std_ulogic; | ||||
utxd1 : out std_ulogic; | ||||
LED : out std_ulogic_vector(2 downto 0); | ||||
-------------------------------------------------------- | ||||
---- SDRAM | ||||
---- For SDRAM config have a look on leon3-altera-ep1c20 | ||||
---- design from GRLIB, the IS42S32400E is similar to | ||||
---- MT48LC4M32B2. | ||||
-------------------------------------------------------- | ||||
sdcke : out std_logic_vector ( 1 downto 0); -- clk en | ||||
sdcsn : out std_logic_vector ( 1 downto 0); -- chip sel | ||||
sdwen : out std_logic; -- write en | ||||
sdrasn : out std_logic; -- row addr stb | ||||
sdcasn : out std_logic; -- col addr stb | ||||
sddqm : out std_logic_vector (3 downto 0); -- data i/o mask | ||||
sdclk : out std_logic; -- sdram clk output | ||||
sdba : out std_logic_vector (3 downto 0); -- bank select address | ||||
Address : out std_logic_vector(11 downto 0); -- sdram address | ||||
Data : inout std_logic_vector(31 downto 0) -- optional sdram data | ||||
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r255 | ); | ||
end; | ||||
architecture rtl of BeagleSynth is | ||||
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r263 | constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+ | ||
CFG_GRETH+CFG_AHB_JTAG; | ||||
constant maxahbm : integer := maxahbmsp; | ||||
constant IOAEN : integer := CFG_CAN; | ||||
constant boardfreq : integer := 100000; | ||||
signal clk2x : std_ulogic; | ||||
signal lclk : std_ulogic; | ||||
signal clkm : std_ulogic; | ||||
signal rstn : std_ulogic; | ||||
signal rstraw : std_ulogic; | ||||
signal pciclk : std_ulogic; | ||||
signal sdclkl : std_ulogic; | ||||
signal cgi : clkgen_in_type; | ||||
signal cgo : clkgen_out_type; | ||||
--- AHB / APB | ||||
signal apbi : apb_slv_in_type; | ||||
signal apbo : apb_slv_out_vector := (others => apb_none); | ||||
signal ahbsi : ahb_slv_in_type; | ||||
signal ahbso : ahb_slv_out_vector := (others => ahbs_none); | ||||
signal ahbmi : ahb_mst_in_type; | ||||
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none); | ||||
--- MEM CTRLR | ||||
signal memi : memory_in_type; | ||||
signal memo : memory_out_type; | ||||
signal sdo : sdram_out_type; | ||||
--UART | ||||
signal ahbuarti : uart_in_type; | ||||
signal ahbuarto : uart_out_type; | ||||
signal apbuarti : uart_in_type; | ||||
signal apbuarto : uart_out_type; | ||||
signal led2int : std_logic; | ||||
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r255 | |||
begin | ||||
DAC_nCLR <= '1'; | ||||
DAC_nCS <= '1'; | ||||
CAL_IN_SCK <= '1'; | ||||
DAC_SDI <= (others =>'1'); | ||||
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r263 | rst0 : rstgen port map (reset, clkm, cgo.clklock, rstn, rstraw); | ||
lclk <= clk; | ||||
clkgen0 : clkgen -- clock generatorsa | ||||
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, | ||||
CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV) | ||||
port map (lclk, lclk, clkm, open, clk2x, sdclkl, pciclk, cgi, cgo); | ||||
---------------------------------------------------------------------- | ||||
--- AHB CONTROLLER ------------------------------------------------- | ||||
---------------------------------------------------------------------- | ||||
ahb0 : ahbctrl -- AHB arbiter/multiplexer | ||||
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT, | ||||
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, | ||||
ioen => IOAEN, nahbm => maxahbm, nahbs => 8) | ||||
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); | ||||
---------------------------------------------------------------------- | ||||
--- AHB UART ------------------------------------------------------- | ||||
---------------------------------------------------------------------- | ||||
dcomgen : if CFG_AHB_UART = 1 generate | ||||
dcom0: ahbuart -- Debug UART | ||||
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7) | ||||
port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU)); | ||||
ahbuarti.rxd <= RXD; | ||||
TXD <= ahbuarto.txd; | ||||
led(0) <= not ahbuarti.rxd; led(1) <= not ahbuarto.txd; | ||||
end generate; | ||||
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate; | ||||
---------------------------------------------------------------------- | ||||
--- APB Bridge ----------------------------------------------------- | ||||
---------------------------------------------------------------------- | ||||
apb0 : apbctrl -- AHB/APB bridge | ||||
generic map (hindex => 1, haddr => CFG_APBADDR) | ||||
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo ); | ||||
---------------------------------------------------------------------- | ||||
--- APB UART ------------------------------------------------------- | ||||
---------------------------------------------------------------------- | ||||
ua1 : if CFG_UART1_ENABLE /= 0 generate | ||||
uart1 : apbuart -- UART 1 | ||||
generic map (pindex => 1, paddr => 1, pirq => 2, console => CFG_DUART, | ||||
fifosize => CFG_UART1_FIFO) | ||||
port map (rstn, clkm, apbi, apbo(1), ahbuarti, apbuarto); | ||||
apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd; | ||||
apbuarti.ctsn <= '0'; | ||||
end generate; | ||||
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate; | ||||
--div0: Clk_divider | ||||
-- generic map( 100000000,1) | ||||
-- Port map( clkm,rstn,LED(2)); | ||||
LED(2) <= led2int; | ||||
process(clkm,rstn) | ||||
begin | ||||
if rstn = '0' then | ||||
led2int <= '0'; | ||||
elsif clkm'event and clkm='1' then | ||||
led2int <= not led2int; | ||||
end if; | ||||
end process; | ||||
mctrl0 : mctrl generic map (srbanks => 4, sden => 1) | ||||
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wprot, sdo); | ||||
-- memory controller inputs not used in this configuration | ||||
memi.brdyn <= '1'; memi.bexcn <= '1'; memi.wrn <= "1111"; | ||||
memi.sd <= Data; | ||||
-- prom width at reset | ||||
memi.bwidth <= "10"; | ||||
-- I/O pads driving data memory bus data signals | ||||
datapads : for i in 0 to 3 generate | ||||
data_pad : iopadv generic map (width => 8) | ||||
port map ( | ||||
pad => data(31-i*8 downto 24-i*8), | ||||
o => memi.data(31-i*8 downto 24-i*8), | ||||
en => memo.bdrive(i), | ||||
i => memo.data(31-i*8 downto 24-i*8) | ||||
); | ||||
end generate; | ||||
-- connect memory controller outputs to entity output signals | ||||
Address <= memo.sa(11 downto 0); | ||||
sdba <= memo.sa(13 downto 12); | ||||
writen <= memo.writen; read <= memo.read; iosn <= memo.iosn; | ||||
sdcke <= sdo.sdcke; | ||||
sdwen <= sdo.sdwen; | ||||
sdcsn <= sdo.sdcsn; | ||||
sdrasn <= sdo.rasn; | ||||
sdcasn <= sdo.casn; | ||||
sddqm <= sdo.dqm(3 downto 0); | ||||
end; | ||||
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r255 | |||
end rtl; | ||||