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Started preliminary version of BeagleSynth board.
Jeandet Alexis -
r255:0c243809f9f2 alexis
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1 #
2 TECHNOLOGY=Spartan6
3 ISETECH="Spartan6"
4 PART=XC6SLX45
5 PACKAGE=fgg484
6 SPEED=-3
7 SYNFREQ=220
8 PROMGENPAR=
9
10 MANUFACTURER=Xilinx
11 MGCPART=XC6SLX45$(PACKAGE)
12 MGCTECHNOLOGY=SPARTAN-6
13 MGCPACKAGE=$(PACKAGE)
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1 NET "CLK" LOC = "A6" | IOSTANDARD = LVCMOS33;
2
3 NET "RESET" CLOCK_DEDICATED_ROUTE = FALSE;
4 NET "RESET" LOC = "AB11" | IOSTANDARD = LVTTL;
5
6 NET "DAC_nCLR" LOC = "R11" | IOSTANDARD = LVCMOS33;
7 NET "DAC_nCS" LOC = "T12" | IOSTANDARD = LVCMOS33;
8 NET "CAL_IN_SCK" LOC = "R13" | IOSTANDARD = LVCMOS33;
9 NET "DAC_SDI(0)" LOC = "P5" | IOSTANDARD = LVCMOS33;
10 NET "DAC_SDI(1)" LOC = "M5" | IOSTANDARD = LVCMOS33;
11 NET "DAC_SDI(2)" LOC = "C8" | IOSTANDARD = LVCMOS33;
12 NET "DAC_SDI(3)" LOC = "M6" | IOSTANDARD = LVCMOS33;
13 NET "DAC_SDI(4)" LOC = "K22" | IOSTANDARD = LVCMOS33;
14 NET "DAC_SDI(5)" LOC = "L22" | IOSTANDARD = LVCMOS33;
15 NET "DAC_SDI(6)" LOC = "G19" | IOSTANDARD = LVCMOS33;
16 NET "DAC_SDI(7)" LOC = "F20" | IOSTANDARD = LVCMOS33;
17
18
19
20
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1 -g DebugBitstream:No
2 -g Binary:no
3 -b
4 -g CRC:Enable
5 -g ConfigRate:26
6 -g ProgPin:PullUp
7 -g DonePin:PullUp
8 -g TckPin:PullUp
9 -g TdiPin:PullUp
10 -g TdoPin:PullUp
11 -g TmsPin:PullUp
12 -g UnusedPin:PullDown
13 -g UserID:0xFFFFFFFF
14 -g SPI_buswidth:4
15 -g StartUpClk:CCLK
16 -g DONE_cycle:4
17 -g GTS_cycle:5
18 -g GWE_cycle:6
19 -g LCK_cycle:NoWait
20 -g Security:None
21 -g Persist:No
22 -g ReadBack
23 -g DonePipe:No
24 -g DriveDone:Yes
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1 setMode -bscan
2 setCable -p usb21
3 identify
4 assignfile -p 1 -file xilinx-sp605-xc6slx45t.bit
5 program -p 1
6 quit
7
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1 setMode -bs
2 setCable -port auto
3 Identify
4 identifyMPM
5 assignFile -p 2 -file "xilinx-sp605-xc6slx45t.bit"
6 Program -p 2 -defaultVersion 0
7 quit
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1 library ieee;
2 use ieee.std_logic_1164.all;
3 use IEEE.numeric_std.all;
4 library grlib, techmap;
5 use grlib.amba.all;
6 use grlib.amba.all;
7 use grlib.stdlib.all;
8 use techmap.gencomp.all;
9 use techmap.allclkgen.all;
10 library gaisler;
11 use gaisler.memctrl.all;
12 use gaisler.leon3.all;
13 use gaisler.uart.all;
14 use gaisler.misc.all;
15 --use gaisler.sim.all;
16 library lpp;
17 use lpp.lpp_ad_conv.all;
18 use lpp.lpp_amba.all;
19 use lpp.apb_devices_list.all;
20 use lpp.general_purpose.all;
21
22
23 use work.config.all;
24 --==================================================================
25 --
26 --
27 -- FPGA FREQ = 48MHz
28 -- ADC Oscillator frequency = 12MHz
29 --
30 --
31 --==================================================================
32
33 entity BeagleSynth is
34 generic (
35 fabtech : integer := CFG_FABTECH;
36 memtech : integer := CFG_MEMTECH;
37 padtech : integer := CFG_PADTECH;
38 clktech : integer := CFG_CLKTECH
39 );
40 port (
41 reset : in std_ulogic;
42 clk : in std_ulogic;
43 DAC_nCLR : out std_ulogic;
44 DAC_nCS : out std_ulogic;
45 CAL_IN_SCK : out std_ulogic;
46 DAC_SDI : out std_ulogic_vector(7 downto 0)
47 );
48 end;
49
50 architecture rtl of BeagleSynth is
51
52 begin
53
54 DAC_nCLR <= '1';
55 DAC_nCS <= '1';
56 CAL_IN_SCK <= '1';
57 DAC_SDI <= (others =>'1');
58
59
60 end rtl;
61
62
63
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1 include .config
2
3 #GRLIB=$(GRLIB)
4 TOP=BeagleSynth
5 BOARD=BeagleSynth
6 #BOARD=SP601
7 include ../../boards/$(BOARD)/Makefile.inc
8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
9 #UCF=$(GRLIB)/boards/$(BOARD)/ICI3.ucf
10 UCF=../../boards/$(BOARD)/default.ucf
11 QSF=../../boards/$(BOARD)/$(TOP).qsf
12 EFFORT=high
13 ISEMAPOPT="-timing"
14 XSTOPT=""
15 SYNPOPT="set_option -maxfan 100; set_option -pipe 1; set_option -retiming 1; set_option -write_apr_constraint 0"
16 VHDLOPTSYNFILES=
17
18
19 VHDLSYNFILES= \
20 config.vhd BeagleSynth.vhd
21 #VHDLSIMFILES=testbench.vhd
22 #SIMTOP=testbench
23 #SDCFILE=$(GRLIB)/boards/$(BOARD)/default.sdc
24 SDCFILE=default.sdc
25 BITGEN=../../boards/$(BOARD)/default.ut
26 CLEAN=soft-clean
27 VCOMOPT=-explicit
28 TECHLIBS = secureip unisim
29
30 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
31 tmtc openchip cypress ihp gleichmann gsi fmf spansion
32 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan pci leon3ft ambatest \
33 leon4 leon4b64 l2cache gr1553b iommu haps ascs slink coremp7 pwm \
34 ac97 hcan usb
35 DIRADD =
36 FILEADD =
37 FILESKIP = grcan.vhd ddr2.v mobile_ddr.v
38
39 include $(GRLIB)/bin/Makefile
40 include $(GRLIB)/software/leon3/Makefile
41
42
43 ################## project specific targets ##########################
44
45 flash:
46 xc3sprog -c ftdi -p 1 ici4.bit
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1
2
3
4 -----------------------------------------------------------------------------
5 -- LEON3 Demonstration design test bench configuration
6 -- Copyright (C) 2009 Aeroflex Gaisler
7 ------------------------------------------------------------------------------
8
9
10 library techmap;
11 use techmap.gencomp.all;
12 LIBRARY IEEE;
13 USE IEEE.numeric_std.ALL;
14 USE IEEE.std_logic_1164.ALL;
15
16
17 package config is
18 -- Technology and synthesis options
19 constant CFG_FABTECH : integer := spartan6;
20 constant CFG_MEMTECH : integer := spartan6;
21 constant CFG_PADTECH : integer := spartan6;
22 -- Clock generator
23 constant CFG_CLKTECH : integer := spartan6;
24 constant SEND_CONSTANT_DATA : integer := 0;
25 constant SEND_MINF_VALUE : integer := 0;
26
27
28
29 constant LF1cst : std_logic_vector(15 downto 0) := X"1111";
30 constant LF2cst : std_logic_vector(15 downto 0) := X"2222";
31 constant LF3cst : std_logic_vector(15 downto 0) := X"3333";
32
33
34 constant AMR1Xcst : std_logic_vector(23 downto 0):= X"000001";
35 constant AMR1Ycst : std_logic_vector(23 downto 0):= X"111111";
36 constant AMR1Zcst : std_logic_vector(23 downto 0):= X"7FFFFF";
37
38 constant AMR2Xcst : std_logic_vector(23 downto 0):= X"800000";
39 constant AMR2Ycst : std_logic_vector(23 downto 0):= X"000002";
40 constant AMR2Zcst : std_logic_vector(23 downto 0):= X"800001";
41
42 constant AMR3Xcst : std_logic_vector(23 downto 0):= X"AAAAAA";
43 constant AMR3Ycst : std_logic_vector(23 downto 0):= X"BBBBBB";
44 constant AMR3Zcst : std_logic_vector(23 downto 0):= X"CCCCCC";
45
46 constant AMR4Xcst : std_logic_vector(23 downto 0):= X"DDDDDD";
47 constant AMR4Ycst : std_logic_vector(23 downto 0):= X"EEEEEE";
48 constant AMR4Zcst : std_logic_vector(23 downto 0):= X"FFFFFF";
49
50 constant Temp1cst : std_logic_vector(23 downto 0):= X"121212";
51 constant Temp2cst : std_logic_vector(23 downto 0):= X"343434";
52 constant Temp3cst : std_logic_vector(23 downto 0):= X"565656";
53 constant Temp4cst : std_logic_vector(23 downto 0):= X"787878";
54
55
56
57 --===========================================================|
58 --========F I L T E R C O N F I G V A L U E S=============|
59 --===========================================================|
60 --____________________________
61 --Bus Width and chanels number|
62 --____________________________|
63 constant ChanelsCount : integer := 3;
64 constant Sample_SZ : integer := 16;
65 constant Coef_SZ : integer := 9;
66 constant CoefCntPerCel: integer := 6;
67 constant CoefPerCel: integer := 5;
68 constant Cels_count : integer := 5;
69 constant virgPos : integer := 7;
70 constant Mem_use : integer := 1;
71
72
73
74 --============================================================
75 -- create each initial values for each coefs ============
76 --!!!!!!!!!!It should be interfaced with a software !!!!!!!!!!
77 --============================================================
78 constant b0_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(58,Coef_SZ));
79 constant b0_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-66,Coef_SZ));
80 constant b0_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(58,Coef_SZ));
81
82 constant b1_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(58,Coef_SZ));
83 constant b1_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-57,Coef_SZ));
84 constant b1_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(58,Coef_SZ));
85
86 constant b2_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(29,Coef_SZ));
87 constant b2_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-17,Coef_SZ));
88 constant b2_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(29,Coef_SZ));
89
90 constant b3_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(15,Coef_SZ));
91 constant b3_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(4,Coef_SZ));
92 constant b3_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(15,Coef_SZ));
93
94 constant b4_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(15,Coef_SZ));
95 constant b4_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(24,Coef_SZ));
96 constant b4_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(15,Coef_SZ));
97
98 --constant b5_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-81,Coef_SZ));
99 --constant b5_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-153,Coef_SZ));
100 --constant b5_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-171,Coef_SZ));
101
102 --constant b6_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-144,Coef_SZ));
103 --constant b6_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-72,Coef_SZ));
104 --constant b6_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-25,Coef_SZ));
105
106
107 constant a0_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
108 constant a0_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(189,Coef_SZ));
109 constant a0_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-111,Coef_SZ));
110
111 constant a1_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
112 constant a1_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(162,Coef_SZ));
113 constant a1_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-81,Coef_SZ));
114
115 constant a2_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
116 constant a2_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(136,Coef_SZ));
117 constant a2_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-55,Coef_SZ));
118
119 constant a3_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
120 constant a3_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(114,Coef_SZ));
121 constant a3_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-33,Coef_SZ));
122
123 constant a4_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
124 constant a4_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(100,Coef_SZ));
125 constant a4_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-20,Coef_SZ));
126
127 --constant a5_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(60,Coef_SZ));
128 --constant a5_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
129 --constant a5_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(87,Coef_SZ));
130 --constant a6_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(60,Coef_SZ));
131 --constant a6_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
132 --constant a6_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(87,Coef_SZ));
133
134 constant CoefsInitValCst : std_logic_vector((Cels_count*CoefCntPerCel*Coef_SZ)-1 downto 0) := (a4_2 & a4_1 & a4_0 & b4_2 & b4_1 & b4_0 & a3_2 & a3_1 & a3_0 & b3_2 & b3_1 & b3_0 & a2_2 & a2_1 & a2_0 & b2_2 & b2_1 & b2_0 & a1_2 & a1_1 & a1_0 & b1_2 & b1_1 & b1_0 & a0_2 & a0_1 & a0_0 & b0_2 & b0_1 & b0_0);
135
136 constant CoefsInitValCst_v2 : std_logic_vector((Cels_count*CoefPerCel*Coef_SZ)-1 downto 0) :=
137 (a4_1 & a4_2 & b4_0 & b4_1 & b4_2 &
138 a3_1 & a3_2 & b3_0 & b3_1 & b3_2 &
139 a2_1 & a2_2 & b2_0 & b2_1 & b2_2 &
140 a1_1 & a1_2 & b1_0 & b1_1 & b1_2 &
141 a0_1 & a0_2 & b0_0 & b0_1 & b0_2 );
142
143
144
145 end;
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