# HG changeset patch
# User Jeandet Alexis
# Date 2013-12-02 18:46:22
# Node ID 0c243809f9f261acf55caa4ed805b14c9d6fb5e5
# Parent  295951e0580347e44bc3a49e9ce9e48e354398ec

Started preliminary version of BeagleSynth board.

diff --git a/boards/BeagleSynth/Makefile.inc b/boards/BeagleSynth/Makefile.inc
new file mode 100644
--- /dev/null
+++ b/boards/BeagleSynth/Makefile.inc
@@ -0,0 +1,13 @@
+#
+TECHNOLOGY=Spartan6
+ISETECH="Spartan6"
+PART=XC6SLX45
+PACKAGE=fgg484
+SPEED=-3
+SYNFREQ=220
+PROMGENPAR=
+
+MANUFACTURER=Xilinx
+MGCPART=XC6SLX45$(PACKAGE)
+MGCTECHNOLOGY=SPARTAN-6
+MGCPACKAGE=$(PACKAGE)
diff --git a/boards/BeagleSynth/default.ucf b/boards/BeagleSynth/default.ucf
new file mode 100644
--- /dev/null
+++ b/boards/BeagleSynth/default.ucf
@@ -0,0 +1,20 @@
+NET "CLK"              LOC = "A6" | IOSTANDARD = LVCMOS33;
+
+NET "RESET"    CLOCK_DEDICATED_ROUTE = FALSE;
+NET "RESET"            LOC = "AB11"  | IOSTANDARD = LVTTL;
+
+NET "DAC_nCLR"     LOC = "R11"   | IOSTANDARD = LVCMOS33;
+NET "DAC_nCS"      LOC = "T12"   | IOSTANDARD = LVCMOS33;
+NET "CAL_IN_SCK"   LOC = "R13"   | IOSTANDARD = LVCMOS33;
+NET "DAC_SDI(0)"   LOC = "P5"    | IOSTANDARD = LVCMOS33;
+NET "DAC_SDI(1)"   LOC = "M5"    | IOSTANDARD = LVCMOS33;
+NET "DAC_SDI(2)"   LOC = "C8"    | IOSTANDARD = LVCMOS33;
+NET "DAC_SDI(3)"   LOC = "M6"    | IOSTANDARD = LVCMOS33;
+NET "DAC_SDI(4)"   LOC = "K22"   | IOSTANDARD = LVCMOS33;
+NET "DAC_SDI(5)"   LOC = "L22"   | IOSTANDARD = LVCMOS33;
+NET "DAC_SDI(6)"   LOC = "G19"   | IOSTANDARD = LVCMOS33;
+NET "DAC_SDI(7)"   LOC = "F20"   | IOSTANDARD = LVCMOS33;
+
+
+
+
diff --git a/boards/BeagleSynth/default.ut b/boards/BeagleSynth/default.ut
new file mode 100644
--- /dev/null
+++ b/boards/BeagleSynth/default.ut
@@ -0,0 +1,24 @@
+-g DebugBitstream:No
+-g Binary:no
+-b
+-g CRC:Enable
+-g ConfigRate:26
+-g ProgPin:PullUp
+-g DonePin:PullUp
+-g TckPin:PullUp
+-g TdiPin:PullUp
+-g TdoPin:PullUp
+-g TmsPin:PullUp
+-g UnusedPin:PullDown
+-g UserID:0xFFFFFFFF
+-g SPI_buswidth:4 
+-g StartUpClk:CCLK
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Security:None
+-g Persist:No
+-g ReadBack
+-g DonePipe:No
+-g DriveDone:Yes
diff --git a/boards/BeagleSynth/fpga-usb.cmd b/boards/BeagleSynth/fpga-usb.cmd
new file mode 100644
--- /dev/null
+++ b/boards/BeagleSynth/fpga-usb.cmd
@@ -0,0 +1,7 @@
+setMode -bscan
+setCable -p usb21
+identify
+assignfile -p 1 -file xilinx-sp605-xc6slx45t.bit
+program -p 1
+quit
+
diff --git a/boards/BeagleSynth/fpga.cmd b/boards/BeagleSynth/fpga.cmd
new file mode 100644
--- /dev/null
+++ b/boards/BeagleSynth/fpga.cmd
@@ -0,0 +1,7 @@
+setMode -bs
+setCable -port auto
+Identify 
+identifyMPM 
+assignFile -p 2 -file "xilinx-sp605-xc6slx45t.bit"
+Program -p 2 -defaultVersion 0 
+quit
diff --git a/designs/BeagleSynth/BeagleSynth.vhd b/designs/BeagleSynth/BeagleSynth.vhd
new file mode 100644
--- /dev/null
+++ b/designs/BeagleSynth/BeagleSynth.vhd
@@ -0,0 +1,63 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use IEEE.numeric_std.all;
+library grlib, techmap;
+use grlib.amba.all;
+use grlib.amba.all;
+use grlib.stdlib.all;
+use techmap.gencomp.all;
+use techmap.allclkgen.all;
+library gaisler;
+use gaisler.memctrl.all;
+use gaisler.leon3.all;
+use gaisler.uart.all;
+use gaisler.misc.all;
+--use gaisler.sim.all;
+library lpp;
+use lpp.lpp_ad_conv.all;
+use lpp.lpp_amba.all;
+use lpp.apb_devices_list.all;
+use lpp.general_purpose.all;
+
+
+use work.config.all;
+--==================================================================
+--
+--
+--			FPGA FREQ = 48MHz
+--			ADC Oscillator frequency = 12MHz
+--
+--
+--==================================================================
+
+entity BeagleSynth is
+  generic (
+    fabtech       : integer := CFG_FABTECH;
+    memtech       : integer := CFG_MEMTECH;
+    padtech       : integer := CFG_PADTECH;
+    clktech       : integer := CFG_CLKTECH
+  );
+  port (
+    reset         : in  std_ulogic;
+    clk           : in  std_ulogic;
+	 DAC_nCLR		: out std_ulogic;
+	 DAC_nCS       : out std_ulogic;
+	 CAL_IN_SCK		: out std_ulogic;
+	 DAC_SDI			: out std_ulogic_vector(7 downto 0)
+	 );
+end;
+
+architecture rtl of BeagleSynth is
+
+begin
+
+DAC_nCLR		<= '1';
+DAC_nCS     <= '1';
+CAL_IN_SCK  <= '1';
+DAC_SDI		<= (others =>'1');
+
+
+end rtl;
+
+
+ 
diff --git a/designs/BeagleSynth/Makefile b/designs/BeagleSynth/Makefile
new file mode 100644
--- /dev/null
+++ b/designs/BeagleSynth/Makefile
@@ -0,0 +1,46 @@
+include .config
+
+#GRLIB=$(GRLIB)
+TOP=BeagleSynth
+BOARD=BeagleSynth
+#BOARD=SP601
+include ../../boards/$(BOARD)/Makefile.inc
+DEVICE=$(PART)-$(PACKAGE)$(SPEED)
+#UCF=$(GRLIB)/boards/$(BOARD)/ICI3.ucf
+UCF=../../boards/$(BOARD)/default.ucf
+QSF=../../boards/$(BOARD)/$(TOP).qsf
+EFFORT=high
+ISEMAPOPT="-timing"
+XSTOPT=""
+SYNPOPT="set_option -maxfan 100; set_option -pipe 1; set_option -retiming 1; set_option -write_apr_constraint 0"
+VHDLOPTSYNFILES= 
+
+
+VHDLSYNFILES= \
+	config.vhd  BeagleSynth.vhd
+#VHDLSIMFILES=testbench.vhd
+#SIMTOP=testbench
+#SDCFILE=$(GRLIB)/boards/$(BOARD)/default.sdc
+SDCFILE=default.sdc
+BITGEN=../../boards/$(BOARD)/default.ut
+CLEAN=soft-clean
+VCOMOPT=-explicit
+TECHLIBS = secureip unisim 
+
+LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
+	tmtc openchip cypress ihp gleichmann gsi fmf spansion 
+DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan pci leon3ft ambatest \
+	leon4 leon4b64 l2cache gr1553b iommu haps ascs slink coremp7 pwm \
+	ac97 hcan usb
+DIRADD = 
+FILEADD = 
+FILESKIP = grcan.vhd ddr2.v mobile_ddr.v
+
+include $(GRLIB)/bin/Makefile
+include $(GRLIB)/software/leon3/Makefile
+
+
+##################  project specific targets ##########################
+
+flash:
+	xc3sprog -c ftdi -p 1 ici4.bit
diff --git a/designs/BeagleSynth/config.vhd b/designs/BeagleSynth/config.vhd
new file mode 100644
--- /dev/null
+++ b/designs/BeagleSynth/config.vhd
@@ -0,0 +1,145 @@
+
+
+
+-----------------------------------------------------------------------------
+-- LEON3 Demonstration design test bench configuration
+-- Copyright (C) 2009 Aeroflex Gaisler
+------------------------------------------------------------------------------
+
+
+library techmap;
+use techmap.gencomp.all;
+LIBRARY IEEE;
+USE IEEE.numeric_std.ALL;
+USE IEEE.std_logic_1164.ALL;
+
+
+package config is
+-- Technology and synthesis options
+  constant CFG_FABTECH : integer := spartan6;
+  constant CFG_MEMTECH : integer := spartan6;
+  constant CFG_PADTECH : integer := spartan6;
+-- Clock generator
+  constant CFG_CLKTECH : integer := spartan6;
+  constant SEND_CONSTANT_DATA : integer := 0;
+  constant SEND_MINF_VALUE    : integer := 0;
+  
+  
+  
+constant LF1cst :   std_logic_vector(15 downto 0) := X"1111";
+constant LF2cst :   std_logic_vector(15 downto 0) := X"2222";
+constant LF3cst :   std_logic_vector(15 downto 0) := X"3333";
+
+
+constant  AMR1Xcst   :     std_logic_vector(23 downto 0):= X"000001";
+constant  AMR1Ycst   :     std_logic_vector(23 downto 0):= X"111111";
+constant  AMR1Zcst   :     std_logic_vector(23 downto 0):= X"7FFFFF";
+
+constant  AMR2Xcst   :     std_logic_vector(23 downto 0):= X"800000";
+constant  AMR2Ycst   :     std_logic_vector(23 downto 0):= X"000002";
+constant  AMR2Zcst   :     std_logic_vector(23 downto 0):= X"800001";
+
+constant  AMR3Xcst   :     std_logic_vector(23 downto 0):= X"AAAAAA";
+constant  AMR3Ycst   :     std_logic_vector(23 downto 0):= X"BBBBBB";
+constant  AMR3Zcst   :     std_logic_vector(23 downto 0):= X"CCCCCC";
+
+constant  AMR4Xcst   :     std_logic_vector(23 downto 0):= X"DDDDDD";
+constant  AMR4Ycst   :     std_logic_vector(23 downto 0):= X"EEEEEE";
+constant  AMR4Zcst   :     std_logic_vector(23 downto 0):= X"FFFFFF";
+
+constant  Temp1cst   :     std_logic_vector(23 downto 0):= X"121212";
+constant  Temp2cst   :     std_logic_vector(23 downto 0):= X"343434";
+constant  Temp3cst   :     std_logic_vector(23 downto 0):= X"565656";
+constant  Temp4cst   :     std_logic_vector(23 downto 0):= X"787878";
+
+
+
+--===========================================================|
+--========F I L T E R   C O N F I G  V A L U E S=============|
+--===========================================================|
+--____________________________
+--Bus Width and chanels number|
+--____________________________|
+constant ChanelsCount :   integer :=  3;
+constant Sample_SZ    :   integer := 16;
+constant Coef_SZ    :   integer := 9;
+constant CoefCntPerCel:   integer := 6;
+constant CoefPerCel:   integer := 5;
+constant Cels_count :   integer := 5;
+constant virgPos      : integer := 7;
+constant Mem_use    :   integer := 1;
+
+
+
+--============================================================
+--      create each initial values for each coefs ============
+--!!!!!!!!!!It should be interfaced with a software !!!!!!!!!!
+--============================================================
+constant b0_0       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(58,Coef_SZ));
+constant b0_1       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-66,Coef_SZ));
+constant b0_2       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(58,Coef_SZ));
+
+constant b1_0       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(58,Coef_SZ));
+constant b1_1       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-57,Coef_SZ));
+constant b1_2       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(58,Coef_SZ));
+
+constant b2_0       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(29,Coef_SZ));
+constant b2_1       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-17,Coef_SZ));
+constant b2_2       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(29,Coef_SZ));
+
+constant b3_0       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(15,Coef_SZ));
+constant b3_1       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(4,Coef_SZ));
+constant b3_2       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(15,Coef_SZ));
+
+constant b4_0       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(15,Coef_SZ));
+constant b4_1       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(24,Coef_SZ));
+constant b4_2       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(15,Coef_SZ));
+
+--constant b5_0       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-81,Coef_SZ));
+--constant b5_1       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-153,Coef_SZ));
+--constant b5_2       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-171,Coef_SZ));
+
+--constant b6_0       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-144,Coef_SZ));
+--constant b6_1       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-72,Coef_SZ));
+--constant b6_2       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-25,Coef_SZ));
+
+
+constant a0_0       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
+constant a0_1       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(189,Coef_SZ));
+constant a0_2       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-111,Coef_SZ));
+
+constant a1_0       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
+constant a1_1       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(162,Coef_SZ));
+constant a1_2       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-81,Coef_SZ));
+
+constant a2_0       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
+constant a2_1       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(136,Coef_SZ));
+constant a2_2       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-55,Coef_SZ));
+
+constant a3_0       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
+constant a3_1       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(114,Coef_SZ));
+constant a3_2       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-33,Coef_SZ));
+
+constant a4_0       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
+constant a4_1       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(100,Coef_SZ));
+constant a4_2       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-20,Coef_SZ));
+
+--constant a5_0       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(60,Coef_SZ));
+--constant a5_1       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
+--constant a5_2       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(87,Coef_SZ));
+--constant a6_0       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(60,Coef_SZ));
+--constant a6_1       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
+--constant a6_2       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(87,Coef_SZ));
+
+constant CoefsInitValCst  :   std_logic_vector((Cels_count*CoefCntPerCel*Coef_SZ)-1 downto 0) := (a4_2 & a4_1 & a4_0 & b4_2 & b4_1 & b4_0 & a3_2 & a3_1 & a3_0 & b3_2 & b3_1 & b3_0 & a2_2 & a2_1 & a2_0 & b2_2 & b2_1 & b2_0 & a1_2 & a1_1 & a1_0 & b1_2 & b1_1 &  b1_0 & a0_2 & a0_1 & a0_0 & b0_2 & b0_1 & b0_0);
+
+constant CoefsInitValCst_v2  :   std_logic_vector((Cels_count*CoefPerCel*Coef_SZ)-1 downto 0) :=
+  (a4_1 & a4_2 & b4_0 & b4_1 & b4_2 &
+   a3_1 & a3_2 & b3_0 & b3_1 & b3_2 &
+   a2_1 & a2_2 & b2_0 & b2_1 & b2_2 &
+   a1_1 & a1_2 & b1_0 & b1_1 & b1_2 &
+   a0_1 & a0_2 & b0_0 & b0_1 & b0_2  );
+
+
+
+end;