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Started preliminary version of BeagleSynth board.
Started preliminary version of BeagleSynth board.
Jeandet Alexis - - Load All Authors

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default.ucf
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NET "CLK" LOC = "A6" | IOSTANDARD = LVCMOS33;
NET "RESET" CLOCK_DEDICATED_ROUTE = FALSE;
NET "RESET" LOC = "AB11" | IOSTANDARD = LVTTL;
NET "DAC_nCLR" LOC = "R11" | IOSTANDARD = LVCMOS33;
NET "DAC_nCS" LOC = "T12" | IOSTANDARD = LVCMOS33;
NET "CAL_IN_SCK" LOC = "R13" | IOSTANDARD = LVCMOS33;
NET "DAC_SDI(0)" LOC = "P5" | IOSTANDARD = LVCMOS33;
NET "DAC_SDI(1)" LOC = "M5" | IOSTANDARD = LVCMOS33;
NET "DAC_SDI(2)" LOC = "C8" | IOSTANDARD = LVCMOS33;
NET "DAC_SDI(3)" LOC = "M6" | IOSTANDARD = LVCMOS33;
NET "DAC_SDI(4)" LOC = "K22" | IOSTANDARD = LVCMOS33;
NET "DAC_SDI(5)" LOC = "L22" | IOSTANDARD = LVCMOS33;
NET "DAC_SDI(6)" LOC = "G19" | IOSTANDARD = LVCMOS33;
NET "DAC_SDI(7)" LOC = "F20" | IOSTANDARD = LVCMOS33;