HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · designs/BeagleSynth/BeagleSynth.vhd

Started preliminary version of BeagleSynth board.

Jeandet Alexis - - Load All Authors

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      library ieee;

      use ieee.std_logic_1164.all;

      use IEEE.numeric_std.all;

      library grlib, techmap;

      use grlib.amba.all;

      use grlib.amba.all;

      use grlib.stdlib.all;

      use techmap.gencomp.all;

      use techmap.allclkgen.all;

      library gaisler;

      use gaisler.memctrl.all;

      use gaisler.leon3.all;

      use gaisler.uart.all;

      use gaisler.misc.all;

      --use gaisler.sim.all;

      library lpp;

      use lpp.lpp_ad_conv.all;

      use lpp.lpp_amba.all;

      use lpp.apb_devices_list.all;

      use lpp.general_purpose.all;

      use work.config.all;

      --==================================================================

      --

      --

      --			FPGA FREQ = 48MHz

      --			ADC Oscillator frequency = 12MHz

      --

      --

      --==================================================================

      entity BeagleSynth is

        generic (

          fabtech       : integer := CFG_FABTECH;

          memtech       : integer := CFG_MEMTECH;

          padtech       : integer := CFG_PADTECH;

          clktech       : integer := CFG_CLKTECH

        );

        port (

          reset         : in  std_ulogic;

          clk           : in  std_ulogic;

      	 DAC_nCLR		: out std_ulogic;

      	 DAC_nCS       : out std_ulogic;

      	 CAL_IN_SCK		: out std_ulogic;

      	 DAC_SDI			: out std_ulogic_vector(7 downto 0)

      	 );

      end;

      architecture rtl of BeagleSynth is

      begin

      DAC_nCLR		<= '1';

      DAC_nCS     <= '1';

      CAL_IN_SCK  <= '1';

      DAC_SDI		<= (others =>'1');

      end rtl;

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				library ieee;
				use ieee.std_logic_1164.all;
				use IEEE.numeric_std.all;
				library grlib, techmap;
				use grlib.amba.all;
				use grlib.amba.all;
				use grlib.stdlib.all;
				use techmap.gencomp.all;
				use techmap.allclkgen.all;
				library gaisler;
				use gaisler.memctrl.all;
				use gaisler.leon3.all;
				use gaisler.uart.all;
				use gaisler.misc.all;
				--use gaisler.sim.all;
				library lpp;
				use lpp.lpp_ad_conv.all;
				use lpp.lpp_amba.all;
				use lpp.apb_devices_list.all;
				use lpp.general_purpose.all;


				use work.config.all;
				--==================================================================
				--
				--
				-- FPGA FREQ = 48MHz
				-- ADC Oscillator frequency = 12MHz
				--
				--
				--==================================================================

				entity BeagleSynth is
				generic (
				fabtech : integer := CFG_FABTECH;
				memtech : integer := CFG_MEMTECH;
				padtech : integer := CFG_PADTECH;
				clktech : integer := CFG_CLKTECH
				);
				port (
				reset : in std_ulogic;
				clk : in std_ulogic;
				DAC_nCLR : out std_ulogic;
				DAC_nCS : out std_ulogic;
				CAL_IN_SCK : out std_ulogic;
				DAC_SDI : out std_ulogic_vector(7 downto 0)
				);
				end;

				architecture rtl of BeagleSynth is

				begin

				DAC_nCLR <= '1';
				DAC_nCS <= '1';
				CAL_IN_SCK <= '1';
				DAC_SDI <= (others =>'1');


				end rtl;