HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · designs/BeagleSynth/Makefile

Partially Working BeagleSynth base design, SDRAM still f****** buggy.

Jeandet Alexis - - Load All Authors

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             Makefile
        
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      include .config

      #GRLIB=$(GRLIB)

      TOP=BeagleSynth

      BOARD=BeagleSynth

      #BOARD=SP601

      include ../../boards/$(BOARD)/Makefile.inc

      DEVICE=$(PART)-$(PACKAGE)$(SPEED)

      #UCF=$(GRLIB)/boards/$(BOARD)/ICI3.ucf

      UCF=../../boards/$(BOARD)/default.ucf

      QSF=../../boards/$(BOARD)/$(TOP).qsf

      EFFORT=high

      ISEMAPOPT="-timing"

      XSTOPT=""

      SYNPOPT="set_option -maxfan 100; set_option -pipe 1; set_option -retiming 1; set_option -write_apr_constraint 0"

      VHDLOPTSYNFILES= 

      VHDLSYNFILES= \

      	config.vhd  BeagleSynth.vhd

      #VHDLSIMFILES=testbench.vhd

      #SIMTOP=testbench

      #SDCFILE=$(GRLIB)/boards/$(BOARD)/default.sdc

      SDCFILE=default.sdc

      BITGEN=../../boards/$(BOARD)/default.ut

      CLEAN=soft-clean

      VCOMOPT=-explicit

      TECHLIBS = secureip unisim 

      LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \

      	tmtc openchip cypress ihp gleichmann gsi fmf spansion 

      DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan pci leon3ft ambatest \

      	leon4 leon4b64 l2cache gr1553b iommu haps ascs slink coremp7 pwm \

      	ac97 hcan usb

      DIRADD = 

      FILEADD = 

      FILESKIP = grcan.vhd ddr2.v mobile_ddr.v

      include $(GRLIB)/bin/Makefile

      include $(GRLIB)/software/leon3/Makefile

      ##################  project specific targets ##########################

      flash:

      	xc3sprog -c ftdi -p 1 BeagleSynth.bit

      ram:

      	xc3sprog -c ftdi -p 0 BeagleSynth.bit

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				include .config

				#GRLIB=$(GRLIB)
				TOP=BeagleSynth
				BOARD=BeagleSynth
				#BOARD=SP601
				include ../../boards/$(BOARD)/Makefile.inc
				DEVICE=$(PART)-$(PACKAGE)$(SPEED)
				#UCF=$(GRLIB)/boards/$(BOARD)/ICI3.ucf
				UCF=../../boards/$(BOARD)/default.ucf
				QSF=../../boards/$(BOARD)/$(TOP).qsf
				EFFORT=high
				ISEMAPOPT="-timing"
				XSTOPT=""
				SYNPOPT="set_option -maxfan 100; set_option -pipe 1; set_option -retiming 1; set_option -write_apr_constraint 0"
				VHDLOPTSYNFILES=


				VHDLSYNFILES= \
				config.vhd BeagleSynth.vhd
				#VHDLSIMFILES=testbench.vhd
				#SIMTOP=testbench
				#SDCFILE=$(GRLIB)/boards/$(BOARD)/default.sdc
				SDCFILE=default.sdc
				BITGEN=../../boards/$(BOARD)/default.ut
				CLEAN=soft-clean
				VCOMOPT=-explicit
				TECHLIBS = secureip unisim

				LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
				tmtc openchip cypress ihp gleichmann gsi fmf spansion
				DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan pci leon3ft ambatest \
				leon4 leon4b64 l2cache gr1553b iommu haps ascs slink coremp7 pwm \
				ac97 hcan usb
				DIRADD =
				FILEADD =
				FILESKIP = grcan.vhd ddr2.v mobile_ddr.v

				include $(GRLIB)/bin/Makefile
				include $(GRLIB)/software/leon3/Makefile


				################## project specific targets ##########################

				flash:
				xc3sprog -c ftdi -p 1 BeagleSynth.bit

				ram:
				xc3sprog -c ftdi -p 0 BeagleSynth.bit