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Clone from http://pc-instru.lpp.polytechnique.fr:5000/VHD_Lib

Added missing files (sdc/pdc/makefile) for LFR-EQM boards...
pellion -
r639:5ffe6bd0368c default draft
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1 set_io clk49_152MHz -pinname D5 -fixed yes -DIRECTION Inout
2 set_io clk50MHz -pinname B3 -fixed yes -DIRECTION Inout
3 set_io reset -pinname N18 -fixed yes -DIRECTION Inout
4
5 set_io {address[0]} -pinname H16 -fixed yes -DIRECTION Inout
6 set_io {address[1]} -pinname J15 -fixed yes -DIRECTION Inout
7 set_io {address[2]} -pinname B18 -fixed yes -DIRECTION Inout
8 set_io {address[3]} -pinname C17 -fixed yes -DIRECTION Inout
9 set_io {address[4]} -pinname C18 -fixed yes -DIRECTION Inout
10 set_io {address[5]} -pinname U2 -fixed yes -DIRECTION Inout
11 set_io {address[6]} -pinname U3 -fixed yes -DIRECTION Inout
12 set_io {address[7]} -pinname R5 -fixed yes -DIRECTION Inout
13 set_io {address[8]} -pinname N11 -fixed yes -DIRECTION Inout
14 set_io {address[9]} -pinname R13 -fixed yes -DIRECTION Inout
15 set_io {address[10]} -pinname V13 -fixed yes -DIRECTION Inout
16 set_io {address[11]} -pinname U13 -fixed yes -DIRECTION Inout
17 set_io {address[12]} -pinname V15 -fixed yes -DIRECTION Inout
18 set_io {address[13]} -pinname V16 -fixed yes -DIRECTION Inout
19 set_io {address[14]} -pinname V17 -fixed yes -DIRECTION Inout
20 set_io {address[15]} -pinname N1 -fixed yes -DIRECTION Inout
21 set_io {address[16]} -pinname R3 -fixed yes -DIRECTION Inout
22 set_io {address[17]} -pinname P4 -fixed yes -DIRECTION Inout
23 set_io {address[18]} -pinname N3 -fixed yes -DIRECTION Inout
24 set_io {address[19]} -pinname M7 -fixed yes -DIRECTION Inout
25
26 set_io {data[0]} -pinname P17 -fixed yes -DIRECTION Inout
27 set_io {data[1]} -pinname R18 -fixed yes -DIRECTION Inout
28 set_io {data[2]} -pinname T18 -fixed yes -DIRECTION Inout
29 set_io {data[3]} -pinname J13 -fixed yes -DIRECTION Inout
30 set_io {data[4]} -pinname T13 -fixed yes -DIRECTION Inout
31 set_io {data[5]} -pinname T12 -fixed yes -DIRECTION Inout
32 set_io {data[6]} -pinname R12 -fixed yes -DIRECTION Inout
33 set_io {data[7]} -pinname T11 -fixed yes -DIRECTION Inout
34 set_io {data[8]} -pinname N2 -fixed yes -DIRECTION Inout
35 set_io {data[9]} -pinname P1 -fixed yes -DIRECTION Inout
36 set_io {data[10]} -pinname R1 -fixed yes -DIRECTION Inout
37 set_io {data[11]} -pinname T1 -fixed yes -DIRECTION Inout
38 set_io {data[12]} -pinname M4 -fixed yes -DIRECTION Inout
39 set_io {data[13]} -pinname K1 -fixed yes -DIRECTION Inout
40 set_io {data[14]} -pinname J1 -fixed yes -DIRECTION Inout
41 set_io {data[15]} -pinname H1 -fixed yes -DIRECTION Inout
42 set_io {data[16]} -pinname H15 -fixed yes -DIRECTION Inout
43 set_io {data[17]} -pinname G15 -fixed yes -DIRECTION Inout
44 set_io {data[18]} -pinname H13 -fixed yes -DIRECTION Inout
45 set_io {data[19]} -pinname G12 -fixed yes -DIRECTION Inout
46 set_io {data[20]} -pinname V14 -fixed yes -DIRECTION Inout
47 set_io {data[21]} -pinname N9 -fixed yes -DIRECTION Inout
48 set_io {data[22]} -pinname M13 -fixed yes -DIRECTION Inout
49 set_io {data[23]} -pinname M15 -fixed yes -DIRECTION Inout
50 set_io {data[24]} -pinname J17 -fixed yes -DIRECTION Inout
51 set_io {data[25]} -pinname K15 -fixed yes -DIRECTION Inout
52 set_io {data[26]} -pinname J14 -fixed yes -DIRECTION Inout
53 set_io {data[27]} -pinname U18 -fixed yes -DIRECTION Inout
54 set_io {data[28]} -pinname H18 -fixed yes -DIRECTION Inout
55 set_io {data[29]} -pinname J18 -fixed yes -DIRECTION Inout
56 set_io {data[30]} -pinname G17 -fixed yes -DIRECTION Inout
57 set_io {data[31]} -pinname F18 -fixed yes -DIRECTION Inout
58
59 set_io nSRAM_BE0 -pinname U12 -fixed yes -DIRECTION Inout
60 set_io nSRAM_BE1 -pinname K18 -fixed yes -DIRECTION Inout
61 set_io nSRAM_BE2 -pinname K12 -fixed yes -DIRECTION Inout
62 set_io nSRAM_BE3 -pinname F17 -fixed yes -DIRECTION Inout
63 set_io nSRAM_WE -pinname D18 -fixed yes -DIRECTION Inout
64 set_io nSRAM_CE -pinname M6 -fixed yes -DIRECTION Inout
65 set_io nSRAM_OE -pinname N12 -fixed yes -DIRECTION Inout
66
67 set_io spw1_din -pinname D6 -fixed yes -DIRECTION Inout
68 set_io spw1_sin -pinname C6 -fixed yes -DIRECTION Inout
69 set_io spw1_dout -pinname C16 -fixed yes -DIRECTION Inout
70 set_io spw1_sout -pinname C4 -fixed yes -DIRECTION Inout
71
72 set_io spw2_din -pinname E6 -fixed yes -DIRECTION Inout
73 set_io spw2_sin -pinname C15 -fixed yes -DIRECTION Inout
74 set_io spw2_dout -pinname B7 -fixed yes -DIRECTION Inout
75 set_io spw2_sout -pinname D7 -fixed yes -DIRECTION Inout
76
77 set_io {led[0]} -pinname K17 -fixed yes -DIRECTION Inout
78 set_io {led[1]} -pinname L18 -fixed yes -DIRECTION Inout
79 set_io {led[2]} -pinname M17 -fixed yes -DIRECTION Inout
80
81 set_io TAG1 -pinname J12 -fixed yes -DIRECTION Inout
82 set_io TAG2 -pinname K13 -fixed yes -DIRECTION Inout
83 set_io TAG3 -pinname L16 -fixed yes -DIRECTION Inout
84 set_io TAG4 -pinname L15 -fixed yes -DIRECTION Inout
85 #set_io TAG5 -pinname M16 -fixed yes -DIRECTION Inout
86 #set_io TAG6 -pinname L13 -fixed yes -DIRECTION Inout
87 #set_io TAG7 -pinname P6 -fixed yes -DIRECTION Inout
88 set_io TAG8 -pinname R6 -fixed yes -DIRECTION Inout
89 #set_io TAG9 -pinname T4 -fixed yes -DIRECTION Inout
90
91 set_io bias_fail_sw -pinname A3 -fixed yes -DIRECTION Inout
92
93 set_io {ADC_OEB_bar_CH[0]} -pinname A13 -fixed yes -DIRECTION Inout
94 set_io {ADC_OEB_bar_CH[1]} -pinname A14 -fixed yes -DIRECTION Inout
95 set_io {ADC_OEB_bar_CH[2]} -pinname A10 -fixed yes -DIRECTION Inout
96 set_io {ADC_OEB_bar_CH[3]} -pinname B10 -fixed yes -DIRECTION Inout
97 set_io {ADC_OEB_bar_CH[4]} -pinname B13 -fixed yes -DIRECTION Inout
98 set_io {ADC_OEB_bar_CH[5]} -pinname D13 -fixed yes -DIRECTION Inout
99 set_io {ADC_OEB_bar_CH[6]} -pinname A11 -fixed yes -DIRECTION Inout
100 set_io {ADC_OEB_bar_CH[7]} -pinname B12 -fixed yes -DIRECTION Inout
101
102 set_io ADC_smpclk -pinname A15 -fixed yes -DIRECTION Inout
103
104 set_io HK_smpclk -pinname R11 -fixed yes -DIRECTION Inout
105 set_io ADC_OEB_bar_HK -pinname D14 -fixed yes -DIRECTION Inout
106 set_io {HK_SEL[0]} -pinname A2 -fixed yes -DIRECTION Inout
107 set_io {HK_SEL[1]} -pinname C3 -fixed yes -DIRECTION Inout
108
109 set_io {ADC_data[0]} -pinname A16 -fixed yes -DIRECTION Inout
110 set_io {ADC_data[1]} -pinname B16 -fixed yes -DIRECTION Inout
111 set_io {ADC_data[2]} -pinname A17 -fixed yes -DIRECTION Inout
112 set_io {ADC_data[3]} -pinname C12 -fixed yes -DIRECTION Inout
113 set_io {ADC_data[4]} -pinname B17 -fixed yes -DIRECTION Inout
114 set_io {ADC_data[5]} -pinname C13 -fixed yes -DIRECTION Inout
115 set_io {ADC_data[6]} -pinname D15 -fixed yes -DIRECTION Inout
116 set_io {ADC_data[7]} -pinname E15 -fixed yes -DIRECTION Inout
117 set_io {ADC_data[8]} -pinname D16 -fixed yes -DIRECTION Inout
118 set_io {ADC_data[9]} -pinname F16 -fixed yes -DIRECTION Inout
119 set_io {ADC_data[10]} -pinname F15 -fixed yes -DIRECTION Inout
120 set_io {ADC_data[11]} -pinname G16 -fixed yes -DIRECTION Inout
121 set_io {ADC_data[12]} -pinname F13 -fixed yes -DIRECTION Inout
122 set_io {ADC_data[13]} -pinname G13 -fixed yes -DIRECTION Inout
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@@ -0,0 +1,124
1 set_io clk49_152MHz -pinname D5 -fixed yes -DIRECTION Inout
2 set_io clk50MHz -pinname B3 -fixed yes -DIRECTION Inout
3 set_io reset -pinname R4 -fixed yes -DIRECTION Inout -SCHMITT_TRIGGER On
4
5 set_io {address[0]} -pinname U3 -fixed yes -DIRECTION Inout
6 set_io {address[1]} -pinname V14 -fixed yes -DIRECTION Inout
7 set_io {address[2]} -pinname V13 -fixed yes -DIRECTION Inout
8 set_io {address[3]} -pinname V16 -fixed yes -DIRECTION Inout
9 set_io {address[4]} -pinname N9 -fixed yes -DIRECTION Inout
10 set_io {address[5]} -pinname T11 -fixed yes -DIRECTION Inout
11 set_io {address[6]} -pinname U13 -fixed yes -DIRECTION Inout
12 set_io {address[7]} -pinname R5 -fixed yes -DIRECTION Inout
13 set_io {address[8]} -pinname U2 -fixed yes -DIRECTION Inout
14 set_io {address[9]} -pinname N11 -fixed yes -DIRECTION Inout
15 set_io {address[10]} -pinname R13 -fixed yes -DIRECTION Inout
16 set_io {address[11]} -pinname R12 -fixed yes -DIRECTION Inout
17 set_io {address[12]} -pinname M15 -fixed yes -DIRECTION Inout
18 set_io {address[13]} -pinname T12 -fixed yes -DIRECTION Inout
19 set_io {address[14]} -pinname M13 -fixed yes -DIRECTION Inout
20 set_io {address[15]} -pinname T13 -fixed yes -DIRECTION Inout
21 set_io {address[16]} -pinname L13 -fixed yes -DIRECTION Inout
22 set_io {address[17]} -pinname V17 -fixed yes -DIRECTION Inout
23 set_io {address[18]} -pinname V15 -fixed yes -DIRECTION Inout
24
25 set_io {data[0]} -pinname V4 -fixed yes -DIRECTION Inout
26 set_io {data[1]} -pinname V3 -fixed yes -DIRECTION Inout
27 set_io {data[2]} -pinname V2 -fixed yes -DIRECTION Inout
28 set_io {data[3]} -pinname T3 -fixed yes -DIRECTION Inout
29 set_io {data[4]} -pinname N6 -fixed yes -DIRECTION Inout
30 set_io {data[5]} -pinname P6 -fixed yes -DIRECTION Inout
31 set_io {data[6]} -pinname R6 -fixed yes -DIRECTION Inout
32 set_io {data[7]} -pinname T4 -fixed yes -DIRECTION Inout
33 set_io {data[8]} -pinname T1 -fixed yes -DIRECTION Inout
34 set_io {data[9]} -pinname R1 -fixed yes -DIRECTION Inout
35 set_io {data[10]} -pinname P1 -fixed yes -DIRECTION Inout
36 set_io {data[11]} -pinname N2 -fixed yes -DIRECTION Inout
37 set_io {data[12]} -pinname R3 -fixed yes -DIRECTION Inout
38 set_io {data[13]} -pinname P4 -fixed yes -DIRECTION Inout
39 set_io {data[14]} -pinname N4 -fixed yes -DIRECTION Inout
40 set_io {data[15]} -pinname N3 -fixed yes -DIRECTION Inout
41 set_io {data[16]} -pinname G12 -fixed yes -DIRECTION Inout
42 set_io {data[17]} -pinname G15 -fixed yes -DIRECTION Inout
43 set_io {data[18]} -pinname H15 -fixed yes -DIRECTION Inout
44 set_io {data[19]} -pinname F17 -fixed yes -DIRECTION Inout
45 set_io {data[20]} -pinname F18 -fixed yes -DIRECTION Inout
46 set_io {data[21]} -pinname G17 -fixed yes -DIRECTION Inout
47 set_io {data[22]} -pinname H18 -fixed yes -DIRECTION Inout
48 set_io {data[23]} -pinname J18 -fixed yes -DIRECTION Inout
49 set_io {data[24]} -pinname R18 -fixed yes -DIRECTION Inout
50 set_io {data[25]} -pinname N18 -fixed yes -DIRECTION Inout
51 set_io {data[26]} -pinname P17 -fixed yes -DIRECTION Inout
52 set_io {data[27]} -pinname N17 -fixed yes -DIRECTION Inout
53 set_io {data[28]} -pinname T18 -fixed yes -DIRECTION Inout
54 set_io {data[29]} -pinname M17 -fixed yes -DIRECTION Inout
55 set_io {data[30]} -pinname U18 -fixed yes -DIRECTION Inout
56 set_io {data[31]} -pinname L18 -fixed yes -DIRECTION Inout
57
58 set_io nSRAM_MBE -pinname E4 -fixed yes -DIRECTION Inout
59 set_io nSRAM_E1 -pinname D1 -fixed yes -DIRECTION Inout
60 set_io nSRAM_E2 -pinname C1 -fixed yes -DIRECTION Inout
61 #set_io nSRAM_SCRUB -pinname C2 -fixed yes -DIRECTION Inout
62 set_io nSRAM_W -pinname D4 -fixed yes -DIRECTION Inout
63 set_io nSRAM_G -pinname E1 -fixed yes -DIRECTION Inout
64 set_io nSRAM_BUSY -pinname F4 -fixed yes -DIRECTION Inout
65
66 set_io spw1_en -pinname G4 -fixed yes -DIRECTION Inout
67 set_io spw1_din -pinname D13 -fixed yes -DIRECTION Inout
68 set_io spw1_sin -pinname D14 -fixed yes -DIRECTION Inout
69 set_io spw1_dout -pinname C16 -fixed yes -DIRECTION Inout
70 set_io spw1_sout -pinname C4 -fixed yes -DIRECTION Inout
71
72 set_io spw2_en -pinname G3 -fixed yes -DIRECTION Inout
73 set_io spw2_din -pinname E6 -fixed yes -DIRECTION Inout
74 set_io spw2_sin -pinname C15 -fixed yes -DIRECTION Inout
75 set_io spw2_dout -pinname B7 -fixed yes -DIRECTION Inout
76 set_io spw2_sout -pinname D7 -fixed yes -DIRECTION Inout
77
78 set_io {TAG[1]} -pinname J12 -fixed yes -DIRECTION Inout
79 set_io {TAG[2]} -pinname K12 -fixed yes -DIRECTION Inout
80 set_io {TAG[3]} -pinname K13 -fixed yes -DIRECTION Inout
81 set_io {TAG[4]} -pinname L16 -fixed yes -DIRECTION Inout
82 set_io {TAG[5]} -pinname L15 -fixed yes -DIRECTION Inout
83 set_io {TAG[6]} -pinname M16 -fixed yes -DIRECTION Inout
84 set_io {TAG[7]} -pinname J14 -fixed yes -DIRECTION Inout
85 set_io {TAG[8]} -pinname K15 -fixed yes -DIRECTION Inout
86 set_io {TAG[9]} -pinname J17 -fixed yes -DIRECTION Inout
87
88 set_io bias_fail_sw -pinname A3 -fixed yes -DIRECTION Inout
89
90 set_io {ADC_OEB_bar_CH[0]} -pinname A10 -fixed yes -DIRECTION Inout
91 set_io {ADC_OEB_bar_CH[1]} -pinname B10 -fixed yes -DIRECTION Inout
92 set_io {ADC_OEB_bar_CH[2]} -pinname B12 -fixed yes -DIRECTION Inout
93 set_io {ADC_OEB_bar_CH[3]} -pinname A11 -fixed yes -DIRECTION Inout
94 set_io {ADC_OEB_bar_CH[4]} -pinname B13 -fixed yes -DIRECTION Inout
95 set_io {ADC_OEB_bar_CH[5]} -pinname C6 -fixed yes -DIRECTION Inout
96 set_io {ADC_OEB_bar_CH[6]} -pinname A13 -fixed yes -DIRECTION Inout
97 set_io {ADC_OEB_bar_CH[7]} -pinname A14 -fixed yes -DIRECTION Inout
98
99 set_io ADC_smpclk -pinname A15 -fixed yes -DIRECTION Inout
100
101 set_io HK_smpclk -pinname R11 -fixed yes -DIRECTION Inout
102 set_io ADC_OEB_bar_HK -pinname D6 -fixed yes -DIRECTION Inout
103 set_io {HK_SEL[0]} -pinname C3 -fixed yes -DIRECTION Inout
104 set_io {HK_SEL[1]} -pinname A2 -fixed yes -DIRECTION Inout
105
106 #set_io {ADC_data[0]} -pinname G13 -fixed yes -DIRECTION Inout
107 #set_io {ADC_data[1]} -pinname G16 -fixed yes -DIRECTION Inout
108 #set_io {ADC_data[2]} -pinname F16 -fixed yes -DIRECTION Inout
109 #set_io {ADC_data[3]} -pinname E15 -fixed yes -DIRECTION Inout
110 #set_io {ADC_data[4]} -pinname F13 -fixed yes -DIRECTION Inout
111 #set_io {ADC_data[5]} -pinname F15 -fixed yes -DIRECTION Inout
112 #set_io {ADC_data[6]} -pinname D16 -fixed yes -DIRECTION Inout
113 #set_io {ADC_data[7]} -pinname D15 -fixed yes -DIRECTION Inout
114 #set_io {ADC_data[8]} -pinname B17 -fixed yes -DIRECTION Inout
115 #set_io {ADC_data[9]} -pinname A17 -fixed yes -DIRECTION Inout
116 #set_io {ADC_data[10]} -pinname A16 -fixed yes -DIRECTION Inout
117 #set_io {ADC_data[11]} -pinname B16 -fixed yes -DIRECTION Inout
118 #set_io {ADC_data[12]} -pinname C12 -fixed yes -DIRECTION Inout
119 #set_io {ADC_data[13]} -pinname C13 -fixed yes -DIRECTION Inout
120
121 set_io DAC_SDO -pinname A4 -fixed yes -DIRECTION Inout
122 set_io DAC_SCK -pinname A5 -fixed yes -DIRECTION Inout
123 set_io DAC_SYNC -pinname B6 -fixed yes -DIRECTION Inout
124 set_io DAC_CAL_EN -pinname A6 -fixed yes -DIRECTION Inout
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@@ -0,0 +1,123
1 set_io clk50MHz -pinname B3 -fixed yes -DIRECTION Inout
2 set_io reset -pinname R4 -fixed yes -DIRECTION Inout -SCHMITT_TRIGGER On
3
4 set_io {address[0]} -pinname U3 -fixed yes -DIRECTION Inout
5 set_io {address[1]} -pinname V14 -fixed yes -DIRECTION Inout
6 set_io {address[2]} -pinname V13 -fixed yes -DIRECTION Inout
7 set_io {address[3]} -pinname V16 -fixed yes -DIRECTION Inout
8 set_io {address[4]} -pinname N9 -fixed yes -DIRECTION Inout
9 set_io {address[5]} -pinname T11 -fixed yes -DIRECTION Inout
10 set_io {address[6]} -pinname U13 -fixed yes -DIRECTION Inout
11 set_io {address[7]} -pinname R5 -fixed yes -DIRECTION Inout
12 set_io {address[8]} -pinname U2 -fixed yes -DIRECTION Inout
13 set_io {address[9]} -pinname N11 -fixed yes -DIRECTION Inout
14 set_io {address[10]} -pinname R13 -fixed yes -DIRECTION Inout
15 set_io {address[11]} -pinname R12 -fixed yes -DIRECTION Inout
16 set_io {address[12]} -pinname M15 -fixed yes -DIRECTION Inout
17 set_io {address[13]} -pinname T12 -fixed yes -DIRECTION Inout
18 set_io {address[14]} -pinname M13 -fixed yes -DIRECTION Inout
19 set_io {address[15]} -pinname T13 -fixed yes -DIRECTION Inout
20 set_io {address[16]} -pinname L13 -fixed yes -DIRECTION Inout
21 set_io {address[17]} -pinname V17 -fixed yes -DIRECTION Inout
22 set_io {address[18]} -pinname V15 -fixed yes -DIRECTION Inout
23
24 set_io {data[0]} -pinname V4 -fixed yes -DIRECTION Inout
25 set_io {data[1]} -pinname V3 -fixed yes -DIRECTION Inout
26 set_io {data[2]} -pinname V2 -fixed yes -DIRECTION Inout
27 set_io {data[3]} -pinname T3 -fixed yes -DIRECTION Inout
28 set_io {data[4]} -pinname N6 -fixed yes -DIRECTION Inout
29 set_io {data[5]} -pinname P6 -fixed yes -DIRECTION Inout
30 set_io {data[6]} -pinname R6 -fixed yes -DIRECTION Inout
31 set_io {data[7]} -pinname T4 -fixed yes -DIRECTION Inout
32 set_io {data[8]} -pinname T1 -fixed yes -DIRECTION Inout
33 set_io {data[9]} -pinname R1 -fixed yes -DIRECTION Inout
34 set_io {data[10]} -pinname P1 -fixed yes -DIRECTION Inout
35 set_io {data[11]} -pinname N2 -fixed yes -DIRECTION Inout
36 set_io {data[12]} -pinname R3 -fixed yes -DIRECTION Inout
37 set_io {data[13]} -pinname P4 -fixed yes -DIRECTION Inout
38 set_io {data[14]} -pinname N4 -fixed yes -DIRECTION Inout
39 set_io {data[15]} -pinname N3 -fixed yes -DIRECTION Inout
40 set_io {data[16]} -pinname G12 -fixed yes -DIRECTION Inout
41 set_io {data[17]} -pinname G15 -fixed yes -DIRECTION Inout
42 set_io {data[18]} -pinname H15 -fixed yes -DIRECTION Inout
43 set_io {data[19]} -pinname F17 -fixed yes -DIRECTION Inout
44 set_io {data[20]} -pinname F18 -fixed yes -DIRECTION Inout
45 set_io {data[21]} -pinname G17 -fixed yes -DIRECTION Inout
46 set_io {data[22]} -pinname H18 -fixed yes -DIRECTION Inout
47 set_io {data[23]} -pinname J18 -fixed yes -DIRECTION Inout
48 set_io {data[24]} -pinname R18 -fixed yes -DIRECTION Inout
49 set_io {data[25]} -pinname N18 -fixed yes -DIRECTION Inout
50 set_io {data[26]} -pinname P17 -fixed yes -DIRECTION Inout
51 set_io {data[27]} -pinname N17 -fixed yes -DIRECTION Inout
52 set_io {data[28]} -pinname T18 -fixed yes -DIRECTION Inout
53 set_io {data[29]} -pinname M17 -fixed yes -DIRECTION Inout
54 set_io {data[30]} -pinname U18 -fixed yes -DIRECTION Inout
55 set_io {data[31]} -pinname L18 -fixed yes -DIRECTION Inout
56
57 set_io nSRAM_MBE -pinname E4 -fixed yes -DIRECTION Inout
58 set_io nSRAM_E1 -pinname D1 -fixed yes -DIRECTION Inout
59 set_io nSRAM_E2 -pinname C1 -fixed yes -DIRECTION Inout
60 #set_io nSRAM_SCRUB -pinname C2 -fixed yes -DIRECTION Inout
61 set_io nSRAM_W -pinname D4 -fixed yes -DIRECTION Inout
62 set_io nSRAM_G -pinname E1 -fixed yes -DIRECTION Inout
63 set_io nSRAM_BUSY -pinname F4 -fixed yes -DIRECTION Inout
64
65 set_io spw1_en -pinname G4 -fixed yes -DIRECTION Inout
66 set_io spw1_din -pinname D13 -fixed yes -DIRECTION Inout
67 set_io spw1_sin -pinname D14 -fixed yes -DIRECTION Inout
68 set_io spw1_dout -pinname C16 -fixed yes -DIRECTION Inout
69 set_io spw1_sout -pinname C4 -fixed yes -DIRECTION Inout
70
71 set_io spw2_en -pinname G3 -fixed yes -DIRECTION Inout
72 set_io spw2_din -pinname E6 -fixed yes -DIRECTION Inout
73 set_io spw2_sin -pinname C15 -fixed yes -DIRECTION Inout
74 set_io spw2_dout -pinname B7 -fixed yes -DIRECTION Inout
75 set_io spw2_sout -pinname D7 -fixed yes -DIRECTION Inout
76
77 set_io TAG1 -pinname J12 -fixed yes -DIRECTION Inout
78 set_io TAG2 -pinname K12 -fixed yes -DIRECTION Inout
79 set_io TAG3 -pinname K13 -fixed yes -DIRECTION Inout
80 set_io TAG4 -pinname L16 -fixed yes -DIRECTION Inout
81 #set_io TAG5 -pinname L15 -fixed yes -DIRECTION Inout
82 #set_io TAG6 -pinname M16 -fixed yes -DIRECTION Inout
83 #set_io TAG7 -pinname J14 -fixed yes -DIRECTION Inout
84 set_io TAG8 -pinname K15 -fixed yes -DIRECTION Inout
85 #set_io TAG9 -pinname J17 -fixed yes -DIRECTION Inout
86
87 set_io bias_fail_sw -pinname A3 -fixed yes -DIRECTION Inout
88
89 set_io {ADC_OEB_bar_CH[0]} -pinname A10 -fixed yes -DIRECTION Inout
90 set_io {ADC_OEB_bar_CH[1]} -pinname B10 -fixed yes -DIRECTION Inout
91 set_io {ADC_OEB_bar_CH[2]} -pinname B12 -fixed yes -DIRECTION Inout
92 set_io {ADC_OEB_bar_CH[3]} -pinname A11 -fixed yes -DIRECTION Inout
93 set_io {ADC_OEB_bar_CH[4]} -pinname B13 -fixed yes -DIRECTION Inout
94 set_io {ADC_OEB_bar_CH[5]} -pinname C6 -fixed yes -DIRECTION Inout
95 set_io {ADC_OEB_bar_CH[6]} -pinname A13 -fixed yes -DIRECTION Inout
96 set_io {ADC_OEB_bar_CH[7]} -pinname A14 -fixed yes -DIRECTION Inout
97
98 set_io ADC_smpclk -pinname A15 -fixed yes -DIRECTION Inout
99
100 set_io HK_smpclk -pinname R11 -fixed yes -DIRECTION Inout
101 set_io ADC_OEB_bar_HK -pinname D6 -fixed yes -DIRECTION Inout
102 set_io {HK_SEL[0]} -pinname C3 -fixed yes -DIRECTION Inout
103 set_io {HK_SEL[1]} -pinname A2 -fixed yes -DIRECTION Inout
104
105 set_io {ADC_data[0]} -pinname G13 -fixed yes -DIRECTION Inout
106 set_io {ADC_data[1]} -pinname G16 -fixed yes -DIRECTION Inout
107 set_io {ADC_data[2]} -pinname F16 -fixed yes -DIRECTION Inout
108 set_io {ADC_data[3]} -pinname E15 -fixed yes -DIRECTION Inout
109 set_io {ADC_data[4]} -pinname F13 -fixed yes -DIRECTION Inout
110 set_io {ADC_data[5]} -pinname F15 -fixed yes -DIRECTION Inout
111 set_io {ADC_data[6]} -pinname D16 -fixed yes -DIRECTION Inout
112 set_io {ADC_data[7]} -pinname D15 -fixed yes -DIRECTION Inout
113 set_io {ADC_data[8]} -pinname B17 -fixed yes -DIRECTION Inout
114 set_io {ADC_data[9]} -pinname A17 -fixed yes -DIRECTION Inout
115 set_io {ADC_data[10]} -pinname A16 -fixed yes -DIRECTION Inout
116 set_io {ADC_data[11]} -pinname B16 -fixed yes -DIRECTION Inout
117 set_io {ADC_data[12]} -pinname C12 -fixed yes -DIRECTION Inout
118 set_io {ADC_data[13]} -pinname C13 -fixed yes -DIRECTION Inout
119
120 set_io DAC_SDO -pinname A4 -fixed yes -DIRECTION Inout
121 set_io DAC_SCK -pinname A5 -fixed yes -DIRECTION Inout
122 set_io DAC_SYNC -pinname B6 -fixed yes -DIRECTION Inout
123 set_io DAC_CAL_EN -pinname A6 -fixed yes -DIRECTION Inout
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1 ################################################################################
2 # SDC WRITER VERSION "3.1";
3 # DESIGN "LFR_EQM";
4 # Timing constraints scenario: "Primary";
5 # DATE "Fri Jul 24 14:50:40 2015";
6 # VENDOR "Actel";
7 # PROGRAM "Actel Designer Software Release v9.1 SP5";
8 # VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp.
9 ################################################################################
10
11
12 set sdc_version 1.7
13
14
15 ######## Clock Constraints ########
16
17 create_clock -name { clk50MHz } -period 20.000 -waveform { 0.000 10.000 } { clk50MHz }
18
19 create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz }
20
21 create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_pad_25/U0:Y }
22
23 create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q }
24
25 create_clock -name { spw_inputloop.1.spw_phy0/rxclki_1_0:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_1:Y }
26
27 create_clock -name { spw_inputloop.0.spw_phy0/rxclki_1_0:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_1:Y }
28
29
30
31 ######## Generated Clock Constraints ########
32
33
34
35 ######## Clock Source Latency Constraints #########
36
37
38
39 ######## Input Delay Constraints ########
40
41
42
43 ######## Output Delay Constraints ########
44 set_max_delay 10.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address }]
45
46 set_min_delay 10.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 }]
47
48
49
50 ######## Delay Constraints ########
51
52
53
54 ######## Delay Constraints ########
55
56
57
58 ######## Multicycle Constraints ########
59
60
61
62 ######## False Path Constraints ########
63
64
65
66 ######## Output load Constraints ########
67
68
69
70 ######## Disable Timing Constraints #########
71
72
73
74 ######## Clock Uncertainty Constraints #########
75
76
77
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1 ################################################################################
2 # SDC WRITER VERSION "3.1";
3 # DESIGN "LFR_EQM";
4 # Timing constraints scenario: "Primary";
5 # DATE "Tue May 19 15:46:14 2015";
6 # VENDOR "Actel";
7 # PROGRAM "Actel Designer Software Release v9.1 SP5";
8 # VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp.
9 ################################################################################
10
11
12 set sdc_version 1.7
13
14
15 ######## Clock Constraints ########
16
17 create_clock -name { clk50MHz } -period 20.000 -waveform { 0.000 10.000 } { clk50MHz }
18
19 create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz }
20
21 create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_25:Q }
22
23 create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q }
24
25 create_clock -name { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_RNO:Y }
26
27 create_clock -name { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_RNO:Y }
28
29
30
31 ######## Generated Clock Constraints ########
32
33
34
35 ######## Clock Source Latency Constraints #########
36
37
38
39 ######## Input Delay Constraints ########
40
41 set_input_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
42
43 set_input_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BUSY }]
44
45 set_input_delay -max 35.000 -clock { clk_25:Q } [get_ports { ADC_data[0] ADC_data[10] ADC_data[11] ADC_data[12] ADC_data[13] ADC_data[1] ADC_data[2] ADC_data[3] ADC_data[4] ADC_data[5] ADC_data[6] ADC_data[7] ADC_data[8] ADC_data[9] }]
46 set_input_delay -min 15.000 -clock { clk_25:Q } [get_ports { ADC_data[0] ADC_data[10] ADC_data[11] ADC_data[12] ADC_data[13] ADC_data[1] ADC_data[2] ADC_data[3] ADC_data[4] ADC_data[5] ADC_data[6] ADC_data[7] ADC_data[8] ADC_data[9] }]
47
48
49
50 ######## Output Delay Constraints ########
51
52 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
53
54 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { address[0] address[10] address[11] address[12] address[13] address[14] address[15] address[16] address[17] address[18] address[1] address[2] address[3] address[4] address[5] address[6] address[7] address[8] address[9] }]
55
56 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
57
58 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_G }]
59
60 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_MBE }]
61
62 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { ADC_OEB_bar_CH[0] ADC_OEB_bar_CH[1] ADC_OEB_bar_CH[2] ADC_OEB_bar_CH[3] ADC_OEB_bar_CH[4] ADC_OEB_bar_CH[5] ADC_OEB_bar_CH[6] ADC_OEB_bar_CH[7] ADC_OEB_bar_HK }]
63 set_max_delay 25.000 -from [get_clocks {clk_25:Q}] -to [get_ports { ADC_OEB_bar_CH[0] \
64 ADC_OEB_bar_CH[1] ADC_OEB_bar_CH[2] ADC_OEB_bar_CH[3] ADC_OEB_bar_CH[4] \
65 ADC_OEB_bar_CH[5] ADC_OEB_bar_CH[6] ADC_OEB_bar_CH[7] ADC_OEB_bar_HK }]
66 set_min_delay 8.000 -from [get_clocks {clk_25:Q}] -to [get_ports { ADC_OEB_bar_CH[0] \
67 ADC_OEB_bar_CH[1] ADC_OEB_bar_CH[2] ADC_OEB_bar_CH[3] ADC_OEB_bar_CH[4] \
68 ADC_OEB_bar_CH[5] ADC_OEB_bar_CH[6] ADC_OEB_bar_CH[7] ADC_OEB_bar_HK }]
69
70
71
72 ######## Delay Constraints ########
73
74 set_max_delay 30.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \
75 data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \
76 data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \
77 data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}]
78
79 set_max_delay 12.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
80
81 set_max_delay 12.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \
82 data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \
83 data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \
84 data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
85
86 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \
87 address[11] address[12] address[13] address[14] address[15] address[16] address[17] \
88 address[18] address[1] address[2] address[3] address[4] address[5] address[6] \
89 address[7] address[8] address[9] }]
90
91 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
92
93 set_max_delay 30.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }]
94
95 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }]
96
97 set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to \
98 [get_clocks {spw_inputloop.0.spw_phy0/rxclki_RNO:Y}]
99
100 set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to \
101 [get_clocks {spw_inputloop.1.spw_phy0/rxclki_RNO:Y}]
102
103
104
105 ######## Delay Constraints ########
106
107 set_min_delay 0.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \
108 data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \
109 data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \
110 data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}]
111
112 set_min_delay 0.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
113
114 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \
115 data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \
116 data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \
117 data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
118
119 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \
120 address[11] address[12] address[13] address[14] address[15] address[16] address[17] \
121 address[18] address[1] address[2] address[3] address[4] address[5] address[6] \
122 address[7] address[8] address[9] }]
123
124 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
125
126 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }]
127
128 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }]
129
130
131
132 ######## Multicycle Constraints ########
133
134
135
136 ######## False Path Constraints ########
137
138
139
140 ######## Output load Constraints ########
141
142
143
144 ######## Disable Timing Constraints #########
145
146
147
148 ######## Clock Uncertainty Constraints #########
149
150
151
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1 ################################################################################
2 # SDC WRITER VERSION "3.1";
3 # DESIGN "LFR_EQM";
4 # Timing constraints scenario: "Primary";
5 # DATE "Tue May 05 13:46:34 2015";
6 # VENDOR "Actel";
7 # PROGRAM "Actel Designer Software Release v9.1 SP5";
8 # VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp.
9 ################################################################################
10
11
12 set sdc_version 1.7
13
14
15 ######## Clock Constraints ########
16
17 create_clock -name { clk50MHz } -period 20.000 -waveform { 0.000 10.000 } { clk50MHz }
18
19 create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz }
20
21 create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_25:Q }
22
23 create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q }
24
25 create_clock -name { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_RNO:Y }
26
27 create_clock -name { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_RNO:Y }
28
29
30
31 ######## Generated Clock Constraints ########
32
33
34
35 ######## Clock Source Latency Constraints #########
36
37
38
39 ######## Input Delay Constraints ########
40
41 set_input_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
42
43 set_input_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BUSY }]
44
45 set_input_delay -max 20.000 -clock { clk_25:Q } [get_ports { ADC_data[0] ADC_data[10] ADC_data[11] ADC_data[12] ADC_data[13] ADC_data[1] ADC_data[2] ADC_data[3] ADC_data[4] ADC_data[5] ADC_data[6] ADC_data[7] ADC_data[8] ADC_data[9] }]
46
47
48
49 ######## Output Delay Constraints ########
50
51 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
52
53 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { address[0] address[10] address[11] address[12] address[13] address[14] address[15] address[16] address[17] address[18] address[1] address[2] address[3] address[4] address[5] address[6] address[7] address[8] address[9] }]
54
55 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
56
57 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_G }]
58
59 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_MBE }]
60
61 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { ADC_OEB_bar_CH[0] ADC_OEB_bar_CH[1] ADC_OEB_bar_CH[2] ADC_OEB_bar_CH[3] ADC_OEB_bar_CH[4] ADC_OEB_bar_CH[5] ADC_OEB_bar_CH[6] ADC_OEB_bar_CH[7] ADC_OEB_bar_HK }]
62 set_max_delay 35.000 -from [get_clocks {clk_25:Q}] -to [get_ports { ADC_OEB_bar_CH[0] \
63 ADC_OEB_bar_CH[1] ADC_OEB_bar_CH[2] ADC_OEB_bar_CH[3] ADC_OEB_bar_CH[4] \
64 ADC_OEB_bar_CH[5] ADC_OEB_bar_CH[6] ADC_OEB_bar_CH[7] ADC_OEB_bar_HK }]
65 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { ADC_OEB_bar_CH[0] \
66 ADC_OEB_bar_CH[1] ADC_OEB_bar_CH[2] ADC_OEB_bar_CH[3] ADC_OEB_bar_CH[4] \
67 ADC_OEB_bar_CH[5] ADC_OEB_bar_CH[6] ADC_OEB_bar_CH[7] ADC_OEB_bar_HK }]
68
69
70
71 ######## Delay Constraints ########
72
73 set_max_delay 30.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \
74 data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \
75 data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \
76 data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}]
77
78 set_max_delay 10.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
79
80 set_max_delay 10.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \
81 data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \
82 data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \
83 data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
84
85 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \
86 address[11] address[12] address[13] address[14] address[15] address[16] address[17] \
87 address[18] address[1] address[2] address[3] address[4] address[5] address[6] \
88 address[7] address[8] address[9] }]
89
90 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
91
92 set_max_delay 30.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }]
93
94 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }]
95
96 set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to \
97 [get_clocks {spw_inputloop.0.spw_phy0/rxclki_RNO:Y}]
98
99 set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to \
100 [get_clocks {spw_inputloop.1.spw_phy0/rxclki_RNO:Y}]
101
102
103
104 ######## Delay Constraints ########
105
106 set_min_delay 0.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \
107 data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \
108 data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \
109 data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}]
110
111 set_min_delay 0.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
112
113 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \
114 data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \
115 data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \
116 data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
117
118 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \
119 address[11] address[12] address[13] address[14] address[15] address[16] address[17] \
120 address[18] address[1] address[2] address[3] address[4] address[5] address[6] \
121 address[7] address[8] address[9] }]
122
123 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
124
125 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }]
126
127 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }]
128
129
130
131 ######## Multicycle Constraints ########
132
133
134
135 ######## False Path Constraints ########
136
137 set_false_path -from [get_pins { \
138 USE_ADCDRIVER_true.top_ad_conv_RHF1401_withFilter_1/cnv_s_reg:CLK }] -to [get_pins { \
139 USE_ADCDRIVER_true.top_ad_conv_RHF1401_withFilter_1/SYNC_FF_cnv/sync_loop.1.A_temp[1]:D \
140 }]
141 # SYNC PATH of ADC_CNV signal from CLK_domain_24 to CLK_domain_25
142
143
144
145 ######## Output load Constraints ########
146
147
148
149 ######## Disable Timing Constraints #########
150
151
152
153 ######## Clock Uncertainty Constraints #########
154
155
156
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1 ################################################################################
2 # SDC WRITER VERSION "3.1";
3 # DESIGN "LFR_EQM";
4 # Timing constraints scenario: "Primary";
5 # DATE "Fri Apr 24 16:02:16 2015";
6 # VENDOR "Actel";
7 # PROGRAM "Actel Designer Software Release v9.1 SP5";
8 # VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp.
9 ################################################################################
10
11
12 set sdc_version 1.7
13
14
15 ######## Clock Constraints ########
16
17 create_clock -name { clk50MHz } -period 20.000 -waveform { 0.000 10.000 } { clk50MHz }
18
19 create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz }
20
21 create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_25:Q }
22
23 create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q }
24
25 create_clock -name { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_RNO:Y }
26
27 create_clock -name { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_RNO:Y }
28
29
30
31 ######## Generated Clock Constraints ########
32
33
34
35 ######## Clock Source Latency Constraints #########
36
37
38
39 ######## Input Delay Constraints ########
40
41 set_input_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
42 set_max_delay 30.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \
43 data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \
44 data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \
45 data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}]
46 set_min_delay 0.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \
47 data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \
48 data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \
49 data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}]
50
51 set_input_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BUSY }]
52 set_max_delay 10.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
53 set_min_delay 0.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
54
55
56
57 ######## Output Delay Constraints ########
58
59 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
60 set_max_delay 10.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \
61 data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \
62 data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \
63 data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
64 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \
65 data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \
66 data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \
67 data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
68
69 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { address[0] address[10] address[11] address[12] address[13] address[14] address[15] address[16] address[17] address[18] address[1] address[2] address[3] address[4] address[5] address[6] address[7] address[8] address[9] }]
70 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \
71 address[11] address[12] address[13] address[14] address[15] address[16] address[17] \
72 address[18] address[1] address[2] address[3] address[4] address[5] address[6] \
73 address[7] address[8] address[9] }]
74 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \
75 address[11] address[12] address[13] address[14] address[15] address[16] address[17] \
76 address[18] address[1] address[2] address[3] address[4] address[5] address[6] \
77 address[7] address[8] address[9] }]
78
79 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
80 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
81 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
82
83 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_G }]
84 set_max_delay 30.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }]
85 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }]
86
87 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_MBE }]
88 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }]
89 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }]
90
91
92
93 ######## Delay Constraints ########
94
95 set_max_delay 4.000 -from [get_ports { clk50MHz ADC_data spw2_sin spw2_din spw1_sin spw1_din \
96 nSRAM_BUSY data TAG2 TAG1 reset clk49_152MHz }] -to [get_clocks \
97 {spw_inputloop.0.spw_phy0/rxclki_RNO:Y}]
98
99 set_max_delay 4.000 -from [get_ports { clk50MHz ADC_data spw2_sin spw2_din spw1_sin spw1_din \
100 nSRAM_BUSY data TAG2 TAG1 reset clk49_152MHz }] -to [get_clocks \
101 {spw_inputloop.1.spw_phy0/rxclki_RNO:Y}]
102
103
104
105 ######## Delay Constraints ########
106
107
108
109 ######## Multicycle Constraints ########
110
111
112
113 ######## False Path Constraints ########
114
115
116
117 ######## Output load Constraints ########
118
119
120
121 ######## Disable Timing Constraints #########
122
123
124
125 ######## Clock Uncertainty Constraints #########
126
127
128
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1 ################################################################################
2 # SDC WRITER VERSION "3.1";
3 # DESIGN "LFR_EQM";
4 # Timing constraints scenario: "Primary";
5 # DATE "Fri Apr 24 16:02:16 2015";
6 # VENDOR "Actel";
7 # PROGRAM "Actel Designer Software Release v9.1 SP5";
8 # VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp.
9 ################################################################################
10
11
12 set sdc_version 1.7
13
14
15 ######## Clock Constraints ########
16
17 create_clock -name { clk50MHz } -period 20.000 -waveform { 0.000 10.000 } { clk50MHz }
18
19 create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz }
20
21 create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_25:Q }
22
23 create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q }
24
25
26 create_clock -name { spw_inputloop.0.spw_phy0/rxclki_1_0:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_1_0:Y }
27
28 create_clock -name { spw_inputloop.1.spw_phy0/rxclki_1_0:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_1_0:Y }
29
30
31
32 ######## Generated Clock Constraints ########
33
34
35
36 ######## Clock Source Latency Constraints #########
37
38
39
40 ######## Input Delay Constraints ########
41
42 set_input_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
43 set_max_delay 30.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \
44 data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \
45 data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \
46 data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}]
47 set_min_delay 0.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \
48 data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \
49 data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \
50 data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}]
51
52 set_input_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BUSY }]
53 set_max_delay 10.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
54 set_min_delay 0.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
55
56
57
58 ######## Output Delay Constraints ########
59
60 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
61 set_max_delay 10.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \
62 data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \
63 data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \
64 data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
65 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \
66 data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \
67 data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \
68 data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
69
70 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { address[0] address[10] address[11] address[12] address[13] address[14] address[15] address[16] address[17] address[18] address[1] address[2] address[3] address[4] address[5] address[6] address[7] address[8] address[9] }]
71 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \
72 address[11] address[12] address[13] address[14] address[15] address[16] address[17] \
73 address[18] address[1] address[2] address[3] address[4] address[5] address[6] \
74 address[7] address[8] address[9] }]
75 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \
76 address[11] address[12] address[13] address[14] address[15] address[16] address[17] \
77 address[18] address[1] address[2] address[3] address[4] address[5] address[6] \
78 address[7] address[8] address[9] }]
79
80 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
81 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
82 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
83
84 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_G }]
85 set_max_delay 30.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }]
86 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }]
87
88 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_MBE }]
89 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }]
90 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }]
91
92
93
94 ######## Delay Constraints ########
95
96 set_max_delay 4.000 -from [get_ports { clk50MHz ADC_data spw2_sin spw2_din spw1_sin spw1_din \
97 nSRAM_BUSY data TAG2 TAG1 reset clk49_152MHz }] -to [get_clocks \
98 {spw_inputloop.0.spw_phy0/rxclki_1_0:Y}]
99
100 set_max_delay 4.000 -from [get_ports { clk50MHz ADC_data spw2_sin spw2_din spw1_sin spw1_din \
101 nSRAM_BUSY data TAG2 TAG1 reset clk49_152MHz }] -to [get_clocks \
102 {spw_inputloop.1.spw_phy0/rxclki_1_0:YY}]
103
104
105
106 ######## Delay Constraints ########
107
108
109
110 ######## Multicycle Constraints ########
111
112
113
114 ######## False Path Constraints ########
115
116
117
118 ######## Output load Constraints ########
119
120
121
122 ######## Disable Timing Constraints #########
123
124
125
126 ######## Clock Uncertainty Constraints #########
127
128
129
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1 ################################################################################
2 # SDC WRITER VERSION "3.1";
3 # DESIGN "LFR_EQM";
4 # Timing constraints scenario: "Primary";
5 # DATE "Fri Apr 24 16:02:16 2015";
6 # VENDOR "Actel";
7 # PROGRAM "Actel Designer Software Release v9.1 SP5";
8 # VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp.
9 ################################################################################
10
11
12 set sdc_version 1.7
13
14
15 ######## Clock Constraints ########
16
17 create_clock -name { clk50MHz } -period 20.000 -waveform { 0.000 10.000 } { clk50MHz }
18
19 ##create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz }
20
21 create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_25:Q }
22
23 ##create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q }
24
25 create_clock -name { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_RNO:Y }
26
27 create_clock -name { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_RNO:Y }
28
29
30
31 ######## Generated Clock Constraints ########
32
33
34
35 ######## Clock Source Latency Constraints #########
36
37
38
39 ######## Input Delay Constraints ########
40
41 set_input_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
42 set_max_delay 30.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \
43 data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \
44 data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \
45 data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}]
46 set_min_delay 0.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \
47 data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \
48 data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \
49 data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}]
50
51 set_input_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BUSY }]
52 set_max_delay 10.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
53 set_min_delay 0.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
54
55
56
57 ######## Output Delay Constraints ########
58
59 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
60 set_max_delay 10.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \
61 data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \
62 data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \
63 data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
64 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \
65 data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \
66 data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \
67 data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
68
69 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { address[0] address[10] address[11] address[12] address[13] address[14] address[15] address[16] address[17] address[18] address[1] address[2] address[3] address[4] address[5] address[6] address[7] address[8] address[9] }]
70 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \
71 address[11] address[12] address[13] address[14] address[15] address[16] address[17] \
72 address[18] address[1] address[2] address[3] address[4] address[5] address[6] \
73 address[7] address[8] address[9] }]
74 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \
75 address[11] address[12] address[13] address[14] address[15] address[16] address[17] \
76 address[18] address[1] address[2] address[3] address[4] address[5] address[6] \
77 address[7] address[8] address[9] }]
78
79 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
80 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
81 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
82
83 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_G }]
84 set_max_delay 30.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }]
85 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }]
86
87 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_MBE }]
88 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }]
89 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }]
90
91
92
93 ######## Delay Constraints ########
94
95 set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to [get_clocks {spw_inputloop.0.spw_phy0/rxclki_RNO:Y}]
96
97 set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to [get_clocks {spw_inputloop.1.spw_phy0/rxclki_RNO:Y}]
98
99
100
101 ######## Delay Constraints ########
102
103
104
105 ######## Multicycle Constraints ########
106
107
108
109 ######## False Path Constraints ########
110
111
112
113 ######## Output load Constraints ########
114
115
116
117 ######## Disable Timing Constraints #########
118
119
120
121 ######## Clock Uncertainty Constraints #########
122
123
124
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1 ################################################################################
2 # SDC WRITER VERSION "3.1";
3 # DESIGN "LFR_EQM";
4 # Timing constraints scenario: "Primary";
5 # DATE "Wed May 13 13:09:37 2015";
6 # VENDOR "Actel";
7 # PROGRAM "Actel Designer Software Release v9.1 SP5";
8 # VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp.
9 ################################################################################
10
11
12 set sdc_version 1.7
13
14
15 ######## Clock Constraints ########
16
17 create_clock -name { clk50MHz } -period 20.000 -waveform { 0.000 10.000 } { clk50MHz }
18
19 create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_25:Q }
20
21 create_clock -name { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_RNO:Y }
22
23 create_clock -name { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_RNO:Y }
24
25
26
27 ######## Generated Clock Constraints ########
28
29
30
31 ######## Clock Source Latency Constraints #########
32
33
34
35 ######## Input Delay Constraints ########
36
37 set_input_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
38
39 set_input_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BUSY }]
40
41 set_input_delay -max 0.000 -clock { clk_25:Q } [get_ports { ADC_data[0] ADC_data[10] ADC_data[11] ADC_data[12] ADC_data[13] ADC_data[1] ADC_data[2] ADC_data[3] ADC_data[4] ADC_data[5] ADC_data[6] ADC_data[7] ADC_data[8] ADC_data[9] }]
42 set_input_delay -min 0.000 -clock { clk_25:Q } [get_ports { ADC_data[0] ADC_data[10] ADC_data[11] ADC_data[12] ADC_data[13] ADC_data[1] ADC_data[2] ADC_data[3] ADC_data[4] ADC_data[5] ADC_data[6] ADC_data[7] ADC_data[8] ADC_data[9] }]
43
44
45
46 ######## Output Delay Constraints ########
47
48 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
49
50 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { address[0] address[10] address[11] address[12] address[13] address[14] address[15] address[16] address[17] address[18] address[1] address[2] address[3] address[4] address[5] address[6] address[7] address[8] address[9] }]
51
52 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
53
54 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_G }]
55
56 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_MBE }]
57
58 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { ADC_OEB_bar_CH[0] ADC_OEB_bar_CH[1] ADC_OEB_bar_CH[2] ADC_OEB_bar_CH[3] ADC_OEB_bar_CH[4] ADC_OEB_bar_CH[5] ADC_OEB_bar_CH[6] ADC_OEB_bar_CH[7] ADC_OEB_bar_HK }]
59
60
61
62 ######## Delay Constraints ########
63
64 set_max_delay 30.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \
65 data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \
66 data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \
67 data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}]
68
69 set_max_delay 10.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
70
71 set_max_delay 10.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \
72 data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \
73 data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \
74 data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
75
76 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \
77 address[11] address[12] address[13] address[14] address[15] address[16] address[17] \
78 address[18] address[1] address[2] address[3] address[4] address[5] address[6] \
79 address[7] address[8] address[9] }]
80
81 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
82
83 set_max_delay 30.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }]
84
85 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }]
86
87 set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to \
88 [get_clocks {spw_inputloop.0.spw_phy0/rxclki_RNO:Y}]
89
90 set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to \
91 [get_clocks {spw_inputloop.1.spw_phy0/rxclki_RNO:Y}]
92
93 set_max_delay 30.000 -from [get_ports { ADC_data[0] ADC_data[10] ADC_data[11] ADC_data[12] \
94 ADC_data[13] ADC_data[1] ADC_data[2] ADC_data[3] ADC_data[4] ADC_data[5] ADC_data[6] \
95 ADC_data[7] ADC_data[8] ADC_data[9] }] -to [get_clocks {clk_25:Q}]
96
97 set_max_delay 15.000 -from [get_clocks {clk_25:Q}] -to [get_ports { ADC_OEB_bar_CH[0] \
98 ADC_OEB_bar_CH[1] ADC_OEB_bar_CH[2] ADC_OEB_bar_CH[3] ADC_OEB_bar_CH[4] \
99 ADC_OEB_bar_CH[5] ADC_OEB_bar_CH[6] ADC_OEB_bar_CH[7] ADC_OEB_bar_HK }]
100
101
102
103 ######## Delay Constraints ########
104
105 set_min_delay 0.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \
106 data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \
107 data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \
108 data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}]
109
110 set_min_delay 0.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
111
112 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \
113 data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \
114 data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \
115 data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
116
117 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \
118 address[11] address[12] address[13] address[14] address[15] address[16] address[17] \
119 address[18] address[1] address[2] address[3] address[4] address[5] address[6] \
120 address[7] address[8] address[9] }]
121
122 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
123
124 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }]
125
126 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }]
127
128 set_min_delay 0.000 -from [get_ports { ADC_data[0] ADC_data[10] ADC_data[11] ADC_data[12] \
129 ADC_data[13] ADC_data[1] ADC_data[2] ADC_data[3] ADC_data[4] ADC_data[5] ADC_data[6] \
130 ADC_data[7] ADC_data[8] ADC_data[9] }] -to [get_clocks {clk_25:Q}]
131
132 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { ADC_OEB_bar_CH[0] \
133 ADC_OEB_bar_CH[1] ADC_OEB_bar_CH[2] ADC_OEB_bar_CH[3] ADC_OEB_bar_CH[4] \
134 ADC_OEB_bar_CH[5] ADC_OEB_bar_CH[6] ADC_OEB_bar_CH[7] ADC_OEB_bar_HK }]
135
136
137
138 ######## Multicycle Constraints ########
139
140
141
142 ######## False Path Constraints ########
143
144
145
146 ######## Output load Constraints ########
147
148
149
150 ######## Disable Timing Constraints #########
151
152
153
154 ######## Clock Uncertainty Constraints #########
155
156
157
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1 # Synplicity, Inc. constraint file
2 # /home/jiri/ibm/vhdl/grlib/boards/actel-coremp7-1000/default.sdc
3 # Written on Wed Aug 1 19:29:24 2007
4 # by Synplify Pro, Synplify Pro 8.8.0.4 Scope Editor
5
6 #
7 # Collections
8 #
9
10 #
11 # Clocks
12 #
13
14 define_clock -name {clk50MHz} -freq 50 -clockgroup default_clkgroup_50 -route 5
15 define_clock -name {clk49_152MHz} -freq 49.152 -clockgroup default_clkgroup_49 -route 5
16
17 #
18 # Clock to Clock
19 #
20
21 #
22 # Inputs/Outputs
23 #
24
25
26 #
27 # Registers
28 #
29
30 #
31 # Multicycle Path
32 #
33
34 #
35 # False Path
36 #
37
38 set_false_path -from reset
39
40 #
41 # Path Delay
42 #
43
44 #
45 # Attributes
46 #
47
48 define_global_attribute syn_useioff {1}
49 define_global_attribute -disable syn_netlist_hierarchy {0}
50
51 #
52 # I/O standards
53 #
54
55 #
56 # Compile Points
57 #
58
59 #
60 # Other Constraints
61 #
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1 PACKAGE=CQFP352
2 SPEED=Std
3 SYNFREQ=50
4
5 TECHNOLOGY=Axcelerator
6
7 DESIGNER_PACKAGE=CQFP
8 DESIGNER_PINS=352
9 DESIGNER_VOLTAGE=COM
10 DESIGNER_TEMP=COM
11
12 #ifeq ("$(FPGA_RTAX4000)","S")
13 # LIBERO_DIE=70800rts
14 # PART=RTAX4000S
15 # LIBERO_PACKAGE=cqfp$(DESIGNER_PINS)r
16 #endif
17
18 #ifeq ("$(FPGA_RTAX4000)","D")
19 LIBERO_DIE=70800d
20 PART=RTAX4000D
21 LIBERO_PACKAGE=cq$(DESIGNER_PINS)
22 #endif
23
24 MANUFACTURER=Actel
25 MGCPART=$(PART)
26 MGCTECHNOLOGY=Axcelerator
27 MGCPACKAGE= {$(DESIGNER_PINS) $(DESIGNER_PACKAGE)}
28
29 ## RTAX4000S OPTIONS
30 #LIBERO_DIE=70800rts
31 #PART=RTAX4000S
32
33 ## RTAX4000D OPTIONS
34 #LIBERO_DIE=70800d
35 #PART=RTAX4000D
36
37 # RTAX4000D
38 #LIBERO_PACKAGE=cq$(DESIGNER_PINS)
39
40 # RTAX4000S
41 #LIBERO_PACKAGE=cqfp$(DESIGNER_PINS)r
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1 {
2 "cells": [
3 {
4 "cell_type": "code",
5 "execution_count": null,
6 "metadata": {
7 "collapsed": false
8 },
9 "outputs": [],
10 "source": [
11 "#%matplotlib qt\n",
12 "%matplotlib inline\n",
13 "import matplotlib.pyplot as plt\n",
14 "plt.rcParams[\"figure.figsize\"] = [12,12]\n",
15 "import numpy as np\n",
16 "import pandas as pds"
17 ]
18 },
19 {
20 "cell_type": "code",
21 "execution_count": null,
22 "metadata": {
23 "collapsed": false
24 },
25 "outputs": [],
26 "source": [
27 "def try_plot(df,ax,left,right):\n",
28 " try:\n",
29 " df[(df.index >= left) & (df.index <= right)].plot(ax=ax,subplots=True,legend=False)\n",
30 " except:\n",
31 " pass\n",
32 " \n",
33 "def make_plots(path=\"./simulation\",left=50e-3,right=100e-3):\n",
34 " inputSig = pds.read_csv(path+\"/log_input.txt\",index_col=0,delim_whitespace=True,header=None,names=[\"TSTAMP\",\"BIAS1\",\"BIAS2\",\"BIAS3\",\"BIAS4\",\"BIAS5\",\"B1\",\"B2\",\"B3\"])\n",
35 " fXSig=[]\n",
36 " G=[0.89,0.87,0.89]\n",
37 " [fXSig.append(pds.read_csv(\n",
38 " path+\"./log_output_f{0}.txt\".format(F),index_col=0,delim_whitespace=True,header=None,\n",
39 " names=[\"TSTAMP\",\"BIAS1\",\"BIAS4\",\"BIAS5\",\"B1\",\"B2\",\"B3\"])) for F in range(3) ]\n",
40 " inputSig.index*=5e-9\n",
41 " for F in range(3):\n",
42 " if len(fXSig[F].index):\n",
43 " fXSig[F].index*=5e-9\n",
44 " fXSig[F]/=G[F]\n",
45 " axes=inputSig[(inputSig.index >= left) & (inputSig.index <= right)].filter([\"BIAS1\",\"BIAS4\",\"BIAS5\",\"B1\",\"B2\",\"B3\"]).plot(subplots=True,layout=(3,2)) \n",
46 " [ try_plot(df,axes,left,right) for df in fXSig ]\n",
47 " "
48 ]
49 },
50 {
51 "cell_type": "code",
52 "execution_count": null,
53 "metadata": {
54 "collapsed": false
55 },
56 "outputs": [],
57 "source": [
58 "make_plots()"
59 ]
60 }
61 ],
62 "metadata": {
63 "kernelspec": {
64 "display_name": "Python 3",
65 "language": "python",
66 "name": "python3"
67 },
68 "language_info": {
69 "codemirror_mode": {
70 "name": "ipython",
71 "version": 3
72 },
73 "file_extension": ".py",
74 "mimetype": "text/x-python",
75 "name": "python",
76 "nbconvert_exporter": "python",
77 "pygments_lexer": "ipython3",
78 "version": "3.5.2"
79 }
80 },
81 "nbformat": 4,
82 "nbformat_minor": 1
83 }
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1 {
2 "cells": [
3 {
4 "cell_type": "code",
5 "execution_count": null,
6 "metadata": {
7 "collapsed": false
8 },
9 "outputs": [],
10 "source": [
11 "import random\n",
12 "import time\n",
13 "#%matplotlib inline\n",
14 "import matplotlib.pyplot as plt\n",
15 "import numpy as np\n",
16 "import pandas as pds\n",
17 "import datetime as dt"
18 ]
19 },
20 {
21 "cell_type": "code",
22 "execution_count": null,
23 "metadata": {
24 "collapsed": true
25 },
26 "outputs": [],
27 "source": [
28 "DOFILE=\"run.do.in\"\n",
29 "RAM1={\n",
30 "\"instance\":\"testbench/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/IIR_CEL_CTRLR_v2_DATAFLOW_1/RAM_CTRLR_v2_1/memRAM/SRAM/axc/x0/a8to12/agen(0)/u0/u0/MEMORYFILE\",\n",
31 "\"abits\":8,\n",
32 "\"dbits\":12,\n",
33 "\"name\":\"RAM1.txt\"\n",
34 "}\n",
35 "RAM2={\n",
36 "\"instance\":\"testbench/lpp_lfr_filter_1/IIR_CEL_f0_to_f1/IIR_CEL_CTRLR_v2_DATAFLOW_1/RAM_CTRLR_v2_1/memRAM/SRAM/axc/x0/a8to12/agen(0)/u0/u0/MEMORYFILE\",\n",
37 "\"abits\":8,\n",
38 "\"dbits\":12,\n",
39 "\"name\":\"RAM2.txt\"\n",
40 "}\n",
41 "RAM3={\n",
42 "\"instance\":\"testbench/lpp_lfr_filter_1/cic_lfr_1/memRAM/SRAM/axc/x0/a8to12/agen(0)/u0/u0/MEMORYFILE\",\n",
43 "\"abits\":9,\n",
44 "\"dbits\":10,\n",
45 "\"name\":\"RAM3.txt\"\n",
46 "}\n",
47 "RAM4={\n",
48 "\"instance\":\"testbench/lpp_lfr_filter_1/cic_lfr_1/memRAM/SRAM/axc/x0/a8to12/agen(1)/u0/u0/MEMORYFILE\",\n",
49 "\"abits\":9,\n",
50 "\"dbits\":10,\n",
51 "\"name\":\"RAM4.txt\"\n",
52 "}\n",
53 "RAM5={\n",
54 "\"instance\":\"testbench/lpp_lfr_filter_1/YES_IIR_FILTER_f2_f3/IIR_CEL_CTRLR_v3_1/RAM_CTRLR_v2_1/memRAM/SRAM/axc/x0/a8to12/agen(0)/u0/u0/MEMORYFILE\",\n",
55 "\"abits\":8,\n",
56 "\"dbits\":12,\n",
57 "\"name\":\"RAM5.txt\"\n",
58 "}\n",
59 "RAM6={\n",
60 "\"instance\":\"testbench/lpp_lfr_filter_1/YES_IIR_FILTER_f2_f3/IIR_CEL_CTRLR_v3_1/RAM_CTRLR_v2_2/memRAM/SRAM/axc/x0/a8to12/agen(0)/u0/u0/MEMORYFILE\",\n",
61 "\"abits\":8,\n",
62 "\"dbits\":12,\n",
63 "\"name\":\"RAM6.txt\"\n",
64 "}\n",
65 "\n",
66 "RAMS=[RAM1,RAM2,RAM3,RAM4,RAM5,RAM6]"
67 ]
68 },
69 {
70 "cell_type": "code",
71 "execution_count": null,
72 "metadata": {
73 "collapsed": false
74 },
75 "outputs": [],
76 "source": [
77 "def mkram(length,width,gentype='rand',**kwargs):\n",
78 " return toBinStr(gen(length,width,gentype,**kwargs),width)\n",
79 "\n",
80 "def toBinStr(data,width):\n",
81 " return [format(val, 'b').zfill(width) for val in data]\n",
82 "\n",
83 "def gen(length,width,gentype='rand',**kwargs):\n",
84 " LUT={\n",
85 " \"rand\":gen_rand,\n",
86 " \"const\":gen_const\n",
87 " }\n",
88 " return LUT[gentype](length,width,**kwargs)\n",
89 "\n",
90 "def gen_rand(length,width,**kwargs):\n",
91 " random.seed(time.time())\n",
92 " mask=(2**width)-1\n",
93 " data=[]\n",
94 " for line in range(length):\n",
95 " data.append(int(2**32*random.random())&mask)\n",
96 " return data\n",
97 "\n",
98 "def gen_const(length,width, value):\n",
99 " mask=(2**width)-1\n",
100 " return [value&mask for i in range(length)]\n",
101 "\n",
102 "def save(data,file):\n",
103 " f = open(file,\"w\")\n",
104 " [f.write(line+'\\n') for line in data]\n",
105 " f.close()\n",
106 " \n",
107 "def start_Vsim(gentype='rand',**kwargs):\n",
108 " args=\"\"\n",
109 " for RAM in RAMS:\n",
110 " save(mkram(2**RAM[\"abits\"],RAM[\"dbits\"],gentype=gentype,**kwargs),\"simulation/\"+RAM[\"name\"])\n",
111 " args = args + \" -g\" + RAM[\"instance\"] + \"=\\\"\" + RAM[\"name\"] + \"\\\"\"\n",
112 " with open(\"run.do.in\",\"r\") as inFile, open(\"simulation/run.do\",\"w\") as outFile:\n",
113 " input = inFile.read()\n",
114 " outFile.write(input.replace(\"#VSIM_ARGS#\",args))\n",
115 " $(cd simulation)\n",
116 " vsim -do run.do > sim.log\n",
117 " folder=dt.datetime.today().strftime(\"%Y-%m-%d_%H-%M\")\n",
118 " mkdir @(folder)\n",
119 " for RAM in RAMS:\n",
120 " cp @(RAM[\"name\"]) @(folder+\"/\"+RAM[\"name\"])\n",
121 " cp log*.txt run.do sim.log @(folder) \n",
122 " $(cd ..)\n",
123 " \n"
124 ]
125 },
126 {
127 "cell_type": "code",
128 "execution_count": null,
129 "metadata": {
130 "collapsed": false
131 },
132 "outputs": [],
133 "source": []
134 },
135 {
136 "cell_type": "code",
137 "execution_count": null,
138 "metadata": {
139 "collapsed": false
140 },
141 "outputs": [],
142 "source": [
143 "df = pds.read_csv(\"./simulation/log_input.txt\",index_col=0,delim_whitespace=True,header=None,names=[\"TSTAMP\",\"BIAS1\",\"BIAS2\",\"BIAS3\",\"BIAS4\",\"BIAS5\",\"B1\",\"B2\",\"B3\"])\n",
144 "df2 = pds.read_csv(\"./simulation/log_output_f0.txt\",index_col=0,delim_whitespace=True,header=None,names=[\"TSTAMP\",\"BIAS1\",\"BIAS4\",\"BIAS5\",\"B1\",\"B2\",\"B3\"])\n",
145 "df3 = pds.read_csv(\"./simulation/log_output_f1.txt\",index_col=0,delim_whitespace=True,header=None,names=[\"TSTAMP\",\"BIAS1\",\"BIAS4\",\"BIAS5\",\"B1\",\"B2\",\"B3\"])\n",
146 "df4 = pds.read_csv(\"./simulation/log_output_f2.txt\",index_col=0,delim_whitespace=True,header=None,names=[\"TSTAMP\",\"BIAS1\",\"BIAS4\",\"BIAS5\",\"B1\",\"B2\",\"B3\"])\n",
147 "\n",
148 "df.index*=5e-9\n",
149 "if len(df2.index):\n",
150 " df2.index*=5e-9\n",
151 " df2/=0.89\n",
152 "if len(df3.index):\n",
153 " df3.index*=5e-9\n",
154 " df3/=0.87\n",
155 "if len(df4.index):\n",
156 " df4.index*=5e-9\n",
157 " df4/=0.89\n",
158 "\n",
159 "print(len(df))\n",
160 "df.filter([\"B1\"]).plot()\n",
161 "#plt.plot(df2)\n",
162 "plt.plot(df3.filter([\"B1\"]))\n",
163 "#plt.plot(df4)\n",
164 "plt.show()"
165 ]
166 },
167 {
168 "cell_type": "code",
169 "execution_count": null,
170 "metadata": {
171 "collapsed": false
172 },
173 "outputs": [],
174 "source": [
175 "cd .."
176 ]
177 },
178 {
179 "cell_type": "code",
180 "execution_count": null,
181 "metadata": {
182 "collapsed": false
183 },
184 "outputs": [],
185 "source": [
186 "mkram(2,32)\n",
187 "\n",
188 "mkram(20,32,gentype='const',value=55)\n",
189 "\n",
190 "save(mkram(10,32),\"RAM_FILE.txt\")"
191 ]
192 },
193 {
194 "cell_type": "code",
195 "execution_count": null,
196 "metadata": {
197 "collapsed": false,
198 "scrolled": false
199 },
200 "outputs": [],
201 "source": [
202 "for i in range(2):\n",
203 " start_Vsim(gentype='rand',value=0)"
204 ]
205 }
206 ],
207 "metadata": {
208 "kernelspec": {
209 "display_name": "Xonsh",
210 "language": "xonsh",
211 "name": "xonsh"
212 },
213 "language_info": {
214 "codemirror_mode": "shell",
215 "file_extension": ".xsh",
216 "mimetype": "text/x-sh",
217 "name": "xonsh",
218 "pygments_lexer": "xonsh"
219 }
220 },
221 "nbformat": 4,
222 "nbformat_minor": 1
223 }
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@@ -0,0 +1,74
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
23
24 LIBRARY ieee;
25 USE ieee.std_logic_1164.ALL;
26 use ieee.numeric_std.all;
27 USE IEEE.std_logic_signed.ALL;
28 USE IEEE.MATH_real.ALL;
29
30 ENTITY generator IS
31
32 GENERIC (
33 AMPLITUDE : INTEGER := 100;
34 NB_BITS : INTEGER := 16);
35
36 PORT (
37 clk : IN STD_LOGIC;
38 rstn : IN STD_LOGIC;
39 run : IN STD_LOGIC;
40
41 data_ack : IN STD_LOGIC;
42 offset : IN STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0);
43 data : OUT STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0)
44 );
45
46 END generator;
47
48 ARCHITECTURE beh OF generator IS
49
50 SIGNAL reg : STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0);
51 BEGIN -- beh
52
53
54 PROCESS (clk, rstn)
55 variable seed1, seed2: positive; -- seed values for random generator
56 variable rand: real; -- random real-number value in range 0 to 1.0
57 BEGIN -- PROCESS
58 uniform(seed1, seed2, rand);--more entropy by skipping values
59 IF rstn = '0' THEN -- asynchronous reset (active low)
60 reg <= (OTHERS => '0');
61 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
62 IF run = '0' THEN
63 reg <= (OTHERS => '0');
64 ELSE
65 IF data_ack = '1' THEN
66 reg <= std_logic_vector(to_signed(INTEGER( (REAL(AMPLITUDE) * rand) + REAL(to_integer(SIGNED(offset))) ),NB_BITS));
67 END IF;
68 END IF;
69 END IF;
70 END PROCESS;
71
72 data <= reg;
73
74 END beh;
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This diff has been collapsed as it changes many lines, (516 lines changed) Show them Hide them
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1 quietly set ACTELLIBNAME Axcelerator
2 quietly set PROJECT_DIR "C:/opt/VHDLIB/designs/Validation_IIR_LFR"
3
4 if {[file exists presynth/_info]} {
5 echo "INFO: Simulation library presynth already exists"
6 } else {
7 vlib presynth
8 }
9 vmap presynth presynth
10 vmap Axcelerator "C:/Microsemi/Libero_v9.2/Designer/lib/modelsim/precompiled/vhdl/Axcelerator"
11 if {[file exists grlib/_info]} {
12 echo "INFO: Simulation library grlib already exists"
13 } else {
14 vlib grlib
15 }
16 vmap grlib "grlib"
17 if {[file exists synplify/_info]} {
18 echo "INFO: Simulation library synplify already exists"
19 } else {
20 vlib synplify
21 }
22 vmap synplify "synplify"
23 if {[file exists techmap/_info]} {
24 echo "INFO: Simulation library techmap already exists"
25 } else {
26 vlib techmap
27 }
28 vmap techmap "techmap"
29 if {[file exists spw/_info]} {
30 echo "INFO: Simulation library spw already exists"
31 } else {
32 vlib spw
33 }
34 vmap spw "spw"
35 if {[file exists eth/_info]} {
36 echo "INFO: Simulation library eth already exists"
37 } else {
38 vlib eth
39 }
40 vmap eth "eth"
41 if {[file exists gaisler/_info]} {
42 echo "INFO: Simulation library gaisler already exists"
43 } else {
44 vlib gaisler
45 }
46 vmap gaisler "gaisler"
47 if {[file exists esa/_info]} {
48 echo "INFO: Simulation library esa already exists"
49 } else {
50 vlib esa
51 }
52 vmap esa "esa"
53 if {[file exists fmf/_info]} {
54 echo "INFO: Simulation library fmf already exists"
55 } else {
56 vlib fmf
57 }
58 vmap fmf "fmf"
59 if {[file exists spansion/_info]} {
60 echo "INFO: Simulation library spansion already exists"
61 } else {
62 vlib spansion
63 }
64 vmap spansion "spansion"
65 if {[file exists gsi/_info]} {
66 echo "INFO: Simulation library gsi already exists"
67 } else {
68 vlib gsi
69 }
70 vmap gsi "gsi"
71 if {[file exists iap/_info]} {
72 echo "INFO: Simulation library iap already exists"
73 } else {
74 vlib iap
75 }
76 vmap iap "iap"
77 if {[file exists lpp/_info]} {
78 echo "INFO: Simulation library lpp already exists"
79 } else {
80 vlib lpp
81 }
82 vmap lpp "lpp"
83 if {[file exists cypress/_info]} {
84 echo "INFO: Simulation library cypress already exists"
85 } else {
86 vlib cypress
87 }
88 vmap cypress "cypress"
89
90 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/stdlib/version.vhd"
91 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/stdlib/config_types.vhd"
92 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/stdlib/config.vhd"
93 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/stdlib/stdlib.vhd"
94 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/stdlib/stdio.vhd"
95 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/stdlib/testlib.vhd"
96 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/ftlib/mtie_ftlib.vhd"
97 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/util/util.vhd"
98 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/sparc/sparc.vhd"
99 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/sparc/sparc_disas.vhd"
100 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/sparc/cpu_disas.vhd"
101 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/modgen/multlib.vhd"
102 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/modgen/leaves.vhd"
103 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/amba/amba.vhd"
104 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/amba/devices.vhd"
105 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/amba/defmst.vhd"
106 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/amba/apbctrl.vhd"
107 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/amba/ahbctrl.vhd"
108 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/amba/dma2ahb_pkg.vhd"
109 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/amba/dma2ahb.vhd"
110 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/amba/ahbmst.vhd"
111 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/amba/ahbmon.vhd"
112 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/amba/apbmon.vhd"
113 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/amba/ambamon.vhd"
114 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/amba/dma2ahb_tp.vhd"
115 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/amba/amba_tp.vhd"
116 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/atf/at_pkg.vhd"
117 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/atf/at_ahb_mst_pkg.vhd"
118 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/atf/at_ahb_slv_pkg.vhd"
119 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/atf/at_util.vhd"
120 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/atf/at_ahb_mst.vhd"
121 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/atf/at_ahb_slv.vhd"
122 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/atf/at_ahbs.vhd"
123 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/atf/at_ahb_ctrl.vhd"
124 vcom -93 -explicit -work synplify "${PROJECT_DIR}/../../../GRLIB/lib/synplify/sim/synplify.vhd"
125 vcom -93 -explicit -work synplify "${PROJECT_DIR}/../../../GRLIB/lib/synplify/sim/synattr.vhd"
126 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/gencomp/gencomp.vhd"
127 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/gencomp/netcomp.vhd"
128 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/inferred/memory_inferred.vhd"
129 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/inferred/tap_inferred.vhd"
130 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/inferred/ddr_inferred.vhd"
131 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/inferred/mul_inferred.vhd"
132 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/inferred/ddr_phy_inferred.vhd"
133 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/inferred/ddrphy_datapath.vhd"
134 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/inferred/sim_pll.vhd"
135 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/inferred/lpddr2_phy_inferred.vhd"
136 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/axcelerator/axcomp.vhd"
137 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/axcelerator/memory_axcelerator.vhd"
138 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/axcelerator/buffer_axcelerator.vhd"
139 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/axcelerator/pads_axcelerator.vhd"
140 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/axcelerator/clkgen_axcelerator.vhd"
141 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/axcelerator/ddr_axcelerator.vhd"
142 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/axcelerator/mul_axcelerator.vhd"
143 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/axcelerator/grpci2_phy_rtax_bypass.vhd"
144 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/allclkgen.vhd"
145 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/allddr.vhd"
146 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/allmem.vhd"
147 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/allmul.vhd"
148 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/allpads.vhd"
149 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/alltap.vhd"
150 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/clkgen.vhd"
151 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/clkmux.vhd"
152 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/clkinv.vhd"
153 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/clkand.vhd"
154 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/ddr_ireg.vhd"
155 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/ddr_oreg.vhd"
156 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/ddrphy.vhd"
157 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/syncram.vhd"
158 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/syncram64.vhd"
159 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/syncram_2p.vhd"
160 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/syncram_dp.vhd"
161 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/syncfifo_2p.vhd"
162 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/regfile_3p.vhd"
163 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/tap.vhd"
164 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/techbuf.vhd"
165 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/nandtree.vhd"
166 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/clkpad.vhd"
167 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/clkpad_ds.vhd"
168 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/inpad.vhd"
169 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/inpad_ds.vhd"
170 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/iodpad.vhd"
171 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/iopad.vhd"
172 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/iopad_ds.vhd"
173 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/lvds_combo.vhd"
174 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/odpad.vhd"
175 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/outpad.vhd"
176 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/outpad_ds.vhd"
177 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/toutpad.vhd"
178 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/skew_outpad.vhd"
179 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/mul_61x61.vhd"
180 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/cpu_disas_net.vhd"
181 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/ringosc.vhd"
182 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/grpci2_phy_net.vhd"
183 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/system_monitor.vhd"
184 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/grgates.vhd"
185 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/inpad_ddr.vhd"
186 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/outpad_ddr.vhd"
187 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/iopad_ddr.vhd"
188 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/syncram128bw.vhd"
189 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/syncram256bw.vhd"
190 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/syncram128.vhd"
191 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/syncram156bw.vhd"
192 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/techmult.vhd"
193 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/spictrl_net.vhd"
194 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/syncrambw.vhd"
195 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/syncram_2pbw.vhd"
196 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/sdram_phy.vhd"
197 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/from.vhd"
198 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/syncreg.vhd"
199 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/serdes.vhd"
200 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/mtie_maps.vhd"
201 vcom -93 -explicit -work spw "${PROJECT_DIR}/../../../GRLIB/lib/spw/comp/spwcomp.vhd"
202 vcom -93 -explicit -work spw "${PROJECT_DIR}/../../../GRLIB/lib/spw/core/mtie_core.vhd"
203 vcom -93 -explicit -work spw "${PROJECT_DIR}/../../../GRLIB/lib/spw/wrapper/grspw_gen.vhd"
204 vcom -93 -explicit -work spw "${PROJECT_DIR}/../../../GRLIB/lib/spw/wrapper/grspw2_gen.vhd"
205 vcom -93 -explicit -work spw "${PROJECT_DIR}/../../../GRLIB/lib/spw/wrapper/grspw_codec_gen.vhd"
206 vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/comp/ethcomp.vhd"
207 vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/core/greth_pkg.vhd"
208 vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/core/eth_rstgen.vhd"
209 vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/core/eth_edcl_ahb_mst.vhd"
210 vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/core/eth_ahb_mst_gbit.vhd"
211 vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/core/eth_ahb_mst.vhd"
212 vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/core/greth_gbit_rx.vhd"
213 vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/core/greth_gbit_tx.vhd"
214 vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/core/greth_gbit_gtx.vhd"
215 vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/core/greth_tx.vhd"
216 vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/core/greth_rx.vhd"
217 vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/core/greth_gbitc.vhd"
218 vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/core/grethc.vhd"
219 vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/wrapper/greth_gen.vhd"
220 vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/wrapper/greth_gbit_gen.vhd"
221 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/arith/arith.vhd"
222 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/arith/mul32.vhd"
223 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/arith/div32.vhd"
224 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/memctrl/memctrl.vhd"
225 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/memctrl/sdctrl.vhd"
226 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/memctrl/sdctrl64.vhd"
227 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/memctrl/sdmctrl.vhd"
228 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/memctrl/srctrl.vhd"
229 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/memctrl/ssrctrl.vhd"
230 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/memctrl/ftsrctrlc.vhd"
231 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/memctrl/ftsrctrl.vhd"
232 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/memctrl/ftsdctrl.vhd"
233 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/memctrl/ftsrctrl8.vhd"
234 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/memctrl/ftsdmctrl.vhd"
235 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/memctrl/ftmctrl.vhd"
236 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/memctrl/ftsdctrl64.vhd"
237 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/grlfpu/mtie_grlfpu.vhd"
238 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/grlfpc/mtie_grlfpc.vhd"
239 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/srmmu/mmuconfig.vhd"
240 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/srmmu/mmuiface.vhd"
241 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/srmmu/libmmu.vhd"
242 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/srmmu/mmutlbcam.vhd"
243 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/srmmu/mmulrue.vhd"
244 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/srmmu/mmulru.vhd"
245 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/srmmu/mmutlb.vhd"
246 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/srmmu/mmutw.vhd"
247 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/srmmu/mmu.vhd"
248 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/leon3/leon3.vhd"
249 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/leon3/grfpushwx.vhd"
250 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/leon3v3/mtie_leon3v3.vhd"
251 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/irqmp/irqmp.vhd"
252 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/irqmp/irqmp2x.vhd"
253 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/irqmp/irqamp.vhd"
254 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/irqmp/irqamp2x.vhd"
255 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/l2cache/v2-pkg/l2cache.vhd"
256 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/misc.vhd"
257 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/rstgen.vhd"
258 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/gptimer.vhd"
259 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/ahbram.vhd"
260 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/ahbdpram.vhd"
261 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/ahbtrace_mmb.vhd"
262 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/ahbtrace_mb.vhd"
263 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/ahbtrace.vhd"
264 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/grgpio.vhd"
265 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/ftahbram.vhd"
266 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/ftahbram2.vhd"
267 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/ahbstat.vhd"
268 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/logan.vhd"
269 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/apbps2.vhd"
270 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/charrom_package.vhd"
271 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/charrom.vhd"
272 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/apbvga.vhd"
273 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/ahb2ahb.vhd"
274 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/ahbbridge.vhd"
275 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/svgactrl.vhd"
276 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/grfifo.vhd"
277 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/gradcdac.vhd"
278 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/grsysmon.vhd"
279 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/gracectrl.vhd"
280 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/grgpreg.vhd"
281 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/memscrub.vhd"
282 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/ahb_mst_iface.vhd"
283 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/grgprbank.vhd"
284 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/grclkgate.vhd"
285 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/grclkgate2x.vhd"
286 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/grtimer.vhd"
287 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/grpulse.vhd"
288 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/grversion.vhd"
289 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/ahbfrom.vhd"
290 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/ambatest/ahbtbp.vhd"
291 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/ambatest/ahbtbm.vhd"
292 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/net/net.vhd"
293 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/uart/uart.vhd"
294 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/uart/libdcom.vhd"
295 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/uart/apbuart.vhd"
296 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/uart/dcom.vhd"
297 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/uart/dcom_uart.vhd"
298 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/uart/ahbuart.vhd"
299 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/sim.vhd"
300 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/sram.vhd"
301 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/sramft.vhd"
302 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/sram16.vhd"
303 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/phy.vhd"
304 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/ahbrep.vhd"
305 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/delay_wire.vhd"
306 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/pwm_check.vhd"
307 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/ramback.vhd"
308 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/zbtssram.vhd"
309 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/slavecheck.vhd"
310 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/spwtrace.vhd"
311 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/spwtracev.vhd"
312 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/ddrram.vhd"
313 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/ddr2ram.vhd"
314 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/ddr3ram.vhd"
315 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/jtag/jtag.vhd"
316 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/jtag/libjtagcom.vhd"
317 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/jtag/jtagcom.vhd"
318 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/jtag/ahbjtag.vhd"
319 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/jtag/ahbjtag_bsd.vhd"
320 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/jtag/bscanctrl.vhd"
321 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/jtag/bscanregs.vhd"
322 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/jtag/bscanregsbd.vhd"
323 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/jtag/jtagcom2.vhd"
324 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/jtag/jtagtst.vhd"
325 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/spacewire/spacewire.vhd"
326 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/spacewire/grspw.vhd"
327 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/spacewire/grspw2.vhd"
328 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/spacewire/grspwm.vhd"
329 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/spacewire/grspw2_phy.vhd"
330 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/spacewire/grspw_codec_clockgate.vhd"
331 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/spacewire/grspw_phy.vhd"
332 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/gr1553b/gr1553b_pkg.vhd"
333 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/gr1553b/gr1553b_pads.vhd"
334 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/gr1553b/simtrans1553.vhd"
335 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/nand/nandpkg.vhd"
336 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/nand/nandfctrlx.vhd"
337 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/nand/nandfctrl.vhd"
338 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/clk2x/clk2x.vhd"
339 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/clk2x/qmod.vhd"
340 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/clk2x/qmod_prect.vhd"
341 vcom -93 -explicit -work esa "${PROJECT_DIR}/../../../GRLIB/lib/esa/memoryctrl/memoryctrl.vhd"
342 vcom -93 -explicit -work esa "${PROJECT_DIR}/../../../GRLIB/lib/esa/memoryctrl/mctrl.vhd"
343 vcom -93 -explicit -work fmf "${PROJECT_DIR}/../../../GRLIB/lib/fmf/utilities/conversions.vhd"
344 vcom -93 -explicit -work fmf "${PROJECT_DIR}/../../../GRLIB/lib/fmf/utilities/gen_utils.vhd"
345 vcom -93 -explicit -work fmf "${PROJECT_DIR}/../../../GRLIB/lib/fmf/flash/flash.vhd"
346 vcom -93 -explicit -work fmf "${PROJECT_DIR}/../../../GRLIB/lib/fmf/flash/s25fl064a.vhd"
347 vcom -93 -explicit -work fmf "${PROJECT_DIR}/../../../GRLIB/lib/fmf/flash/m25p80.vhd"
348 vcom -93 -explicit -work fmf "${PROJECT_DIR}/../../../GRLIB/lib/fmf/fifo/idt7202.vhd"
349 vcom -93 -explicit -work gsi "${PROJECT_DIR}/../../../GRLIB/lib/gsi/ssram/functions.vhd"
350 vcom -93 -explicit -work gsi "${PROJECT_DIR}/../../../GRLIB/lib/gsi/ssram/core_burst.vhd"
351 vcom -93 -explicit -work gsi "${PROJECT_DIR}/../../../GRLIB/lib/gsi/ssram/g880e18bt.vhd"
352 vcom -93 -explicit -work iap "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB_NONFREE/lib/iap/./apb_devices/apb_devices_list.vhd"
353 vcom -93 -explicit -work iap "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB_NONFREE/lib/iap/./apb_devices/apb_devices.vhd"
354 vcom -93 -explicit -work iap "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB_NONFREE/lib/iap/./memctrlr/memctrlr.vhd"
355 vcom -93 -explicit -work iap "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB_NONFREE/lib/iap/./memctrlr/srctrle-0ws.vhd"
356 vcom -93 -explicit -work iap "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB_NONFREE/lib/iap/./memctrlr/srctrle-1ws.vhd"
357 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/data_type_pkg.vhd"
358 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/general_purpose.vhd"
359 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/ADDRcntr.vhd"
360 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/ALU.vhd"
361 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/Adder.vhd"
362 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/Clk_Divider2.vhd"
363 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/Clk_divider.vhd"
364 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/MAC.vhd"
365 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/MAC_CONTROLER.vhd"
366 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/MAC_MUX.vhd"
367 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/MAC_MUX2.vhd"
368 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/MAC_REG.vhd"
369 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/MUX2.vhd"
370 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/MUXN.vhd"
371 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/Multiplier.vhd"
372 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/REG.vhd"
373 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/SYNC_FF.vhd"
374 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/Shifter.vhd"
375 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/TwoComplementer.vhd"
376 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/Clock_Divider.vhd"
377 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/lpp_front_to_level.vhd"
378 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/lpp_front_detection.vhd"
379 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/SYNC_VALID_BIT.vhd"
380 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/RR_Arbiter_4.vhd"
381 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/general_counter.vhd"
382 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/ramp_generator.vhd"
383 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_amba/apb_devices_list.vhd"
384 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_amba/lpp_amba.vhd"
385 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/chirp/chirp_pkg.vhd"
386 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/chirp/chirp.vhd"
387 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/iir_filter/iir_filter.vhd"
388 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/iir_filter/FILTERcfg.vhd"
389 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/iir_filter/RAM.vhd"
390 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/iir_filter/RAM_CEL.vhd"
391 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/iir_filter/RAM_CTRLR_v2.vhd"
392 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd"
393 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd"
394 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd"
395 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v3_DATAFLOW.vhd"
396 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v3.vhd"
397 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/cic/cic_pkg.vhd"
398 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/cic/cic.vhd"
399 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/cic/cic_integrator.vhd"
400 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/cic/cic_downsampler.vhd"
401 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/cic/cic_comb.vhd"
402 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/cic/cic_lfr.vhd"
403 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/cic/cic_lfr_control.vhd"
404 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/cic/cic_lfr_add_sub.vhd"
405 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/cic/cic_lfr_address_gen.vhd"
406 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/cic/cic_lfr_r2.vhd"
407 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/cic/cic_lfr_control_r2.vhd"
408 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/lpp_downsampling/Downsampling.vhd"
409 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/lpp_fft_rtax/fft_components.vhd"
410 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/lpp_fft_rtax/lpp_fft.vhd"
411 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/lpp_fft_rtax/actar.vhd"
412 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/lpp_fft_rtax/actram.vhd"
413 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/lpp_fft_rtax/fftDp.vhd"
414 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/lpp_fft_rtax/fftSm.vhd"
415 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/lpp_fft_rtax/primitives.vhd"
416 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/lpp_fft_rtax/twiddle.vhd"
417 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/lpp_fft_rtax/Driver_FFT.vhd"
418 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/lpp_fft_rtax/FFT.vhd"
419 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/lpp_fft_rtax/Linker_FFT.vhd"
420 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/window_function/window_function_pkg.vhd"
421 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/window_function/window_function.vhd"
422 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/window_function/WF_processing.vhd"
423 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/window_function/WF_rom.vhd"
424 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_memory/lpp_memory.vhd"
425 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_memory/lpp_FIFO.vhd"
426 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_memory/lpp_FIFO_4_Shared.vhd"
427 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_memory/lpp_FIFO_control.vhd"
428 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_memory/lpp_FIFO_4_Shared_headreg_latency_0.vhd"
429 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_memory/lpp_FIFO_4_Shared_headreg_latency_1.vhd"
430 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_memory/lppFIFOxN.vhd"
431 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_ad_Conv/lpp_ad_Conv.vhd"
432 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_ad_Conv/RHF1401.vhd"
433 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_ad_Conv/top_ad_conv_RHF1401.vhd"
434 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_ad_Conv/top_ad_conv_RHF1401_withFilter.vhd"
435 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_ad_Conv/TestModule_RHF1401.vhd"
436 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_ad_Conv/top_ad_conv_ADS7886_v2.vhd"
437 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_ad_Conv/ADS7886_drvr_v2.vhd"
438 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_ad_Conv/lpp_lfr_hk.vhd"
439 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_spectral_matrix/spectral_matrix_package.vhd"
440 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_spectral_matrix/MS_calculation.vhd"
441 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_spectral_matrix/MS_control.vhd"
442 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_spectral_matrix/spectral_matrix_switch_f0.vhd"
443 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_spectral_matrix/spectral_matrix_time_managment.vhd"
444 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_demux/DEMUX.vhd"
445 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_demux/lpp_demux.vhd"
446 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_Header/lpp_Header.vhd"
447 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_Header/HeaderBuilder.vhd"
448 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_matrix/lpp_matrix.vhd"
449 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_matrix/ALU_Driver.vhd"
450 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_matrix/ReUse_CTRLR.vhd"
451 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_matrix/Dispatch.vhd"
452 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_matrix/DriveInputs.vhd"
453 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_matrix/GetResult.vhd"
454 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_matrix/MatriceSpectrale.vhd"
455 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_matrix/Matrix.vhd"
456 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_matrix/SpectralMatrix.vhd"
457 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_matrix/TopSpecMatrix.vhd"
458 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_dma/lpp_dma_pkg.vhd"
459 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_dma/fifo_latency_correction.vhd"
460 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_dma/lpp_dma.vhd"
461 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_dma/lpp_dma_ip.vhd"
462 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_dma/lpp_dma_send_16word.vhd"
463 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_dma/lpp_dma_send_1word.vhd"
464 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_dma/lpp_dma_singleOrBurst.vhd"
465 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_dma/DMA_SubSystem.vhd"
466 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_dma/DMA_SubSystem_GestionBuffer.vhd"
467 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_dma/DMA_SubSystem_Arbiter.vhd"
468 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_dma/DMA_SubSystem_MUX.vhd"
469 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_dma/lpp_dma_SEND16B_FIFO2DMA.vhd"
470 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform_pkg.vhd"
471 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform.vhd"
472 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform_burst.vhd"
473 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform_fifo_withoutLatency.vhd"
474 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform_fifo_latencyCorrection.vhd"
475 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform_fifo.vhd"
476 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform_fifo_arbiter.vhd"
477 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform_fifo_ctrl.vhd"
478 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform_fifo_headreg.vhd"
479 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform_snapshot.vhd"
480 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform_snapshot_controler.vhd"
481 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform_genaddress.vhd"
482 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform_dma_genvalid.vhd"
483 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform_fifo_arbiter_reg.vhd"
484 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform_fsmdma.vhd"
485 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_top_lfr/lpp_top_lfr_pkg.vhd"
486 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_top_lfr/lpp_lfr_pkg.vhd"
487 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_top_lfr/lpp_lfr_apbreg_pkg.vhd"
488 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_top_lfr/lpp_lfr_filter_coeff.vhd"
489 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_top_lfr/lpp_lfr_filter.vhd"
490 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_top_lfr/lpp_lfr_apbreg_ms_pointer.vhd"
491 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd"
492 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_FFT.vhd"
493 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_top_lfr/lpp_lfr_ms.vhd"
494 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_reg_head.vhd"
495 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_top_lfr/lpp_lfr.vhd"
496 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_leon3_soc/lpp_leon3_soc_pkg.vhd"
497 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_leon3_soc/leon3_soc.vhd"
498 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_debug_lfr/lpp_debug_lfr_pkg.vhd"
499 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_debug_lfr/lpp_debug_dma_singleOrBurst.vhd"
500 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_file/reader_pkg.vhd"
501 vcom -93 -explicit -work cypress "${PROJECT_DIR}/../../../GRLIB/lib/cypress/ssram/components.vhd"
502 vcom -93 -explicit -work cypress "${PROJECT_DIR}/../../../GRLIB/lib/cypress/ssram/package_utility.vhd"
503 vcom -93 -explicit -work cypress "${PROJECT_DIR}/../../../GRLIB/lib/cypress/ssram/cy7c1354b.vhd"
504 vcom -93 -explicit -work cypress "${PROJECT_DIR}/../../../GRLIB/lib/cypress/ssram/cy7c1380d.vhd"
505 vcom -93 -explicit -work presynth "${PROJECT_DIR}/../../../GRLIB/lib/work/debug/debug.vhd"
506 vcom -93 -explicit -work presynth "${PROJECT_DIR}/../../../GRLIB/lib/work/debug/grtestmod.vhd"
507 vcom -93 -explicit -work presynth "${PROJECT_DIR}/../../../GRLIB/lib/work/debug/cpu_disas.vhd"
508 vcom -93 -explicit -work presynth "${PROJECT_DIR}/IIR_CEL_TEST.vhd"
509 vcom -93 -explicit -work presynth "${PROJECT_DIR}/tb.vhd"
510 vcom -93 -explicit -work presynth "${PROJECT_DIR}/IIR_CEL_TEST_v3.vhd"
511 vcom -93 -explicit -work presynth "${PROJECT_DIR}/generator.vhd"
512
513 vsim #VSIM_ARGS# -L Axcelerator -L presynth -L grlib -L synplify -L techmap -L spw -L eth -L gaisler -L esa -L fmf -L spansion -L gsi -L iap -L lpp -L cypress -t 1ps presynth.testbench
514 # The following lines are commented because no testbench is associated with the project
515 # do "wave.do"
516 run 2000ms
Show file before | Show file after | Hide comments
@@ -1,41 +1,42
1 # use glob syntax.
1 # use glob syntax.
2 syntax: glob
2 syntax: glob
3
3
4 *.tex
4 *.tex
5 *.html
5 *.html
6 *log*
6 *log*
7 *.png
7 *.png
8 *.dot
8 *.dot
9 *.css
9 *.css
10 *.md5
10 *.md5
11 *.eps
11 *.eps
12 *.pdf
12 *.pdf
13 *.toc
13 *.toc
14 *.map
14 *.map
15 *.sty
15 *.sty
16 *.3
16 *.3
17 *.js
17 *.js
18 *.aux
18 *.aux
19 *.idx
19 *.idx
20 *doc*
20 *doc*
21 *Doc*
21 *Doc*
22 *vhdlsyn.txt
22 *vhdlsyn.txt
23 *dirs.txt
23 *dirs.txt
24 *.orig
24 *.orig
25 *.o
25 *.o
26 *.a
26 *.a
27 *.bin
27 *.bin
28 *~
28 *~
29 apb_devices_list.h
29 apb_devices_list.h
30 apb_devices_list.vhd
30 apb_devices_list.vhd
31 twiddle.vhd
31 twiddle.vhd
32 primitives.vhd
32 primitives.vhd
33 fftSm.vhd
33 fftSm.vhd
34 fftDp.vhd
34 fftDp.vhd
35 fft_components.vhd
35 fft_components.vhd
36 CoreFFT.vhd
36 CoreFFT.vhd
37 actram.vhd
37 actram.vhd
38 actar.vhd
38 actar.vhd
39 *.bak
39 *.bak
40 *.pdc.ce
40 *.pdc.ce
41 *.zip
41 *.zip
42 */.ipynb_checkpoints/*
Show file before | Show file after | Hide comments
@@ -1,53 +1,56
1 #GRLIB=../..
1 #GRLIB=../..
2 VHDLIB=../..
2 VHDLIB=../..
3 SCRIPTSDIR=$(VHDLIB)/scripts/
3 SCRIPTSDIR=$(VHDLIB)/scripts/
4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
5 TOP=leon3mp
5 TOP=testbench
6 BOARD=em-LeonLPP-A3PE3kL-v3-core1
6 BOARD=LFR-EQM
7 include $(GRLIB)/boards/$(BOARD)/Makefile.inc
7 include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc
8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
9 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
9 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
10 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
10 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
11 EFFORT=high
11 EFFORT=high
12 XSTOPT=
12 XSTOPT=
13 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
13 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
15 VHDLSYNFILES=
15 VHDLSYNFILES= IIR_CEL_TEST.vhd tb.vhd IIR_CEL_TEST_v3.vhd generator.vhd
16 VHDLSIMFILES= tb.vhd
16 VHDLSIMFILES= tb.vhd
17 SIMTOP=testbench
17 SIMTOP=testbench
18 #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
18 #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
19 #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc
19 PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_RTAX.pdc
20 PDC=$(GRLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc
20 SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_altran_syn_fanout.sdc
21 BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
21 BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
22 CLEAN=soft-clean
22 CLEAN=soft-clean
23
23
24 TECHLIBS = proasic3e
24 TECHLIBS = axcelerator
25
25
26 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
26 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
27 tmtc openchip hynix ihp gleichmann micron usbhc
27 tmtc openchip hynix ihp gleichmann micron usbhc opencores
28
28
29 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
29 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
30 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
30 pci grusbhc haps slink ascs can pwm greth coremp7 spi ac97 \
31 ./amba_lcd_16x2_ctrlr \
31 ./amba_lcd_16x2_ctrlr \
32 ./general_purpose/lpp_AMR \
32 ./general_purpose/lpp_AMR \
33 ./general_purpose/lpp_balise \
33 ./general_purpose/lpp_balise \
34 ./general_purpose/lpp_delay \
34 ./general_purpose/lpp_delay \
35 ./lpp_bootloader \
35 ./lpp_bootloader \
36 ./lfr_management \
37 ./lpp_sim \
38 ./lpp_sim/CY7C1061DV33 \
36 ./lpp_cna \
39 ./lpp_cna \
37 ./lpp_uart \
40 ./lpp_uart \
38 ./lpp_usb \
41 ./lpp_usb \
39 ./dsp/lpp_fft_rtax \
42 ./dsp/lpp_fft \
40
43
41 FILESKIP = i2cmst.vhd \
44 FILESKIP = i2cmst.vhd \
42 APB_MULTI_DIODE.vhd \
45 APB_MULTI_DIODE.vhd \
43 APB_MULTI_DIODE.vhd \
46 APB_MULTI_DIODE.vhd \
44 Top_MatrixSpec.vhd \
47 Top_MatrixSpec.vhd \
45 APB_FFT.vhd \
48 APB_FFT.vhd \
46 lpp_lfr_apbreg.vhd \
49 lpp_lfr_apbreg.vhd \
47 CoreFFT.vhd
50 CoreFFT.vhd
48
51
49 include $(GRLIB)/bin/Makefile
52 include $(GRLIB)/bin/Makefile
50 include $(GRLIB)/software/leon3/Makefile
53 include $(GRLIB)/software/leon3/Makefile
51
54
52 ################## project specific targets ##########################
55 ################## project specific targets ##########################
53
56
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@@ -1,262 +1,276
1
1
2 LIBRARY ieee;
2 LIBRARY ieee;
3 USE ieee.std_logic_1164.ALL;
3 USE ieee.std_logic_1164.ALL;
4 USE IEEE.MATH_REAL.ALL;
4 use ieee.numeric_std.all;
5 USE ieee.numeric_std.ALL;
5 USE IEEE.std_logic_signed.ALL;
6 USE IEEE.MATH_real.ALL;
6
7
7 LIBRARY techmap;
8 LIBRARY techmap;
8 USE techmap.gencomp.ALL;
9 USE techmap.gencomp.ALL;
9
10
11 library std;
12 use std.textio.all;
13
10 LIBRARY lpp;
14 LIBRARY lpp;
11 USE lpp.iir_filter.ALL;
15 USE lpp.iir_filter.ALL;
12 USE lpp.lpp_ad_conv.ALL;
16 USE lpp.lpp_ad_conv.ALL;
13 USE lpp.FILTERcfg.ALL;
17 USE lpp.FILTERcfg.ALL;
14 USE lpp.lpp_lfr_filter_coeff.ALL;
18 USE lpp.lpp_lfr_filter_coeff.ALL;
15 USE lpp.general_purpose.ALL;
19 USE lpp.general_purpose.ALL;
16 USE lpp.data_type_pkg.ALL;
20 USE lpp.data_type_pkg.ALL;
17 USE lpp.chirp_pkg.ALL;
18 USE lpp.lpp_lfr_pkg.ALL;
21 USE lpp.lpp_lfr_pkg.ALL;
19 USE lpp.general_purpose.ALL;
22 USE lpp.general_purpose.ALL;
20
23
21 ENTITY testbench IS
24 ENTITY testbench IS
22 END;
25 END;
23
26
24 ARCHITECTURE behav OF testbench IS
27 ARCHITECTURE behav OF testbench IS
25
28
26 COMPONENT IIR_CEL_TEST
29 SIGNAL TSTAMP : INTEGER:=0;
27 PORT (
28 rstn : IN STD_LOGIC;
29 clk : IN STD_LOGIC;
30 sample_in_val : IN STD_LOGIC;
31 sample_in : IN samplT(7 DOWNTO 0, 17 DOWNTO 0);
32 sample_out_val : OUT STD_LOGIC;
33 sample_out : OUT samplT(7 DOWNTO 0, 17 DOWNTO 0));
34 END COMPONENT;
35
36 COMPONENT IIR_CEL_TEST_v3
37 PORT (
38 rstn : IN STD_LOGIC;
39 clk : IN STD_LOGIC;
40 sample_in1_val : IN STD_LOGIC;
41 sample_in1 : IN samplT(7 DOWNTO 0, 17 DOWNTO 0);
42 sample_in2_val : IN STD_LOGIC;
43 sample_in2 : IN samplT(7 DOWNTO 0, 17 DOWNTO 0);
44 sample_out1_val : OUT STD_LOGIC;
45 sample_out1 : OUT samplT(7 DOWNTO 0, 17 DOWNTO 0);
46 sample_out2_val : OUT STD_LOGIC;
47 sample_out2 : OUT samplT(7 DOWNTO 0, 17 DOWNTO 0));
48 END COMPONENT;
49
50 SIGNAL clk : STD_LOGIC := '0';
30 SIGNAL clk : STD_LOGIC := '0';
51 SIGNAL clk_24k : STD_LOGIC := '0';
31 SIGNAL clk_24k : STD_LOGIC := '0';
52 SIGNAL clk_24k_r : STD_LOGIC := '0';
32 SIGNAL clk_24k_r : STD_LOGIC := '0';
53 SIGNAL rstn : STD_LOGIC;
33 SIGNAL rstn : STD_LOGIC;
54
34
35 SIGNAL signal_gen : Samples(7 DOWNTO 0);
36 SIGNAL offset_gen : Samples(7 DOWNTO 0);
37
55 SIGNAL sample : Samples(7 DOWNTO 0);
38 SIGNAL sample : Samples(7 DOWNTO 0);
39
56 SIGNAL sample_val : STD_LOGIC;
40 SIGNAL sample_val : STD_LOGIC;
57 SIGNAL sample_val_2 : STD_LOGIC;
58
41
59 SIGNAL data_chirp : STD_LOGIC_VECTOR(15 DOWNTO 0);
42 SIGNAL sample_f0_val : STD_LOGIC;
60 SIGNAL data_chirp_2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
43 SIGNAL sample_f1_val : STD_LOGIC;
44 SIGNAL sample_f2_val : STD_LOGIC;
45 SIGNAL sample_f3_val : STD_LOGIC;
61
46
62 SIGNAL sample_s : samplT(7 DOWNTO 0, 17 DOWNTO 0);
47 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
63 SIGNAL sample_out_s : samplT(7 DOWNTO 0, 17 DOWNTO 0);
48 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
64 SIGNAL sample_out_s2 : samplT(7 DOWNTO 0, 17 DOWNTO 0);
49 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
65 SIGNAL sample_out_val : STD_LOGIC;
50 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
51
52 SIGNAL sample_f0 : Samples(5 DOWNTO 0);
53 SIGNAL sample_f1 : Samples(5 DOWNTO 0);
54 SIGNAL sample_f2 : Samples(5 DOWNTO 0);
55 SIGNAL sample_f3 : Samples(5 DOWNTO 0);
56
66
57
67
58
68 SIGNAL sample_out1_val : STD_LOGIC;
59 SIGNAL temp : STD_LOGIC;
69 SIGNAL sample_out2_val : STD_LOGIC;
60
70 SIGNAL sample_out1 : samplT(7 DOWNTO 0, 17 DOWNTO 0);
61
71 SIGNAL sample_out2 : samplT(7 DOWNTO 0, 17 DOWNTO 0);
62 COMPONENT generator IS
72 SIGNAL sample_out1_reg : samplT(7 DOWNTO 0, 17 DOWNTO 0);
63 GENERIC (
73 SIGNAL sample_out2_reg : samplT(7 DOWNTO 0, 17 DOWNTO 0);
64 AMPLITUDE : INTEGER := 100;
65 NB_BITS : INTEGER := 16);
66
67 PORT (
68 clk : IN STD_LOGIC;
69 rstn : IN STD_LOGIC;
70 run : IN STD_LOGIC;
74
71
75 SIGNAL sample_s_v3 : samplT(7 DOWNTO 0, 17 DOWNTO 0);
72 data_ack : IN STD_LOGIC;
76 SIGNAL sample_val_v3 : STD_LOGIC;
73 offset : IN STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0);
77 SIGNAL sample_val_v3_2 : STD_LOGIC;
74 data : OUT STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0)
75 );
76 END COMPONENT;
77
78
78
79 SIGNAL temp : STD_LOGIC;
79 file log_input : TEXT open write_mode is "log_input.txt";
80 file log_output_f0 : TEXT open write_mode is "log_output_f0.txt";
81 file log_output_f1 : TEXT open write_mode is "log_output_f1.txt";
82 file log_output_f2 : TEXT open write_mode is "log_output_f2.txt";
83 file log_output_f3 : TEXT open write_mode is "log_output_f3.txt";
84
85
80 BEGIN
86 BEGIN
81
87
82 -----------------------------------------------------------------------------
88 -----------------------------------------------------------------------------
83 -- CLOCK and RESET
89 -- CLOCK and RESET
84 -----------------------------------------------------------------------------
90 -----------------------------------------------------------------------------
85 clk <= NOT clk AFTER 5 ns;
91 clk <= NOT clk AFTER 5 ns;
86 PROCESS
92 PROCESS
87 BEGIN -- PROCESS
93 BEGIN -- PROCESS
88 WAIT UNTIL clk = '1';
94 WAIT UNTIL clk = '1';
89 rstn <= '0';
95 rstn <= '0';
90 WAIT UNTIL clk = '1';
96 WAIT UNTIL clk = '1';
91 WAIT UNTIL clk = '1';
97 WAIT UNTIL clk = '1';
92 WAIT UNTIL clk = '1';
98 WAIT UNTIL clk = '1';
93 rstn <= '1';
99 rstn <= '1';
94 WAIT FOR 30 ms;
100 WAIT FOR 2000 ms;
95 REPORT "*** END simulation ***" SEVERITY failure;
101 REPORT "*** END simulation ***" SEVERITY failure;
96 WAIT;
102 WAIT;
97 END PROCESS;
103 END PROCESS;
98 -----------------------------------------------------------------------------
104 -----------------------------------------------------------------------------
99
105
100
106
101 -----------------------------------------------------------------------------
107 -----------------------------------------------------------------------------
108 -- COMMON TIMESTAMPS
109 -----------------------------------------------------------------------------
110
111 PROCESS(clk)
112 BEGIN
113 IF clk'event and clk ='1' THEN
114 TSTAMP <= TSTAMP+1;
115 END IF;
116 END PROCESS;
117 -----------------------------------------------------------------------------
118
119
120 -----------------------------------------------------------------------------
102 -- LPP_LFR_FILTER
121 -- LPP_LFR_FILTER
103 -----------------------------------------------------------------------------
122 -----------------------------------------------------------------------------
104 lpp_lfr_filter_1: lpp_lfr_filter
123 lpp_lfr_filter_1: lpp_lfr_filter
105 GENERIC MAP (
124 GENERIC MAP (
106 Mem_use => use_CEL)
125 --tech => 0,
126 --Mem_use => use_CEL,
127 tech => axcel,
128 Mem_use => use_RAM,
129 RTL_DESIGN_LIGHT =>0
130 )
107 PORT MAP (
131 PORT MAP (
108 sample => sample,
132 sample => sample,
109 sample_val => sample_val,
133 sample_val => sample_val,
110
134 sample_time => (others=>'0'),
111 clk => clk,
135 clk => clk,
112 rstn => rstn,
136 rstn => rstn,
113
137
114 data_shaping_SP0 => '0',
138 data_shaping_SP0 => '0',
115 data_shaping_SP1 => '0',
139 data_shaping_SP1 => '0',
116 data_shaping_R0 => '0',
140 data_shaping_R0 => '0',
117 data_shaping_R1 => '0',
141 data_shaping_R1 => '0',
118 data_shaping_R2 => '0',
142 data_shaping_R2 => '0',
119
143
120 sample_f0_val => OPEN,
144 sample_f0_val => sample_f0_val,
121 sample_f1_val => OPEN,
145 sample_f1_val => sample_f1_val,
122 sample_f2_val => OPEN,
146 sample_f2_val => sample_f2_val,
123 sample_f3_val => OPEN,
147 sample_f3_val => sample_f3_val,
124 sample_f0_wdata => OPEN,
148
125 sample_f1_wdata => OPEN,
149 sample_f0_wdata => sample_f0_wdata,
126 sample_f2_wdata => OPEN,
150 sample_f1_wdata => sample_f1_wdata,
127 sample_f3_wdata => OPEN);
151 sample_f2_wdata => sample_f2_wdata,
152 sample_f3_wdata => sample_f3_wdata
153 );
128 -----------------------------------------------------------------------------
154 -----------------------------------------------------------------------------
129
155
130
156
131 -----------------------------------------------------------------------------
157 -----------------------------------------------------------------------------
132 -- SAMPLE GENERATION
158 -- SAMPLE GENERATION
133 -----------------------------------------------------------------------------
159 -----------------------------------------------------------------------------
134 clk_24k <= NOT clk_24k AFTER 20345 ns;
160 clk_24k <= NOT clk_24k AFTER 20345 ns;
135
161
136 PROCESS (clk, rstn)
162 PROCESS (clk, rstn)
137 BEGIN -- PROCESS
163 BEGIN -- PROCESS
138 IF rstn = '0' THEN -- asynchronous reset (active low)
164 IF rstn = '0' THEN -- asynchronous reset (active low)
139 sample_val <= '0';
165 sample_val <= '0';
140 sample_val_2 <= '0';
141 clk_24k_r <= '0';
166 clk_24k_r <= '0';
142 temp <= '0';
167 temp <= '0';
143 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
168 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
144 clk_24k_r <= clk_24k;
169 clk_24k_r <= clk_24k;
145 IF clk_24k = '1' AND clk_24k_r = '0' THEN
170 IF clk_24k = '1' AND clk_24k_r = '0' THEN
146 sample_val <= '1';
171 sample_val <= '1';
147 sample_val_2 <= temp;
148 temp <= NOT temp;
172 temp <= NOT temp;
149 ELSE
173 ELSE
150 sample_val <= '0';
174 sample_val <= '0';
151 sample_val_2 <= '0';
152 END IF;
175 END IF;
153 END IF;
176 END IF;
154 END PROCESS;
177 END PROCESS;
155 -----------------------------------------------------------------------------
178 -----------------------------------------------------------------------------
156 chirp_1: chirp
179 generators: FOR I IN 0 TO 7 GENERATE
180 gen1: generator
157 GENERIC MAP (
181 GENERIC MAP (
158 LOW_FREQUENCY_LIMIT => 0,
159 HIGH_FREQUENCY_LIMIT => 2000,
160 NB_POINT_TO_GEN => 10000,
161 AMPLITUDE => 100,
182 AMPLITUDE => 100,
162 NB_BITS => 16)
183 NB_BITS => 16)
163 PORT MAP (
184 PORT MAP (
164 clk => clk,
185 clk => clk,
165 rstn => rstn,
186 rstn => rstn,
166 run => '1',
187 run => '1',
167 data_ack => sample_val,
188 data_ack => sample_val,
168 data => data_chirp);
189 offset => offset_gen(I),
190 data => signal_gen(I)
191 );
192 offset_gen(I) <= std_logic_vector( to_signed((I*200),16) );
193 END GENERATE generators;
169
194
170 chirp_2: chirp
195 output_splitter: FOR CHAN IN 0 TO 5 GENERATE
171 GENERIC MAP (
196 bits_splitter: FOR BIT IN 0 TO 15 GENERATE
172 LOW_FREQUENCY_LIMIT => 0,
197 sample_f0(CHAN)(BIT) <= sample_f0_wdata((CHAN*16) + BIT);
173 HIGH_FREQUENCY_LIMIT => 2000,
198 sample_f1(CHAN)(BIT) <= sample_f1_wdata((CHAN*16) + BIT);
174 NB_POINT_TO_GEN => 100000,
199 sample_f2(CHAN)(BIT) <= sample_f2_wdata((CHAN*16) + BIT);
175 AMPLITUDE => 200,
200 sample_f3(CHAN)(BIT) <= sample_f3_wdata((CHAN*16) + BIT);
176 NB_BITS => 16)
201 END GENERATE bits_splitter;
177 PORT MAP (
202 END GENERATE output_splitter;
178 clk => clk,
179 rstn => rstn,
180 run => '1',
181 data_ack => sample_val,
182 data => data_chirp_2);
183
203
184 all_channel: FOR I IN 0 TO 3 GENERATE
204
185 sample(2*I) <= data_chirp;
205 sample <= signal_gen;
186 sample(2*I+1) <= data_chirp_2;
206
187 END GENERATE all_channel;
207 -----------------------------------------------------------------------------
208 -- RECORD SIGNALS
188 -----------------------------------------------------------------------------
209 -----------------------------------------------------------------------------
189
210
190 all_channel_test: FOR I IN 0 TO 3 GENERATE
211 process(sample_val)
191 all_bit_test: FOR J IN 0 TO 15 GENERATE
212 variable line_var : line;
192 sample_s(2*I ,J) <= data_chirp(J);
213 begin
193 sample_s(2*I+1,J) <= data_chirp_2(J);
214 if sample_val'event and sample_val='1' then
194 END GENERATE all_bit_test;
215 write(line_var,integer'image(TSTAMP) );
195 sample_s(2*I,16) <= data_chirp(15);
216 for I IN 0 TO 7 loop
196 sample_s(2*I,17) <= data_chirp(15);
217 write(line_var, " " & integer'image(to_integer(signed(signal_gen(I)))));
197 sample_s(2*I+1,16) <= data_chirp_2(15);
218 end loop;
198 sample_s(2*I+1,17) <= data_chirp_2(15);
219 writeline(log_input,line_var);
199 END GENERATE all_channel_test;
220 end if;
221 end process;
200
222
201 IIR_CEL_TEST_1: IIR_CEL_TEST
223 process(sample_f0_val)
202 PORT MAP (
224 variable line_var : line;
203 rstn => rstn,
225 begin
204 clk => clk,
226 if sample_f0_val'event and sample_f0_val='1' then
205 sample_in_val => sample_val,
227 write(line_var,integer'image(TSTAMP) );
206 sample_in => sample_s,
228 for I IN 0 TO 5 loop
207 sample_out_val => sample_out_val,
229 write(line_var, " " & integer'image(to_integer(signed(sample_f0(I)))));
208 sample_out => sample_out_s);
230 end loop;
231 writeline(log_output_f0,line_var);
232 end if;
233 end process;
209
234
210 PROCESS (clk, rstn)
211 BEGIN -- PROCESS
212 IF rstn = '0' THEN -- asynchronous reset (active low)
213 all_channel: FOR I IN 0 TO 7 LOOP
214 all_bit: FOR J IN 0 TO 17 LOOP
215 sample_out_s2(I,J) <= '0';
216 END LOOP all_bit;
217 END LOOP all_channel;
218
235
219 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
236 process(sample_f1_val)
220 IF sample_out_val = '1' THEN
237 variable line_var : line;
221 sample_out_s2 <= sample_out_s;
238 begin
222 END IF;
239 if sample_f1_val'event and sample_f1_val='1' then
223 END IF;
240 write(line_var,integer'image(TSTAMP) );
224 END PROCESS;
241 for I IN 0 TO 5 loop
225 -----------------------------------------------------------------------------
242 write(line_var, " " & integer'image(to_integer(signed(sample_f1(I)))));
226 IIR_CEL_TEST_v3_1: IIR_CEL_TEST_v3
243 end loop;
227 PORT MAP (
244 writeline(log_output_f1,line_var);
228 rstn => rstn,
245 end if;
229 clk => clk,
246 end process;
230 sample_in1_val => sample_val_v3,
247
231 sample_in1 => sample_s_v3,
232 sample_in2_val => sample_val_v3_2,
233 sample_in2 => sample_s_v3,
234 sample_out1_val => sample_out1_val,
235 sample_out1 => sample_out1,
236 sample_out2_val => sample_out2_val,
237 sample_out2 => sample_out2);
238
248
239 PROCESS (clk, rstn)
249 process(sample_f2_val)
240 BEGIN -- PROCESS
250 variable line_var : line;
241 IF rstn = '0' THEN -- asynchronous reset (active low)
251 begin
252 if sample_f2_val'event and sample_f2_val='1' then
253 write(line_var,integer'image(TSTAMP) );
254 for I IN 0 TO 5 loop
255 write(line_var, " " & integer'image(to_integer(signed(sample_f2(I)))));
256 end loop;
257 writeline(log_output_f2,line_var);
258 end if;
259 end process;
242
260
243 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
261 process(sample_f3_val)
244 IF sample_val = '1' THEN
262 variable line_var : line;
245 sample_s_v3 <= sample_s;
263 begin
246 END IF;
264 if sample_f3_val'event and sample_f3_val='1' then
247 sample_val_v3 <= sample_val;
265 write(line_var,integer'image(TSTAMP) );
248 sample_val_v3_2 <= sample_val_2;
266 for I IN 0 TO 5 loop
267 write(line_var, " " & integer'image(to_integer(signed(sample_f3(I)))));
268 end loop;
269 writeline(log_output_f3,line_var);
270 end if;
271 end process;
249
272
250 IF sample_out1_val = '1' THEN
251 sample_out1_reg <= sample_out1;
252 END IF;
253 IF sample_out2_val = '1' THEN
254 sample_out2_reg <= sample_out2;
255 END IF;
256 END IF;
257
258 END PROCESS;
259
273
260
274
261
275
262 END;
276 END;
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@@ -1,258 +1,265
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22
22
23 LIBRARY IEEE;
23 LIBRARY IEEE;
24 USE IEEE.numeric_std.ALL;
24 USE IEEE.numeric_std.ALL;
25 USE IEEE.std_logic_1164.ALL;
25 USE IEEE.std_logic_1164.ALL;
26
26
27 LIBRARY techmap;
27 LIBRARY techmap;
28 USE techmap.gencomp.ALL;
28 USE techmap.gencomp.ALL;
29
29
30 LIBRARY lpp;
30 LIBRARY lpp;
31 USE lpp.iir_filter.ALL;
31 USE lpp.iir_filter.ALL;
32 USE lpp.general_purpose.ALL;
32 USE lpp.general_purpose.ALL;
33
33
34 ENTITY IIR_CEL_CTRLR_v2 IS
34 ENTITY IIR_CEL_CTRLR_v2 IS
35 GENERIC (
35 GENERIC (
36 tech : INTEGER := 0;
36 tech : INTEGER := 0;
37 Mem_use : INTEGER := use_RAM;
37 Mem_use : INTEGER := use_RAM;
38 Sample_SZ : INTEGER := 18;
38 Sample_SZ : INTEGER := 18;
39 Coef_SZ : INTEGER := 9;
39 Coef_SZ : INTEGER := 9;
40 Coef_Nb : INTEGER := 25;
40 Coef_Nb : INTEGER := 25;
41 Coef_sel_SZ : INTEGER := 5;
41 Coef_sel_SZ : INTEGER := 5;
42 Cels_count : INTEGER := 5;
42 Cels_count : INTEGER := 5;
43 ChanelsCount : INTEGER := 8);
43 ChanelsCount : INTEGER := 8);
44 PORT (
44 PORT (
45 rstn : IN STD_LOGIC;
45 rstn : IN STD_LOGIC;
46 clk : IN STD_LOGIC;
46 clk : IN STD_LOGIC;
47
47
48 virg_pos : IN INTEGER;
48 virg_pos : IN INTEGER;
49 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
49 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
50
50
51 sample_in_val : IN STD_LOGIC;
51 sample_in_val : IN STD_LOGIC;
52 sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
52 sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
53
53
54 sample_out_val : OUT STD_LOGIC;
54 sample_out_val : OUT STD_LOGIC;
55 sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0));
55 sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0));
56 END IIR_CEL_CTRLR_v2;
56 END IIR_CEL_CTRLR_v2;
57
57
58 ARCHITECTURE ar_IIR_CEL_CTRLR_v2 OF IIR_CEL_CTRLR_v2 IS
58 ARCHITECTURE ar_IIR_CEL_CTRLR_v2 OF IIR_CEL_CTRLR_v2 IS
59
59
60 COMPONENT IIR_CEL_CTRLR_v2_DATAFLOW
60 COMPONENT IIR_CEL_CTRLR_v2_DATAFLOW
61 GENERIC (
61 GENERIC (
62 tech : INTEGER;
62 tech : INTEGER;
63 Mem_use : INTEGER;
63 Mem_use : INTEGER;
64 Sample_SZ : INTEGER;
64 Sample_SZ : INTEGER;
65 Coef_SZ : INTEGER;
65 Coef_SZ : INTEGER;
66 Coef_Nb : INTEGER;
66 Coef_Nb : INTEGER;
67 Coef_sel_SZ : INTEGER);
67 Coef_sel_SZ : INTEGER);
68 PORT (
68 PORT (
69 rstn : IN STD_LOGIC;
69 rstn : IN STD_LOGIC;
70 clk : IN STD_LOGIC;
70 clk : IN STD_LOGIC;
71 virg_pos : IN INTEGER;
71 virg_pos : IN INTEGER;
72 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
72 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
73 in_sel_src : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
73 in_sel_src : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
74 init_mem_done : out STD_LOGIC;
74 ram_sel_Wdata : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
75 ram_sel_Wdata : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
75 ram_write : IN STD_LOGIC;
76 ram_write : IN STD_LOGIC;
76 ram_read : IN STD_LOGIC;
77 ram_read : IN STD_LOGIC;
77 raddr_rst : IN STD_LOGIC;
78 raddr_rst : IN STD_LOGIC;
78 raddr_add1 : IN STD_LOGIC;
79 raddr_add1 : IN STD_LOGIC;
79 waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
80 waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
80 alu_sel_input : IN STD_LOGIC;
81 alu_sel_input : IN STD_LOGIC;
81 alu_sel_coeff : IN STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
82 alu_sel_coeff : IN STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
82 alu_ctrl : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
83 alu_ctrl : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
83 alu_comp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
84 alu_comp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
84 sample_in : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
85 sample_in : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
85 sample_out : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0));
86 sample_out : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0));
86 END COMPONENT;
87 END COMPONENT;
87
88
88 COMPONENT IIR_CEL_CTRLR_v2_CONTROL
89 COMPONENT IIR_CEL_CTRLR_v2_CONTROL
89 GENERIC (
90 GENERIC (
90 Coef_sel_SZ : INTEGER;
91 Coef_sel_SZ : INTEGER;
91 Cels_count : INTEGER;
92 Cels_count : INTEGER;
92 ChanelsCount : INTEGER);
93 ChanelsCount : INTEGER);
93 PORT (
94 PORT (
94 rstn : IN STD_LOGIC;
95 rstn : IN STD_LOGIC;
95 clk : IN STD_LOGIC;
96 clk : IN STD_LOGIC;
96 sample_in_val : IN STD_LOGIC;
97 sample_in_val : IN STD_LOGIC;
97 sample_in_rot : OUT STD_LOGIC;
98 sample_in_rot : OUT STD_LOGIC;
98 sample_out_val : OUT STD_LOGIC;
99 sample_out_val : OUT STD_LOGIC;
99 sample_out_rot : OUT STD_LOGIC;
100 sample_out_rot : OUT STD_LOGIC;
101 init_mem_done : in STD_LOGIC; --TODO
100 in_sel_src : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
102 in_sel_src : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
101 ram_sel_Wdata : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
103 ram_sel_Wdata : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
102 ram_write : OUT STD_LOGIC;
104 ram_write : OUT STD_LOGIC;
103 ram_read : OUT STD_LOGIC;
105 ram_read : OUT STD_LOGIC;
104 raddr_rst : OUT STD_LOGIC;
106 raddr_rst : OUT STD_LOGIC;
105 raddr_add1 : OUT STD_LOGIC;
107 raddr_add1 : OUT STD_LOGIC;
106 waddr_previous : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
108 waddr_previous : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
107 alu_sel_input : OUT STD_LOGIC;
109 alu_sel_input : OUT STD_LOGIC;
108 alu_sel_coeff : OUT STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
110 alu_sel_coeff : OUT STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
109 alu_ctrl : OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
111 alu_ctrl : OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
110 END COMPONENT;
112 END COMPONENT;
111
113
112 SIGNAL in_sel_src : STD_LOGIC_VECTOR(1 DOWNTO 0);
114 SIGNAL in_sel_src : STD_LOGIC_VECTOR(1 DOWNTO 0);
113 SIGNAL ram_sel_Wdata : STD_LOGIC_VECTOR(1 DOWNTO 0);
115 SIGNAL ram_sel_Wdata : STD_LOGIC_VECTOR(1 DOWNTO 0);
114 SIGNAL ram_write : STD_LOGIC;
116 SIGNAL ram_write : STD_LOGIC;
115 SIGNAL ram_read : STD_LOGIC;
117 SIGNAL ram_read : STD_LOGIC;
116 SIGNAL raddr_rst : STD_LOGIC;
118 SIGNAL raddr_rst : STD_LOGIC;
117 SIGNAL raddr_add1 : STD_LOGIC;
119 SIGNAL raddr_add1 : STD_LOGIC;
118 SIGNAL waddr_previous : STD_LOGIC_VECTOR(1 DOWNTO 0);
120 SIGNAL waddr_previous : STD_LOGIC_VECTOR(1 DOWNTO 0);
119 SIGNAL alu_sel_input : STD_LOGIC;
121 SIGNAL alu_sel_input : STD_LOGIC;
120 SIGNAL alu_sel_coeff : STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
122 SIGNAL alu_sel_coeff : STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
121 SIGNAL alu_ctrl : STD_LOGIC_VECTOR(2 DOWNTO 0);
123 SIGNAL alu_ctrl : STD_LOGIC_VECTOR(2 DOWNTO 0);
122
124
123 SIGNAL sample_in_buf : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
125 SIGNAL sample_in_buf : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
124 SIGNAL sample_in_rotate : STD_LOGIC;
126 SIGNAL sample_in_rotate : STD_LOGIC;
125 SIGNAL sample_in_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
127 SIGNAL sample_in_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
126 SIGNAL sample_out_val_s : STD_LOGIC;
128 SIGNAL sample_out_val_s : STD_LOGIC;
127 SIGNAL sample_out_val_s2 : STD_LOGIC;
129 SIGNAL sample_out_val_s2 : STD_LOGIC;
128 SIGNAL sample_out_rot_s : STD_LOGIC;
130 SIGNAL sample_out_rot_s : STD_LOGIC;
129 SIGNAL sample_out_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
131 SIGNAL sample_out_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
130
132
131 SIGNAL sample_out_s2 : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
133 SIGNAL sample_out_s2 : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
132
134
135 signal init_mem_done : std_logic;
136
133 BEGIN
137 BEGIN
134
138
135 IIR_CEL_CTRLR_v2_DATAFLOW_1 : IIR_CEL_CTRLR_v2_DATAFLOW
139 IIR_CEL_CTRLR_v2_DATAFLOW_1 : IIR_CEL_CTRLR_v2_DATAFLOW
136 GENERIC MAP (
140 GENERIC MAP (
137 tech => tech,
141 tech => tech,
138 Mem_use => Mem_use,
142 Mem_use => Mem_use,
139 Sample_SZ => Sample_SZ,
143 Sample_SZ => Sample_SZ,
140 Coef_SZ => Coef_SZ,
144 Coef_SZ => Coef_SZ,
141 Coef_Nb => Coef_Nb,
145 Coef_Nb => Coef_Nb,
142 Coef_sel_SZ => Coef_sel_SZ)
146 Coef_sel_SZ => Coef_sel_SZ)
143 PORT MAP (
147 PORT MAP (
144 rstn => rstn,
148 rstn => rstn,
145 clk => clk,
149 clk => clk,
146 virg_pos => virg_pos,
150 virg_pos => virg_pos,
147 coefs => coefs,
151 coefs => coefs,
148 --CTRL
152 --CTRL
149 in_sel_src => in_sel_src,
153 in_sel_src => in_sel_src,
154 init_mem_done => init_mem_done, --TODO
150 ram_sel_Wdata => ram_sel_Wdata,
155 ram_sel_Wdata => ram_sel_Wdata,
151 ram_write => ram_write,
156 ram_write => ram_write,
152 ram_read => ram_read,
157 ram_read => ram_read,
153 raddr_rst => raddr_rst,
158 raddr_rst => raddr_rst,
154 raddr_add1 => raddr_add1,
159 raddr_add1 => raddr_add1,
155 waddr_previous => waddr_previous,
160 waddr_previous => waddr_previous,
156 alu_sel_input => alu_sel_input,
161 alu_sel_input => alu_sel_input,
157 alu_sel_coeff => alu_sel_coeff,
162 alu_sel_coeff => alu_sel_coeff,
158 alu_ctrl => alu_ctrl,
163 alu_ctrl => alu_ctrl,
159 alu_comp => "00",
164 alu_comp => "00",
160 --DATA
165 --DATA
161 sample_in => sample_in_s,
166 sample_in => sample_in_s,
162 sample_out => sample_out_s);
167 sample_out => sample_out_s);
163
168
164
169
165 IIR_CEL_CTRLR_v2_CONTROL_1 : IIR_CEL_CTRLR_v2_CONTROL
170 IIR_CEL_CTRLR_v2_CONTROL_1 : IIR_CEL_CTRLR_v2_CONTROL
166 GENERIC MAP (
171 GENERIC MAP (
167 Coef_sel_SZ => Coef_sel_SZ,
172 Coef_sel_SZ => Coef_sel_SZ,
168 Cels_count => Cels_count,
173 Cels_count => Cels_count,
169 ChanelsCount => ChanelsCount)
174 ChanelsCount => ChanelsCount)
170 PORT MAP (
175 PORT MAP (
171 rstn => rstn,
176 rstn => rstn,
172 clk => clk,
177 clk => clk,
173 sample_in_val => sample_in_val,
178 sample_in_val => sample_in_val,
174 sample_in_rot => sample_in_rotate,
179 sample_in_rot => sample_in_rotate,
175 sample_out_val => sample_out_val_s,
180 sample_out_val => sample_out_val_s,
176 sample_out_rot => sample_out_rot_s,
181 sample_out_rot => sample_out_rot_s,
177
182
183 init_mem_done => init_mem_done, --TODO
184
178 in_sel_src => in_sel_src,
185 in_sel_src => in_sel_src,
179 ram_sel_Wdata => ram_sel_Wdata,
186 ram_sel_Wdata => ram_sel_Wdata,
180 ram_write => ram_write,
187 ram_write => ram_write,
181 ram_read => ram_read,
188 ram_read => ram_read,
182 raddr_rst => raddr_rst,
189 raddr_rst => raddr_rst,
183 raddr_add1 => raddr_add1,
190 raddr_add1 => raddr_add1,
184 waddr_previous => waddr_previous,
191 waddr_previous => waddr_previous,
185 alu_sel_input => alu_sel_input,
192 alu_sel_input => alu_sel_input,
186 alu_sel_coeff => alu_sel_coeff,
193 alu_sel_coeff => alu_sel_coeff,
187 alu_ctrl => alu_ctrl);
194 alu_ctrl => alu_ctrl);
188
195
189 -----------------------------------------------------------------------------
196 -----------------------------------------------------------------------------
190 -- SAMPLE IN
197 -- SAMPLE IN
191 -----------------------------------------------------------------------------
198 -----------------------------------------------------------------------------
192 loop_all_sample : FOR J IN Sample_SZ-1 DOWNTO 0 GENERATE
199 loop_all_sample : FOR J IN Sample_SZ-1 DOWNTO 0 GENERATE
193
200
194 loop_all_chanel : FOR I IN ChanelsCount-1 DOWNTO 0 GENERATE
201 loop_all_chanel : FOR I IN ChanelsCount-1 DOWNTO 0 GENERATE
195 PROCESS (clk, rstn)
202 PROCESS (clk, rstn)
196 BEGIN -- PROCESS
203 BEGIN -- PROCESS
197 IF rstn = '0' THEN -- asynchronous reset (active low)
204 IF rstn = '0' THEN -- asynchronous reset (active low)
198 sample_in_buf(I, J) <= '0';
205 sample_in_buf(I, J) <= '0';
199 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
206 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
200 IF sample_in_val = '1' THEN
207 IF sample_in_val = '1' THEN
201 sample_in_buf(I, J) <= sample_in(I, J);
208 sample_in_buf(I, J) <= sample_in(I, J);
202 ELSIF sample_in_rotate = '1' THEN
209 ELSIF sample_in_rotate = '1' THEN
203 sample_in_buf(I, J) <= sample_in_buf((I+1) MOD ChanelsCount, J);
210 sample_in_buf(I, J) <= sample_in_buf((I+1) MOD ChanelsCount, J);
204 END IF;
211 END IF;
205 END IF;
212 END IF;
206 END PROCESS;
213 END PROCESS;
207 END GENERATE loop_all_chanel;
214 END GENERATE loop_all_chanel;
208
215
209 sample_in_s(J) <= sample_in(0, J) WHEN sample_in_val = '1' ELSE sample_in_buf(0, J);
216 sample_in_s(J) <= sample_in(0, J) WHEN sample_in_val = '1' ELSE sample_in_buf(0, J);
210
217
211 END GENERATE loop_all_sample;
218 END GENERATE loop_all_sample;
212
219
213 -----------------------------------------------------------------------------
220 -----------------------------------------------------------------------------
214 -- SAMPLE OUT
221 -- SAMPLE OUT
215 -----------------------------------------------------------------------------
222 -----------------------------------------------------------------------------
216 PROCESS (clk, rstn)
223 PROCESS (clk, rstn)
217 BEGIN -- PROCESS
224 BEGIN -- PROCESS
218 IF rstn = '0' THEN -- asynchronous reset (active low)
225 IF rstn = '0' THEN -- asynchronous reset (active low)
219 sample_out_val <= '0';
226 sample_out_val <= '0';
220 sample_out_val_s2 <= '0';
227 sample_out_val_s2 <= '0';
221 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
228 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
222 sample_out_val <= sample_out_val_s2;
229 sample_out_val <= sample_out_val_s2;
223 sample_out_val_s2 <= sample_out_val_s;
230 sample_out_val_s2 <= sample_out_val_s;
224 END IF;
231 END IF;
225 END PROCESS;
232 END PROCESS;
226
233
227 chanel_HIGH : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE
234 chanel_HIGH : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE
228 PROCESS (clk, rstn)
235 PROCESS (clk, rstn)
229 BEGIN -- PROCESS
236 BEGIN -- PROCESS
230 IF rstn = '0' THEN -- asynchronous reset (active low)
237 IF rstn = '0' THEN -- asynchronous reset (active low)
231 sample_out_s2(ChanelsCount-1, I) <= '0';
238 sample_out_s2(ChanelsCount-1, I) <= '0';
232 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
239 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
233 IF sample_out_rot_s = '1' THEN
240 IF sample_out_rot_s = '1' THEN
234 sample_out_s2(ChanelsCount-1, I) <= sample_out_s(I);
241 sample_out_s2(ChanelsCount-1, I) <= sample_out_s(I);
235 END IF;
242 END IF;
236 END IF;
243 END IF;
237 END PROCESS;
244 END PROCESS;
238 END GENERATE chanel_HIGH;
245 END GENERATE chanel_HIGH;
239
246
240 chanel_more : IF ChanelsCount > 1 GENERATE
247 chanel_more : IF ChanelsCount > 1 GENERATE
241 all_chanel : FOR J IN ChanelsCount-1 DOWNTO 1 GENERATE
248 all_chanel : FOR J IN ChanelsCount-1 DOWNTO 1 GENERATE
242 all_bit : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE
249 all_bit : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE
243 PROCESS (clk, rstn)
250 PROCESS (clk, rstn)
244 BEGIN -- PROCESS
251 BEGIN -- PROCESS
245 IF rstn = '0' THEN -- asynchronous reset (active low)
252 IF rstn = '0' THEN -- asynchronous reset (active low)
246 sample_out_s2(J-1, I) <= '0';
253 sample_out_s2(J-1, I) <= '0';
247 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
254 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
248 IF sample_out_rot_s = '1' THEN
255 IF sample_out_rot_s = '1' THEN
249 sample_out_s2(J-1, I) <= sample_out_s2(J, I);
256 sample_out_s2(J-1, I) <= sample_out_s2(J, I);
250 END IF;
257 END IF;
251 END IF;
258 END IF;
252 END PROCESS;
259 END PROCESS;
253 END GENERATE all_bit;
260 END GENERATE all_bit;
254 END GENERATE all_chanel;
261 END GENERATE all_chanel;
255 END GENERATE chanel_more;
262 END GENERATE chanel_more;
256
263
257 sample_out <= sample_out_s2;
264 sample_out <= sample_out_s2;
258 END ar_IIR_CEL_CTRLR_v2;
265 END ar_IIR_CEL_CTRLR_v2;
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@@ -1,315 +1,317
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more Cdetails.
13 -- GNU General Public License for more Cdetails.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22
22
23 LIBRARY IEEE;
23 LIBRARY IEEE;
24 USE IEEE.numeric_std.ALL;
24 USE IEEE.numeric_std.ALL;
25 USE IEEE.std_logic_1164.ALL;
25 USE IEEE.std_logic_1164.ALL;
26 LIBRARY lpp;
26 LIBRARY lpp;
27 USE lpp.iir_filter.ALL;
27 USE lpp.iir_filter.ALL;
28 USE lpp.general_purpose.ALL;
28 USE lpp.general_purpose.ALL;
29
29
30 ENTITY IIR_CEL_CTRLR_v2_CONTROL IS
30 ENTITY IIR_CEL_CTRLR_v2_CONTROL IS
31 GENERIC (
31 GENERIC (
32 Coef_sel_SZ : INTEGER;
32 Coef_sel_SZ : INTEGER;
33 Cels_count : INTEGER := 5;
33 Cels_count : INTEGER := 5;
34 ChanelsCount : INTEGER := 1);
34 ChanelsCount : INTEGER := 1);
35 PORT (
35 PORT (
36 rstn : IN STD_LOGIC;
36 rstn : IN STD_LOGIC;
37 clk : IN STD_LOGIC;
37 clk : IN STD_LOGIC;
38
38
39 sample_in_val : IN STD_LOGIC;
39 sample_in_val : IN STD_LOGIC;
40 sample_in_rot : OUT STD_LOGIC;
40 sample_in_rot : OUT STD_LOGIC;
41 sample_out_val : OUT STD_LOGIC;
41 sample_out_val : OUT STD_LOGIC;
42 sample_out_rot : OUT STD_LOGIC;
42 sample_out_rot : OUT STD_LOGIC;
43
43
44 init_mem_done : in STD_LOGIC; --TODO
45
44 in_sel_src : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
46 in_sel_src : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
45 ram_sel_Wdata : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
47 ram_sel_Wdata : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
46 ram_write : OUT STD_LOGIC;
48 ram_write : OUT STD_LOGIC;
47 ram_read : OUT STD_LOGIC;
49 ram_read : OUT STD_LOGIC;
48 raddr_rst : OUT STD_LOGIC;
50 raddr_rst : OUT STD_LOGIC;
49 raddr_add1 : OUT STD_LOGIC;
51 raddr_add1 : OUT STD_LOGIC;
50 waddr_previous : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
52 waddr_previous : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
51 alu_sel_input : OUT STD_LOGIC;
53 alu_sel_input : OUT STD_LOGIC;
52 alu_sel_coeff : OUT STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
54 alu_sel_coeff : OUT STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
53 alu_ctrl : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
55 alu_ctrl : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
54 );
56 );
55 END IIR_CEL_CTRLR_v2_CONTROL;
57 END IIR_CEL_CTRLR_v2_CONTROL;
56
58
57 ARCHITECTURE ar_IIR_CEL_CTRLR_v2_CONTROL OF IIR_CEL_CTRLR_v2_CONTROL IS
59 ARCHITECTURE ar_IIR_CEL_CTRLR_v2_CONTROL OF IIR_CEL_CTRLR_v2_CONTROL IS
58
60
59 TYPE fsmIIR_CEL_T IS (waiting,
61 TYPE fsmIIR_CEL_T IS (waiting,
60 first_read,
62 first_read,
61 compute_b0,
63 compute_b0,
62 compute_b1,
64 compute_b1,
63 compute_b2,
65 compute_b2,
64 compute_a1,
66 compute_a1,
65 compute_a2,
67 compute_a2,
66 LAST_CEL,
68 LAST_CEL,
67 wait_valid_last_output,
69 wait_valid_last_output,
68 wait_valid_last_output_2);
70 wait_valid_last_output_2);
69 SIGNAL IIR_CEL_STATE : fsmIIR_CEL_T;
71 SIGNAL IIR_CEL_STATE : fsmIIR_CEL_T;
70
72
71 SIGNAL alu_selected_coeff : INTEGER RANGE 0 TO 2**Coef_sel_SZ-1;
73 SIGNAL alu_selected_coeff : INTEGER RANGE 0 TO 2**Coef_sel_SZ-1;
72 SIGNAL Chanel_ongoing : INTEGER;
74 SIGNAL Chanel_ongoing : INTEGER;
73 SIGNAL Cel_ongoing : INTEGER;
75 SIGNAL Cel_ongoing : INTEGER;
74
76
75 BEGIN
77 BEGIN
76
78
77 alu_sel_coeff <= STD_LOGIC_VECTOR(to_unsigned(alu_selected_coeff, Coef_sel_SZ));
79 alu_sel_coeff <= STD_LOGIC_VECTOR(to_unsigned(alu_selected_coeff, Coef_sel_SZ));
78
80
79 PROCESS (clk, rstn)
81 PROCESS (clk, rstn)
80 BEGIN -- PROCESS
82 BEGIN -- PROCESS
81 IF rstn = '0' THEN -- asynchronous reset (active low)
83 IF rstn = '0' THEN -- asynchronous reset (active low)
82 --REG -------------------------------------------------------------------
84 --REG -------------------------------------------------------------------
83 in_sel_src <= (OTHERS => '0'); --
85 in_sel_src <= (OTHERS => '0'); --
84 --RAM_WRitE -------------------------------------------------------------
86 --RAM_WRitE -------------------------------------------------------------
85 ram_sel_Wdata <= "00"; --
87 ram_sel_Wdata <= "00"; --
86 ram_write <= '0'; --
88 ram_write <= '0'; --
87 waddr_previous <= "00"; --
89 waddr_previous <= "00"; --
88 --RAM_READ --------------------------------------------------------------
90 --RAM_READ --------------------------------------------------------------
89 ram_read <= '0'; --
91 ram_read <= '0'; --
90 raddr_rst <= '0'; --
92 raddr_rst <= '0'; --
91 raddr_add1 <= '0'; --
93 raddr_add1 <= '0'; --
92 --ALU -------------------------------------------------------------------
94 --ALU -------------------------------------------------------------------
93 alu_selected_coeff <= 0; --
95 alu_selected_coeff <= 0; --
94 alu_sel_input <= '0'; --
96 alu_sel_input <= '0'; --
95 alu_ctrl <= ctrl_IDLE; --
97 alu_ctrl <= ctrl_IDLE; --
96 --OUT
98 --OUT
97 sample_out_val <= '0'; --
99 sample_out_val <= '0'; --
98 sample_out_rot <= '0'; --
100 sample_out_rot <= '0'; --
99
101
100 Chanel_ongoing <= 0; --
102 Chanel_ongoing <= 0; --
101 Cel_ongoing <= 0; --
103 Cel_ongoing <= 0; --
102 sample_in_rot <= '0';
104 sample_in_rot <= '0';
103
105
104 IIR_CEL_STATE <= waiting;
106 IIR_CEL_STATE <= waiting;
105
107
106 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
108 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
107
109
108 CASE IIR_CEL_STATE IS
110 CASE IIR_CEL_STATE IS
109 WHEN waiting =>
111 WHEN waiting =>
110 sample_out_rot <= '0';
112 sample_out_rot <= '0';
111 sample_in_rot <= '0';
113 sample_in_rot <= '0';
112 sample_out_val <= '0';
114 sample_out_val <= '0';
113 alu_ctrl <= ctrl_CLRMAC;
115 alu_ctrl <= ctrl_CLRMAC;
114 alu_selected_coeff <= 0;
116 alu_selected_coeff <= 0;
115 in_sel_src <= "01";
117 in_sel_src <= "01";
116 ram_read <= '0';
118 ram_read <= '0';
117 ram_sel_Wdata <= "00";
119 ram_sel_Wdata <= "00";
118 ram_write <= '0';
120 ram_write <= '0';
119 waddr_previous <= "00";
121 waddr_previous <= "00";
120 IF sample_in_val = '1' THEN
122 IF sample_in_val = '1' and init_mem_done = '1' THEN
121 raddr_rst <= '0';
123 raddr_rst <= '0';
122 alu_sel_input <= '1';
124 alu_sel_input <= '1';
123 ram_read <= '1';
125 ram_read <= '1';
124 raddr_add1 <= '1';
126 raddr_add1 <= '1';
125 IIR_CEL_STATE <= first_read;
127 IIR_CEL_STATE <= first_read;
126 Chanel_ongoing <= Chanel_ongoing + 1;
128 Chanel_ongoing <= Chanel_ongoing + 1;
127 Cel_ongoing <= 1;
129 Cel_ongoing <= 1;
128 ELSE
130 ELSE
129 raddr_add1 <= '0';
131 raddr_add1 <= '0';
130 raddr_rst <= '1';
132 raddr_rst <= '1';
131 Chanel_ongoing <= 0;
133 Chanel_ongoing <= 0;
132 Cel_ongoing <= 0;
134 Cel_ongoing <= 0;
133 END IF;
135 END IF;
134
136
135 WHEN first_read =>
137 WHEN first_read =>
136 IIR_CEL_STATE <= compute_b2;
138 IIR_CEL_STATE <= compute_b2;
137 ram_read <= '1';
139 ram_read <= '1';
138 raddr_add1 <= '1';
140 raddr_add1 <= '1';
139 alu_ctrl <= ctrl_MULT;
141 alu_ctrl <= ctrl_MULT;
140 alu_sel_input <= '1';
142 alu_sel_input <= '1';
141 in_sel_src <= "01";
143 in_sel_src <= "01";
142
144
143
145
144 WHEN compute_b2 =>
146 WHEN compute_b2 =>
145 sample_out_rot <= '0';
147 sample_out_rot <= '0';
146
148
147 sample_in_rot <= '0';
149 sample_in_rot <= '0';
148 sample_out_val <= '0';
150 sample_out_val <= '0';
149
151
150 alu_sel_input <= '1';
152 alu_sel_input <= '1';
151 --
153 --
152 ram_sel_Wdata <= "10";
154 ram_sel_Wdata <= "10";
153 ram_write <= '1';
155 ram_write <= '1';
154 waddr_previous <= "10";
156 waddr_previous <= "10";
155 --
157 --
156 ram_read <= '1';
158 ram_read <= '1';
157 raddr_rst <= '0';
159 raddr_rst <= '0';
158 raddr_add1 <= '0';
160 raddr_add1 <= '0';
159 IF Cel_ongoing = 1 THEN
161 IF Cel_ongoing = 1 THEN
160 in_sel_src <= "00";
162 in_sel_src <= "00";
161 ELSE
163 ELSE
162 in_sel_src <= "11";
164 in_sel_src <= "11";
163 END IF;
165 END IF;
164 alu_selected_coeff <= alu_selected_coeff+1;
166 alu_selected_coeff <= alu_selected_coeff+1;
165 alu_ctrl <= ctrl_MAC;
167 alu_ctrl <= ctrl_MAC;
166 IIR_CEL_STATE <= compute_b1;
168 IIR_CEL_STATE <= compute_b1;
167
169
168 WHEN compute_b1 =>
170 WHEN compute_b1 =>
169 sample_in_rot <= '0';
171 sample_in_rot <= '0';
170 alu_sel_input <= '0';
172 alu_sel_input <= '0';
171 --
173 --
172 ram_sel_Wdata <= "00";
174 ram_sel_Wdata <= "00";
173 ram_write <= '1';
175 ram_write <= '1';
174 waddr_previous <= "01";
176 waddr_previous <= "01";
175 --
177 --
176 ram_read <= '1';
178 ram_read <= '1';
177 raddr_rst <= '0';
179 raddr_rst <= '0';
178 raddr_add1 <= '1';
180 raddr_add1 <= '1';
179 sample_out_rot <= '0';
181 sample_out_rot <= '0';
180 IF Cel_ongoing = 1 THEN
182 IF Cel_ongoing = 1 THEN
181 in_sel_src <= "10";
183 in_sel_src <= "10";
182 sample_out_val <= '0';
184 sample_out_val <= '0';
183 ELSE
185 ELSE
184 sample_out_val <= '0';
186 sample_out_val <= '0';
185 in_sel_src <= "00";
187 in_sel_src <= "00";
186 END IF;
188 END IF;
187 alu_selected_coeff <= alu_selected_coeff+1;
189 alu_selected_coeff <= alu_selected_coeff+1;
188 alu_ctrl <= ctrl_MAC;
190 alu_ctrl <= ctrl_MAC;
189 IIR_CEL_STATE <= compute_b0;
191 IIR_CEL_STATE <= compute_b0;
190
192
191 WHEN compute_b0 =>
193 WHEN compute_b0 =>
192 sample_out_rot <= '0';
194 sample_out_rot <= '0';
193 sample_out_val <= '0';
195 sample_out_val <= '0';
194 sample_in_rot <= '0';
196 sample_in_rot <= '0';
195 alu_sel_input <= '1';
197 alu_sel_input <= '1';
196 ram_sel_Wdata <= "00";
198 ram_sel_Wdata <= "00";
197 ram_write <= '0';
199 ram_write <= '0';
198 waddr_previous <= "01";
200 waddr_previous <= "01";
199 ram_read <= '1';
201 ram_read <= '1';
200 raddr_rst <= '0';
202 raddr_rst <= '0';
201 raddr_add1 <= '0';
203 raddr_add1 <= '0';
202 in_sel_src <= "10";
204 in_sel_src <= "10";
203 alu_selected_coeff <= alu_selected_coeff+1;
205 alu_selected_coeff <= alu_selected_coeff+1;
204 alu_ctrl <= ctrl_MAC;
206 alu_ctrl <= ctrl_MAC;
205 IIR_CEL_STATE <= compute_a2;
207 IIR_CEL_STATE <= compute_a2;
206 IF Cel_ongoing = Cels_count THEN
208 IF Cel_ongoing = Cels_count THEN
207 sample_in_rot <= '1';
209 sample_in_rot <= '1';
208 ELSE
210 ELSE
209 sample_in_rot <= '0';
211 sample_in_rot <= '0';
210 END IF;
212 END IF;
211
213
212 WHEN compute_a2 =>
214 WHEN compute_a2 =>
213 sample_out_val <= '0';
215 sample_out_val <= '0';
214 sample_out_rot <= '0';
216 sample_out_rot <= '0';
215 alu_sel_input <= '1';
217 alu_sel_input <= '1';
216 ram_sel_Wdata <= "00";
218 ram_sel_Wdata <= "00";
217 ram_write <= '0';
219 ram_write <= '0';
218 waddr_previous <= "01";
220 waddr_previous <= "01";
219 ram_read <= '1';
221 ram_read <= '1';
220 raddr_rst <= '0';
222 raddr_rst <= '0';
221 IF Cel_ongoing = Cels_count THEN
223 IF Cel_ongoing = Cels_count THEN
222 raddr_add1 <= '1';
224 raddr_add1 <= '1';
223 ELSE
225 ELSE
224 raddr_add1 <= '0';
226 raddr_add1 <= '0';
225 END IF;
227 END IF;
226 in_sel_src <= "00";
228 in_sel_src <= "00";
227 alu_selected_coeff <= alu_selected_coeff+1;
229 alu_selected_coeff <= alu_selected_coeff+1;
228 alu_ctrl <= ctrl_MAC;
230 alu_ctrl <= ctrl_MAC;
229 IIR_CEL_STATE <= compute_a1;
231 IIR_CEL_STATE <= compute_a1;
230 sample_in_rot <= '0';
232 sample_in_rot <= '0';
231
233
232 WHEN compute_a1 =>
234 WHEN compute_a1 =>
233 sample_out_val <= '0';
235 sample_out_val <= '0';
234 sample_out_rot <= '0';
236 sample_out_rot <= '0';
235 alu_sel_input <= '0';
237 alu_sel_input <= '0';
236 ram_sel_Wdata <= "00";
238 ram_sel_Wdata <= "00";
237 ram_write <= '0';
239 ram_write <= '0';
238 waddr_previous <= "01";
240 waddr_previous <= "01";
239 ram_read <= '1';
241 ram_read <= '1';
240 raddr_rst <= '0';
242 raddr_rst <= '0';
241 alu_ctrl <= ctrl_MULT;
243 alu_ctrl <= ctrl_MULT;
242 sample_in_rot <= '0';
244 sample_in_rot <= '0';
243 IF Cel_ongoing = Cels_count THEN
245 IF Cel_ongoing = Cels_count THEN
244 alu_selected_coeff <= 0;
246 alu_selected_coeff <= 0;
245
247
246 ram_sel_Wdata <= "10";
248 ram_sel_Wdata <= "10";
247 raddr_add1 <= '1';
249 raddr_add1 <= '1';
248 ram_write <= '1';
250 ram_write <= '1';
249 waddr_previous <= "10";
251 waddr_previous <= "10";
250
252
251 IF Chanel_ongoing = ChanelsCount THEN
253 IF Chanel_ongoing = ChanelsCount THEN
252 IIR_CEL_STATE <= wait_valid_last_output;
254 IIR_CEL_STATE <= wait_valid_last_output;
253 ELSE
255 ELSE
254 Chanel_ongoing <= Chanel_ongoing + 1;
256 Chanel_ongoing <= Chanel_ongoing + 1;
255 Cel_ongoing <= 1;
257 Cel_ongoing <= 1;
256 IIR_CEL_STATE <= LAST_CEL;
258 IIR_CEL_STATE <= LAST_CEL;
257 in_sel_src <= "01";
259 in_sel_src <= "01";
258 END IF;
260 END IF;
259 ELSE
261 ELSE
260 raddr_add1 <= '1';
262 raddr_add1 <= '1';
261 alu_selected_coeff <= alu_selected_coeff+1;
263 alu_selected_coeff <= alu_selected_coeff+1;
262 Cel_ongoing <= Cel_ongoing+1;
264 Cel_ongoing <= Cel_ongoing+1;
263 IIR_CEL_STATE <= compute_b2;
265 IIR_CEL_STATE <= compute_b2;
264 END IF;
266 END IF;
265
267
266 WHEN LAST_CEL =>
268 WHEN LAST_CEL =>
267 alu_sel_input <= '1';
269 alu_sel_input <= '1';
268 IIR_CEL_STATE <= compute_b2;
270 IIR_CEL_STATE <= compute_b2;
269 raddr_add1 <= '1';
271 raddr_add1 <= '1';
270 ram_sel_Wdata <= "01";
272 ram_sel_Wdata <= "01";
271 ram_write <= '1';
273 ram_write <= '1';
272 waddr_previous <= "10";
274 waddr_previous <= "10";
273 sample_out_rot <= '1';
275 sample_out_rot <= '1';
274
276
275
277
276 WHEN wait_valid_last_output =>
278 WHEN wait_valid_last_output =>
277 IIR_CEL_STATE <= wait_valid_last_output_2;
279 IIR_CEL_STATE <= wait_valid_last_output_2;
278 sample_in_rot <= '0';
280 sample_in_rot <= '0';
279 alu_ctrl <= ctrl_IDLE;
281 alu_ctrl <= ctrl_IDLE;
280 alu_selected_coeff <= 0;
282 alu_selected_coeff <= 0;
281 in_sel_src <= "01";
283 in_sel_src <= "01";
282 ram_read <= '0';
284 ram_read <= '0';
283 raddr_rst <= '1';
285 raddr_rst <= '1';
284 raddr_add1 <= '1';
286 raddr_add1 <= '1';
285 ram_sel_Wdata <= "01";
287 ram_sel_Wdata <= "01";
286 ram_write <= '1';
288 ram_write <= '1';
287 waddr_previous <= "10";
289 waddr_previous <= "10";
288 Chanel_ongoing <= 0;
290 Chanel_ongoing <= 0;
289 Cel_ongoing <= 0;
291 Cel_ongoing <= 0;
290 sample_out_val <= '0';
292 sample_out_val <= '0';
291 sample_out_rot <= '1';
293 sample_out_rot <= '1';
292
294
293 WHEN wait_valid_last_output_2 =>
295 WHEN wait_valid_last_output_2 =>
294 IIR_CEL_STATE <= waiting;
296 IIR_CEL_STATE <= waiting;
295 sample_in_rot <= '0';
297 sample_in_rot <= '0';
296 alu_ctrl <= ctrl_IDLE;
298 alu_ctrl <= ctrl_IDLE;
297 alu_selected_coeff <= 0;
299 alu_selected_coeff <= 0;
298 in_sel_src <= "01";
300 in_sel_src <= "01";
299 ram_read <= '0';
301 ram_read <= '0';
300 raddr_rst <= '1';
302 raddr_rst <= '1';
301 raddr_add1 <= '1';
303 raddr_add1 <= '1';
302 ram_sel_Wdata <= "10";
304 ram_sel_Wdata <= "10";
303 ram_write <= '1';
305 ram_write <= '1';
304 waddr_previous <= "10";
306 waddr_previous <= "10";
305 Chanel_ongoing <= 0;
307 Chanel_ongoing <= 0;
306 Cel_ongoing <= 0;
308 Cel_ongoing <= 0;
307 sample_out_val <= '1';
309 sample_out_val <= '1';
308 sample_out_rot <= '0';
310 sample_out_rot <= '0';
309 WHEN OTHERS => NULL;
311 WHEN OTHERS => NULL;
310 END CASE;
312 END CASE;
311
313
312 END IF;
314 END IF;
313 END PROCESS;
315 END PROCESS;
314
316
315 END ar_IIR_CEL_CTRLR_v2_CONTROL; No newline at end of file
317 END ar_IIR_CEL_CTRLR_v2_CONTROL;
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@@ -1,251 +1,254
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY lpp;
25 LIBRARY lpp;
26 USE lpp.iir_filter.ALL;
26 USE lpp.iir_filter.ALL;
27 USE lpp.general_purpose.ALL;
27 USE lpp.general_purpose.ALL;
28
28
29
29
30
30
31 ENTITY IIR_CEL_CTRLR_v2_DATAFLOW IS
31 ENTITY IIR_CEL_CTRLR_v2_DATAFLOW IS
32 GENERIC(
32 GENERIC(
33 tech : INTEGER := 0;
33 tech : INTEGER := 0;
34 Mem_use : INTEGER := use_RAM;
34 Mem_use : INTEGER := use_RAM;
35 Sample_SZ : INTEGER := 16;
35 Sample_SZ : INTEGER := 16;
36 Coef_SZ : INTEGER := 9;
36 Coef_SZ : INTEGER := 9;
37 Coef_Nb : INTEGER := 30;
37 Coef_Nb : INTEGER := 30;
38 Coef_sel_SZ : INTEGER := 5
38 Coef_sel_SZ : INTEGER := 5
39 );
39 );
40 PORT(
40 PORT(
41 rstn : IN STD_LOGIC;
41 rstn : IN STD_LOGIC;
42 clk : IN STD_LOGIC;
42 clk : IN STD_LOGIC;
43 -- PARAMETER
43 -- PARAMETER
44 virg_pos : IN INTEGER;
44 virg_pos : IN INTEGER;
45 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
45 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
46 -- CONTROL
46 -- CONTROL
47 in_sel_src : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
47 in_sel_src : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
48 --
48 --
49 init_mem_done : out STD_LOGIC;
49 ram_sel_Wdata : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
50 ram_sel_Wdata : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
50 ram_write : IN STD_LOGIC;
51 ram_write : IN STD_LOGIC;
51 ram_read : IN STD_LOGIC;
52 ram_read : IN STD_LOGIC;
52 raddr_rst : IN STD_LOGIC;
53 raddr_rst : IN STD_LOGIC;
53 raddr_add1 : IN STD_LOGIC;
54 raddr_add1 : IN STD_LOGIC;
54 waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
55 waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
55 --
56 --
56 alu_sel_input : IN STD_LOGIC;
57 alu_sel_input : IN STD_LOGIC;
57 alu_sel_coeff : IN STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
58 alu_sel_coeff : IN STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
58 alu_ctrl : IN STD_LOGIC_VECTOR(2 DOWNTO 0);--(MAC_op, MULT_with_clear_ADD, IDLE)
59 alu_ctrl : IN STD_LOGIC_VECTOR(2 DOWNTO 0);--(MAC_op, MULT_with_clear_ADD, IDLE)
59 alu_comp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
60 alu_comp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
60 -- DATA
61 -- DATA
61 sample_in : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
62 sample_in : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
62 sample_out : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0)
63 sample_out : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0)
63 );
64 );
64 END IIR_CEL_CTRLR_v2_DATAFLOW;
65 END IIR_CEL_CTRLR_v2_DATAFLOW;
65
66
66 ARCHITECTURE ar_IIR_CEL_CTRLR_v2_DATAFLOW OF IIR_CEL_CTRLR_v2_DATAFLOW IS
67 ARCHITECTURE ar_IIR_CEL_CTRLR_v2_DATAFLOW OF IIR_CEL_CTRLR_v2_DATAFLOW IS
67
68
68 COMPONENT RAM_CTRLR_v2
69 COMPONENT RAM_CTRLR_v2
69 GENERIC (
70 GENERIC (
70 tech : INTEGER;
71 tech : INTEGER;
71 Input_SZ_1 : INTEGER;
72 Input_SZ_1 : INTEGER;
72 Mem_use : INTEGER);
73 Mem_use : INTEGER);
73 PORT (
74 PORT (
74 rstn : IN STD_LOGIC;
75 rstn : IN STD_LOGIC;
75 clk : IN STD_LOGIC;
76 clk : IN STD_LOGIC;
77 init_mem_done : out STD_LOGIC;
76 ram_write : IN STD_LOGIC;
78 ram_write : IN STD_LOGIC;
77 ram_read : IN STD_LOGIC;
79 ram_read : IN STD_LOGIC;
78 raddr_rst : IN STD_LOGIC;
80 raddr_rst : IN STD_LOGIC;
79 raddr_add1 : IN STD_LOGIC;
81 raddr_add1 : IN STD_LOGIC;
80 waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
82 waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
81 sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
83 sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
82 sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0));
84 sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0));
83 END COMPONENT;
85 END COMPONENT;
84
86
85 SIGNAL reg_sample_in : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
87 SIGNAL reg_sample_in : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
86 SIGNAL ram_output : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
88 SIGNAL ram_output : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
87 SIGNAL alu_output : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
89 SIGNAL alu_output : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
88 SIGNAL ram_input : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
90 SIGNAL ram_input : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
89 SIGNAL alu_sample : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
91 SIGNAL alu_sample : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
90 SIGNAL alu_output_s : STD_LOGIC_VECTOR(Sample_SZ+Coef_SZ-1 DOWNTO 0);
92 SIGNAL alu_output_s : STD_LOGIC_VECTOR(Sample_SZ+Coef_SZ-1 DOWNTO 0);
91
93
92 SIGNAL arrayCoeff : MUX_INPUT_TYPE(0 TO (2**Coef_sel_SZ)-1,Coef_SZ-1 DOWNTO 0);
94 SIGNAL arrayCoeff : MUX_INPUT_TYPE(0 TO (2**Coef_sel_SZ)-1,Coef_SZ-1 DOWNTO 0);
93 SIGNAL alu_coef_s : MUX_OUTPUT_TYPE(Coef_SZ-1 DOWNTO 0);
95 SIGNAL alu_coef_s : MUX_OUTPUT_TYPE(Coef_SZ-1 DOWNTO 0);
94
96
95 SIGNAL alu_coef : STD_LOGIC_VECTOR(Coef_SZ-1 DOWNTO 0);
97 SIGNAL alu_coef : STD_LOGIC_VECTOR(Coef_SZ-1 DOWNTO 0);
96
98
97 BEGIN
99 BEGIN
98
100
99 -----------------------------------------------------------------------------
101 -----------------------------------------------------------------------------
100 -- INPUT
102 -- INPUT
101 -----------------------------------------------------------------------------
103 -----------------------------------------------------------------------------
102 PROCESS (clk, rstn)
104 PROCESS (clk, rstn)
103 BEGIN -- PROCESS
105 BEGIN -- PROCESS
104 IF rstn = '0' THEN -- asynchronous reset (active low)
106 IF rstn = '0' THEN -- asynchronous reset (active low)
105 reg_sample_in <= (OTHERS => '0');
107 reg_sample_in <= (OTHERS => '0');
106 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
108 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
107 CASE in_sel_src IS
109 CASE in_sel_src IS
108 WHEN "00" => reg_sample_in <= reg_sample_in;
110 WHEN "00" => reg_sample_in <= reg_sample_in;
109 WHEN "01" => reg_sample_in <= sample_in;
111 WHEN "01" => reg_sample_in <= sample_in;
110 WHEN "10" => reg_sample_in <= ram_output;
112 WHEN "10" => reg_sample_in <= ram_output;
111 WHEN "11" => reg_sample_in <= alu_output;
113 WHEN "11" => reg_sample_in <= alu_output;
112 WHEN OTHERS => NULL;
114 WHEN OTHERS => NULL;
113 END CASE;
115 END CASE;
114 END IF;
116 END IF;
115 END PROCESS;
117 END PROCESS;
116
118
117
119
118 -----------------------------------------------------------------------------
120 -----------------------------------------------------------------------------
119 -- RAM + CTRL
121 -- RAM + CTRL
120 -----------------------------------------------------------------------------
122 -----------------------------------------------------------------------------
121
123
122 ram_input <= reg_sample_in WHEN ram_sel_Wdata = "00" ELSE
124 ram_input <= reg_sample_in WHEN ram_sel_Wdata = "00" ELSE
123 alu_output WHEN ram_sel_Wdata = "01" ELSE
125 alu_output WHEN ram_sel_Wdata = "01" ELSE
124 ram_output;
126 ram_output;
125
127
126 RAM_CTRLR_v2_1: RAM_CTRLR_v2
128 RAM_CTRLR_v2_1: RAM_CTRLR_v2
127 GENERIC MAP (
129 GENERIC MAP (
128 tech => tech,
130 tech => tech,
129 Input_SZ_1 => Sample_SZ,
131 Input_SZ_1 => Sample_SZ,
130 Mem_use => Mem_use)
132 Mem_use => Mem_use)
131 PORT MAP (
133 PORT MAP (
132 clk => clk,
134 clk => clk,
133 rstn => rstn,
135 rstn => rstn,
136 init_mem_done => init_mem_done,
134 ram_write => ram_write,
137 ram_write => ram_write,
135 ram_read => ram_read,
138 ram_read => ram_read,
136 raddr_rst => raddr_rst,
139 raddr_rst => raddr_rst,
137 raddr_add1 => raddr_add1,
140 raddr_add1 => raddr_add1,
138 waddr_previous => waddr_previous,
141 waddr_previous => waddr_previous,
139 sample_in => ram_input,
142 sample_in => ram_input,
140 sample_out => ram_output);
143 sample_out => ram_output);
141
144
142 -----------------------------------------------------------------------------
145 -----------------------------------------------------------------------------
143 -- MAC_ACC
146 -- MAC_ACC
144 -----------------------------------------------------------------------------
147 -----------------------------------------------------------------------------
145 -- Control : mac_ctrl (MAC_op, MULT_with_clear_ADD, IDLE)
148 -- Control : mac_ctrl (MAC_op, MULT_with_clear_ADD, IDLE)
146 -- Data In : mac_sample, mac_coef
149 -- Data In : mac_sample, mac_coef
147 -- Data Out: mac_output
150 -- Data Out: mac_output
148
151
149 alu_sample <= reg_sample_in WHEN alu_sel_input = '0' ELSE ram_output;
152 alu_sample <= reg_sample_in WHEN alu_sel_input = '0' ELSE ram_output;
150
153
151 coefftable: FOR I IN 0 TO (2**Coef_sel_SZ)-1 GENERATE
154 coefftable: FOR I IN 0 TO (2**Coef_sel_SZ)-1 GENERATE
152 coeff_in: IF I < Coef_Nb GENERATE
155 coeff_in: IF I < Coef_Nb GENERATE
153 all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE
156 all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE
154 arrayCoeff(I,J) <= coefs(Coef_SZ*I+J);
157 arrayCoeff(I,J) <= coefs(Coef_SZ*I+J);
155 END GENERATE all_bit;
158 END GENERATE all_bit;
156 END GENERATE coeff_in;
159 END GENERATE coeff_in;
157 coeff_null: IF I > (Coef_Nb -1) GENERATE
160 coeff_null: IF I > (Coef_Nb -1) GENERATE
158 all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE
161 all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE
159 arrayCoeff(I,J) <= '0';
162 arrayCoeff(I,J) <= '0';
160 END GENERATE all_bit;
163 END GENERATE all_bit;
161 END GENERATE coeff_null;
164 END GENERATE coeff_null;
162 END GENERATE coefftable;
165 END GENERATE coefftable;
163
166
164 Coeff_Mux : MUXN
167 Coeff_Mux : MUXN
165 GENERIC MAP (
168 GENERIC MAP (
166 Input_SZ => Coef_SZ,
169 Input_SZ => Coef_SZ,
167 NbStage => Coef_sel_SZ)
170 NbStage => Coef_sel_SZ)
168 PORT MAP (
171 PORT MAP (
169 sel => alu_sel_coeff,
172 sel => alu_sel_coeff,
170 INPUT => arrayCoeff,
173 INPUT => arrayCoeff,
171 RES => alu_coef_s);
174 RES => alu_coef_s);
172
175
173
176
174 all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE
177 all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE
175 alu_coef(J) <= alu_coef_s(J);
178 alu_coef(J) <= alu_coef_s(J);
176 END GENERATE all_bit;
179 END GENERATE all_bit;
177
180
178 -----------------------------------------------------------------------------
181 -----------------------------------------------------------------------------
179 -- TODO : just for Synthesis test
182 -- TODO : just for Synthesis test
180
183
181 --PROCESS (clk, rstn)
184 --PROCESS (clk, rstn)
182 --BEGIN
185 --BEGIN
183 -- IF rstn = '0' THEN
186 -- IF rstn = '0' THEN
184 -- alu_coef <= (OTHERS => '0');
187 -- alu_coef <= (OTHERS => '0');
185 -- ELSIF clk'event AND clk = '1' THEN
188 -- ELSIF clk'event AND clk = '1' THEN
186 -- all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 LOOP
189 -- all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 LOOP
187 -- alu_coef(J) <= alu_coef_s(J);
190 -- alu_coef(J) <= alu_coef_s(J);
188 -- END LOOP all_bit;
191 -- END LOOP all_bit;
189 -- END IF;
192 -- END IF;
190 --END PROCESS;
193 --END PROCESS;
191
194
192 -----------------------------------------------------------------------------
195 -----------------------------------------------------------------------------
193
196
194
197
195 ALU_1: ALU
198 ALU_1: ALU
196 GENERIC MAP (
199 GENERIC MAP (
197 Arith_en => 1,
200 Arith_en => 1,
198 Input_SZ_1 => Sample_SZ,
201 Input_SZ_1 => Sample_SZ,
199 Input_SZ_2 => Coef_SZ,
202 Input_SZ_2 => Coef_SZ,
200 COMP_EN => 1)
203 COMP_EN => 1)
201 PORT MAP (
204 PORT MAP (
202 clk => clk,
205 clk => clk,
203 reset => rstn,
206 reset => rstn,
204 ctrl => alu_ctrl,
207 ctrl => alu_ctrl,
205 comp => alu_comp,
208 comp => alu_comp,
206 OP1 => alu_sample,
209 OP1 => alu_sample,
207 OP2 => alu_coef,
210 OP2 => alu_coef,
208 RES => alu_output_s);
211 RES => alu_output_s);
209
212
210 alu_output <= alu_output_s(Sample_SZ+virg_pos-1 DOWNTO virg_pos);
213 alu_output <= alu_output_s(Sample_SZ+virg_pos-1 DOWNTO virg_pos);
211
214
212 sample_out <= alu_output;
215 sample_out <= alu_output;
213
216
214 END ar_IIR_CEL_CTRLR_v2_DATAFLOW;
217 END ar_IIR_CEL_CTRLR_v2_DATAFLOW;
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Show file before | Show file after | Hide comments
@@ -1,442 +1,454
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22
22
23 LIBRARY IEEE;
23 LIBRARY IEEE;
24 USE IEEE.numeric_std.ALL;
24 USE IEEE.numeric_std.ALL;
25 USE IEEE.std_logic_1164.ALL;
25 USE IEEE.std_logic_1164.ALL;
26
26
27 LIBRARY techmap;
27 LIBRARY techmap;
28 USE techmap.gencomp.ALL;
28 USE techmap.gencomp.ALL;
29
29
30 LIBRARY lpp;
30 LIBRARY lpp;
31 USE lpp.iir_filter.ALL;
31 USE lpp.iir_filter.ALL;
32 USE lpp.general_purpose.ALL;
32 USE lpp.general_purpose.ALL;
33
33
34 ENTITY IIR_CEL_CTRLR_v3 IS
34 ENTITY IIR_CEL_CTRLR_v3 IS
35 GENERIC (
35 GENERIC (
36 tech : INTEGER := 0;
36 tech : INTEGER := 0;
37 Mem_use : INTEGER := use_RAM;
37 Mem_use : INTEGER := use_RAM;
38 Sample_SZ : INTEGER := 18;
38 Sample_SZ : INTEGER := 18;
39 Coef_SZ : INTEGER := 9;
39 Coef_SZ : INTEGER := 9;
40 Coef_Nb : INTEGER := 25;
40 Coef_Nb : INTEGER := 25;
41 Coef_sel_SZ : INTEGER := 5;
41 Coef_sel_SZ : INTEGER := 5;
42 Cels_count : INTEGER := 5;
42 Cels_count : INTEGER := 5;
43 ChanelsCount : INTEGER := 8);
43 ChanelsCount : INTEGER := 8);
44 PORT (
44 PORT (
45 rstn : IN STD_LOGIC;
45 rstn : IN STD_LOGIC;
46 clk : IN STD_LOGIC;
46 clk : IN STD_LOGIC;
47
47
48 virg_pos : IN INTEGER;
48 virg_pos : IN INTEGER;
49 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
49 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
50
50
51 sample_in1_val : IN STD_LOGIC;
51 sample_in1_val : IN STD_LOGIC;
52 sample_in1 : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
52 sample_in1 : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
53 sample_in2_val : IN STD_LOGIC;
53 sample_in2_val : IN STD_LOGIC;
54 sample_in2 : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
54 sample_in2 : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
55
55
56 sample_out1_val : OUT STD_LOGIC;
56 sample_out1_val : OUT STD_LOGIC;
57 sample_out1 : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
57 sample_out1 : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
58 sample_out2_val : OUT STD_LOGIC;
58 sample_out2_val : OUT STD_LOGIC;
59 sample_out2 : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0));
59 sample_out2 : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0));
60 END IIR_CEL_CTRLR_v3;
60 END IIR_CEL_CTRLR_v3;
61
61
62 ARCHITECTURE ar_IIR_CEL_CTRLR_v3 OF IIR_CEL_CTRLR_v3 IS
62 ARCHITECTURE ar_IIR_CEL_CTRLR_v3 OF IIR_CEL_CTRLR_v3 IS
63
63
64 COMPONENT RAM_CTRLR_v2
64 COMPONENT RAM_CTRLR_v2
65 GENERIC (
65 GENERIC (
66 tech : INTEGER;
66 tech : INTEGER;
67 Input_SZ_1 : INTEGER;
67 Input_SZ_1 : INTEGER;
68 Mem_use : INTEGER);
68 Mem_use : INTEGER);
69 PORT (
69 PORT (
70 rstn : IN STD_LOGIC;
70 rstn : IN STD_LOGIC;
71 clk : IN STD_LOGIC;
71 clk : IN STD_LOGIC;
72 init_mem_done : out STD_LOGIC;
72 ram_write : IN STD_LOGIC;
73 ram_write : IN STD_LOGIC;
73 ram_read : IN STD_LOGIC;
74 ram_read : IN STD_LOGIC;
74 raddr_rst : IN STD_LOGIC;
75 raddr_rst : IN STD_LOGIC;
75 raddr_add1 : IN STD_LOGIC;
76 raddr_add1 : IN STD_LOGIC;
76 waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
77 waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
77 sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
78 sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
78 sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0));
79 sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0));
79 END COMPONENT;
80 END COMPONENT;
80
81
81 COMPONENT IIR_CEL_CTRLR_v3_DATAFLOW
82 COMPONENT IIR_CEL_CTRLR_v3_DATAFLOW
82 GENERIC (
83 GENERIC (
83 Sample_SZ : INTEGER;
84 Sample_SZ : INTEGER;
84 Coef_SZ : INTEGER;
85 Coef_SZ : INTEGER;
85 Coef_Nb : INTEGER;
86 Coef_Nb : INTEGER;
86 Coef_sel_SZ : INTEGER);
87 Coef_sel_SZ : INTEGER);
87 PORT (
88 PORT (
88 rstn : IN STD_LOGIC;
89 rstn : IN STD_LOGIC;
89 clk : IN STD_LOGIC;
90 clk : IN STD_LOGIC;
90 virg_pos : IN INTEGER;
91 virg_pos : IN INTEGER;
91 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
92 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
92 in_sel_src : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
93 in_sel_src : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
93 ram_sel_Wdata : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
94 ram_sel_Wdata : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
94 ram_input : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
95 ram_input : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
95 ram_output : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
96 ram_output : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
96 alu_sel_input : IN STD_LOGIC;
97 alu_sel_input : IN STD_LOGIC;
97 alu_sel_coeff : IN STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
98 alu_sel_coeff : IN STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
98 alu_ctrl : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
99 alu_ctrl : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
99 alu_comp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
100 alu_comp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
100 sample_in : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
101 sample_in : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
101 sample_out : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0));
102 sample_out : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0));
102 END COMPONENT;
103 END COMPONENT;
103
104
104 COMPONENT IIR_CEL_CTRLR_v2_CONTROL
105 COMPONENT IIR_CEL_CTRLR_v2_CONTROL
105 GENERIC (
106 GENERIC (
106 Coef_sel_SZ : INTEGER;
107 Coef_sel_SZ : INTEGER;
107 Cels_count : INTEGER;
108 Cels_count : INTEGER;
108 ChanelsCount : INTEGER);
109 ChanelsCount : INTEGER);
109 PORT (
110 PORT (
110 rstn : IN STD_LOGIC;
111 rstn : IN STD_LOGIC;
111 clk : IN STD_LOGIC;
112 clk : IN STD_LOGIC;
112 sample_in_val : IN STD_LOGIC;
113 sample_in_val : IN STD_LOGIC;
113 sample_in_rot : OUT STD_LOGIC;
114 sample_in_rot : OUT STD_LOGIC;
114 sample_out_val : OUT STD_LOGIC;
115 sample_out_val : OUT STD_LOGIC;
115 sample_out_rot : OUT STD_LOGIC;
116 sample_out_rot : OUT STD_LOGIC;
117
118 init_mem_done : in STD_LOGIC; --TODO
119
116 in_sel_src : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
120 in_sel_src : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
117 ram_sel_Wdata : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
121 ram_sel_Wdata : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
118 ram_write : OUT STD_LOGIC;
122 ram_write : OUT STD_LOGIC;
119 ram_read : OUT STD_LOGIC;
123 ram_read : OUT STD_LOGIC;
120 raddr_rst : OUT STD_LOGIC;
124 raddr_rst : OUT STD_LOGIC;
121 raddr_add1 : OUT STD_LOGIC;
125 raddr_add1 : OUT STD_LOGIC;
122 waddr_previous : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
126 waddr_previous : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
123 alu_sel_input : OUT STD_LOGIC;
127 alu_sel_input : OUT STD_LOGIC;
124 alu_sel_coeff : OUT STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
128 alu_sel_coeff : OUT STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
125 alu_ctrl : OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
129 alu_ctrl : OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
126 END COMPONENT;
130 END COMPONENT;
127
131
128 SIGNAL in_sel_src : STD_LOGIC_VECTOR(1 DOWNTO 0);
132 SIGNAL in_sel_src : STD_LOGIC_VECTOR(1 DOWNTO 0);
129 SIGNAL ram_sel_Wdata : STD_LOGIC_VECTOR(1 DOWNTO 0);
133 SIGNAL ram_sel_Wdata : STD_LOGIC_VECTOR(1 DOWNTO 0);
130 SIGNAL ram_write : STD_LOGIC;
134 SIGNAL ram_write : STD_LOGIC;
131 SIGNAL ram_read : STD_LOGIC;
135 SIGNAL ram_read : STD_LOGIC;
132 SIGNAL raddr_rst : STD_LOGIC;
136 SIGNAL raddr_rst : STD_LOGIC;
133 SIGNAL raddr_add1 : STD_LOGIC;
137 SIGNAL raddr_add1 : STD_LOGIC;
134 SIGNAL waddr_previous : STD_LOGIC_VECTOR(1 DOWNTO 0);
138 SIGNAL waddr_previous : STD_LOGIC_VECTOR(1 DOWNTO 0);
135 SIGNAL alu_sel_input : STD_LOGIC;
139 SIGNAL alu_sel_input : STD_LOGIC;
136 SIGNAL alu_sel_coeff : STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
140 SIGNAL alu_sel_coeff : STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
137 SIGNAL alu_ctrl : STD_LOGIC_VECTOR(2 DOWNTO 0);
141 SIGNAL alu_ctrl : STD_LOGIC_VECTOR(2 DOWNTO 0);
138
142
139 SIGNAL sample_in_buf : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
143 SIGNAL sample_in_buf : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
140 SIGNAL sample_in_rotate : STD_LOGIC;
144 SIGNAL sample_in_rotate : STD_LOGIC;
141 SIGNAL sample_in_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
145 SIGNAL sample_in_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
142 SIGNAL sample_out_val_s : STD_LOGIC;
146 SIGNAL sample_out_val_s : STD_LOGIC;
143 SIGNAL sample_out_val_s2 : STD_LOGIC;
147 SIGNAL sample_out_val_s2 : STD_LOGIC;
144 SIGNAL sample_out_rot_s : STD_LOGIC;
148 SIGNAL sample_out_rot_s : STD_LOGIC;
145 SIGNAL sample_out_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
149 SIGNAL sample_out_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
146
150
147 SIGNAL sample_out_s2 : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
151 SIGNAL sample_out_s2 : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
148
152
149 SIGNAL ram_input : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
153 SIGNAL ram_input : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
150 SIGNAL ram_output : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
154 SIGNAL ram_output : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
151 --
155 --
152 SIGNAL sample_in_val : STD_LOGIC;
156 SIGNAL sample_in_val : STD_LOGIC;
153 SIGNAL sample_in : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
157 SIGNAL sample_in : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
154 SIGNAL sample_out_val : STD_LOGIC;
158 SIGNAL sample_out_val : STD_LOGIC;
155 SIGNAL sample_out : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
159 SIGNAL sample_out : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
156
160
157 -----------------------------------------------------------------------------
161 -----------------------------------------------------------------------------
158 --
162 --
159 -----------------------------------------------------------------------------
163 -----------------------------------------------------------------------------
160 SIGNAL CHANNEL_SEL : STD_LOGIC;
164 SIGNAL CHANNEL_SEL : STD_LOGIC;
161
165
162 SIGNAL ram_output_1 : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
166 SIGNAL ram_output_1 : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
163 SIGNAL ram_output_2 : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
167 SIGNAL ram_output_2 : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
164
168
165 SIGNAL ram_write_1 : STD_LOGIC;
169 SIGNAL ram_write_1 : STD_LOGIC;
166 SIGNAL ram_read_1 : STD_LOGIC;
170 SIGNAL ram_read_1 : STD_LOGIC;
167 SIGNAL raddr_rst_1 : STD_LOGIC;
171 SIGNAL raddr_rst_1 : STD_LOGIC;
168 SIGNAL raddr_add1_1 : STD_LOGIC;
172 SIGNAL raddr_add1_1 : STD_LOGIC;
169 SIGNAL waddr_previous_1 : STD_LOGIC_VECTOR(1 DOWNTO 0);
173 SIGNAL waddr_previous_1 : STD_LOGIC_VECTOR(1 DOWNTO 0);
170
174
171 SIGNAL ram_write_2 : STD_LOGIC;
175 SIGNAL ram_write_2 : STD_LOGIC;
172 SIGNAL ram_read_2 : STD_LOGIC;
176 SIGNAL ram_read_2 : STD_LOGIC;
173 SIGNAL raddr_rst_2 : STD_LOGIC;
177 SIGNAL raddr_rst_2 : STD_LOGIC;
174 SIGNAL raddr_add1_2 : STD_LOGIC;
178 SIGNAL raddr_add1_2 : STD_LOGIC;
175 SIGNAL waddr_previous_2 : STD_LOGIC_VECTOR(1 DOWNTO 0);
179 SIGNAL waddr_previous_2 : STD_LOGIC_VECTOR(1 DOWNTO 0);
176 -----------------------------------------------------------------------------
180 -----------------------------------------------------------------------------
177 SIGNAL channel_ready : STD_LOGIC_VECTOR(1 DOWNTO 0);
181 SIGNAL channel_ready : STD_LOGIC_VECTOR(1 DOWNTO 0);
178 SIGNAL channel_val : STD_LOGIC_VECTOR(1 DOWNTO 0);
182 SIGNAL channel_val : STD_LOGIC_VECTOR(1 DOWNTO 0);
179 SIGNAL channel_done : STD_LOGIC_VECTOR(1 DOWNTO 0);
183 SIGNAL channel_done : STD_LOGIC_VECTOR(1 DOWNTO 0);
180 -----------------------------------------------------------------------------
184 -----------------------------------------------------------------------------
181 TYPE FSM_CHANNEL_SELECTION IS (IDLE, ONGOING_1, ONGOING_2, WAIT_STATE);
185 TYPE FSM_CHANNEL_SELECTION IS (IDLE, ONGOING_1, ONGOING_2, WAIT_STATE);
182 SIGNAL state_channel_selection : FSM_CHANNEL_SELECTION;
186 SIGNAL state_channel_selection : FSM_CHANNEL_SELECTION;
183
187
184 --SIGNAL sample_out_zero : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
188 --SIGNAL sample_out_zero : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
185
189 signal init_mem_done : std_logic;
190 signal init_mem_done_1 : std_logic;
191 signal init_mem_done_2 : std_logic;
186 BEGIN
192 BEGIN
187
193
188 -----------------------------------------------------------------------------
194 -----------------------------------------------------------------------------
189 channel_val(0) <= sample_in1_val;
195 channel_val(0) <= sample_in1_val when init_mem_done = '1' else '0';
190 channel_val(1) <= sample_in2_val;
196 channel_val(1) <= sample_in2_val when init_mem_done = '1' else '0';
191 all_channel_input_valid : FOR I IN 1 DOWNTO 0 GENERATE
197 all_channel_input_valid : FOR I IN 1 DOWNTO 0 GENERATE
192 PROCESS (clk, rstn)
198 PROCESS (clk, rstn)
193 BEGIN -- PROCESS
199 BEGIN -- PROCESS
194 IF rstn = '0' THEN -- asynchronous reset (active low)
200 IF rstn = '0' THEN -- asynchronous reset (active low)
195 channel_ready(I) <= '0';
201 channel_ready(I) <= '0';
196 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
202 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
197 IF channel_val(I) = '1' THEN
203 IF channel_val(I) = '1' THEN
198 channel_ready(I) <= '1';
204 channel_ready(I) <= '1';
199 ELSIF channel_done(I) = '1' THEN
205 ELSIF channel_done(I) = '1' THEN
200 channel_ready(I) <= '0';
206 channel_ready(I) <= '0';
201 END IF;
207 END IF;
202 END IF;
208 END IF;
203 END PROCESS;
209 END PROCESS;
204 END GENERATE all_channel_input_valid;
210 END GENERATE all_channel_input_valid;
205 -----------------------------------------------------------------------------
211 -----------------------------------------------------------------------------
206
212
207
213
208 PROCESS (clk, rstn)
214 PROCESS (clk, rstn)
209 BEGIN -- PROCESS
215 BEGIN -- PROCESS
210 IF rstn = '0' THEN -- asynchronous reset (active low)
216 IF rstn = '0' THEN -- asynchronous reset (active low)
211 state_channel_selection <= IDLE;
217 state_channel_selection <= IDLE;
212 CHANNEL_SEL <= '0';
218 CHANNEL_SEL <= '0';
213 sample_in_val <= '0';
219 sample_in_val <= '0';
214 sample_out1_val <= '0';
220 sample_out1_val <= '0';
215 sample_out2_val <= '0';
221 sample_out2_val <= '0';
216 all_channel_sample_out : FOR I IN ChanelsCount-1 DOWNTO 0 LOOP
222 all_channel_sample_out : FOR I IN ChanelsCount-1 DOWNTO 0 LOOP
217 all_bit : FOR J IN Sample_SZ-1 DOWNTO 0 LOOP
223 all_bit : FOR J IN Sample_SZ-1 DOWNTO 0 LOOP
218 sample_out1(I, J) <= '0';
224 sample_out1(I, J) <= '0';
219 sample_out2(I, J) <= '0';
225 sample_out2(I, J) <= '0';
220 END LOOP all_bit;
226 END LOOP all_bit;
221 END LOOP all_channel_sample_out;
227 END LOOP all_channel_sample_out;
222 channel_done <= "00";
228 channel_done <= "00";
223
229
224 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
230 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
225 CASE state_channel_selection IS
231 CASE state_channel_selection IS
226 WHEN IDLE =>
232 WHEN IDLE =>
227 CHANNEL_SEL <= '0';
233 CHANNEL_SEL <= '0';
228 sample_in_val <= '0';
234 sample_in_val <= '0';
229 sample_out1_val <= '0';
235 sample_out1_val <= '0';
230 sample_out2_val <= '0';
236 sample_out2_val <= '0';
231 channel_done <= "00";
237 channel_done <= "00";
232 IF channel_ready(0) = '1' THEN
238 IF channel_ready(0) = '1' THEN
233 state_channel_selection <= ONGOING_1;
239 state_channel_selection <= ONGOING_1;
234 CHANNEL_SEL <= '0';
240 CHANNEL_SEL <= '0';
235 sample_in_val <= '1';
241 sample_in_val <= '1';
236 ELSIF channel_ready(1) = '1' THEN
242 ELSIF channel_ready(1) = '1' THEN
237 state_channel_selection <= ONGOING_2;
243 state_channel_selection <= ONGOING_2;
238 CHANNEL_SEL <= '1';
244 CHANNEL_SEL <= '1';
239 sample_in_val <= '1';
245 sample_in_val <= '1';
240 END IF;
246 END IF;
241 WHEN ONGOING_1 =>
247 WHEN ONGOING_1 =>
242 sample_in_val <= '0';
248 sample_in_val <= '0';
243 IF sample_out_val = '1' THEN
249 IF sample_out_val = '1' THEN
244 state_channel_selection <= WAIT_STATE;
250 state_channel_selection <= WAIT_STATE;
245 sample_out1 <= sample_out;
251 sample_out1 <= sample_out;
246 sample_out1_val <= '1';
252 sample_out1_val <= '1';
247 channel_done(0) <= '1';
253 channel_done(0) <= '1';
248 END IF;
254 END IF;
249 WHEN ONGOING_2 =>
255 WHEN ONGOING_2 =>
250 sample_in_val <= '0';
256 sample_in_val <= '0';
251 IF sample_out_val = '1' THEN
257 IF sample_out_val = '1' THEN
252 state_channel_selection <= WAIT_STATE;
258 state_channel_selection <= WAIT_STATE;
253 sample_out2 <= sample_out;
259 sample_out2 <= sample_out;
254 sample_out2_val <= '1';
260 sample_out2_val <= '1';
255 channel_done(1) <= '1';
261 channel_done(1) <= '1';
256 END IF;
262 END IF;
257 WHEN WAIT_STATE =>
263 WHEN WAIT_STATE =>
258 state_channel_selection <= IDLE;
264 state_channel_selection <= IDLE;
259 CHANNEL_SEL <= '0';
265 CHANNEL_SEL <= '0';
260 sample_in_val <= '0';
266 sample_in_val <= '0';
261 sample_out1_val <= '0';
267 sample_out1_val <= '0';
262 sample_out2_val <= '0';
268 sample_out2_val <= '0';
263 channel_done <= "00";
269 channel_done <= "00";
264
270
265 WHEN OTHERS => NULL;
271 WHEN OTHERS => NULL;
266 END CASE;
272 END CASE;
267
273
268 END IF;
274 END IF;
269 END PROCESS;
275 END PROCESS;
270
276
271 sample_in <= sample_in1 WHEN CHANNEL_SEL = '0' ELSE sample_in2;
277 sample_in <= sample_in1 WHEN CHANNEL_SEL = '0' ELSE sample_in2;
272 -----------------------------------------------------------------------------
278 -----------------------------------------------------------------------------
273 ram_output <= ram_output_1 WHEN CHANNEL_SEL = '0' ELSE
279 ram_output <= ram_output_1 WHEN CHANNEL_SEL = '0' ELSE
274 ram_output_2;
280 ram_output_2;
275
281
276 ram_write_1 <= ram_write WHEN CHANNEL_SEL = '0' ELSE '0';
282 ram_write_1 <= ram_write WHEN CHANNEL_SEL = '0' ELSE '0';
277 ram_read_1 <= ram_read WHEN CHANNEL_SEL = '0' ELSE '0';
283 ram_read_1 <= ram_read WHEN CHANNEL_SEL = '0' ELSE '0';
278 raddr_rst_1 <= raddr_rst WHEN CHANNEL_SEL = '0' ELSE '1';
284 raddr_rst_1 <= raddr_rst WHEN CHANNEL_SEL = '0' ELSE '1';
279 raddr_add1_1 <= raddr_add1 WHEN CHANNEL_SEL = '0' ELSE '0';
285 raddr_add1_1 <= raddr_add1 WHEN CHANNEL_SEL = '0' ELSE '0';
280 waddr_previous_1 <= waddr_previous WHEN CHANNEL_SEL = '0' ELSE "00";
286 waddr_previous_1 <= waddr_previous WHEN CHANNEL_SEL = '0' ELSE "00";
281
287
282 ram_write_2 <= ram_write WHEN CHANNEL_SEL = '1' ELSE '0';
288 ram_write_2 <= ram_write WHEN CHANNEL_SEL = '1' ELSE '0';
283 ram_read_2 <= ram_read WHEN CHANNEL_SEL = '1' ELSE '0';
289 ram_read_2 <= ram_read WHEN CHANNEL_SEL = '1' ELSE '0';
284 raddr_rst_2 <= raddr_rst WHEN CHANNEL_SEL = '1' ELSE '1';
290 raddr_rst_2 <= raddr_rst WHEN CHANNEL_SEL = '1' ELSE '1';
285 raddr_add1_2 <= raddr_add1 WHEN CHANNEL_SEL = '1' ELSE '0';
291 raddr_add1_2 <= raddr_add1 WHEN CHANNEL_SEL = '1' ELSE '0';
286 waddr_previous_2 <= waddr_previous WHEN CHANNEL_SEL = '1' ELSE "00";
292 waddr_previous_2 <= waddr_previous WHEN CHANNEL_SEL = '1' ELSE "00";
287
293
294 init_mem_done <= init_mem_done_1 and init_mem_done_2;
295
288 RAM_CTRLR_v2_1 : RAM_CTRLR_v2
296 RAM_CTRLR_v2_1 : RAM_CTRLR_v2
289 GENERIC MAP (
297 GENERIC MAP (
290 tech => tech,
298 tech => tech,
291 Input_SZ_1 => Sample_SZ,
299 Input_SZ_1 => Sample_SZ,
292 Mem_use => Mem_use)
300 Mem_use => Mem_use)
293 PORT MAP (
301 PORT MAP (
294 clk => clk,
302 clk => clk,
295 rstn => rstn,
303 rstn => rstn,
304 init_mem_done => init_mem_done_1,
296 ram_write => ram_write_1,
305 ram_write => ram_write_1,
297 ram_read => ram_read_1,
306 ram_read => ram_read_1,
298 raddr_rst => raddr_rst_1,
307 raddr_rst => raddr_rst_1,
299 raddr_add1 => raddr_add1_1,
308 raddr_add1 => raddr_add1_1,
300 waddr_previous => waddr_previous_1,
309 waddr_previous => waddr_previous_1,
301 sample_in => ram_input,
310 sample_in => ram_input,
302 sample_out => ram_output_1);
311 sample_out => ram_output_1);
303
312
304 RAM_CTRLR_v2_2 : RAM_CTRLR_v2
313 RAM_CTRLR_v2_2 : RAM_CTRLR_v2
305 GENERIC MAP (
314 GENERIC MAP (
306 tech => tech,
315 tech => tech,
307 Input_SZ_1 => Sample_SZ,
316 Input_SZ_1 => Sample_SZ,
308 Mem_use => Mem_use)
317 Mem_use => Mem_use)
309 PORT MAP (
318 PORT MAP (
310 clk => clk,
319 clk => clk,
311 rstn => rstn,
320 rstn => rstn,
321 init_mem_done => init_mem_done_2,
312 ram_write => ram_write_2,
322 ram_write => ram_write_2,
313 ram_read => ram_read_2,
323 ram_read => ram_read_2,
314 raddr_rst => raddr_rst_2,
324 raddr_rst => raddr_rst_2,
315 raddr_add1 => raddr_add1_2,
325 raddr_add1 => raddr_add1_2,
316 waddr_previous => waddr_previous_2,
326 waddr_previous => waddr_previous_2,
317 sample_in => ram_input,
327 sample_in => ram_input,
318 sample_out => ram_output_2);
328 sample_out => ram_output_2);
319 -----------------------------------------------------------------------------
329 -----------------------------------------------------------------------------
320
330
321 IIR_CEL_CTRLR_v3_DATAFLOW_1 : IIR_CEL_CTRLR_v3_DATAFLOW
331 IIR_CEL_CTRLR_v3_DATAFLOW_1 : IIR_CEL_CTRLR_v3_DATAFLOW
322 GENERIC MAP (
332 GENERIC MAP (
323 Sample_SZ => Sample_SZ,
333 Sample_SZ => Sample_SZ,
324 Coef_SZ => Coef_SZ,
334 Coef_SZ => Coef_SZ,
325 Coef_Nb => Coef_Nb,
335 Coef_Nb => Coef_Nb,
326 Coef_sel_SZ => Coef_sel_SZ)
336 Coef_sel_SZ => Coef_sel_SZ)
327 PORT MAP (
337 PORT MAP (
328 rstn => rstn,
338 rstn => rstn,
329 clk => clk,
339 clk => clk,
330 virg_pos => virg_pos,
340 virg_pos => virg_pos,
331 coefs => coefs,
341 coefs => coefs,
332 --CTRL
342 --CTRL
333 in_sel_src => in_sel_src,
343 in_sel_src => in_sel_src,
334 ram_sel_Wdata => ram_sel_Wdata,
344 ram_sel_Wdata => ram_sel_Wdata,
335 --
345 --
336 ram_input => ram_input,
346 ram_input => ram_input,
337 ram_output => ram_output,
347 ram_output => ram_output,
338 --
348 --
339 alu_sel_input => alu_sel_input,
349 alu_sel_input => alu_sel_input,
340 alu_sel_coeff => alu_sel_coeff,
350 alu_sel_coeff => alu_sel_coeff,
341 alu_ctrl => alu_ctrl,
351 alu_ctrl => alu_ctrl,
342 alu_comp => "00",
352 alu_comp => "00",
343 --DATA
353 --DATA
344 sample_in => sample_in_s,
354 sample_in => sample_in_s,
345 sample_out => sample_out_s);
355 sample_out => sample_out_s);
346 -----------------------------------------------------------------------------
356 -----------------------------------------------------------------------------
347
357
348
358
349 IIR_CEL_CTRLR_v3_CONTROL_1 : IIR_CEL_CTRLR_v2_CONTROL
359 IIR_CEL_CTRLR_v3_CONTROL_1 : IIR_CEL_CTRLR_v2_CONTROL
350 GENERIC MAP (
360 GENERIC MAP (
351 Coef_sel_SZ => Coef_sel_SZ,
361 Coef_sel_SZ => Coef_sel_SZ,
352 Cels_count => Cels_count,
362 Cels_count => Cels_count,
353 ChanelsCount => ChanelsCount)
363 ChanelsCount => ChanelsCount)
354 PORT MAP (
364 PORT MAP (
355 rstn => rstn,
365 rstn => rstn,
356 clk => clk,
366 clk => clk,
357 sample_in_val => sample_in_val,
367 sample_in_val => sample_in_val,
358 sample_in_rot => sample_in_rotate,
368 sample_in_rot => sample_in_rotate,
359 sample_out_val => sample_out_val_s,
369 sample_out_val => sample_out_val_s,
360 sample_out_rot => sample_out_rot_s,
370 sample_out_rot => sample_out_rot_s,
361
371
372 init_mem_done => init_mem_done,
373
362 in_sel_src => in_sel_src,
374 in_sel_src => in_sel_src,
363 ram_sel_Wdata => ram_sel_Wdata,
375 ram_sel_Wdata => ram_sel_Wdata,
364 ram_write => ram_write,
376 ram_write => ram_write,
365 ram_read => ram_read,
377 ram_read => ram_read,
366 raddr_rst => raddr_rst,
378 raddr_rst => raddr_rst,
367 raddr_add1 => raddr_add1,
379 raddr_add1 => raddr_add1,
368 waddr_previous => waddr_previous,
380 waddr_previous => waddr_previous,
369 alu_sel_input => alu_sel_input,
381 alu_sel_input => alu_sel_input,
370 alu_sel_coeff => alu_sel_coeff,
382 alu_sel_coeff => alu_sel_coeff,
371 alu_ctrl => alu_ctrl);
383 alu_ctrl => alu_ctrl);
372
384
373 -----------------------------------------------------------------------------
385 -----------------------------------------------------------------------------
374 -- SAMPLE IN
386 -- SAMPLE IN
375 -----------------------------------------------------------------------------
387 -----------------------------------------------------------------------------
376 loop_all_sample : FOR J IN Sample_SZ-1 DOWNTO 0 GENERATE
388 loop_all_sample : FOR J IN Sample_SZ-1 DOWNTO 0 GENERATE
377
389
378 loop_all_chanel : FOR I IN ChanelsCount-1 DOWNTO 0 GENERATE
390 loop_all_chanel : FOR I IN ChanelsCount-1 DOWNTO 0 GENERATE
379 PROCESS (clk, rstn)
391 PROCESS (clk, rstn)
380 BEGIN -- PROCESS
392 BEGIN -- PROCESS
381 IF rstn = '0' THEN -- asynchronous reset (active low)
393 IF rstn = '0' THEN -- asynchronous reset (active low)
382 sample_in_buf(I, J) <= '0';
394 sample_in_buf(I, J) <= '0';
383 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
395 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
384 IF sample_in_val = '1' THEN
396 IF sample_in_val = '1' THEN
385 sample_in_buf(I, J) <= sample_in(I, J);
397 sample_in_buf(I, J) <= sample_in(I, J);
386 ELSIF sample_in_rotate = '1' THEN
398 ELSIF sample_in_rotate = '1' THEN
387 sample_in_buf(I, J) <= sample_in_buf((I+1) MOD ChanelsCount, J);
399 sample_in_buf(I, J) <= sample_in_buf((I+1) MOD ChanelsCount, J);
388 END IF;
400 END IF;
389 END IF;
401 END IF;
390 END PROCESS;
402 END PROCESS;
391 END GENERATE loop_all_chanel;
403 END GENERATE loop_all_chanel;
392
404
393 sample_in_s(J) <= sample_in(0, J) WHEN sample_in_val = '1' ELSE sample_in_buf(0, J);
405 sample_in_s(J) <= sample_in(0, J) WHEN sample_in_val = '1' ELSE sample_in_buf(0, J);
394
406
395 END GENERATE loop_all_sample;
407 END GENERATE loop_all_sample;
396
408
397 -----------------------------------------------------------------------------
409 -----------------------------------------------------------------------------
398 -- SAMPLE OUT
410 -- SAMPLE OUT
399 -----------------------------------------------------------------------------
411 -----------------------------------------------------------------------------
400 PROCESS (clk, rstn)
412 PROCESS (clk, rstn)
401 BEGIN -- PROCESS
413 BEGIN -- PROCESS
402 IF rstn = '0' THEN -- asynchronous reset (active low)
414 IF rstn = '0' THEN -- asynchronous reset (active low)
403 sample_out_val <= '0';
415 sample_out_val <= '0';
404 sample_out_val_s2 <= '0';
416 sample_out_val_s2 <= '0';
405 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
417 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
406 sample_out_val <= sample_out_val_s2;
418 sample_out_val <= sample_out_val_s2;
407 sample_out_val_s2 <= sample_out_val_s;
419 sample_out_val_s2 <= sample_out_val_s;
408 END IF;
420 END IF;
409 END PROCESS;
421 END PROCESS;
410
422
411 chanel_HIGH : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE
423 chanel_HIGH : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE
412 PROCESS (clk, rstn)
424 PROCESS (clk, rstn)
413 BEGIN -- PROCESS
425 BEGIN -- PROCESS
414 IF rstn = '0' THEN -- asynchronous reset (active low)
426 IF rstn = '0' THEN -- asynchronous reset (active low)
415 sample_out_s2(ChanelsCount-1, I) <= '0';
427 sample_out_s2(ChanelsCount-1, I) <= '0';
416 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
428 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
417 IF sample_out_rot_s = '1' THEN
429 IF sample_out_rot_s = '1' THEN
418 sample_out_s2(ChanelsCount-1, I) <= sample_out_s(I);
430 sample_out_s2(ChanelsCount-1, I) <= sample_out_s(I);
419 END IF;
431 END IF;
420 END IF;
432 END IF;
421 END PROCESS;
433 END PROCESS;
422 END GENERATE chanel_HIGH;
434 END GENERATE chanel_HIGH;
423
435
424 chanel_more : IF ChanelsCount > 1 GENERATE
436 chanel_more : IF ChanelsCount > 1 GENERATE
425 all_chanel : FOR J IN ChanelsCount-1 DOWNTO 1 GENERATE
437 all_chanel : FOR J IN ChanelsCount-1 DOWNTO 1 GENERATE
426 all_bit : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE
438 all_bit : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE
427 PROCESS (clk, rstn)
439 PROCESS (clk, rstn)
428 BEGIN -- PROCESS
440 BEGIN -- PROCESS
429 IF rstn = '0' THEN -- asynchronous reset (active low)
441 IF rstn = '0' THEN -- asynchronous reset (active low)
430 sample_out_s2(J-1, I) <= '0';
442 sample_out_s2(J-1, I) <= '0';
431 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
443 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
432 IF sample_out_rot_s = '1' THEN
444 IF sample_out_rot_s = '1' THEN
433 sample_out_s2(J-1, I) <= sample_out_s2(J, I);
445 sample_out_s2(J-1, I) <= sample_out_s2(J, I);
434 END IF;
446 END IF;
435 END IF;
447 END IF;
436 END PROCESS;
448 END PROCESS;
437 END GENERATE all_bit;
449 END GENERATE all_bit;
438 END GENERATE all_chanel;
450 END GENERATE all_chanel;
439 END GENERATE chanel_more;
451 END GENERATE chanel_more;
440
452
441 sample_out <= sample_out_s2;
453 sample_out <= sample_out_s2;
442 END ar_IIR_CEL_CTRLR_v3;
454 END ar_IIR_CEL_CTRLR_v3;
Show file before | Show file after | Hide comments
@@ -1,122 +1,138
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
21 ----------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY lpp;
25 LIBRARY lpp;
26 USE lpp.iir_filter.ALL;
26 USE lpp.iir_filter.ALL;
27 USE lpp.FILTERcfg.ALL;
27 USE lpp.FILTERcfg.ALL;
28 USE lpp.general_purpose.ALL;
28 USE lpp.general_purpose.ALL;
29 LIBRARY techmap;
29 LIBRARY techmap;
30 USE techmap.gencomp.ALL;
30 USE techmap.gencomp.ALL;
31
31
32 ENTITY RAM_CTRLR_v2 IS
32 ENTITY RAM_CTRLR_v2 IS
33 GENERIC(
33 GENERIC(
34 tech : INTEGER := 0;
34 tech : INTEGER := 0;
35 Input_SZ_1 : INTEGER := 16;
35 Input_SZ_1 : INTEGER := 16;
36 Mem_use : INTEGER := use_RAM
36 Mem_use : INTEGER := use_RAM
37 );
37 );
38 PORT(
38 PORT(
39 rstn : IN STD_LOGIC;
39 rstn : IN STD_LOGIC;
40 clk : IN STD_LOGIC;
40 clk : IN STD_LOGIC;
41 -- ram init done
42 init_mem_done: out STD_LOGIC;
41 -- R/W Ctrl
43 -- R/W Ctrl
42 ram_write : IN STD_LOGIC;
44 ram_write : IN STD_LOGIC;
43 ram_read : IN STD_LOGIC;
45 ram_read : IN STD_LOGIC;
44 -- ADDR Ctrl
46 -- ADDR Ctrl
45 raddr_rst : IN STD_LOGIC;
47 raddr_rst : IN STD_LOGIC;
46 raddr_add1 : IN STD_LOGIC;
48 raddr_add1 : IN STD_LOGIC;
47 waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
49 waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
48 -- Data
50 -- Data
49 sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
51 sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
50 sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0)
52 sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0)
51 );
53 );
52 END RAM_CTRLR_v2;
54 END RAM_CTRLR_v2;
53
55
54
56
55 ARCHITECTURE ar_RAM_CTRLR_v2 OF RAM_CTRLR_v2 IS
57 ARCHITECTURE ar_RAM_CTRLR_v2 OF RAM_CTRLR_v2 IS
56
58
57 SIGNAL WD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
59 SIGNAL WD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
58 SIGNAL RD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
60 SIGNAL RD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
59 SIGNAL WEN, REN : STD_LOGIC;
61 SIGNAL WEN, REN : STD_LOGIC;
60 SIGNAL RADDR : STD_LOGIC_VECTOR(7 DOWNTO 0);
62 SIGNAL RADDR : STD_LOGIC_VECTOR(7 DOWNTO 0);
61 SIGNAL WADDR : STD_LOGIC_VECTOR(7 DOWNTO 0);
63 SIGNAL WADDR : STD_LOGIC_VECTOR(7 DOWNTO 0);
62 SIGNAL counter : STD_LOGIC_VECTOR(7 DOWNTO 0);
64 SIGNAL counter : STD_LOGIC_VECTOR(7 DOWNTO 0);
63
65
66 signal rst_mem_done_s : std_logic;
67 signal ram_write_s : std_logic;
68
64 BEGIN
69 BEGIN
65
70
66 sample_out <= RD(Input_SZ_1-1 DOWNTO 0);
71 init_mem_done <= rst_mem_done_s;
67 WD(Input_SZ_1-1 DOWNTO 0) <= sample_in;
72
73 sample_out <= RD(Input_SZ_1-1 DOWNTO 0) when rst_mem_done_s = '1' else (others => '0');
74 WD(Input_SZ_1-1 DOWNTO 0) <= sample_in when rst_mem_done_s = '1' else (others => '0');
75 ram_write_s <= ram_write when rst_mem_done_s = '1' else '1';
68 -----------------------------------------------------------------------------
76 -----------------------------------------------------------------------------
69 -- RAM
77 -- RAM
70 -----------------------------------------------------------------------------
78 -----------------------------------------------------------------------------
71
79
72 memCEL : IF Mem_use = use_CEL GENERATE
80 memCEL : IF Mem_use = use_CEL GENERATE
73 WEN <= NOT ram_write;
81 WEN <= NOT ram_write_s;
74 REN <= NOT ram_read;
82 REN <= NOT ram_read;
75 -- RAMblk : RAM_CEL_N
76 -- GENERIC MAP(Input_SZ_1)
77 RAMblk : RAM_CEL
83 RAMblk : RAM_CEL
78 GENERIC MAP(Input_SZ_1, 8)
84 GENERIC MAP(Input_SZ_1, 8)
79 PORT MAP(
85 PORT MAP(
80 WD => WD,
86 WD => WD,
81 RD => RD,
87 RD => RD,
82 WEN => WEN,
88 WEN => WEN,
83 REN => REN,
89 REN => REN,
84 WADDR => WADDR,
90 WADDR => WADDR,
85 RADDR => RADDR,
91 RADDR => RADDR,
86 RWCLK => clk,
92 RWCLK => clk,
87 RESET => rstn
93 RESET => rstn
88 ) ;
94 ) ;
89 END GENERATE;
95 END GENERATE;
90
96
91 memRAM : IF Mem_use = use_RAM GENERATE
97 memRAM : IF Mem_use = use_RAM GENERATE
92 SRAM : syncram_2p
98 SRAM : syncram_2p
93 GENERIC MAP(tech, 8, Input_SZ_1)
99 GENERIC MAP(tech, 8, Input_SZ_1)
94 PORT MAP(clk, ram_read, RADDR, RD, clk, ram_write, WADDR, WD);
100 PORT MAP(clk, ram_read, RADDR, RD, clk, ram_write_s, WADDR, WD);
95 END GENERATE;
101 END GENERATE;
96
102
97 -----------------------------------------------------------------------------
103 -----------------------------------------------------------------------------
98 -- RADDR
104 -- RADDR
99 -----------------------------------------------------------------------------
105 -----------------------------------------------------------------------------
100 PROCESS (clk, rstn)
106 PROCESS (clk, rstn)
101 BEGIN -- PROCESS
107 BEGIN -- PROCESS
102 IF rstn = '0' THEN -- asynchronous reset (active low)
108 IF rstn = '0' THEN -- asynchronous reset (active low)
103 counter <= (OTHERS => '0');
109 counter <= (OTHERS => '0');
110 rst_mem_done_s <= '0';
104 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
111 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
112 if rst_mem_done_s = '0' then
113 counter <= STD_LOGIC_VECTOR(UNSIGNED(counter)+1);
114 else
105 IF raddr_rst = '1' THEN
115 IF raddr_rst = '1' THEN
106 counter <= (OTHERS => '0');
116 counter <= (OTHERS => '0');
107 ELSIF raddr_add1 = '1' THEN
117 ELSIF raddr_add1 = '1' THEN
108 counter <= STD_LOGIC_VECTOR(UNSIGNED(counter)+1);
118 counter <= STD_LOGIC_VECTOR(UNSIGNED(counter)+1);
109 END IF;
119 END IF;
120 end if;
121 if counter = x"FF" then
122 rst_mem_done_s <= '1';
123 end if;
124
110 END IF;
125 END IF;
111 END PROCESS;
126 END PROCESS;
112 RADDR <= counter;
127 RADDR <= counter;
113
128
114 -----------------------------------------------------------------------------
129 -----------------------------------------------------------------------------
115 -- WADDR
130 -- WADDR
116 -----------------------------------------------------------------------------
131 -----------------------------------------------------------------------------
117 WADDR <= STD_LOGIC_VECTOR(UNSIGNED(counter)-2) WHEN waddr_previous = "10" ELSE
132 WADDR <= STD_LOGIC_VECTOR(UNSIGNED(counter)) when rst_mem_done_s = '0' else
133 STD_LOGIC_VECTOR(UNSIGNED(counter)-2) WHEN waddr_previous = "10" ELSE
118 STD_LOGIC_VECTOR(UNSIGNED(counter)-1) WHEN waddr_previous = "01" ELSE
134 STD_LOGIC_VECTOR(UNSIGNED(counter)-1) WHEN waddr_previous = "01" ELSE
119 STD_LOGIC_VECTOR(UNSIGNED(counter));
135 STD_LOGIC_VECTOR(UNSIGNED(counter));
120
136
121
137
122 END ar_RAM_CTRLR_v2;
138 END ar_RAM_CTRLR_v2;
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