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Clone from http://pc-instru.lpp.polytechnique.fr:5000/VHD_Lib

Added missing files (sdc/pdc/makefile) for LFR-EQM boards...
pellion -
r639:5ffe6bd0368c default draft
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1 set_io clk49_152MHz -pinname D5 -fixed yes -DIRECTION Inout
2 set_io clk50MHz -pinname B3 -fixed yes -DIRECTION Inout
3 set_io reset -pinname N18 -fixed yes -DIRECTION Inout
4
5 set_io {address[0]} -pinname H16 -fixed yes -DIRECTION Inout
6 set_io {address[1]} -pinname J15 -fixed yes -DIRECTION Inout
7 set_io {address[2]} -pinname B18 -fixed yes -DIRECTION Inout
8 set_io {address[3]} -pinname C17 -fixed yes -DIRECTION Inout
9 set_io {address[4]} -pinname C18 -fixed yes -DIRECTION Inout
10 set_io {address[5]} -pinname U2 -fixed yes -DIRECTION Inout
11 set_io {address[6]} -pinname U3 -fixed yes -DIRECTION Inout
12 set_io {address[7]} -pinname R5 -fixed yes -DIRECTION Inout
13 set_io {address[8]} -pinname N11 -fixed yes -DIRECTION Inout
14 set_io {address[9]} -pinname R13 -fixed yes -DIRECTION Inout
15 set_io {address[10]} -pinname V13 -fixed yes -DIRECTION Inout
16 set_io {address[11]} -pinname U13 -fixed yes -DIRECTION Inout
17 set_io {address[12]} -pinname V15 -fixed yes -DIRECTION Inout
18 set_io {address[13]} -pinname V16 -fixed yes -DIRECTION Inout
19 set_io {address[14]} -pinname V17 -fixed yes -DIRECTION Inout
20 set_io {address[15]} -pinname N1 -fixed yes -DIRECTION Inout
21 set_io {address[16]} -pinname R3 -fixed yes -DIRECTION Inout
22 set_io {address[17]} -pinname P4 -fixed yes -DIRECTION Inout
23 set_io {address[18]} -pinname N3 -fixed yes -DIRECTION Inout
24 set_io {address[19]} -pinname M7 -fixed yes -DIRECTION Inout
25
26 set_io {data[0]} -pinname P17 -fixed yes -DIRECTION Inout
27 set_io {data[1]} -pinname R18 -fixed yes -DIRECTION Inout
28 set_io {data[2]} -pinname T18 -fixed yes -DIRECTION Inout
29 set_io {data[3]} -pinname J13 -fixed yes -DIRECTION Inout
30 set_io {data[4]} -pinname T13 -fixed yes -DIRECTION Inout
31 set_io {data[5]} -pinname T12 -fixed yes -DIRECTION Inout
32 set_io {data[6]} -pinname R12 -fixed yes -DIRECTION Inout
33 set_io {data[7]} -pinname T11 -fixed yes -DIRECTION Inout
34 set_io {data[8]} -pinname N2 -fixed yes -DIRECTION Inout
35 set_io {data[9]} -pinname P1 -fixed yes -DIRECTION Inout
36 set_io {data[10]} -pinname R1 -fixed yes -DIRECTION Inout
37 set_io {data[11]} -pinname T1 -fixed yes -DIRECTION Inout
38 set_io {data[12]} -pinname M4 -fixed yes -DIRECTION Inout
39 set_io {data[13]} -pinname K1 -fixed yes -DIRECTION Inout
40 set_io {data[14]} -pinname J1 -fixed yes -DIRECTION Inout
41 set_io {data[15]} -pinname H1 -fixed yes -DIRECTION Inout
42 set_io {data[16]} -pinname H15 -fixed yes -DIRECTION Inout
43 set_io {data[17]} -pinname G15 -fixed yes -DIRECTION Inout
44 set_io {data[18]} -pinname H13 -fixed yes -DIRECTION Inout
45 set_io {data[19]} -pinname G12 -fixed yes -DIRECTION Inout
46 set_io {data[20]} -pinname V14 -fixed yes -DIRECTION Inout
47 set_io {data[21]} -pinname N9 -fixed yes -DIRECTION Inout
48 set_io {data[22]} -pinname M13 -fixed yes -DIRECTION Inout
49 set_io {data[23]} -pinname M15 -fixed yes -DIRECTION Inout
50 set_io {data[24]} -pinname J17 -fixed yes -DIRECTION Inout
51 set_io {data[25]} -pinname K15 -fixed yes -DIRECTION Inout
52 set_io {data[26]} -pinname J14 -fixed yes -DIRECTION Inout
53 set_io {data[27]} -pinname U18 -fixed yes -DIRECTION Inout
54 set_io {data[28]} -pinname H18 -fixed yes -DIRECTION Inout
55 set_io {data[29]} -pinname J18 -fixed yes -DIRECTION Inout
56 set_io {data[30]} -pinname G17 -fixed yes -DIRECTION Inout
57 set_io {data[31]} -pinname F18 -fixed yes -DIRECTION Inout
58
59 set_io nSRAM_BE0 -pinname U12 -fixed yes -DIRECTION Inout
60 set_io nSRAM_BE1 -pinname K18 -fixed yes -DIRECTION Inout
61 set_io nSRAM_BE2 -pinname K12 -fixed yes -DIRECTION Inout
62 set_io nSRAM_BE3 -pinname F17 -fixed yes -DIRECTION Inout
63 set_io nSRAM_WE -pinname D18 -fixed yes -DIRECTION Inout
64 set_io nSRAM_CE -pinname M6 -fixed yes -DIRECTION Inout
65 set_io nSRAM_OE -pinname N12 -fixed yes -DIRECTION Inout
66
67 set_io spw1_din -pinname D6 -fixed yes -DIRECTION Inout
68 set_io spw1_sin -pinname C6 -fixed yes -DIRECTION Inout
69 set_io spw1_dout -pinname C16 -fixed yes -DIRECTION Inout
70 set_io spw1_sout -pinname C4 -fixed yes -DIRECTION Inout
71
72 set_io spw2_din -pinname E6 -fixed yes -DIRECTION Inout
73 set_io spw2_sin -pinname C15 -fixed yes -DIRECTION Inout
74 set_io spw2_dout -pinname B7 -fixed yes -DIRECTION Inout
75 set_io spw2_sout -pinname D7 -fixed yes -DIRECTION Inout
76
77 set_io {led[0]} -pinname K17 -fixed yes -DIRECTION Inout
78 set_io {led[1]} -pinname L18 -fixed yes -DIRECTION Inout
79 set_io {led[2]} -pinname M17 -fixed yes -DIRECTION Inout
80
81 set_io TAG1 -pinname J12 -fixed yes -DIRECTION Inout
82 set_io TAG2 -pinname K13 -fixed yes -DIRECTION Inout
83 set_io TAG3 -pinname L16 -fixed yes -DIRECTION Inout
84 set_io TAG4 -pinname L15 -fixed yes -DIRECTION Inout
85 #set_io TAG5 -pinname M16 -fixed yes -DIRECTION Inout
86 #set_io TAG6 -pinname L13 -fixed yes -DIRECTION Inout
87 #set_io TAG7 -pinname P6 -fixed yes -DIRECTION Inout
88 set_io TAG8 -pinname R6 -fixed yes -DIRECTION Inout
89 #set_io TAG9 -pinname T4 -fixed yes -DIRECTION Inout
90
91 set_io bias_fail_sw -pinname A3 -fixed yes -DIRECTION Inout
92
93 set_io {ADC_OEB_bar_CH[0]} -pinname A13 -fixed yes -DIRECTION Inout
94 set_io {ADC_OEB_bar_CH[1]} -pinname A14 -fixed yes -DIRECTION Inout
95 set_io {ADC_OEB_bar_CH[2]} -pinname A10 -fixed yes -DIRECTION Inout
96 set_io {ADC_OEB_bar_CH[3]} -pinname B10 -fixed yes -DIRECTION Inout
97 set_io {ADC_OEB_bar_CH[4]} -pinname B13 -fixed yes -DIRECTION Inout
98 set_io {ADC_OEB_bar_CH[5]} -pinname D13 -fixed yes -DIRECTION Inout
99 set_io {ADC_OEB_bar_CH[6]} -pinname A11 -fixed yes -DIRECTION Inout
100 set_io {ADC_OEB_bar_CH[7]} -pinname B12 -fixed yes -DIRECTION Inout
101
102 set_io ADC_smpclk -pinname A15 -fixed yes -DIRECTION Inout
103
104 set_io HK_smpclk -pinname R11 -fixed yes -DIRECTION Inout
105 set_io ADC_OEB_bar_HK -pinname D14 -fixed yes -DIRECTION Inout
106 set_io {HK_SEL[0]} -pinname A2 -fixed yes -DIRECTION Inout
107 set_io {HK_SEL[1]} -pinname C3 -fixed yes -DIRECTION Inout
108
109 set_io {ADC_data[0]} -pinname A16 -fixed yes -DIRECTION Inout
110 set_io {ADC_data[1]} -pinname B16 -fixed yes -DIRECTION Inout
111 set_io {ADC_data[2]} -pinname A17 -fixed yes -DIRECTION Inout
112 set_io {ADC_data[3]} -pinname C12 -fixed yes -DIRECTION Inout
113 set_io {ADC_data[4]} -pinname B17 -fixed yes -DIRECTION Inout
114 set_io {ADC_data[5]} -pinname C13 -fixed yes -DIRECTION Inout
115 set_io {ADC_data[6]} -pinname D15 -fixed yes -DIRECTION Inout
116 set_io {ADC_data[7]} -pinname E15 -fixed yes -DIRECTION Inout
117 set_io {ADC_data[8]} -pinname D16 -fixed yes -DIRECTION Inout
118 set_io {ADC_data[9]} -pinname F16 -fixed yes -DIRECTION Inout
119 set_io {ADC_data[10]} -pinname F15 -fixed yes -DIRECTION Inout
120 set_io {ADC_data[11]} -pinname G16 -fixed yes -DIRECTION Inout
121 set_io {ADC_data[12]} -pinname F13 -fixed yes -DIRECTION Inout
122 set_io {ADC_data[13]} -pinname G13 -fixed yes -DIRECTION Inout
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@@ -0,0 +1,124
1 set_io clk49_152MHz -pinname D5 -fixed yes -DIRECTION Inout
2 set_io clk50MHz -pinname B3 -fixed yes -DIRECTION Inout
3 set_io reset -pinname R4 -fixed yes -DIRECTION Inout -SCHMITT_TRIGGER On
4
5 set_io {address[0]} -pinname U3 -fixed yes -DIRECTION Inout
6 set_io {address[1]} -pinname V14 -fixed yes -DIRECTION Inout
7 set_io {address[2]} -pinname V13 -fixed yes -DIRECTION Inout
8 set_io {address[3]} -pinname V16 -fixed yes -DIRECTION Inout
9 set_io {address[4]} -pinname N9 -fixed yes -DIRECTION Inout
10 set_io {address[5]} -pinname T11 -fixed yes -DIRECTION Inout
11 set_io {address[6]} -pinname U13 -fixed yes -DIRECTION Inout
12 set_io {address[7]} -pinname R5 -fixed yes -DIRECTION Inout
13 set_io {address[8]} -pinname U2 -fixed yes -DIRECTION Inout
14 set_io {address[9]} -pinname N11 -fixed yes -DIRECTION Inout
15 set_io {address[10]} -pinname R13 -fixed yes -DIRECTION Inout
16 set_io {address[11]} -pinname R12 -fixed yes -DIRECTION Inout
17 set_io {address[12]} -pinname M15 -fixed yes -DIRECTION Inout
18 set_io {address[13]} -pinname T12 -fixed yes -DIRECTION Inout
19 set_io {address[14]} -pinname M13 -fixed yes -DIRECTION Inout
20 set_io {address[15]} -pinname T13 -fixed yes -DIRECTION Inout
21 set_io {address[16]} -pinname L13 -fixed yes -DIRECTION Inout
22 set_io {address[17]} -pinname V17 -fixed yes -DIRECTION Inout
23 set_io {address[18]} -pinname V15 -fixed yes -DIRECTION Inout
24
25 set_io {data[0]} -pinname V4 -fixed yes -DIRECTION Inout
26 set_io {data[1]} -pinname V3 -fixed yes -DIRECTION Inout
27 set_io {data[2]} -pinname V2 -fixed yes -DIRECTION Inout
28 set_io {data[3]} -pinname T3 -fixed yes -DIRECTION Inout
29 set_io {data[4]} -pinname N6 -fixed yes -DIRECTION Inout
30 set_io {data[5]} -pinname P6 -fixed yes -DIRECTION Inout
31 set_io {data[6]} -pinname R6 -fixed yes -DIRECTION Inout
32 set_io {data[7]} -pinname T4 -fixed yes -DIRECTION Inout
33 set_io {data[8]} -pinname T1 -fixed yes -DIRECTION Inout
34 set_io {data[9]} -pinname R1 -fixed yes -DIRECTION Inout
35 set_io {data[10]} -pinname P1 -fixed yes -DIRECTION Inout
36 set_io {data[11]} -pinname N2 -fixed yes -DIRECTION Inout
37 set_io {data[12]} -pinname R3 -fixed yes -DIRECTION Inout
38 set_io {data[13]} -pinname P4 -fixed yes -DIRECTION Inout
39 set_io {data[14]} -pinname N4 -fixed yes -DIRECTION Inout
40 set_io {data[15]} -pinname N3 -fixed yes -DIRECTION Inout
41 set_io {data[16]} -pinname G12 -fixed yes -DIRECTION Inout
42 set_io {data[17]} -pinname G15 -fixed yes -DIRECTION Inout
43 set_io {data[18]} -pinname H15 -fixed yes -DIRECTION Inout
44 set_io {data[19]} -pinname F17 -fixed yes -DIRECTION Inout
45 set_io {data[20]} -pinname F18 -fixed yes -DIRECTION Inout
46 set_io {data[21]} -pinname G17 -fixed yes -DIRECTION Inout
47 set_io {data[22]} -pinname H18 -fixed yes -DIRECTION Inout
48 set_io {data[23]} -pinname J18 -fixed yes -DIRECTION Inout
49 set_io {data[24]} -pinname R18 -fixed yes -DIRECTION Inout
50 set_io {data[25]} -pinname N18 -fixed yes -DIRECTION Inout
51 set_io {data[26]} -pinname P17 -fixed yes -DIRECTION Inout
52 set_io {data[27]} -pinname N17 -fixed yes -DIRECTION Inout
53 set_io {data[28]} -pinname T18 -fixed yes -DIRECTION Inout
54 set_io {data[29]} -pinname M17 -fixed yes -DIRECTION Inout
55 set_io {data[30]} -pinname U18 -fixed yes -DIRECTION Inout
56 set_io {data[31]} -pinname L18 -fixed yes -DIRECTION Inout
57
58 set_io nSRAM_MBE -pinname E4 -fixed yes -DIRECTION Inout
59 set_io nSRAM_E1 -pinname D1 -fixed yes -DIRECTION Inout
60 set_io nSRAM_E2 -pinname C1 -fixed yes -DIRECTION Inout
61 #set_io nSRAM_SCRUB -pinname C2 -fixed yes -DIRECTION Inout
62 set_io nSRAM_W -pinname D4 -fixed yes -DIRECTION Inout
63 set_io nSRAM_G -pinname E1 -fixed yes -DIRECTION Inout
64 set_io nSRAM_BUSY -pinname F4 -fixed yes -DIRECTION Inout
65
66 set_io spw1_en -pinname G4 -fixed yes -DIRECTION Inout
67 set_io spw1_din -pinname D13 -fixed yes -DIRECTION Inout
68 set_io spw1_sin -pinname D14 -fixed yes -DIRECTION Inout
69 set_io spw1_dout -pinname C16 -fixed yes -DIRECTION Inout
70 set_io spw1_sout -pinname C4 -fixed yes -DIRECTION Inout
71
72 set_io spw2_en -pinname G3 -fixed yes -DIRECTION Inout
73 set_io spw2_din -pinname E6 -fixed yes -DIRECTION Inout
74 set_io spw2_sin -pinname C15 -fixed yes -DIRECTION Inout
75 set_io spw2_dout -pinname B7 -fixed yes -DIRECTION Inout
76 set_io spw2_sout -pinname D7 -fixed yes -DIRECTION Inout
77
78 set_io {TAG[1]} -pinname J12 -fixed yes -DIRECTION Inout
79 set_io {TAG[2]} -pinname K12 -fixed yes -DIRECTION Inout
80 set_io {TAG[3]} -pinname K13 -fixed yes -DIRECTION Inout
81 set_io {TAG[4]} -pinname L16 -fixed yes -DIRECTION Inout
82 set_io {TAG[5]} -pinname L15 -fixed yes -DIRECTION Inout
83 set_io {TAG[6]} -pinname M16 -fixed yes -DIRECTION Inout
84 set_io {TAG[7]} -pinname J14 -fixed yes -DIRECTION Inout
85 set_io {TAG[8]} -pinname K15 -fixed yes -DIRECTION Inout
86 set_io {TAG[9]} -pinname J17 -fixed yes -DIRECTION Inout
87
88 set_io bias_fail_sw -pinname A3 -fixed yes -DIRECTION Inout
89
90 set_io {ADC_OEB_bar_CH[0]} -pinname A10 -fixed yes -DIRECTION Inout
91 set_io {ADC_OEB_bar_CH[1]} -pinname B10 -fixed yes -DIRECTION Inout
92 set_io {ADC_OEB_bar_CH[2]} -pinname B12 -fixed yes -DIRECTION Inout
93 set_io {ADC_OEB_bar_CH[3]} -pinname A11 -fixed yes -DIRECTION Inout
94 set_io {ADC_OEB_bar_CH[4]} -pinname B13 -fixed yes -DIRECTION Inout
95 set_io {ADC_OEB_bar_CH[5]} -pinname C6 -fixed yes -DIRECTION Inout
96 set_io {ADC_OEB_bar_CH[6]} -pinname A13 -fixed yes -DIRECTION Inout
97 set_io {ADC_OEB_bar_CH[7]} -pinname A14 -fixed yes -DIRECTION Inout
98
99 set_io ADC_smpclk -pinname A15 -fixed yes -DIRECTION Inout
100
101 set_io HK_smpclk -pinname R11 -fixed yes -DIRECTION Inout
102 set_io ADC_OEB_bar_HK -pinname D6 -fixed yes -DIRECTION Inout
103 set_io {HK_SEL[0]} -pinname C3 -fixed yes -DIRECTION Inout
104 set_io {HK_SEL[1]} -pinname A2 -fixed yes -DIRECTION Inout
105
106 #set_io {ADC_data[0]} -pinname G13 -fixed yes -DIRECTION Inout
107 #set_io {ADC_data[1]} -pinname G16 -fixed yes -DIRECTION Inout
108 #set_io {ADC_data[2]} -pinname F16 -fixed yes -DIRECTION Inout
109 #set_io {ADC_data[3]} -pinname E15 -fixed yes -DIRECTION Inout
110 #set_io {ADC_data[4]} -pinname F13 -fixed yes -DIRECTION Inout
111 #set_io {ADC_data[5]} -pinname F15 -fixed yes -DIRECTION Inout
112 #set_io {ADC_data[6]} -pinname D16 -fixed yes -DIRECTION Inout
113 #set_io {ADC_data[7]} -pinname D15 -fixed yes -DIRECTION Inout
114 #set_io {ADC_data[8]} -pinname B17 -fixed yes -DIRECTION Inout
115 #set_io {ADC_data[9]} -pinname A17 -fixed yes -DIRECTION Inout
116 #set_io {ADC_data[10]} -pinname A16 -fixed yes -DIRECTION Inout
117 #set_io {ADC_data[11]} -pinname B16 -fixed yes -DIRECTION Inout
118 #set_io {ADC_data[12]} -pinname C12 -fixed yes -DIRECTION Inout
119 #set_io {ADC_data[13]} -pinname C13 -fixed yes -DIRECTION Inout
120
121 set_io DAC_SDO -pinname A4 -fixed yes -DIRECTION Inout
122 set_io DAC_SCK -pinname A5 -fixed yes -DIRECTION Inout
123 set_io DAC_SYNC -pinname B6 -fixed yes -DIRECTION Inout
124 set_io DAC_CAL_EN -pinname A6 -fixed yes -DIRECTION Inout
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@@ -0,0 +1,123
1 set_io clk50MHz -pinname B3 -fixed yes -DIRECTION Inout
2 set_io reset -pinname R4 -fixed yes -DIRECTION Inout -SCHMITT_TRIGGER On
3
4 set_io {address[0]} -pinname U3 -fixed yes -DIRECTION Inout
5 set_io {address[1]} -pinname V14 -fixed yes -DIRECTION Inout
6 set_io {address[2]} -pinname V13 -fixed yes -DIRECTION Inout
7 set_io {address[3]} -pinname V16 -fixed yes -DIRECTION Inout
8 set_io {address[4]} -pinname N9 -fixed yes -DIRECTION Inout
9 set_io {address[5]} -pinname T11 -fixed yes -DIRECTION Inout
10 set_io {address[6]} -pinname U13 -fixed yes -DIRECTION Inout
11 set_io {address[7]} -pinname R5 -fixed yes -DIRECTION Inout
12 set_io {address[8]} -pinname U2 -fixed yes -DIRECTION Inout
13 set_io {address[9]} -pinname N11 -fixed yes -DIRECTION Inout
14 set_io {address[10]} -pinname R13 -fixed yes -DIRECTION Inout
15 set_io {address[11]} -pinname R12 -fixed yes -DIRECTION Inout
16 set_io {address[12]} -pinname M15 -fixed yes -DIRECTION Inout
17 set_io {address[13]} -pinname T12 -fixed yes -DIRECTION Inout
18 set_io {address[14]} -pinname M13 -fixed yes -DIRECTION Inout
19 set_io {address[15]} -pinname T13 -fixed yes -DIRECTION Inout
20 set_io {address[16]} -pinname L13 -fixed yes -DIRECTION Inout
21 set_io {address[17]} -pinname V17 -fixed yes -DIRECTION Inout
22 set_io {address[18]} -pinname V15 -fixed yes -DIRECTION Inout
23
24 set_io {data[0]} -pinname V4 -fixed yes -DIRECTION Inout
25 set_io {data[1]} -pinname V3 -fixed yes -DIRECTION Inout
26 set_io {data[2]} -pinname V2 -fixed yes -DIRECTION Inout
27 set_io {data[3]} -pinname T3 -fixed yes -DIRECTION Inout
28 set_io {data[4]} -pinname N6 -fixed yes -DIRECTION Inout
29 set_io {data[5]} -pinname P6 -fixed yes -DIRECTION Inout
30 set_io {data[6]} -pinname R6 -fixed yes -DIRECTION Inout
31 set_io {data[7]} -pinname T4 -fixed yes -DIRECTION Inout
32 set_io {data[8]} -pinname T1 -fixed yes -DIRECTION Inout
33 set_io {data[9]} -pinname R1 -fixed yes -DIRECTION Inout
34 set_io {data[10]} -pinname P1 -fixed yes -DIRECTION Inout
35 set_io {data[11]} -pinname N2 -fixed yes -DIRECTION Inout
36 set_io {data[12]} -pinname R3 -fixed yes -DIRECTION Inout
37 set_io {data[13]} -pinname P4 -fixed yes -DIRECTION Inout
38 set_io {data[14]} -pinname N4 -fixed yes -DIRECTION Inout
39 set_io {data[15]} -pinname N3 -fixed yes -DIRECTION Inout
40 set_io {data[16]} -pinname G12 -fixed yes -DIRECTION Inout
41 set_io {data[17]} -pinname G15 -fixed yes -DIRECTION Inout
42 set_io {data[18]} -pinname H15 -fixed yes -DIRECTION Inout
43 set_io {data[19]} -pinname F17 -fixed yes -DIRECTION Inout
44 set_io {data[20]} -pinname F18 -fixed yes -DIRECTION Inout
45 set_io {data[21]} -pinname G17 -fixed yes -DIRECTION Inout
46 set_io {data[22]} -pinname H18 -fixed yes -DIRECTION Inout
47 set_io {data[23]} -pinname J18 -fixed yes -DIRECTION Inout
48 set_io {data[24]} -pinname R18 -fixed yes -DIRECTION Inout
49 set_io {data[25]} -pinname N18 -fixed yes -DIRECTION Inout
50 set_io {data[26]} -pinname P17 -fixed yes -DIRECTION Inout
51 set_io {data[27]} -pinname N17 -fixed yes -DIRECTION Inout
52 set_io {data[28]} -pinname T18 -fixed yes -DIRECTION Inout
53 set_io {data[29]} -pinname M17 -fixed yes -DIRECTION Inout
54 set_io {data[30]} -pinname U18 -fixed yes -DIRECTION Inout
55 set_io {data[31]} -pinname L18 -fixed yes -DIRECTION Inout
56
57 set_io nSRAM_MBE -pinname E4 -fixed yes -DIRECTION Inout
58 set_io nSRAM_E1 -pinname D1 -fixed yes -DIRECTION Inout
59 set_io nSRAM_E2 -pinname C1 -fixed yes -DIRECTION Inout
60 #set_io nSRAM_SCRUB -pinname C2 -fixed yes -DIRECTION Inout
61 set_io nSRAM_W -pinname D4 -fixed yes -DIRECTION Inout
62 set_io nSRAM_G -pinname E1 -fixed yes -DIRECTION Inout
63 set_io nSRAM_BUSY -pinname F4 -fixed yes -DIRECTION Inout
64
65 set_io spw1_en -pinname G4 -fixed yes -DIRECTION Inout
66 set_io spw1_din -pinname D13 -fixed yes -DIRECTION Inout
67 set_io spw1_sin -pinname D14 -fixed yes -DIRECTION Inout
68 set_io spw1_dout -pinname C16 -fixed yes -DIRECTION Inout
69 set_io spw1_sout -pinname C4 -fixed yes -DIRECTION Inout
70
71 set_io spw2_en -pinname G3 -fixed yes -DIRECTION Inout
72 set_io spw2_din -pinname E6 -fixed yes -DIRECTION Inout
73 set_io spw2_sin -pinname C15 -fixed yes -DIRECTION Inout
74 set_io spw2_dout -pinname B7 -fixed yes -DIRECTION Inout
75 set_io spw2_sout -pinname D7 -fixed yes -DIRECTION Inout
76
77 set_io TAG1 -pinname J12 -fixed yes -DIRECTION Inout
78 set_io TAG2 -pinname K12 -fixed yes -DIRECTION Inout
79 set_io TAG3 -pinname K13 -fixed yes -DIRECTION Inout
80 set_io TAG4 -pinname L16 -fixed yes -DIRECTION Inout
81 #set_io TAG5 -pinname L15 -fixed yes -DIRECTION Inout
82 #set_io TAG6 -pinname M16 -fixed yes -DIRECTION Inout
83 #set_io TAG7 -pinname J14 -fixed yes -DIRECTION Inout
84 set_io TAG8 -pinname K15 -fixed yes -DIRECTION Inout
85 #set_io TAG9 -pinname J17 -fixed yes -DIRECTION Inout
86
87 set_io bias_fail_sw -pinname A3 -fixed yes -DIRECTION Inout
88
89 set_io {ADC_OEB_bar_CH[0]} -pinname A10 -fixed yes -DIRECTION Inout
90 set_io {ADC_OEB_bar_CH[1]} -pinname B10 -fixed yes -DIRECTION Inout
91 set_io {ADC_OEB_bar_CH[2]} -pinname B12 -fixed yes -DIRECTION Inout
92 set_io {ADC_OEB_bar_CH[3]} -pinname A11 -fixed yes -DIRECTION Inout
93 set_io {ADC_OEB_bar_CH[4]} -pinname B13 -fixed yes -DIRECTION Inout
94 set_io {ADC_OEB_bar_CH[5]} -pinname C6 -fixed yes -DIRECTION Inout
95 set_io {ADC_OEB_bar_CH[6]} -pinname A13 -fixed yes -DIRECTION Inout
96 set_io {ADC_OEB_bar_CH[7]} -pinname A14 -fixed yes -DIRECTION Inout
97
98 set_io ADC_smpclk -pinname A15 -fixed yes -DIRECTION Inout
99
100 set_io HK_smpclk -pinname R11 -fixed yes -DIRECTION Inout
101 set_io ADC_OEB_bar_HK -pinname D6 -fixed yes -DIRECTION Inout
102 set_io {HK_SEL[0]} -pinname C3 -fixed yes -DIRECTION Inout
103 set_io {HK_SEL[1]} -pinname A2 -fixed yes -DIRECTION Inout
104
105 set_io {ADC_data[0]} -pinname G13 -fixed yes -DIRECTION Inout
106 set_io {ADC_data[1]} -pinname G16 -fixed yes -DIRECTION Inout
107 set_io {ADC_data[2]} -pinname F16 -fixed yes -DIRECTION Inout
108 set_io {ADC_data[3]} -pinname E15 -fixed yes -DIRECTION Inout
109 set_io {ADC_data[4]} -pinname F13 -fixed yes -DIRECTION Inout
110 set_io {ADC_data[5]} -pinname F15 -fixed yes -DIRECTION Inout
111 set_io {ADC_data[6]} -pinname D16 -fixed yes -DIRECTION Inout
112 set_io {ADC_data[7]} -pinname D15 -fixed yes -DIRECTION Inout
113 set_io {ADC_data[8]} -pinname B17 -fixed yes -DIRECTION Inout
114 set_io {ADC_data[9]} -pinname A17 -fixed yes -DIRECTION Inout
115 set_io {ADC_data[10]} -pinname A16 -fixed yes -DIRECTION Inout
116 set_io {ADC_data[11]} -pinname B16 -fixed yes -DIRECTION Inout
117 set_io {ADC_data[12]} -pinname C12 -fixed yes -DIRECTION Inout
118 set_io {ADC_data[13]} -pinname C13 -fixed yes -DIRECTION Inout
119
120 set_io DAC_SDO -pinname A4 -fixed yes -DIRECTION Inout
121 set_io DAC_SCK -pinname A5 -fixed yes -DIRECTION Inout
122 set_io DAC_SYNC -pinname B6 -fixed yes -DIRECTION Inout
123 set_io DAC_CAL_EN -pinname A6 -fixed yes -DIRECTION Inout
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1 ################################################################################
2 # SDC WRITER VERSION "3.1";
3 # DESIGN "LFR_EQM";
4 # Timing constraints scenario: "Primary";
5 # DATE "Fri Jul 24 14:50:40 2015";
6 # VENDOR "Actel";
7 # PROGRAM "Actel Designer Software Release v9.1 SP5";
8 # VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp.
9 ################################################################################
10
11
12 set sdc_version 1.7
13
14
15 ######## Clock Constraints ########
16
17 create_clock -name { clk50MHz } -period 20.000 -waveform { 0.000 10.000 } { clk50MHz }
18
19 create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz }
20
21 create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_pad_25/U0:Y }
22
23 create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q }
24
25 create_clock -name { spw_inputloop.1.spw_phy0/rxclki_1_0:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_1:Y }
26
27 create_clock -name { spw_inputloop.0.spw_phy0/rxclki_1_0:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_1:Y }
28
29
30
31 ######## Generated Clock Constraints ########
32
33
34
35 ######## Clock Source Latency Constraints #########
36
37
38
39 ######## Input Delay Constraints ########
40
41
42
43 ######## Output Delay Constraints ########
44 set_max_delay 10.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address }]
45
46 set_min_delay 10.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 }]
47
48
49
50 ######## Delay Constraints ########
51
52
53
54 ######## Delay Constraints ########
55
56
57
58 ######## Multicycle Constraints ########
59
60
61
62 ######## False Path Constraints ########
63
64
65
66 ######## Output load Constraints ########
67
68
69
70 ######## Disable Timing Constraints #########
71
72
73
74 ######## Clock Uncertainty Constraints #########
75
76
77
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1 ################################################################################
2 # SDC WRITER VERSION "3.1";
3 # DESIGN "LFR_EQM";
4 # Timing constraints scenario: "Primary";
5 # DATE "Tue May 19 15:46:14 2015";
6 # VENDOR "Actel";
7 # PROGRAM "Actel Designer Software Release v9.1 SP5";
8 # VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp.
9 ################################################################################
10
11
12 set sdc_version 1.7
13
14
15 ######## Clock Constraints ########
16
17 create_clock -name { clk50MHz } -period 20.000 -waveform { 0.000 10.000 } { clk50MHz }
18
19 create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz }
20
21 create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_25:Q }
22
23 create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q }
24
25 create_clock -name { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_RNO:Y }
26
27 create_clock -name { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_RNO:Y }
28
29
30
31 ######## Generated Clock Constraints ########
32
33
34
35 ######## Clock Source Latency Constraints #########
36
37
38
39 ######## Input Delay Constraints ########
40
41 set_input_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
42
43 set_input_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BUSY }]
44
45 set_input_delay -max 35.000 -clock { clk_25:Q } [get_ports { ADC_data[0] ADC_data[10] ADC_data[11] ADC_data[12] ADC_data[13] ADC_data[1] ADC_data[2] ADC_data[3] ADC_data[4] ADC_data[5] ADC_data[6] ADC_data[7] ADC_data[8] ADC_data[9] }]
46 set_input_delay -min 15.000 -clock { clk_25:Q } [get_ports { ADC_data[0] ADC_data[10] ADC_data[11] ADC_data[12] ADC_data[13] ADC_data[1] ADC_data[2] ADC_data[3] ADC_data[4] ADC_data[5] ADC_data[6] ADC_data[7] ADC_data[8] ADC_data[9] }]
47
48
49
50 ######## Output Delay Constraints ########
51
52 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
53
54 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { address[0] address[10] address[11] address[12] address[13] address[14] address[15] address[16] address[17] address[18] address[1] address[2] address[3] address[4] address[5] address[6] address[7] address[8] address[9] }]
55
56 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
57
58 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_G }]
59
60 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_MBE }]
61
62 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { ADC_OEB_bar_CH[0] ADC_OEB_bar_CH[1] ADC_OEB_bar_CH[2] ADC_OEB_bar_CH[3] ADC_OEB_bar_CH[4] ADC_OEB_bar_CH[5] ADC_OEB_bar_CH[6] ADC_OEB_bar_CH[7] ADC_OEB_bar_HK }]
63 set_max_delay 25.000 -from [get_clocks {clk_25:Q}] -to [get_ports { ADC_OEB_bar_CH[0] \
64 ADC_OEB_bar_CH[1] ADC_OEB_bar_CH[2] ADC_OEB_bar_CH[3] ADC_OEB_bar_CH[4] \
65 ADC_OEB_bar_CH[5] ADC_OEB_bar_CH[6] ADC_OEB_bar_CH[7] ADC_OEB_bar_HK }]
66 set_min_delay 8.000 -from [get_clocks {clk_25:Q}] -to [get_ports { ADC_OEB_bar_CH[0] \
67 ADC_OEB_bar_CH[1] ADC_OEB_bar_CH[2] ADC_OEB_bar_CH[3] ADC_OEB_bar_CH[4] \
68 ADC_OEB_bar_CH[5] ADC_OEB_bar_CH[6] ADC_OEB_bar_CH[7] ADC_OEB_bar_HK }]
69
70
71
72 ######## Delay Constraints ########
73
74 set_max_delay 30.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \
75 data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \
76 data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \
77 data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}]
78
79 set_max_delay 12.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
80
81 set_max_delay 12.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \
82 data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \
83 data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \
84 data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
85
86 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \
87 address[11] address[12] address[13] address[14] address[15] address[16] address[17] \
88 address[18] address[1] address[2] address[3] address[4] address[5] address[6] \
89 address[7] address[8] address[9] }]
90
91 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
92
93 set_max_delay 30.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }]
94
95 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }]
96
97 set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to \
98 [get_clocks {spw_inputloop.0.spw_phy0/rxclki_RNO:Y}]
99
100 set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to \
101 [get_clocks {spw_inputloop.1.spw_phy0/rxclki_RNO:Y}]
102
103
104
105 ######## Delay Constraints ########
106
107 set_min_delay 0.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \
108 data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \
109 data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \
110 data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}]
111
112 set_min_delay 0.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
113
114 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \
115 data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \
116 data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \
117 data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
118
119 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \
120 address[11] address[12] address[13] address[14] address[15] address[16] address[17] \
121 address[18] address[1] address[2] address[3] address[4] address[5] address[6] \
122 address[7] address[8] address[9] }]
123
124 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
125
126 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }]
127
128 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }]
129
130
131
132 ######## Multicycle Constraints ########
133
134
135
136 ######## False Path Constraints ########
137
138
139
140 ######## Output load Constraints ########
141
142
143
144 ######## Disable Timing Constraints #########
145
146
147
148 ######## Clock Uncertainty Constraints #########
149
150
151
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1 ################################################################################
2 # SDC WRITER VERSION "3.1";
3 # DESIGN "LFR_EQM";
4 # Timing constraints scenario: "Primary";
5 # DATE "Tue May 05 13:46:34 2015";
6 # VENDOR "Actel";
7 # PROGRAM "Actel Designer Software Release v9.1 SP5";
8 # VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp.
9 ################################################################################
10
11
12 set sdc_version 1.7
13
14
15 ######## Clock Constraints ########
16
17 create_clock -name { clk50MHz } -period 20.000 -waveform { 0.000 10.000 } { clk50MHz }
18
19 create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz }
20
21 create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_25:Q }
22
23 create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q }
24
25 create_clock -name { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_RNO:Y }
26
27 create_clock -name { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_RNO:Y }
28
29
30
31 ######## Generated Clock Constraints ########
32
33
34
35 ######## Clock Source Latency Constraints #########
36
37
38
39 ######## Input Delay Constraints ########
40
41 set_input_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
42
43 set_input_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BUSY }]
44
45 set_input_delay -max 20.000 -clock { clk_25:Q } [get_ports { ADC_data[0] ADC_data[10] ADC_data[11] ADC_data[12] ADC_data[13] ADC_data[1] ADC_data[2] ADC_data[3] ADC_data[4] ADC_data[5] ADC_data[6] ADC_data[7] ADC_data[8] ADC_data[9] }]
46
47
48
49 ######## Output Delay Constraints ########
50
51 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
52
53 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { address[0] address[10] address[11] address[12] address[13] address[14] address[15] address[16] address[17] address[18] address[1] address[2] address[3] address[4] address[5] address[6] address[7] address[8] address[9] }]
54
55 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
56
57 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_G }]
58
59 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_MBE }]
60
61 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { ADC_OEB_bar_CH[0] ADC_OEB_bar_CH[1] ADC_OEB_bar_CH[2] ADC_OEB_bar_CH[3] ADC_OEB_bar_CH[4] ADC_OEB_bar_CH[5] ADC_OEB_bar_CH[6] ADC_OEB_bar_CH[7] ADC_OEB_bar_HK }]
62 set_max_delay 35.000 -from [get_clocks {clk_25:Q}] -to [get_ports { ADC_OEB_bar_CH[0] \
63 ADC_OEB_bar_CH[1] ADC_OEB_bar_CH[2] ADC_OEB_bar_CH[3] ADC_OEB_bar_CH[4] \
64 ADC_OEB_bar_CH[5] ADC_OEB_bar_CH[6] ADC_OEB_bar_CH[7] ADC_OEB_bar_HK }]
65 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { ADC_OEB_bar_CH[0] \
66 ADC_OEB_bar_CH[1] ADC_OEB_bar_CH[2] ADC_OEB_bar_CH[3] ADC_OEB_bar_CH[4] \
67 ADC_OEB_bar_CH[5] ADC_OEB_bar_CH[6] ADC_OEB_bar_CH[7] ADC_OEB_bar_HK }]
68
69
70
71 ######## Delay Constraints ########
72
73 set_max_delay 30.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \
74 data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \
75 data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \
76 data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}]
77
78 set_max_delay 10.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
79
80 set_max_delay 10.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \
81 data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \
82 data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \
83 data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
84
85 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \
86 address[11] address[12] address[13] address[14] address[15] address[16] address[17] \
87 address[18] address[1] address[2] address[3] address[4] address[5] address[6] \
88 address[7] address[8] address[9] }]
89
90 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
91
92 set_max_delay 30.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }]
93
94 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }]
95
96 set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to \
97 [get_clocks {spw_inputloop.0.spw_phy0/rxclki_RNO:Y}]
98
99 set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to \
100 [get_clocks {spw_inputloop.1.spw_phy0/rxclki_RNO:Y}]
101
102
103
104 ######## Delay Constraints ########
105
106 set_min_delay 0.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \
107 data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \
108 data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \
109 data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}]
110
111 set_min_delay 0.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
112
113 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \
114 data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \
115 data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \
116 data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
117
118 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \
119 address[11] address[12] address[13] address[14] address[15] address[16] address[17] \
120 address[18] address[1] address[2] address[3] address[4] address[5] address[6] \
121 address[7] address[8] address[9] }]
122
123 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
124
125 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }]
126
127 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }]
128
129
130
131 ######## Multicycle Constraints ########
132
133
134
135 ######## False Path Constraints ########
136
137 set_false_path -from [get_pins { \
138 USE_ADCDRIVER_true.top_ad_conv_RHF1401_withFilter_1/cnv_s_reg:CLK }] -to [get_pins { \
139 USE_ADCDRIVER_true.top_ad_conv_RHF1401_withFilter_1/SYNC_FF_cnv/sync_loop.1.A_temp[1]:D \
140 }]
141 # SYNC PATH of ADC_CNV signal from CLK_domain_24 to CLK_domain_25
142
143
144
145 ######## Output load Constraints ########
146
147
148
149 ######## Disable Timing Constraints #########
150
151
152
153 ######## Clock Uncertainty Constraints #########
154
155
156
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1 ################################################################################
2 # SDC WRITER VERSION "3.1";
3 # DESIGN "LFR_EQM";
4 # Timing constraints scenario: "Primary";
5 # DATE "Fri Apr 24 16:02:16 2015";
6 # VENDOR "Actel";
7 # PROGRAM "Actel Designer Software Release v9.1 SP5";
8 # VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp.
9 ################################################################################
10
11
12 set sdc_version 1.7
13
14
15 ######## Clock Constraints ########
16
17 create_clock -name { clk50MHz } -period 20.000 -waveform { 0.000 10.000 } { clk50MHz }
18
19 create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz }
20
21 create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_25:Q }
22
23 create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q }
24
25 create_clock -name { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_RNO:Y }
26
27 create_clock -name { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_RNO:Y }
28
29
30
31 ######## Generated Clock Constraints ########
32
33
34
35 ######## Clock Source Latency Constraints #########
36
37
38
39 ######## Input Delay Constraints ########
40
41 set_input_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
42 set_max_delay 30.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \
43 data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \
44 data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \
45 data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}]
46 set_min_delay 0.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \
47 data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \
48 data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \
49 data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}]
50
51 set_input_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BUSY }]
52 set_max_delay 10.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
53 set_min_delay 0.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
54
55
56
57 ######## Output Delay Constraints ########
58
59 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
60 set_max_delay 10.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \
61 data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \
62 data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \
63 data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
64 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \
65 data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \
66 data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \
67 data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
68
69 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { address[0] address[10] address[11] address[12] address[13] address[14] address[15] address[16] address[17] address[18] address[1] address[2] address[3] address[4] address[5] address[6] address[7] address[8] address[9] }]
70 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \
71 address[11] address[12] address[13] address[14] address[15] address[16] address[17] \
72 address[18] address[1] address[2] address[3] address[4] address[5] address[6] \
73 address[7] address[8] address[9] }]
74 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \
75 address[11] address[12] address[13] address[14] address[15] address[16] address[17] \
76 address[18] address[1] address[2] address[3] address[4] address[5] address[6] \
77 address[7] address[8] address[9] }]
78
79 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
80 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
81 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
82
83 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_G }]
84 set_max_delay 30.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }]
85 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }]
86
87 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_MBE }]
88 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }]
89 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }]
90
91
92
93 ######## Delay Constraints ########
94
95 set_max_delay 4.000 -from [get_ports { clk50MHz ADC_data spw2_sin spw2_din spw1_sin spw1_din \
96 nSRAM_BUSY data TAG2 TAG1 reset clk49_152MHz }] -to [get_clocks \
97 {spw_inputloop.0.spw_phy0/rxclki_RNO:Y}]
98
99 set_max_delay 4.000 -from [get_ports { clk50MHz ADC_data spw2_sin spw2_din spw1_sin spw1_din \
100 nSRAM_BUSY data TAG2 TAG1 reset clk49_152MHz }] -to [get_clocks \
101 {spw_inputloop.1.spw_phy0/rxclki_RNO:Y}]
102
103
104
105 ######## Delay Constraints ########
106
107
108
109 ######## Multicycle Constraints ########
110
111
112
113 ######## False Path Constraints ########
114
115
116
117 ######## Output load Constraints ########
118
119
120
121 ######## Disable Timing Constraints #########
122
123
124
125 ######## Clock Uncertainty Constraints #########
126
127
128
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1 ################################################################################
2 # SDC WRITER VERSION "3.1";
3 # DESIGN "LFR_EQM";
4 # Timing constraints scenario: "Primary";
5 # DATE "Fri Apr 24 16:02:16 2015";
6 # VENDOR "Actel";
7 # PROGRAM "Actel Designer Software Release v9.1 SP5";
8 # VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp.
9 ################################################################################
10
11
12 set sdc_version 1.7
13
14
15 ######## Clock Constraints ########
16
17 create_clock -name { clk50MHz } -period 20.000 -waveform { 0.000 10.000 } { clk50MHz }
18
19 create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz }
20
21 create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_25:Q }
22
23 create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q }
24
25
26 create_clock -name { spw_inputloop.0.spw_phy0/rxclki_1_0:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_1_0:Y }
27
28 create_clock -name { spw_inputloop.1.spw_phy0/rxclki_1_0:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_1_0:Y }
29
30
31
32 ######## Generated Clock Constraints ########
33
34
35
36 ######## Clock Source Latency Constraints #########
37
38
39
40 ######## Input Delay Constraints ########
41
42 set_input_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
43 set_max_delay 30.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \
44 data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \
45 data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \
46 data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}]
47 set_min_delay 0.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \
48 data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \
49 data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \
50 data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}]
51
52 set_input_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BUSY }]
53 set_max_delay 10.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
54 set_min_delay 0.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
55
56
57
58 ######## Output Delay Constraints ########
59
60 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
61 set_max_delay 10.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \
62 data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \
63 data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \
64 data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
65 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \
66 data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \
67 data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \
68 data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
69
70 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { address[0] address[10] address[11] address[12] address[13] address[14] address[15] address[16] address[17] address[18] address[1] address[2] address[3] address[4] address[5] address[6] address[7] address[8] address[9] }]
71 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \
72 address[11] address[12] address[13] address[14] address[15] address[16] address[17] \
73 address[18] address[1] address[2] address[3] address[4] address[5] address[6] \
74 address[7] address[8] address[9] }]
75 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \
76 address[11] address[12] address[13] address[14] address[15] address[16] address[17] \
77 address[18] address[1] address[2] address[3] address[4] address[5] address[6] \
78 address[7] address[8] address[9] }]
79
80 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
81 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
82 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
83
84 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_G }]
85 set_max_delay 30.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }]
86 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }]
87
88 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_MBE }]
89 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }]
90 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }]
91
92
93
94 ######## Delay Constraints ########
95
96 set_max_delay 4.000 -from [get_ports { clk50MHz ADC_data spw2_sin spw2_din spw1_sin spw1_din \
97 nSRAM_BUSY data TAG2 TAG1 reset clk49_152MHz }] -to [get_clocks \
98 {spw_inputloop.0.spw_phy0/rxclki_1_0:Y}]
99
100 set_max_delay 4.000 -from [get_ports { clk50MHz ADC_data spw2_sin spw2_din spw1_sin spw1_din \
101 nSRAM_BUSY data TAG2 TAG1 reset clk49_152MHz }] -to [get_clocks \
102 {spw_inputloop.1.spw_phy0/rxclki_1_0:YY}]
103
104
105
106 ######## Delay Constraints ########
107
108
109
110 ######## Multicycle Constraints ########
111
112
113
114 ######## False Path Constraints ########
115
116
117
118 ######## Output load Constraints ########
119
120
121
122 ######## Disable Timing Constraints #########
123
124
125
126 ######## Clock Uncertainty Constraints #########
127
128
129
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1 ################################################################################
2 # SDC WRITER VERSION "3.1";
3 # DESIGN "LFR_EQM";
4 # Timing constraints scenario: "Primary";
5 # DATE "Fri Apr 24 16:02:16 2015";
6 # VENDOR "Actel";
7 # PROGRAM "Actel Designer Software Release v9.1 SP5";
8 # VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp.
9 ################################################################################
10
11
12 set sdc_version 1.7
13
14
15 ######## Clock Constraints ########
16
17 create_clock -name { clk50MHz } -period 20.000 -waveform { 0.000 10.000 } { clk50MHz }
18
19 ##create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz }
20
21 create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_25:Q }
22
23 ##create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q }
24
25 create_clock -name { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_RNO:Y }
26
27 create_clock -name { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_RNO:Y }
28
29
30
31 ######## Generated Clock Constraints ########
32
33
34
35 ######## Clock Source Latency Constraints #########
36
37
38
39 ######## Input Delay Constraints ########
40
41 set_input_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
42 set_max_delay 30.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \
43 data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \
44 data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \
45 data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}]
46 set_min_delay 0.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \
47 data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \
48 data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \
49 data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}]
50
51 set_input_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BUSY }]
52 set_max_delay 10.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
53 set_min_delay 0.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
54
55
56
57 ######## Output Delay Constraints ########
58
59 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
60 set_max_delay 10.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \
61 data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \
62 data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \
63 data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
64 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \
65 data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \
66 data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \
67 data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
68
69 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { address[0] address[10] address[11] address[12] address[13] address[14] address[15] address[16] address[17] address[18] address[1] address[2] address[3] address[4] address[5] address[6] address[7] address[8] address[9] }]
70 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \
71 address[11] address[12] address[13] address[14] address[15] address[16] address[17] \
72 address[18] address[1] address[2] address[3] address[4] address[5] address[6] \
73 address[7] address[8] address[9] }]
74 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \
75 address[11] address[12] address[13] address[14] address[15] address[16] address[17] \
76 address[18] address[1] address[2] address[3] address[4] address[5] address[6] \
77 address[7] address[8] address[9] }]
78
79 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
80 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
81 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
82
83 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_G }]
84 set_max_delay 30.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }]
85 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }]
86
87 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_MBE }]
88 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }]
89 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }]
90
91
92
93 ######## Delay Constraints ########
94
95 set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to [get_clocks {spw_inputloop.0.spw_phy0/rxclki_RNO:Y}]
96
97 set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to [get_clocks {spw_inputloop.1.spw_phy0/rxclki_RNO:Y}]
98
99
100
101 ######## Delay Constraints ########
102
103
104
105 ######## Multicycle Constraints ########
106
107
108
109 ######## False Path Constraints ########
110
111
112
113 ######## Output load Constraints ########
114
115
116
117 ######## Disable Timing Constraints #########
118
119
120
121 ######## Clock Uncertainty Constraints #########
122
123
124
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1 ################################################################################
2 # SDC WRITER VERSION "3.1";
3 # DESIGN "LFR_EQM";
4 # Timing constraints scenario: "Primary";
5 # DATE "Wed May 13 13:09:37 2015";
6 # VENDOR "Actel";
7 # PROGRAM "Actel Designer Software Release v9.1 SP5";
8 # VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp.
9 ################################################################################
10
11
12 set sdc_version 1.7
13
14
15 ######## Clock Constraints ########
16
17 create_clock -name { clk50MHz } -period 20.000 -waveform { 0.000 10.000 } { clk50MHz }
18
19 create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_25:Q }
20
21 create_clock -name { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_RNO:Y }
22
23 create_clock -name { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_RNO:Y }
24
25
26
27 ######## Generated Clock Constraints ########
28
29
30
31 ######## Clock Source Latency Constraints #########
32
33
34
35 ######## Input Delay Constraints ########
36
37 set_input_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
38
39 set_input_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BUSY }]
40
41 set_input_delay -max 0.000 -clock { clk_25:Q } [get_ports { ADC_data[0] ADC_data[10] ADC_data[11] ADC_data[12] ADC_data[13] ADC_data[1] ADC_data[2] ADC_data[3] ADC_data[4] ADC_data[5] ADC_data[6] ADC_data[7] ADC_data[8] ADC_data[9] }]
42 set_input_delay -min 0.000 -clock { clk_25:Q } [get_ports { ADC_data[0] ADC_data[10] ADC_data[11] ADC_data[12] ADC_data[13] ADC_data[1] ADC_data[2] ADC_data[3] ADC_data[4] ADC_data[5] ADC_data[6] ADC_data[7] ADC_data[8] ADC_data[9] }]
43
44
45
46 ######## Output Delay Constraints ########
47
48 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
49
50 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { address[0] address[10] address[11] address[12] address[13] address[14] address[15] address[16] address[17] address[18] address[1] address[2] address[3] address[4] address[5] address[6] address[7] address[8] address[9] }]
51
52 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
53
54 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_G }]
55
56 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_MBE }]
57
58 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { ADC_OEB_bar_CH[0] ADC_OEB_bar_CH[1] ADC_OEB_bar_CH[2] ADC_OEB_bar_CH[3] ADC_OEB_bar_CH[4] ADC_OEB_bar_CH[5] ADC_OEB_bar_CH[6] ADC_OEB_bar_CH[7] ADC_OEB_bar_HK }]
59
60
61
62 ######## Delay Constraints ########
63
64 set_max_delay 30.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \
65 data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \
66 data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \
67 data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}]
68
69 set_max_delay 10.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
70
71 set_max_delay 10.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \
72 data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \
73 data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \
74 data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
75
76 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \
77 address[11] address[12] address[13] address[14] address[15] address[16] address[17] \
78 address[18] address[1] address[2] address[3] address[4] address[5] address[6] \
79 address[7] address[8] address[9] }]
80
81 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
82
83 set_max_delay 30.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }]
84
85 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }]
86
87 set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to \
88 [get_clocks {spw_inputloop.0.spw_phy0/rxclki_RNO:Y}]
89
90 set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to \
91 [get_clocks {spw_inputloop.1.spw_phy0/rxclki_RNO:Y}]
92
93 set_max_delay 30.000 -from [get_ports { ADC_data[0] ADC_data[10] ADC_data[11] ADC_data[12] \
94 ADC_data[13] ADC_data[1] ADC_data[2] ADC_data[3] ADC_data[4] ADC_data[5] ADC_data[6] \
95 ADC_data[7] ADC_data[8] ADC_data[9] }] -to [get_clocks {clk_25:Q}]
96
97 set_max_delay 15.000 -from [get_clocks {clk_25:Q}] -to [get_ports { ADC_OEB_bar_CH[0] \
98 ADC_OEB_bar_CH[1] ADC_OEB_bar_CH[2] ADC_OEB_bar_CH[3] ADC_OEB_bar_CH[4] \
99 ADC_OEB_bar_CH[5] ADC_OEB_bar_CH[6] ADC_OEB_bar_CH[7] ADC_OEB_bar_HK }]
100
101
102
103 ######## Delay Constraints ########
104
105 set_min_delay 0.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \
106 data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \
107 data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \
108 data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}]
109
110 set_min_delay 0.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
111
112 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \
113 data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \
114 data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \
115 data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
116
117 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \
118 address[11] address[12] address[13] address[14] address[15] address[16] address[17] \
119 address[18] address[1] address[2] address[3] address[4] address[5] address[6] \
120 address[7] address[8] address[9] }]
121
122 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
123
124 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }]
125
126 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }]
127
128 set_min_delay 0.000 -from [get_ports { ADC_data[0] ADC_data[10] ADC_data[11] ADC_data[12] \
129 ADC_data[13] ADC_data[1] ADC_data[2] ADC_data[3] ADC_data[4] ADC_data[5] ADC_data[6] \
130 ADC_data[7] ADC_data[8] ADC_data[9] }] -to [get_clocks {clk_25:Q}]
131
132 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { ADC_OEB_bar_CH[0] \
133 ADC_OEB_bar_CH[1] ADC_OEB_bar_CH[2] ADC_OEB_bar_CH[3] ADC_OEB_bar_CH[4] \
134 ADC_OEB_bar_CH[5] ADC_OEB_bar_CH[6] ADC_OEB_bar_CH[7] ADC_OEB_bar_HK }]
135
136
137
138 ######## Multicycle Constraints ########
139
140
141
142 ######## False Path Constraints ########
143
144
145
146 ######## Output load Constraints ########
147
148
149
150 ######## Disable Timing Constraints #########
151
152
153
154 ######## Clock Uncertainty Constraints #########
155
156
157
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1 # Synplicity, Inc. constraint file
2 # /home/jiri/ibm/vhdl/grlib/boards/actel-coremp7-1000/default.sdc
3 # Written on Wed Aug 1 19:29:24 2007
4 # by Synplify Pro, Synplify Pro 8.8.0.4 Scope Editor
5
6 #
7 # Collections
8 #
9
10 #
11 # Clocks
12 #
13
14 define_clock -name {clk50MHz} -freq 50 -clockgroup default_clkgroup_50 -route 5
15 define_clock -name {clk49_152MHz} -freq 49.152 -clockgroup default_clkgroup_49 -route 5
16
17 #
18 # Clock to Clock
19 #
20
21 #
22 # Inputs/Outputs
23 #
24
25
26 #
27 # Registers
28 #
29
30 #
31 # Multicycle Path
32 #
33
34 #
35 # False Path
36 #
37
38 set_false_path -from reset
39
40 #
41 # Path Delay
42 #
43
44 #
45 # Attributes
46 #
47
48 define_global_attribute syn_useioff {1}
49 define_global_attribute -disable syn_netlist_hierarchy {0}
50
51 #
52 # I/O standards
53 #
54
55 #
56 # Compile Points
57 #
58
59 #
60 # Other Constraints
61 #
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1 PACKAGE=CQFP352
2 SPEED=Std
3 SYNFREQ=50
4
5 TECHNOLOGY=Axcelerator
6
7 DESIGNER_PACKAGE=CQFP
8 DESIGNER_PINS=352
9 DESIGNER_VOLTAGE=COM
10 DESIGNER_TEMP=COM
11
12 #ifeq ("$(FPGA_RTAX4000)","S")
13 # LIBERO_DIE=70800rts
14 # PART=RTAX4000S
15 # LIBERO_PACKAGE=cqfp$(DESIGNER_PINS)r
16 #endif
17
18 #ifeq ("$(FPGA_RTAX4000)","D")
19 LIBERO_DIE=70800d
20 PART=RTAX4000D
21 LIBERO_PACKAGE=cq$(DESIGNER_PINS)
22 #endif
23
24 MANUFACTURER=Actel
25 MGCPART=$(PART)
26 MGCTECHNOLOGY=Axcelerator
27 MGCPACKAGE= {$(DESIGNER_PINS) $(DESIGNER_PACKAGE)}
28
29 ## RTAX4000S OPTIONS
30 #LIBERO_DIE=70800rts
31 #PART=RTAX4000S
32
33 ## RTAX4000D OPTIONS
34 #LIBERO_DIE=70800d
35 #PART=RTAX4000D
36
37 # RTAX4000D
38 #LIBERO_PACKAGE=cq$(DESIGNER_PINS)
39
40 # RTAX4000S
41 #LIBERO_PACKAGE=cqfp$(DESIGNER_PINS)r
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1 {
2 "cells": [
3 {
4 "cell_type": "code",
5 "execution_count": null,
6 "metadata": {
7 "collapsed": false
8 },
9 "outputs": [],
10 "source": [
11 "#%matplotlib qt\n",
12 "%matplotlib inline\n",
13 "import matplotlib.pyplot as plt\n",
14 "plt.rcParams[\"figure.figsize\"] = [12,12]\n",
15 "import numpy as np\n",
16 "import pandas as pds"
17 ]
18 },
19 {
20 "cell_type": "code",
21 "execution_count": null,
22 "metadata": {
23 "collapsed": false
24 },
25 "outputs": [],
26 "source": [
27 "def try_plot(df,ax,left,right):\n",
28 " try:\n",
29 " df[(df.index >= left) & (df.index <= right)].plot(ax=ax,subplots=True,legend=False)\n",
30 " except:\n",
31 " pass\n",
32 " \n",
33 "def make_plots(path=\"./simulation\",left=50e-3,right=100e-3):\n",
34 " inputSig = pds.read_csv(path+\"/log_input.txt\",index_col=0,delim_whitespace=True,header=None,names=[\"TSTAMP\",\"BIAS1\",\"BIAS2\",\"BIAS3\",\"BIAS4\",\"BIAS5\",\"B1\",\"B2\",\"B3\"])\n",
35 " fXSig=[]\n",
36 " G=[0.89,0.87,0.89]\n",
37 " [fXSig.append(pds.read_csv(\n",
38 " path+\"./log_output_f{0}.txt\".format(F),index_col=0,delim_whitespace=True,header=None,\n",
39 " names=[\"TSTAMP\",\"BIAS1\",\"BIAS4\",\"BIAS5\",\"B1\",\"B2\",\"B3\"])) for F in range(3) ]\n",
40 " inputSig.index*=5e-9\n",
41 " for F in range(3):\n",
42 " if len(fXSig[F].index):\n",
43 " fXSig[F].index*=5e-9\n",
44 " fXSig[F]/=G[F]\n",
45 " axes=inputSig[(inputSig.index >= left) & (inputSig.index <= right)].filter([\"BIAS1\",\"BIAS4\",\"BIAS5\",\"B1\",\"B2\",\"B3\"]).plot(subplots=True,layout=(3,2)) \n",
46 " [ try_plot(df,axes,left,right) for df in fXSig ]\n",
47 " "
48 ]
49 },
50 {
51 "cell_type": "code",
52 "execution_count": null,
53 "metadata": {
54 "collapsed": false
55 },
56 "outputs": [],
57 "source": [
58 "make_plots()"
59 ]
60 }
61 ],
62 "metadata": {
63 "kernelspec": {
64 "display_name": "Python 3",
65 "language": "python",
66 "name": "python3"
67 },
68 "language_info": {
69 "codemirror_mode": {
70 "name": "ipython",
71 "version": 3
72 },
73 "file_extension": ".py",
74 "mimetype": "text/x-python",
75 "name": "python",
76 "nbconvert_exporter": "python",
77 "pygments_lexer": "ipython3",
78 "version": "3.5.2"
79 }
80 },
81 "nbformat": 4,
82 "nbformat_minor": 1
83 }
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1 {
2 "cells": [
3 {
4 "cell_type": "code",
5 "execution_count": null,
6 "metadata": {
7 "collapsed": false
8 },
9 "outputs": [],
10 "source": [
11 "import random\n",
12 "import time\n",
13 "#%matplotlib inline\n",
14 "import matplotlib.pyplot as plt\n",
15 "import numpy as np\n",
16 "import pandas as pds\n",
17 "import datetime as dt"
18 ]
19 },
20 {
21 "cell_type": "code",
22 "execution_count": null,
23 "metadata": {
24 "collapsed": true
25 },
26 "outputs": [],
27 "source": [
28 "DOFILE=\"run.do.in\"\n",
29 "RAM1={\n",
30 "\"instance\":\"testbench/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/IIR_CEL_CTRLR_v2_DATAFLOW_1/RAM_CTRLR_v2_1/memRAM/SRAM/axc/x0/a8to12/agen(0)/u0/u0/MEMORYFILE\",\n",
31 "\"abits\":8,\n",
32 "\"dbits\":12,\n",
33 "\"name\":\"RAM1.txt\"\n",
34 "}\n",
35 "RAM2={\n",
36 "\"instance\":\"testbench/lpp_lfr_filter_1/IIR_CEL_f0_to_f1/IIR_CEL_CTRLR_v2_DATAFLOW_1/RAM_CTRLR_v2_1/memRAM/SRAM/axc/x0/a8to12/agen(0)/u0/u0/MEMORYFILE\",\n",
37 "\"abits\":8,\n",
38 "\"dbits\":12,\n",
39 "\"name\":\"RAM2.txt\"\n",
40 "}\n",
41 "RAM3={\n",
42 "\"instance\":\"testbench/lpp_lfr_filter_1/cic_lfr_1/memRAM/SRAM/axc/x0/a8to12/agen(0)/u0/u0/MEMORYFILE\",\n",
43 "\"abits\":9,\n",
44 "\"dbits\":10,\n",
45 "\"name\":\"RAM3.txt\"\n",
46 "}\n",
47 "RAM4={\n",
48 "\"instance\":\"testbench/lpp_lfr_filter_1/cic_lfr_1/memRAM/SRAM/axc/x0/a8to12/agen(1)/u0/u0/MEMORYFILE\",\n",
49 "\"abits\":9,\n",
50 "\"dbits\":10,\n",
51 "\"name\":\"RAM4.txt\"\n",
52 "}\n",
53 "RAM5={\n",
54 "\"instance\":\"testbench/lpp_lfr_filter_1/YES_IIR_FILTER_f2_f3/IIR_CEL_CTRLR_v3_1/RAM_CTRLR_v2_1/memRAM/SRAM/axc/x0/a8to12/agen(0)/u0/u0/MEMORYFILE\",\n",
55 "\"abits\":8,\n",
56 "\"dbits\":12,\n",
57 "\"name\":\"RAM5.txt\"\n",
58 "}\n",
59 "RAM6={\n",
60 "\"instance\":\"testbench/lpp_lfr_filter_1/YES_IIR_FILTER_f2_f3/IIR_CEL_CTRLR_v3_1/RAM_CTRLR_v2_2/memRAM/SRAM/axc/x0/a8to12/agen(0)/u0/u0/MEMORYFILE\",\n",
61 "\"abits\":8,\n",
62 "\"dbits\":12,\n",
63 "\"name\":\"RAM6.txt\"\n",
64 "}\n",
65 "\n",
66 "RAMS=[RAM1,RAM2,RAM3,RAM4,RAM5,RAM6]"
67 ]
68 },
69 {
70 "cell_type": "code",
71 "execution_count": null,
72 "metadata": {
73 "collapsed": false
74 },
75 "outputs": [],
76 "source": [
77 "def mkram(length,width,gentype='rand',**kwargs):\n",
78 " return toBinStr(gen(length,width,gentype,**kwargs),width)\n",
79 "\n",
80 "def toBinStr(data,width):\n",
81 " return [format(val, 'b').zfill(width) for val in data]\n",
82 "\n",
83 "def gen(length,width,gentype='rand',**kwargs):\n",
84 " LUT={\n",
85 " \"rand\":gen_rand,\n",
86 " \"const\":gen_const\n",
87 " }\n",
88 " return LUT[gentype](length,width,**kwargs)\n",
89 "\n",
90 "def gen_rand(length,width,**kwargs):\n",
91 " random.seed(time.time())\n",
92 " mask=(2**width)-1\n",
93 " data=[]\n",
94 " for line in range(length):\n",
95 " data.append(int(2**32*random.random())&mask)\n",
96 " return data\n",
97 "\n",
98 "def gen_const(length,width, value):\n",
99 " mask=(2**width)-1\n",
100 " return [value&mask for i in range(length)]\n",
101 "\n",
102 "def save(data,file):\n",
103 " f = open(file,\"w\")\n",
104 " [f.write(line+'\\n') for line in data]\n",
105 " f.close()\n",
106 " \n",
107 "def start_Vsim(gentype='rand',**kwargs):\n",
108 " args=\"\"\n",
109 " for RAM in RAMS:\n",
110 " save(mkram(2**RAM[\"abits\"],RAM[\"dbits\"],gentype=gentype,**kwargs),\"simulation/\"+RAM[\"name\"])\n",
111 " args = args + \" -g\" + RAM[\"instance\"] + \"=\\\"\" + RAM[\"name\"] + \"\\\"\"\n",
112 " with open(\"run.do.in\",\"r\") as inFile, open(\"simulation/run.do\",\"w\") as outFile:\n",
113 " input = inFile.read()\n",
114 " outFile.write(input.replace(\"#VSIM_ARGS#\",args))\n",
115 " $(cd simulation)\n",
116 " vsim -do run.do > sim.log\n",
117 " folder=dt.datetime.today().strftime(\"%Y-%m-%d_%H-%M\")\n",
118 " mkdir @(folder)\n",
119 " for RAM in RAMS:\n",
120 " cp @(RAM[\"name\"]) @(folder+\"/\"+RAM[\"name\"])\n",
121 " cp log*.txt run.do sim.log @(folder) \n",
122 " $(cd ..)\n",
123 " \n"
124 ]
125 },
126 {
127 "cell_type": "code",
128 "execution_count": null,
129 "metadata": {
130 "collapsed": false
131 },
132 "outputs": [],
133 "source": []
134 },
135 {
136 "cell_type": "code",
137 "execution_count": null,
138 "metadata": {
139 "collapsed": false
140 },
141 "outputs": [],
142 "source": [
143 "df = pds.read_csv(\"./simulation/log_input.txt\",index_col=0,delim_whitespace=True,header=None,names=[\"TSTAMP\",\"BIAS1\",\"BIAS2\",\"BIAS3\",\"BIAS4\",\"BIAS5\",\"B1\",\"B2\",\"B3\"])\n",
144 "df2 = pds.read_csv(\"./simulation/log_output_f0.txt\",index_col=0,delim_whitespace=True,header=None,names=[\"TSTAMP\",\"BIAS1\",\"BIAS4\",\"BIAS5\",\"B1\",\"B2\",\"B3\"])\n",
145 "df3 = pds.read_csv(\"./simulation/log_output_f1.txt\",index_col=0,delim_whitespace=True,header=None,names=[\"TSTAMP\",\"BIAS1\",\"BIAS4\",\"BIAS5\",\"B1\",\"B2\",\"B3\"])\n",
146 "df4 = pds.read_csv(\"./simulation/log_output_f2.txt\",index_col=0,delim_whitespace=True,header=None,names=[\"TSTAMP\",\"BIAS1\",\"BIAS4\",\"BIAS5\",\"B1\",\"B2\",\"B3\"])\n",
147 "\n",
148 "df.index*=5e-9\n",
149 "if len(df2.index):\n",
150 " df2.index*=5e-9\n",
151 " df2/=0.89\n",
152 "if len(df3.index):\n",
153 " df3.index*=5e-9\n",
154 " df3/=0.87\n",
155 "if len(df4.index):\n",
156 " df4.index*=5e-9\n",
157 " df4/=0.89\n",
158 "\n",
159 "print(len(df))\n",
160 "df.filter([\"B1\"]).plot()\n",
161 "#plt.plot(df2)\n",
162 "plt.plot(df3.filter([\"B1\"]))\n",
163 "#plt.plot(df4)\n",
164 "plt.show()"
165 ]
166 },
167 {
168 "cell_type": "code",
169 "execution_count": null,
170 "metadata": {
171 "collapsed": false
172 },
173 "outputs": [],
174 "source": [
175 "cd .."
176 ]
177 },
178 {
179 "cell_type": "code",
180 "execution_count": null,
181 "metadata": {
182 "collapsed": false
183 },
184 "outputs": [],
185 "source": [
186 "mkram(2,32)\n",
187 "\n",
188 "mkram(20,32,gentype='const',value=55)\n",
189 "\n",
190 "save(mkram(10,32),\"RAM_FILE.txt\")"
191 ]
192 },
193 {
194 "cell_type": "code",
195 "execution_count": null,
196 "metadata": {
197 "collapsed": false,
198 "scrolled": false
199 },
200 "outputs": [],
201 "source": [
202 "for i in range(2):\n",
203 " start_Vsim(gentype='rand',value=0)"
204 ]
205 }
206 ],
207 "metadata": {
208 "kernelspec": {
209 "display_name": "Xonsh",
210 "language": "xonsh",
211 "name": "xonsh"
212 },
213 "language_info": {
214 "codemirror_mode": "shell",
215 "file_extension": ".xsh",
216 "mimetype": "text/x-sh",
217 "name": "xonsh",
218 "pygments_lexer": "xonsh"
219 }
220 },
221 "nbformat": 4,
222 "nbformat_minor": 1
223 }
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@@ -0,0 +1,74
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
23
24 LIBRARY ieee;
25 USE ieee.std_logic_1164.ALL;
26 use ieee.numeric_std.all;
27 USE IEEE.std_logic_signed.ALL;
28 USE IEEE.MATH_real.ALL;
29
30 ENTITY generator IS
31
32 GENERIC (
33 AMPLITUDE : INTEGER := 100;
34 NB_BITS : INTEGER := 16);
35
36 PORT (
37 clk : IN STD_LOGIC;
38 rstn : IN STD_LOGIC;
39 run : IN STD_LOGIC;
40
41 data_ack : IN STD_LOGIC;
42 offset : IN STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0);
43 data : OUT STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0)
44 );
45
46 END generator;
47
48 ARCHITECTURE beh OF generator IS
49
50 SIGNAL reg : STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0);
51 BEGIN -- beh
52
53
54 PROCESS (clk, rstn)
55 variable seed1, seed2: positive; -- seed values for random generator
56 variable rand: real; -- random real-number value in range 0 to 1.0
57 BEGIN -- PROCESS
58 uniform(seed1, seed2, rand);--more entropy by skipping values
59 IF rstn = '0' THEN -- asynchronous reset (active low)
60 reg <= (OTHERS => '0');
61 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
62 IF run = '0' THEN
63 reg <= (OTHERS => '0');
64 ELSE
65 IF data_ack = '1' THEN
66 reg <= std_logic_vector(to_signed(INTEGER( (REAL(AMPLITUDE) * rand) + REAL(to_integer(SIGNED(offset))) ),NB_BITS));
67 END IF;
68 END IF;
69 END IF;
70 END PROCESS;
71
72 data <= reg;
73
74 END beh;
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This diff has been collapsed as it changes many lines, (516 lines changed) Show them Hide them
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1 quietly set ACTELLIBNAME Axcelerator
2 quietly set PROJECT_DIR "C:/opt/VHDLIB/designs/Validation_IIR_LFR"
3
4 if {[file exists presynth/_info]} {
5 echo "INFO: Simulation library presynth already exists"
6 } else {
7 vlib presynth
8 }
9 vmap presynth presynth
10 vmap Axcelerator "C:/Microsemi/Libero_v9.2/Designer/lib/modelsim/precompiled/vhdl/Axcelerator"
11 if {[file exists grlib/_info]} {
12 echo "INFO: Simulation library grlib already exists"
13 } else {
14 vlib grlib
15 }
16 vmap grlib "grlib"
17 if {[file exists synplify/_info]} {
18 echo "INFO: Simulation library synplify already exists"
19 } else {
20 vlib synplify
21 }
22 vmap synplify "synplify"
23 if {[file exists techmap/_info]} {
24 echo "INFO: Simulation library techmap already exists"
25 } else {
26 vlib techmap
27 }
28 vmap techmap "techmap"
29 if {[file exists spw/_info]} {
30 echo "INFO: Simulation library spw already exists"
31 } else {
32 vlib spw
33 }
34 vmap spw "spw"
35 if {[file exists eth/_info]} {
36 echo "INFO: Simulation library eth already exists"
37 } else {
38 vlib eth
39 }
40 vmap eth "eth"
41 if {[file exists gaisler/_info]} {
42 echo "INFO: Simulation library gaisler already exists"
43 } else {
44 vlib gaisler
45 }
46 vmap gaisler "gaisler"
47 if {[file exists esa/_info]} {
48 echo "INFO: Simulation library esa already exists"
49 } else {
50 vlib esa
51 }
52 vmap esa "esa"
53 if {[file exists fmf/_info]} {
54 echo "INFO: Simulation library fmf already exists"
55 } else {
56 vlib fmf
57 }
58 vmap fmf "fmf"
59 if {[file exists spansion/_info]} {
60 echo "INFO: Simulation library spansion already exists"
61 } else {
62 vlib spansion
63 }
64 vmap spansion "spansion"
65 if {[file exists gsi/_info]} {
66 echo "INFO: Simulation library gsi already exists"
67 } else {
68 vlib gsi
69 }
70 vmap gsi "gsi"
71 if {[file exists iap/_info]} {
72 echo "INFO: Simulation library iap already exists"
73 } else {
74 vlib iap
75 }
76 vmap iap "iap"
77 if {[file exists lpp/_info]} {
78 echo "INFO: Simulation library lpp already exists"
79 } else {
80 vlib lpp
81 }
82 vmap lpp "lpp"
83 if {[file exists cypress/_info]} {
84 echo "INFO: Simulation library cypress already exists"
85 } else {
86 vlib cypress
87 }
88 vmap cypress "cypress"
89
90 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/stdlib/version.vhd"
91 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/stdlib/config_types.vhd"
92 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/stdlib/config.vhd"
93 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/stdlib/stdlib.vhd"
94 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/stdlib/stdio.vhd"
95 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/stdlib/testlib.vhd"
96 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/ftlib/mtie_ftlib.vhd"
97 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/util/util.vhd"
98 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/sparc/sparc.vhd"
99 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/sparc/sparc_disas.vhd"
100 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/sparc/cpu_disas.vhd"
101 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/modgen/multlib.vhd"
102 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/modgen/leaves.vhd"
103 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/amba/amba.vhd"
104 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/amba/devices.vhd"
105 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/amba/defmst.vhd"
106 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/amba/apbctrl.vhd"
107 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/amba/ahbctrl.vhd"
108 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/amba/dma2ahb_pkg.vhd"
109 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/amba/dma2ahb.vhd"
110 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/amba/ahbmst.vhd"
111 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/amba/ahbmon.vhd"
112 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/amba/apbmon.vhd"
113 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/amba/ambamon.vhd"
114 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/amba/dma2ahb_tp.vhd"
115 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/amba/amba_tp.vhd"
116 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/atf/at_pkg.vhd"
117 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/atf/at_ahb_mst_pkg.vhd"
118 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/atf/at_ahb_slv_pkg.vhd"
119 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/atf/at_util.vhd"
120 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/atf/at_ahb_mst.vhd"
121 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/atf/at_ahb_slv.vhd"
122 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/atf/at_ahbs.vhd"
123 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/atf/at_ahb_ctrl.vhd"
124 vcom -93 -explicit -work synplify "${PROJECT_DIR}/../../../GRLIB/lib/synplify/sim/synplify.vhd"
125 vcom -93 -explicit -work synplify "${PROJECT_DIR}/../../../GRLIB/lib/synplify/sim/synattr.vhd"
126 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/gencomp/gencomp.vhd"
127 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/gencomp/netcomp.vhd"
128 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/inferred/memory_inferred.vhd"
129 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/inferred/tap_inferred.vhd"
130 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/inferred/ddr_inferred.vhd"
131 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/inferred/mul_inferred.vhd"
132 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/inferred/ddr_phy_inferred.vhd"
133 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/inferred/ddrphy_datapath.vhd"
134 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/inferred/sim_pll.vhd"
135 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/inferred/lpddr2_phy_inferred.vhd"
136 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/axcelerator/axcomp.vhd"
137 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/axcelerator/memory_axcelerator.vhd"
138 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/axcelerator/buffer_axcelerator.vhd"
139 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/axcelerator/pads_axcelerator.vhd"
140 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/axcelerator/clkgen_axcelerator.vhd"
141 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/axcelerator/ddr_axcelerator.vhd"
142 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/axcelerator/mul_axcelerator.vhd"
143 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/axcelerator/grpci2_phy_rtax_bypass.vhd"
144 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/allclkgen.vhd"
145 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/allddr.vhd"
146 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/allmem.vhd"
147 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/allmul.vhd"
148 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/allpads.vhd"
149 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/alltap.vhd"
150 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/clkgen.vhd"
151 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/clkmux.vhd"
152 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/clkinv.vhd"
153 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/clkand.vhd"
154 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/ddr_ireg.vhd"
155 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/ddr_oreg.vhd"
156 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/ddrphy.vhd"
157 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/syncram.vhd"
158 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/syncram64.vhd"
159 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/syncram_2p.vhd"
160 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/syncram_dp.vhd"
161 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/syncfifo_2p.vhd"
162 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/regfile_3p.vhd"
163 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/tap.vhd"
164 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/techbuf.vhd"
165 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/nandtree.vhd"
166 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/clkpad.vhd"
167 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/clkpad_ds.vhd"
168 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/inpad.vhd"
169 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/inpad_ds.vhd"
170 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/iodpad.vhd"
171 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/iopad.vhd"
172 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/iopad_ds.vhd"
173 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/lvds_combo.vhd"
174 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/odpad.vhd"
175 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/outpad.vhd"
176 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/outpad_ds.vhd"
177 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/toutpad.vhd"
178 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/skew_outpad.vhd"
179 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/mul_61x61.vhd"
180 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/cpu_disas_net.vhd"
181 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/ringosc.vhd"
182 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/grpci2_phy_net.vhd"
183 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/system_monitor.vhd"
184 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/grgates.vhd"
185 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/inpad_ddr.vhd"
186 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/outpad_ddr.vhd"
187 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/iopad_ddr.vhd"
188 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/syncram128bw.vhd"
189 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/syncram256bw.vhd"
190 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/syncram128.vhd"
191 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/syncram156bw.vhd"
192 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/techmult.vhd"
193 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/spictrl_net.vhd"
194 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/syncrambw.vhd"
195 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/syncram_2pbw.vhd"
196 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/sdram_phy.vhd"
197 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/from.vhd"
198 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/syncreg.vhd"
199 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/serdes.vhd"
200 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/mtie_maps.vhd"
201 vcom -93 -explicit -work spw "${PROJECT_DIR}/../../../GRLIB/lib/spw/comp/spwcomp.vhd"
202 vcom -93 -explicit -work spw "${PROJECT_DIR}/../../../GRLIB/lib/spw/core/mtie_core.vhd"
203 vcom -93 -explicit -work spw "${PROJECT_DIR}/../../../GRLIB/lib/spw/wrapper/grspw_gen.vhd"
204 vcom -93 -explicit -work spw "${PROJECT_DIR}/../../../GRLIB/lib/spw/wrapper/grspw2_gen.vhd"
205 vcom -93 -explicit -work spw "${PROJECT_DIR}/../../../GRLIB/lib/spw/wrapper/grspw_codec_gen.vhd"
206 vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/comp/ethcomp.vhd"
207 vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/core/greth_pkg.vhd"
208 vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/core/eth_rstgen.vhd"
209 vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/core/eth_edcl_ahb_mst.vhd"
210 vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/core/eth_ahb_mst_gbit.vhd"
211 vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/core/eth_ahb_mst.vhd"
212 vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/core/greth_gbit_rx.vhd"
213 vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/core/greth_gbit_tx.vhd"
214 vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/core/greth_gbit_gtx.vhd"
215 vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/core/greth_tx.vhd"
216 vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/core/greth_rx.vhd"
217 vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/core/greth_gbitc.vhd"
218 vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/core/grethc.vhd"
219 vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/wrapper/greth_gen.vhd"
220 vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/wrapper/greth_gbit_gen.vhd"
221 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/arith/arith.vhd"
222 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/arith/mul32.vhd"
223 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/arith/div32.vhd"
224 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/memctrl/memctrl.vhd"
225 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/memctrl/sdctrl.vhd"
226 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/memctrl/sdctrl64.vhd"
227 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/memctrl/sdmctrl.vhd"
228 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/memctrl/srctrl.vhd"
229 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/memctrl/ssrctrl.vhd"
230 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/memctrl/ftsrctrlc.vhd"
231 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/memctrl/ftsrctrl.vhd"
232 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/memctrl/ftsdctrl.vhd"
233 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/memctrl/ftsrctrl8.vhd"
234 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/memctrl/ftsdmctrl.vhd"
235 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/memctrl/ftmctrl.vhd"
236 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/memctrl/ftsdctrl64.vhd"
237 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/grlfpu/mtie_grlfpu.vhd"
238 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/grlfpc/mtie_grlfpc.vhd"
239 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/srmmu/mmuconfig.vhd"
240 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/srmmu/mmuiface.vhd"
241 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/srmmu/libmmu.vhd"
242 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/srmmu/mmutlbcam.vhd"
243 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/srmmu/mmulrue.vhd"
244 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/srmmu/mmulru.vhd"
245 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/srmmu/mmutlb.vhd"
246 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/srmmu/mmutw.vhd"
247 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/srmmu/mmu.vhd"
248 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/leon3/leon3.vhd"
249 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/leon3/grfpushwx.vhd"
250 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/leon3v3/mtie_leon3v3.vhd"
251 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/irqmp/irqmp.vhd"
252 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/irqmp/irqmp2x.vhd"
253 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/irqmp/irqamp.vhd"
254 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/irqmp/irqamp2x.vhd"
255 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/l2cache/v2-pkg/l2cache.vhd"
256 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/misc.vhd"
257 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/rstgen.vhd"
258 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/gptimer.vhd"
259 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/ahbram.vhd"
260 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/ahbdpram.vhd"
261 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/ahbtrace_mmb.vhd"
262 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/ahbtrace_mb.vhd"
263 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/ahbtrace.vhd"
264 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/grgpio.vhd"
265 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/ftahbram.vhd"
266 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/ftahbram2.vhd"
267 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/ahbstat.vhd"
268 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/logan.vhd"
269 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/apbps2.vhd"
270 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/charrom_package.vhd"
271 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/charrom.vhd"
272 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/apbvga.vhd"
273 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/ahb2ahb.vhd"
274 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/ahbbridge.vhd"
275 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/svgactrl.vhd"
276 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/grfifo.vhd"
277 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/gradcdac.vhd"
278 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/grsysmon.vhd"
279 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/gracectrl.vhd"
280 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/grgpreg.vhd"
281 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/memscrub.vhd"
282 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/ahb_mst_iface.vhd"
283 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/grgprbank.vhd"
284 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/grclkgate.vhd"
285 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/grclkgate2x.vhd"
286 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/grtimer.vhd"
287 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/grpulse.vhd"
288 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/grversion.vhd"
289 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/ahbfrom.vhd"
290 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/ambatest/ahbtbp.vhd"
291 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/ambatest/ahbtbm.vhd"
292 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/net/net.vhd"
293 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/uart/uart.vhd"
294 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/uart/libdcom.vhd"
295 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/uart/apbuart.vhd"
296 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/uart/dcom.vhd"
297 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/uart/dcom_uart.vhd"
298 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/uart/ahbuart.vhd"
299 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/sim.vhd"
300 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/sram.vhd"
301 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/sramft.vhd"
302 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/sram16.vhd"
303 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/phy.vhd"
304 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/ahbrep.vhd"
305 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/delay_wire.vhd"
306 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/pwm_check.vhd"
307 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/ramback.vhd"
308 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/zbtssram.vhd"
309 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/slavecheck.vhd"
310 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/spwtrace.vhd"
311 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/spwtracev.vhd"
312 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/ddrram.vhd"
313 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/ddr2ram.vhd"
314 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/ddr3ram.vhd"
315 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/jtag/jtag.vhd"
316 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/jtag/libjtagcom.vhd"
317 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/jtag/jtagcom.vhd"
318 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/jtag/ahbjtag.vhd"
319 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/jtag/ahbjtag_bsd.vhd"
320 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/jtag/bscanctrl.vhd"
321 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/jtag/bscanregs.vhd"
322 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/jtag/bscanregsbd.vhd"
323 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/jtag/jtagcom2.vhd"
324 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/jtag/jtagtst.vhd"
325 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/spacewire/spacewire.vhd"
326 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/spacewire/grspw.vhd"
327 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/spacewire/grspw2.vhd"
328 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/spacewire/grspwm.vhd"
329 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/spacewire/grspw2_phy.vhd"
330 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/spacewire/grspw_codec_clockgate.vhd"
331 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/spacewire/grspw_phy.vhd"
332 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/gr1553b/gr1553b_pkg.vhd"
333 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/gr1553b/gr1553b_pads.vhd"
334 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/gr1553b/simtrans1553.vhd"
335 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/nand/nandpkg.vhd"
336 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/nand/nandfctrlx.vhd"
337 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/nand/nandfctrl.vhd"
338 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/clk2x/clk2x.vhd"
339 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/clk2x/qmod.vhd"
340 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/clk2x/qmod_prect.vhd"
341 vcom -93 -explicit -work esa "${PROJECT_DIR}/../../../GRLIB/lib/esa/memoryctrl/memoryctrl.vhd"
342 vcom -93 -explicit -work esa "${PROJECT_DIR}/../../../GRLIB/lib/esa/memoryctrl/mctrl.vhd"
343 vcom -93 -explicit -work fmf "${PROJECT_DIR}/../../../GRLIB/lib/fmf/utilities/conversions.vhd"
344 vcom -93 -explicit -work fmf "${PROJECT_DIR}/../../../GRLIB/lib/fmf/utilities/gen_utils.vhd"
345 vcom -93 -explicit -work fmf "${PROJECT_DIR}/../../../GRLIB/lib/fmf/flash/flash.vhd"
346 vcom -93 -explicit -work fmf "${PROJECT_DIR}/../../../GRLIB/lib/fmf/flash/s25fl064a.vhd"
347 vcom -93 -explicit -work fmf "${PROJECT_DIR}/../../../GRLIB/lib/fmf/flash/m25p80.vhd"
348 vcom -93 -explicit -work fmf "${PROJECT_DIR}/../../../GRLIB/lib/fmf/fifo/idt7202.vhd"
349 vcom -93 -explicit -work gsi "${PROJECT_DIR}/../../../GRLIB/lib/gsi/ssram/functions.vhd"
350 vcom -93 -explicit -work gsi "${PROJECT_DIR}/../../../GRLIB/lib/gsi/ssram/core_burst.vhd"
351 vcom -93 -explicit -work gsi "${PROJECT_DIR}/../../../GRLIB/lib/gsi/ssram/g880e18bt.vhd"
352 vcom -93 -explicit -work iap "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB_NONFREE/lib/iap/./apb_devices/apb_devices_list.vhd"
353 vcom -93 -explicit -work iap "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB_NONFREE/lib/iap/./apb_devices/apb_devices.vhd"
354 vcom -93 -explicit -work iap "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB_NONFREE/lib/iap/./memctrlr/memctrlr.vhd"
355 vcom -93 -explicit -work iap "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB_NONFREE/lib/iap/./memctrlr/srctrle-0ws.vhd"
356 vcom -93 -explicit -work iap "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB_NONFREE/lib/iap/./memctrlr/srctrle-1ws.vhd"
357 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/data_type_pkg.vhd"
358 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/general_purpose.vhd"
359 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/ADDRcntr.vhd"
360 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/ALU.vhd"
361 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/Adder.vhd"
362 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/Clk_Divider2.vhd"
363 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/Clk_divider.vhd"
364 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/MAC.vhd"
365 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/MAC_CONTROLER.vhd"
366 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/MAC_MUX.vhd"
367 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/MAC_MUX2.vhd"
368 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/MAC_REG.vhd"
369 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/MUX2.vhd"
370 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/MUXN.vhd"
371 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/Multiplier.vhd"
372 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/REG.vhd"
373 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/SYNC_FF.vhd"
374 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/Shifter.vhd"
375 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/TwoComplementer.vhd"
376 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/Clock_Divider.vhd"
377 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/lpp_front_to_level.vhd"
378 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/lpp_front_detection.vhd"
379 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/SYNC_VALID_BIT.vhd"
380 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/RR_Arbiter_4.vhd"
381 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/general_counter.vhd"
382 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/ramp_generator.vhd"
383 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_amba/apb_devices_list.vhd"
384 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_amba/lpp_amba.vhd"
385 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/chirp/chirp_pkg.vhd"
386 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/chirp/chirp.vhd"
387 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/iir_filter/iir_filter.vhd"
388 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/iir_filter/FILTERcfg.vhd"
389 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/iir_filter/RAM.vhd"
390 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/iir_filter/RAM_CEL.vhd"
391 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/iir_filter/RAM_CTRLR_v2.vhd"
392 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd"
393 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd"
394 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd"
395 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v3_DATAFLOW.vhd"
396 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v3.vhd"
397 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/cic/cic_pkg.vhd"
398 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/cic/cic.vhd"
399 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/cic/cic_integrator.vhd"
400 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/cic/cic_downsampler.vhd"
401 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/cic/cic_comb.vhd"
402 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/cic/cic_lfr.vhd"
403 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/cic/cic_lfr_control.vhd"
404 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/cic/cic_lfr_add_sub.vhd"
405 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/cic/cic_lfr_address_gen.vhd"
406 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/cic/cic_lfr_r2.vhd"
407 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/cic/cic_lfr_control_r2.vhd"
408 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/lpp_downsampling/Downsampling.vhd"
409 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/lpp_fft_rtax/fft_components.vhd"
410 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/lpp_fft_rtax/lpp_fft.vhd"
411 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/lpp_fft_rtax/actar.vhd"
412 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/lpp_fft_rtax/actram.vhd"
413 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/lpp_fft_rtax/fftDp.vhd"
414 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/lpp_fft_rtax/fftSm.vhd"
415 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/lpp_fft_rtax/primitives.vhd"
416 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/lpp_fft_rtax/twiddle.vhd"
417 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/lpp_fft_rtax/Driver_FFT.vhd"
418 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/lpp_fft_rtax/FFT.vhd"
419 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/lpp_fft_rtax/Linker_FFT.vhd"
420 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/window_function/window_function_pkg.vhd"
421 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/window_function/window_function.vhd"
422 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/window_function/WF_processing.vhd"
423 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/window_function/WF_rom.vhd"
424 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_memory/lpp_memory.vhd"
425 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_memory/lpp_FIFO.vhd"
426 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_memory/lpp_FIFO_4_Shared.vhd"
427 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_memory/lpp_FIFO_control.vhd"
428 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_memory/lpp_FIFO_4_Shared_headreg_latency_0.vhd"
429 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_memory/lpp_FIFO_4_Shared_headreg_latency_1.vhd"
430 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_memory/lppFIFOxN.vhd"
431 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_ad_Conv/lpp_ad_Conv.vhd"
432 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_ad_Conv/RHF1401.vhd"
433 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_ad_Conv/top_ad_conv_RHF1401.vhd"
434 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_ad_Conv/top_ad_conv_RHF1401_withFilter.vhd"
435 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_ad_Conv/TestModule_RHF1401.vhd"
436 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_ad_Conv/top_ad_conv_ADS7886_v2.vhd"
437 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_ad_Conv/ADS7886_drvr_v2.vhd"
438 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_ad_Conv/lpp_lfr_hk.vhd"
439 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_spectral_matrix/spectral_matrix_package.vhd"
440 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_spectral_matrix/MS_calculation.vhd"
441 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_spectral_matrix/MS_control.vhd"
442 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_spectral_matrix/spectral_matrix_switch_f0.vhd"
443 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_spectral_matrix/spectral_matrix_time_managment.vhd"
444 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_demux/DEMUX.vhd"
445 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_demux/lpp_demux.vhd"
446 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_Header/lpp_Header.vhd"
447 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_Header/HeaderBuilder.vhd"
448 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_matrix/lpp_matrix.vhd"
449 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_matrix/ALU_Driver.vhd"
450 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_matrix/ReUse_CTRLR.vhd"
451 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_matrix/Dispatch.vhd"
452 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_matrix/DriveInputs.vhd"
453 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_matrix/GetResult.vhd"
454 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_matrix/MatriceSpectrale.vhd"
455 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_matrix/Matrix.vhd"
456 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_matrix/SpectralMatrix.vhd"
457 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_matrix/TopSpecMatrix.vhd"
458 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_dma/lpp_dma_pkg.vhd"
459 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_dma/fifo_latency_correction.vhd"
460 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_dma/lpp_dma.vhd"
461 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_dma/lpp_dma_ip.vhd"
462 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_dma/lpp_dma_send_16word.vhd"
463 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_dma/lpp_dma_send_1word.vhd"
464 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_dma/lpp_dma_singleOrBurst.vhd"
465 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_dma/DMA_SubSystem.vhd"
466 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_dma/DMA_SubSystem_GestionBuffer.vhd"
467 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_dma/DMA_SubSystem_Arbiter.vhd"
468 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_dma/DMA_SubSystem_MUX.vhd"
469 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_dma/lpp_dma_SEND16B_FIFO2DMA.vhd"
470 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform_pkg.vhd"
471 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform.vhd"
472 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform_burst.vhd"
473 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform_fifo_withoutLatency.vhd"
474 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform_fifo_latencyCorrection.vhd"
475 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform_fifo.vhd"
476 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform_fifo_arbiter.vhd"
477 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform_fifo_ctrl.vhd"
478 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform_fifo_headreg.vhd"
479 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform_snapshot.vhd"
480 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform_snapshot_controler.vhd"
481 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform_genaddress.vhd"
482 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform_dma_genvalid.vhd"
483 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform_fifo_arbiter_reg.vhd"
484 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform_fsmdma.vhd"
485 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_top_lfr/lpp_top_lfr_pkg.vhd"
486 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_top_lfr/lpp_lfr_pkg.vhd"
487 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_top_lfr/lpp_lfr_apbreg_pkg.vhd"
488 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_top_lfr/lpp_lfr_filter_coeff.vhd"
489 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_top_lfr/lpp_lfr_filter.vhd"
490 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_top_lfr/lpp_lfr_apbreg_ms_pointer.vhd"
491 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd"
492 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_FFT.vhd"
493 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_top_lfr/lpp_lfr_ms.vhd"
494 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_reg_head.vhd"
495 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_top_lfr/lpp_lfr.vhd"
496 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_leon3_soc/lpp_leon3_soc_pkg.vhd"
497 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_leon3_soc/leon3_soc.vhd"
498 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_debug_lfr/lpp_debug_lfr_pkg.vhd"
499 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_debug_lfr/lpp_debug_dma_singleOrBurst.vhd"
500 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_file/reader_pkg.vhd"
501 vcom -93 -explicit -work cypress "${PROJECT_DIR}/../../../GRLIB/lib/cypress/ssram/components.vhd"
502 vcom -93 -explicit -work cypress "${PROJECT_DIR}/../../../GRLIB/lib/cypress/ssram/package_utility.vhd"
503 vcom -93 -explicit -work cypress "${PROJECT_DIR}/../../../GRLIB/lib/cypress/ssram/cy7c1354b.vhd"
504 vcom -93 -explicit -work cypress "${PROJECT_DIR}/../../../GRLIB/lib/cypress/ssram/cy7c1380d.vhd"
505 vcom -93 -explicit -work presynth "${PROJECT_DIR}/../../../GRLIB/lib/work/debug/debug.vhd"
506 vcom -93 -explicit -work presynth "${PROJECT_DIR}/../../../GRLIB/lib/work/debug/grtestmod.vhd"
507 vcom -93 -explicit -work presynth "${PROJECT_DIR}/../../../GRLIB/lib/work/debug/cpu_disas.vhd"
508 vcom -93 -explicit -work presynth "${PROJECT_DIR}/IIR_CEL_TEST.vhd"
509 vcom -93 -explicit -work presynth "${PROJECT_DIR}/tb.vhd"
510 vcom -93 -explicit -work presynth "${PROJECT_DIR}/IIR_CEL_TEST_v3.vhd"
511 vcom -93 -explicit -work presynth "${PROJECT_DIR}/generator.vhd"
512
513 vsim #VSIM_ARGS# -L Axcelerator -L presynth -L grlib -L synplify -L techmap -L spw -L eth -L gaisler -L esa -L fmf -L spansion -L gsi -L iap -L lpp -L cypress -t 1ps presynth.testbench
514 # The following lines are commented because no testbench is associated with the project
515 # do "wave.do"
516 run 2000ms
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@@ -1,41 +1,42
1 # use glob syntax.
1 # use glob syntax.
2 syntax: glob
2 syntax: glob
3
3
4 *.tex
4 *.tex
5 *.html
5 *.html
6 *log*
6 *log*
7 *.png
7 *.png
8 *.dot
8 *.dot
9 *.css
9 *.css
10 *.md5
10 *.md5
11 *.eps
11 *.eps
12 *.pdf
12 *.pdf
13 *.toc
13 *.toc
14 *.map
14 *.map
15 *.sty
15 *.sty
16 *.3
16 *.3
17 *.js
17 *.js
18 *.aux
18 *.aux
19 *.idx
19 *.idx
20 *doc*
20 *doc*
21 *Doc*
21 *Doc*
22 *vhdlsyn.txt
22 *vhdlsyn.txt
23 *dirs.txt
23 *dirs.txt
24 *.orig
24 *.orig
25 *.o
25 *.o
26 *.a
26 *.a
27 *.bin
27 *.bin
28 *~
28 *~
29 apb_devices_list.h
29 apb_devices_list.h
30 apb_devices_list.vhd
30 apb_devices_list.vhd
31 twiddle.vhd
31 twiddle.vhd
32 primitives.vhd
32 primitives.vhd
33 fftSm.vhd
33 fftSm.vhd
34 fftDp.vhd
34 fftDp.vhd
35 fft_components.vhd
35 fft_components.vhd
36 CoreFFT.vhd
36 CoreFFT.vhd
37 actram.vhd
37 actram.vhd
38 actar.vhd
38 actar.vhd
39 *.bak
39 *.bak
40 *.pdc.ce
40 *.pdc.ce
41 *.zip
41 *.zip
42 */.ipynb_checkpoints/*
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@@ -1,208 +1,208
1 -- Technology and synthesis options
1 -- Technology and synthesis options
2 constant CFG_FABTECH : integer := CONFIG_SYN_TECH;
2 constant CFG_FABTECH : integer := CONFIG_SYN_TECH;
3 constant CFG_MEMTECH : integer := CFG_RAM_TECH;
3 constant CFG_MEMTECH : integer := CFG_RAM_TECH;
4 constant CFG_PADTECH : integer := CFG_PAD_TECH;
4 constant CFG_PADTECH : integer := CFG_PAD_TECH;
5 constant CFG_NOASYNC : integer := CONFIG_SYN_NO_ASYNC;
5 constant CFG_NOASYNC : integer := CONFIG_SYN_NO_ASYNC;
6 constant CFG_SCAN : integer := CONFIG_SYN_SCAN;
6 constant CFG_SCAN : integer := CONFIG_SYN_SCAN;
7
7
8 -- Clock generator
8 -- Clock generator
9 constant CFG_CLKTECH : integer := CFG_CLK_TECH;
9 constant CFG_CLKTECH : integer := CFG_CLK_TECH;
10 constant CFG_CLKMUL : integer := CONFIG_CLK_MUL;
10 constant CFG_CLKMUL : integer := CONFIG_CLK_MUL;
11 constant CFG_CLKDIV : integer := CONFIG_CLK_DIV;
11 constant CFG_CLKDIV : integer := CONFIG_CLK_DIV;
12 constant CFG_OCLKDIV : integer := CONFIG_OCLK_DIV;
12 constant CFG_OCLKDIV : integer := CONFIG_OCLK_DIV;
13 constant CFG_PCIDLL : integer := CONFIG_PCI_CLKDLL;
13 constant CFG_PCIDLL : integer := CONFIG_PCI_CLKDLL;
14 constant CFG_PCISYSCLK: integer := CONFIG_PCI_SYSCLK;
14 constant CFG_PCISYSCLK: integer := CONFIG_PCI_SYSCLK;
15 constant CFG_CLK_NOFB : integer := CONFIG_CLK_NOFB;
15 constant CFG_CLK_NOFB : integer := CONFIG_CLK_NOFB;
16
16
17 -- LEON3 processor core
17 -- LEON3 processor core
18 constant CFG_LEON3 : integer := CONFIG_LEON3;
18 constant CFG_LEON3 : integer := CONFIG_LEON3;
19 constant CFG_NCPU : integer := CONFIG_PROC_NUM;
19 constant CFG_NCPU : integer := CONFIG_PROC_NUM;
20 constant CFG_NWIN : integer := CONFIG_IU_NWINDOWS;
20 constant CFG_NWIN : integer := CONFIG_IU_NWINDOWS;
21 constant CFG_V8 : integer := CFG_IU_V8;
21 constant CFG_V8 : integer := CFG_IU_V8;
22 constant CFG_MAC : integer := CONFIG_IU_MUL_MAC;
22 constant CFG_MAC : integer := CONFIG_IU_MUL_MAC;
23 constant CFG_SVT : integer := CONFIG_IU_SVT;
23 constant CFG_SVT : integer := CONFIG_IU_SVT;
24 constant CFG_RSTADDR : integer := 16#CONFIG_IU_RSTADDR#;
24 constant CFG_RSTADDR : integer := 16#CONFIG_IU_RSTADDR#;
25 constant CFG_LDDEL : integer := CONFIG_IU_LDELAY;
25 constant CFG_LDDEL : integer := CONFIG_IU_LDELAY;
26 constant CFG_NWP : integer := CONFIG_IU_WATCHPOINTS;
26 constant CFG_NWP : integer := CONFIG_IU_WATCHPOINTS;
27 constant CFG_PWD : integer := CONFIG_PWD*2;
27 constant CFG_PWD : integer := CONFIG_PWD*2;
28 constant CFG_FPU : integer := CONFIG_FPU + 16*CONFIG_FPU_NETLIST;
28 constant CFG_FPU : integer := CONFIG_FPU + 16*CONFIG_FPU_NETLIST;
29 constant CFG_GRFPUSH : integer := CONFIG_FPU_GRFPU_SHARED;
29 constant CFG_GRFPUSH : integer := CONFIG_FPU_GRFPU_SHARED;
30 constant CFG_ICEN : integer := CONFIG_ICACHE_ENABLE;
30 constant CFG_ICEN : integer := CONFIG_ICACHE_ENABLE;
31 constant CFG_ISETS : integer := CFG_IU_ISETS;
31 constant CFG_ISETS : integer := CFG_IU_ISETS;
32 constant CFG_ISETSZ : integer := CFG_ICACHE_SZ;
32 constant CFG_ISETSZ : integer := CFG_ICACHE_SZ;
33 constant CFG_ILINE : integer := CFG_ILINE_SZ;
33 constant CFG_ILINE : integer := CFG_ILINE_SZ;
34 constant CFG_IREPL : integer := CFG_ICACHE_ALGORND;
34 constant CFG_IREPL : integer := CFG_ICACHE_ALGORND;
35 constant CFG_ILOCK : integer := CONFIG_ICACHE_LOCK;
35 constant CFG_ILOCK : integer := CONFIG_ICACHE_LOCK;
36 constant CFG_ILRAMEN : integer := CONFIG_ICACHE_LRAM;
36 constant CFG_ILRAMEN : integer := CONFIG_ICACHE_LRAM;
37 constant CFG_ILRAMADDR: integer := 16#CONFIG_ICACHE_LRSTART#;
37 constant CFG_ILRAMADDR: integer := 16#CONFIG_ICACHE_LRSTART#;
38 constant CFG_ILRAMSZ : integer := CFG_ILRAM_SIZE;
38 constant CFG_ILRAMSZ : integer := CFG_ILRAM_SIZE;
39 constant CFG_DCEN : integer := CONFIG_DCACHE_ENABLE;
39 constant CFG_DCEN : integer := CONFIG_DCACHE_ENABLE;
40 constant CFG_DSETS : integer := CFG_IU_DSETS;
40 constant CFG_DSETS : integer := CFG_IU_DSETS;
41 constant CFG_DSETSZ : integer := CFG_DCACHE_SZ;
41 constant CFG_DSETSZ : integer := CFG_DCACHE_SZ;
42 constant CFG_DLINE : integer := CFG_DLINE_SZ;
42 constant CFG_DLINE : integer := CFG_DLINE_SZ;
43 constant CFG_DREPL : integer := CFG_DCACHE_ALGORND;
43 constant CFG_DREPL : integer := CFG_DCACHE_ALGORND;
44 constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK;
44 constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK;
45 constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG;
45 constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG;
46 constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#;
46 constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#;
47 constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM;
47 constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM;
48 constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#;
48 constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#;
49 constant CFG_DLRAMSZ : integer := CFG_DLRAM_SIZE;
49 constant CFG_DLRAMSZ : integer := CFG_DLRAM_SIZE;
50 constant CFG_MMUEN : integer := CONFIG_MMUEN;
50 constant CFG_MMUEN : integer := CONFIG_MMUEN;
51 constant CFG_ITLBNUM : integer := CONFIG_ITLBNUM;
51 constant CFG_ITLBNUM : integer := CONFIG_ITLBNUM;
52 constant CFG_DTLBNUM : integer := CONFIG_DTLBNUM;
52 constant CFG_DTLBNUM : integer := CONFIG_DTLBNUM;
53 constant CFG_TLB_TYPE : integer := CONFIG_TLB_TYPE + CFG_MMU_FASTWB*2;
53 constant CFG_TLB_TYPE : integer := CONFIG_TLB_TYPE + CFG_MMU_FASTWB*2;
54 constant CFG_TLB_REP : integer := CONFIG_TLB_REP;
54 constant CFG_TLB_REP : integer := CONFIG_TLB_REP;
55 constant CFG_MMU_PAGE : integer := CONFIG_MMU_PAGE;
55 constant CFG_MMU_PAGE : integer := CONFIG_MMU_PAGE;
56 constant CFG_DSU : integer := CONFIG_DSU_ENABLE;
56 constant CFG_DSU : integer := CONFIG_DSU_ENABLE;
57 constant CFG_ITBSZ : integer := CFG_DSU_ITB;
57 constant CFG_ITBSZ : integer := CFG_DSU_ITB;
58 constant CFG_ATBSZ : integer := CFG_DSU_ATB;
58 constant CFG_ATBSZ : integer := CFG_DSU_ATB;
59 constant CFG_LEON3FT_EN : integer := CONFIG_LEON3FT_EN;
59 constant CFG_LEON3FT_EN : integer := CONFIG_LEON3FT_EN;
60 constant CFG_IUFT_EN : integer := CONFIG_IUFT_EN;
60 constant CFG_IUFT_EN : integer := CONFIG_IUFT_EN;
61 constant CFG_FPUFT_EN : integer := CONFIG_FPUFT;
61 constant CFG_FPUFT_EN : integer := CONFIG_FPUFT;
62 constant CFG_RF_ERRINJ : integer := CONFIG_RF_ERRINJ;
62 constant CFG_RF_ERRINJ : integer := CONFIG_RF_ERRINJ;
63 constant CFG_CACHE_FT_EN : integer := CONFIG_CACHE_FT_EN;
63 constant CFG_CACHE_FT_EN : integer := CONFIG_CACHE_FT_EN;
64 constant CFG_CACHE_ERRINJ : integer := CONFIG_CACHE_ERRINJ;
64 constant CFG_CACHE_ERRINJ : integer := CONFIG_CACHE_ERRINJ;
65 constant CFG_LEON3_NETLIST: integer := CONFIG_LEON3_NETLIST;
65 constant CFG_LEON3_NETLIST: integer := CONFIG_LEON3_NETLIST;
66 constant CFG_DISAS : integer := CONFIG_IU_DISAS + CONFIG_IU_DISAS_NET;
66 constant CFG_DISAS : integer := CONFIG_IU_DISAS + CONFIG_IU_DISAS_NET;
67 constant CFG_PCLOW : integer := CFG_DEBUG_PC32;
67 constant CFG_PCLOW : integer := CFG_DEBUG_PC32;
68
68
69 -- AMBA settings
69 -- AMBA settings
70 constant CFG_DEFMST : integer := CONFIG_AHB_DEFMST;
70 constant CFG_DEFMST : integer := CONFIG_AHB_DEFMST;
71 constant CFG_RROBIN : integer := CONFIG_AHB_RROBIN;
71 constant CFG_RROBIN : integer := CONFIG_AHB_RROBIN;
72 constant CFG_SPLIT : integer := CONFIG_AHB_SPLIT;
72 constant CFG_SPLIT : integer := CONFIG_AHB_SPLIT;
73 constant CFG_AHBIO : integer := 16#CONFIG_AHB_IOADDR#;
73 constant CFG_AHBIO : integer := 16#CONFIG_AHB_IOADDR#;
74 constant CFG_APBADDR : integer := 16#CONFIG_APB_HADDR#;
74 constant CFG_APBADDR : integer := 16#CONFIG_APB_HADDR#;
75 constant CFG_AHB_MON : integer := CONFIG_AHB_MON;
75 constant CFG_AHB_MON : integer := CONFIG_AHB_MON;
76 constant CFG_AHB_MONERR : integer := CONFIG_AHB_MONERR;
76 constant CFG_AHB_MONERR : integer := CONFIG_AHB_MONERR;
77 constant CFG_AHB_MONWAR : integer := CONFIG_AHB_MONWAR;
77 constant CFG_AHB_MONWAR : integer := CONFIG_AHB_MONWAR;
78
78
79 -- DSU UART
79 -- DSU UART
80 constant CFG_AHB_UART : integer := CONFIG_DSU_UART;
80 constant CFG_AHB_UART : integer := CONFIG_DSU_UART;
81
81
82 -- JTAG based DSU interface
82 -- JTAG based DSU interface
83 constant CFG_AHB_JTAG : integer := CONFIG_DSU_JTAG;
83 constant CFG_AHB_JTAG : integer := CONFIG_DSU_JTAG;
84
84
85 -- Ethernet DSU
85 -- Ethernet DSU
86 constant CFG_DSU_ETH : integer := CONFIG_DSU_ETH + CONFIG_DSU_ETH_PROG;
86 constant CFG_DSU_ETH : integer := CONFIG_DSU_ETH + CONFIG_DSU_ETH_PROG;
87 constant CFG_ETH_BUF : integer := CFG_DSU_ETHB;
87 constant CFG_ETH_BUF : integer := CFG_DSU_ETHB;
88 constant CFG_ETH_IPM : integer := 16#CONFIG_DSU_IPMSB#;
88 constant CFG_ETH_IPM : integer := 16#CONFIG_DSU_IPMSB#;
89 constant CFG_ETH_IPL : integer := 16#CONFIG_DSU_IPLSB#;
89 constant CFG_ETH_IPL : integer := 16#CONFIG_DSU_IPLSB#;
90 constant CFG_ETH_ENM : integer := 16#CONFIG_DSU_ETHMSB#;
90 constant CFG_ETH_ENM : integer := 16#CONFIG_DSU_ETHMSB#;
91 constant CFG_ETH_ENL : integer := 16#CONFIG_DSU_ETHLSB#;
91 constant CFG_ETH_ENL : integer := 16#CONFIG_DSU_ETHLSB#;
92
92
93 -- PROM/SRAM controller
93 -- PROM/SRAM controller
94 constant CFG_SRCTRL : integer := CONFIG_SRCTRL;
94 constant CFG_SRCTRL : integer := CONFIG_SRCTRL;
95 constant CFG_SRCTRL_PROMWS : integer := CONFIG_SRCTRL_PROMWS;
95 constant CFG_SRCTRL_PROMWS : integer := CONFIG_SRCTRL_PROMWS;
96 constant CFG_SRCTRL_RAMWS : integer := CONFIG_SRCTRL_RAMWS;
96 constant CFG_SRCTRL_RAMWS : integer := CONFIG_SRCTRL_RAMWS;
97 constant CFG_SRCTRL_IOWS : integer := CONFIG_SRCTRL_IOWS;
97 constant CFG_SRCTRL_IOWS : integer := CONFIG_SRCTRL_IOWS;
98 constant CFG_SRCTRL_RMW : integer := CONFIG_SRCTRL_RMW;
98 constant CFG_SRCTRL_RMW : integer := CONFIG_SRCTRL_RMW;
99 constant CFG_SRCTRL_8BIT : integer := CONFIG_SRCTRL_8BIT;
99 constant CFG_SRCTRL_8BIT : integer := CONFIG_SRCTRL_8BIT;
100
100
101 constant CFG_SRCTRL_SRBANKS : integer := CFG_SR_CTRL_SRBANKS;
101 constant CFG_SRCTRL_SRBANKS : integer := CFG_SR_CTRL_SRBANKS;
102 constant CFG_SRCTRL_BANKSZ : integer := CFG_SR_CTRL_BANKSZ;
102 constant CFG_SRCTRL_BANKSZ : integer := CFG_SR_CTRL_BANKSZ;
103 constant CFG_SRCTRL_ROMASEL : integer := CONFIG_SRCTRL_ROMASEL;
103 constant CFG_SRCTRL_ROMASEL : integer := CONFIG_SRCTRL_ROMASEL;
104 -- LEON2 memory controller
104 -- LEON2 memory controller
105 constant CFG_MCTRL_LEON2 : integer := CONFIG_MCTRL_LEON2;
105 constant CFG_MCTRL_LEON2 : integer := CONFIG_MCTRL_LEON2;
106 constant CFG_MCTRL_RAM8BIT : integer := CONFIG_MCTRL_8BIT;
106 constant CFG_MCTRL_RAM8BIT : integer := CONFIG_MCTRL_8BIT;
107 constant CFG_MCTRL_RAM16BIT : integer := CONFIG_MCTRL_16BIT;
107 constant CFG_MCTRL_RAM16BIT : integer := CONFIG_MCTRL_16BIT;
108 constant CFG_MCTRL_5CS : integer := CONFIG_MCTRL_5CS;
108 constant CFG_MCTRL_5CS : integer := CONFIG_MCTRL_5CS;
109 constant CFG_MCTRL_SDEN : integer := CONFIG_MCTRL_SDRAM;
109 constant CFG_MCTRL_SDEN : integer := CONFIG_MCTRL_SDRAM;
110 constant CFG_MCTRL_SEPBUS : integer := CONFIG_MCTRL_SDRAM_SEPBUS;
110 constant CFG_MCTRL_SEPBUS : integer := CONFIG_MCTRL_SDRAM_SEPBUS;
111 constant CFG_MCTRL_INVCLK : integer := CONFIG_MCTRL_SDRAM_INVCLK;
111 constant CFG_MCTRL_INVCLK : integer := CONFIG_MCTRL_SDRAM_INVCLK;
112 constant CFG_MCTRL_SD64 : integer := CONFIG_MCTRL_SDRAM_BUS64;
112 constant CFG_MCTRL_SD64 : integer := CONFIG_MCTRL_SDRAM_BUS64;
113 constant CFG_MCTRL_PAGE : integer := CONFIG_MCTRL_PAGE + CONFIG_MCTRL_PROGPAGE;
113 constant CFG_MCTRL_PAGE : integer := CONFIG_MCTRL_PAGE + CONFIG_MCTRL_PROGPAGE;
114
114
115 -- SDRAM controller
115 -- SDRAM controller
116 constant CFG_SDCTRL : integer := CONFIG_SDCTRL;
116 constant CFG_SDCTRL : integer := CONFIG_SDCTRL;
117 constant CFG_SDCTRL_INVCLK : integer := CONFIG_SDCTRL_INVCLK;
117 constant CFG_SDCTRL_INVCLK : integer := CONFIG_SDCTRL_INVCLK;
118 constant CFG_SDCTRL_SD64 : integer := CONFIG_SDCTRL_BUS64;
118 constant CFG_SDCTRL_SD64 : integer := CONFIG_SDCTRL_BUS64;
119 constant CFG_SDCTRL_PAGE : integer := CONFIG_SDCTRL_PAGE + CONFIG_SDCTRL_PROGPAGE;
119 constant CFG_SDCTRL_PAGE : integer := CONFIG_SDCTRL_PAGE + CONFIG_SDCTRL_PROGPAGE;
120
120
121 -- AHB ROM
121 -- AHB ROM
122 constant CFG_AHBROMEN : integer := CONFIG_AHBROM_ENABLE;
122 constant CFG_AHBROMEN : integer := CONFIG_AHBROM_ENABLE;
123 constant CFG_AHBROPIP : integer := CONFIG_AHBROM_PIPE;
123 constant CFG_AHBROPIP : integer := CONFIG_AHBROM_PIPE;
124 constant CFG_AHBRODDR : integer := 16#CONFIG_AHBROM_START#;
124 constant CFG_AHBRODDR : integer := 16#CONFIG_AHBROM_START#;
125 constant CFG_ROMADDR : integer := 16#CONFIG_ROM_START#;
125 constant CFG_ROMADDR : integer := 16#CONFIG_ROM_START#;
126 constant CFG_ROMMASK : integer := 16#E00# + 16#CONFIG_ROM_START#;
126 constant CFG_ROMMASK : integer := 16#E00# + 16#CONFIG_ROM_START#;
127
127
128 -- AHB RAM
128 -- AHB RAM
129 constant CFG_AHBRAMEN : integer := CONFIG_AHBRAM_ENABLE;
129 constant CFG_AHBRAMEN : integer := CONFIG_AHBRAM_ENABLE;
130 constant CFG_AHBRSZ : integer := CFG_AHBRAMSZ;
130 constant CFG_AHBRSZ : integer := CFG_AHBRAMSZ;
131 constant CFG_AHBRADDR : integer := 16#CONFIG_AHBRAM_START#;
131 constant CFG_AHBRADDR : integer := 16#CONFIG_AHBRAM_START#;
132
132
133 -- Gaisler Ethernet core
133 -- Gaisler Ethernet core
134 constant CFG_GRETH : integer := CONFIG_GRETH_ENABLE;
134 constant CFG_GRETH : integer := CONFIG_GRETH_ENABLE;
135 constant CFG_GRETH1G : integer := CONFIG_GRETH_GIGA;
135 constant CFG_GRETH1G : integer := CONFIG_GRETH_GIGA;
136 constant CFG_ETH_FIFO : integer := CFG_GRETH_FIFO;
136 constant CFG_ETH_FIFO : integer := CFG_GRETH_FIFO;
137
137
138 -- CAN 2.0 interface
138 -- CAN 2.0 interface
139 constant CFG_CAN : integer := CONFIG_CAN_ENABLE;
139 constant CFG_CAN : integer := CONFIG_CAN_ENABLE;
140 constant CFG_CANIO : integer := 16#CONFIG_CANIO#;
140 constant CFG_CANIO : integer := 16#CONFIG_CANIO#;
141 constant CFG_CANIRQ : integer := CONFIG_CANIRQ;
141 constant CFG_CANIRQ : integer := CONFIG_CANIRQ;
142 constant CFG_CANLOOP : integer := CONFIG_CANLOOP;
142 constant CFG_CANLOOP : integer := CONFIG_CANLOOP;
143 constant CFG_CAN_SYNCRST : integer := CONFIG_CAN_SYNCRST;
143 constant CFG_CAN_SYNCRST : integer := CONFIG_CAN_SYNCRST;
144 constant CFG_CANFT : integer := CONFIG_CAN_FT;
144 constant CFG_CANFT : integer := CONFIG_CAN_FT;
145
145
146 -- PCI interface
146 -- PCI interface
147 constant CFG_PCI : integer := CFG_PCITYPE;
147 constant CFG_PCI : integer := CFG_PCITYPE;
148 constant CFG_PCIVID : integer := 16#CONFIG_PCI_VENDORID#;
148 constant CFG_PCIVID : integer := 16#CONFIG_PCI_VENDORID#;
149 constant CFG_PCIDID : integer := 16#CONFIG_PCI_DEVICEID#;
149 constant CFG_PCIDID : integer := 16#CONFIG_PCI_DEVICEID#;
150 constant CFG_PCIDEPTH : integer := CFG_PCIFIFO;
150 constant CFG_PCIDEPTH : integer := CFG_PCIFIFO;
151 constant CFG_PCI_MTF : integer := CFG_PCI_ENFIFO;
151 constant CFG_PCI_MTF : integer := CFG_PCI_ENFIFO;
152
152
153 -- PCI arbiter
153 -- PCI arbiter
154 constant CFG_PCI_ARB : integer := CONFIG_PCI_ARBITER;
154 constant CFG_PCI_ARB : integer := CONFIG_PCI_ARBITER;
155 constant CFG_PCI_ARBAPB : integer := CONFIG_PCI_ARBITER_APB;
155 constant CFG_PCI_ARBAPB : integer := CONFIG_PCI_ARBITER_APB;
156 constant CFG_PCI_ARB_NGNT : integer := CONFIG_PCI_ARBITER_NREQ;
156 constant CFG_PCI_ARB_NGNT : integer := CONFIG_PCI_ARBITER_NREQ;
157
157
158 -- PCI trace buffer
158 -- PCI trace buffer
159 constant CFG_PCITBUFEN: integer := CONFIG_PCI_TRACE;
159 constant CFG_PCITBUFEN: integer := CONFIG_PCI_TRACE;
160 constant CFG_PCITBUF : integer := CFG_PCI_TRACEBUF;
160 constant CFG_PCITBUF : integer := CFG_PCI_TRACEBUF;
161
161
162 -- Spacewire interface
162 -- Spacewire interface
163 constant CFG_SPW_EN : integer := CONFIG_SPW_ENABLE;
163 constant CFG_SPW_EN : integer := CONFIG_SPW_ENABLE;
164 constant CFG_SPW_NUM : integer := CONFIG_SPW_NUM;
164 constant CFG_SPW_NUM : integer := CONFIG_SPW_NUM;
165 constant CFG_SPW_AHBFIFO : integer := CONFIG_SPW_AHBFIFO;
165 constant CFG_SPW_AHBFIFO : integer := CONFIG_SPW_AHBFIFO;
166 constant CFG_SPW_RXFIFO : integer := CONFIG_SPW_RXFIFO;
166 constant CFG_SPW_RXFIFO : integer := CONFIG_SPW_RXFIFO;
167 constant CFG_SPW_RMAP : integer := CONFIG_SPW_RMAP;
167 constant CFG_SPW_RMAP : integer := CONFIG_SPW_RMAP;
168 constant CFG_SPW_RMAPBUF : integer := CONFIG_SPW_RMAPBUF;
168 constant CFG_SPW_RMAPBUF : integer := CONFIG_SPW_RMAPBUF;
169 constant CFG_SPW_RMAPCRC : integer := CONFIG_SPW_RMAPCRC;
169 constant CFG_SPW_RMAPCRC : integer := CONFIG_SPW_RMAPCRC;
170 constant CFG_SPW_NETLIST : integer := CONFIG_SPW_NETLIST;
170 constant CFG_SPW_NETLIST : integer := CONFIG_SPW_NETLIST;
171 constant CFG_SPW_FT : integer := CONFIG_SPW_FT;
171 constant CFG_SPW_FT : integer := CONFIG_SPW_FT;
172 constant CFG_SPW_GRSPW : integer := CONFIG_SPW_GRSPW;
172 constant CFG_SPW_GRSPW : integer := CONFIG_SPW_GRSPW;
173 constant CFG_SPW_RXUNAL : integer := CONFIG_SPW_RXUNAL;
173 constant CFG_SPW_RXUNAL : integer := CONFIG_SPW_RXUNAL;
174 constant CFG_SPW_DMACHAN : integer := CONFIG_SPW_DMACHAN;
174 constant CFG_SPW_DMACHAN : integer := CONFIG_SPW_DMACHAN;
175 constant CFG_SPW_PORTS : integer := CONFIG_SPW_PORTS;
175 constant CFG_SPW_PORTS : integer := CONFIG_SPW_PORTS;
176 constant CFG_SPW_INPUT : integer := CONFIG_SPW_INPUT;
176 constant CFG_SPW_INPUT : integer := CONFIG_SPW_INPUT;
177 constant CFG_SPW_OUTPUT : integer := CONFIG_SPW_OUTPUT;
177 constant CFG_SPW_OUTPUT : integer := CONFIG_SPW_OUTPUT;
178 constant CFG_SPW_RTSAME : integer := CONFIG_SPW_RTSAME;
178 constant CFG_SPW_RTSAME : integer := CONFIG_SPW_RTSAME;
179 -- UART 1
179 -- UART 1
180 constant CFG_UART1_ENABLE : integer := CONFIG_UART1_ENABLE;
180 constant CFG_UART1_ENABLE : integer := CONFIG_UART1_ENABLE;
181 constant CFG_UART1_FIFO : integer := CFG_UA1_FIFO;
181 constant CFG_UART1_FIFO : integer := CFG_UA1_FIFO;
182
182
183 -- UART 2
183 -- UART 2
184 constant CFG_UART2_ENABLE : integer := CONFIG_UART2_ENABLE;
184 constant CFG_UART2_ENABLE : integer := CONFIG_UART2_ENABLE;
185 constant CFG_UART2_FIFO : integer := CFG_UA2_FIFO;
185 constant CFG_UART2_FIFO : integer := CFG_UA2_FIFO;
186
186
187 -- LEON3 interrupt controller
187 -- LEON3 interrupt controller
188 constant CFG_IRQ3_ENABLE : integer := CONFIG_IRQ3_ENABLE;
188 constant CFG_IRQ3_ENABLE : integer := CONFIG_IRQ3_ENABLE;
189 constant CFG_IRQ3_NSEC : integer := CONFIG_IRQ3_NSEC;
189 constant CFG_IRQ3_NSEC : integer := CONFIG_IRQ3_NSEC;
190
190
191 -- Modular timer
191 -- Modular timer
192 constant CFG_GPT_ENABLE : integer := CONFIG_GPT_ENABLE;
192 constant CFG_GPT_ENABLE : integer := CONFIG_GPT_ENABLE;
193 constant CFG_GPT_NTIM : integer := CONFIG_GPT_NTIM;
193 constant CFG_GPT_NTIM : integer := CONFIG_GPT_NTIM;
194 constant CFG_GPT_SW : integer := CONFIG_GPT_SW;
194 constant CFG_GPT_SW : integer := CONFIG_GPT_SW;
195 constant CFG_GPT_TW : integer := CONFIG_GPT_TW;
195 constant CFG_GPT_TW : integer := CONFIG_GPT_TW;
196 constant CFG_GPT_IRQ : integer := CONFIG_GPT_IRQ;
196 constant CFG_GPT_IRQ : integer := CONFIG_GPT_IRQ;
197 constant CFG_GPT_SEPIRQ : integer := CONFIG_GPT_SEPIRQ;
197 constant CFG_GPT_SEPIRQ : integer := CONFIG_GPT_SEPIRQ;
198 constant CFG_GPT_WDOGEN : integer := CONFIG_GPT_WDOGEN;
198 constant CFG_GPT_WDOGEN : integer := CONFIG_GPT_WDOGEN;
199 constant CFG_GPT_WDOG : integer := 16#CONFIG_GPT_WDOG#;
199 constant CFG_GPT_WDOG : integer := 16#CONFIG_GPT_WDOG#;
200
200
201 -- GPIO port
201 -- GPIO port
202 constant CFG_GRGPIO_ENABLE : integer := CONFIG_GRGPIO_ENABLE;
202 constant CFG_GRGPIO_ENABLE : integer := CONFIG_GRGPIO_ENABLE;
203 constant CFG_GRGPIO_IMASK : integer := 16#CONFIG_GRGPIO_IMASK#;
203 constant CFG_GRGPIO_IMASK : integer := 16#CONFIG_GRGPIO_IMASK#;
204 constant CFG_GRGPIO_WIDTH : integer := CONFIG_GRGPIO_WIDTH;
204 constant CFG_GRGPIO_WIDTH : integer := CONFIG_GRGPIO_WIDTH;
205
205
206 -- GRLIB debugging
206 -- GRLIB debugging
207 constant CFG_DUART : integer := CONFIG_DEBUG_UART;
207 constant CFG_DUART : integer := CONFIG_DEBUG_UART;
208
208
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@@ -1,1189 +1,1189
1 #if defined CONFIG_SYN_INFERRED
1 #if defined CONFIG_SYN_INFERRED
2 #define CONFIG_SYN_TECH inferred
2 #define CONFIG_SYN_TECH inferred
3 #elif defined CONFIG_SYN_UMC
3 #elif defined CONFIG_SYN_UMC
4 #define CONFIG_SYN_TECH umc
4 #define CONFIG_SYN_TECH umc
5 #elif defined CONFIG_SYN_RHUMC
5 #elif defined CONFIG_SYN_RHUMC
6 #define CONFIG_SYN_TECH rhumc
6 #define CONFIG_SYN_TECH rhumc
7 #elif defined CONFIG_SYN_ATC18
7 #elif defined CONFIG_SYN_ATC18
8 #define CONFIG_SYN_TECH atc18s
8 #define CONFIG_SYN_TECH atc18s
9 #elif defined CONFIG_SYN_ATC18RHA
9 #elif defined CONFIG_SYN_ATC18RHA
10 #define CONFIG_SYN_TECH atc18rha
10 #define CONFIG_SYN_TECH atc18rha
11 #elif defined CONFIG_SYN_AXCEL
11 #elif defined CONFIG_SYN_AXCEL
12 #define CONFIG_SYN_TECH axcel
12 #define CONFIG_SYN_TECH axcel
13 #elif defined CONFIG_SYN_PROASICPLUS
13 #elif defined CONFIG_SYN_PROASICPLUS
14 #define CONFIG_SYN_TECH proasic
14 #define CONFIG_SYN_TECH proasic
15 #elif defined CONFIG_SYN_ALTERA
15 #elif defined CONFIG_SYN_ALTERA
16 #define CONFIG_SYN_TECH altera
16 #define CONFIG_SYN_TECH altera
17 #elif defined CONFIG_SYN_STRATIX
17 #elif defined CONFIG_SYN_STRATIX
18 #define CONFIG_SYN_TECH stratix1
18 #define CONFIG_SYN_TECH stratix1
19 #elif defined CONFIG_SYN_STRATIXII
19 #elif defined CONFIG_SYN_STRATIXII
20 #define CONFIG_SYN_TECH stratix2
20 #define CONFIG_SYN_TECH stratix2
21 #elif defined CONFIG_SYN_STRATIXIII
21 #elif defined CONFIG_SYN_STRATIXIII
22 #define CONFIG_SYN_TECH stratix3
22 #define CONFIG_SYN_TECH stratix3
23 #elif defined CONFIG_SYN_CYCLONEIII
23 #elif defined CONFIG_SYN_CYCLONEIII
24 #define CONFIG_SYN_TECH cyclone3
24 #define CONFIG_SYN_TECH cyclone3
25 #elif defined CONFIG_SYN_EASIC90
25 #elif defined CONFIG_SYN_EASIC90
26 #define CONFIG_SYN_TECH easic90
26 #define CONFIG_SYN_TECH easic90
27 #elif defined CONFIG_SYN_IHP25
27 #elif defined CONFIG_SYN_IHP25
28 #define CONFIG_SYN_TECH ihp25
28 #define CONFIG_SYN_TECH ihp25
29 #elif defined CONFIG_SYN_IHP25RH
29 #elif defined CONFIG_SYN_IHP25RH
30 #define CONFIG_SYN_TECH ihp25rh
30 #define CONFIG_SYN_TECH ihp25rh
31 #elif defined CONFIG_SYN_LATTICE
31 #elif defined CONFIG_SYN_LATTICE
32 #define CONFIG_SYN_TECH lattice
32 #define CONFIG_SYN_TECH lattice
33 #elif defined CONFIG_SYN_ECLIPSE
33 #elif defined CONFIG_SYN_ECLIPSE
34 #define CONFIG_SYN_TECH eclipse
34 #define CONFIG_SYN_TECH eclipse
35 #elif defined CONFIG_SYN_PEREGRINE
35 #elif defined CONFIG_SYN_PEREGRINE
36 #define CONFIG_SYN_TECH peregrine
36 #define CONFIG_SYN_TECH peregrine
37 #elif defined CONFIG_SYN_PROASIC
37 #elif defined CONFIG_SYN_PROASIC
38 #define CONFIG_SYN_TECH proasic
38 #define CONFIG_SYN_TECH proasic
39 #elif defined CONFIG_SYN_PROASIC3
39 #elif defined CONFIG_SYN_PROASIC3
40 #define CONFIG_SYN_TECH apa3
40 #define CONFIG_SYN_TECH apa3
41 #elif defined CONFIG_SYN_SPARTAN2
41 #elif defined CONFIG_SYN_SPARTAN2
42 #define CONFIG_SYN_TECH virtex
42 #define CONFIG_SYN_TECH virtex
43 #elif defined CONFIG_SYN_VIRTEX
43 #elif defined CONFIG_SYN_VIRTEX
44 #define CONFIG_SYN_TECH virtex
44 #define CONFIG_SYN_TECH virtex
45 #elif defined CONFIG_SYN_VIRTEXE
45 #elif defined CONFIG_SYN_VIRTEXE
46 #define CONFIG_SYN_TECH virtex
46 #define CONFIG_SYN_TECH virtex
47 #elif defined CONFIG_SYN_SPARTAN3
47 #elif defined CONFIG_SYN_SPARTAN3
48 #define CONFIG_SYN_TECH spartan3
48 #define CONFIG_SYN_TECH spartan3
49 #elif defined CONFIG_SYN_SPARTAN3E
49 #elif defined CONFIG_SYN_SPARTAN3E
50 #define CONFIG_SYN_TECH spartan3e
50 #define CONFIG_SYN_TECH spartan3e
51 #elif defined CONFIG_SYN_VIRTEX2
51 #elif defined CONFIG_SYN_VIRTEX2
52 #define CONFIG_SYN_TECH virtex2
52 #define CONFIG_SYN_TECH virtex2
53 #elif defined CONFIG_SYN_VIRTEX4
53 #elif defined CONFIG_SYN_VIRTEX4
54 #define CONFIG_SYN_TECH virtex4
54 #define CONFIG_SYN_TECH virtex4
55 #elif defined CONFIG_SYN_VIRTEX5
55 #elif defined CONFIG_SYN_VIRTEX5
56 #define CONFIG_SYN_TECH virtex5
56 #define CONFIG_SYN_TECH virtex5
57 #elif defined CONFIG_SYN_RH_LIB18T
57 #elif defined CONFIG_SYN_RH_LIB18T
58 #define CONFIG_SYN_TECH rhlib18t
58 #define CONFIG_SYN_TECH rhlib18t
59 #elif defined CONFIG_SYN_SMIC13
59 #elif defined CONFIG_SYN_SMIC13
60 #define CONFIG_SYN_TECH smic013
60 #define CONFIG_SYN_TECH smic013
61 #elif defined CONFIG_SYN_UT025CRH
61 #elif defined CONFIG_SYN_UT025CRH
62 #define CONFIG_SYN_TECH ut25
62 #define CONFIG_SYN_TECH ut25
63 #elif defined CONFIG_SYN_TSMC90
63 #elif defined CONFIG_SYN_TSMC90
64 #define CONFIG_SYN_TECH tsmc90
64 #define CONFIG_SYN_TECH tsmc90
65 #elif defined CONFIG_SYN_CUSTOM1
65 #elif defined CONFIG_SYN_CUSTOM1
66 #define CONFIG_SYN_TECH custom1
66 #define CONFIG_SYN_TECH custom1
67 #else
67 #else
68 #error "unknown target technology"
68 #error "unknown target technology"
69 #endif
69 #endif
70
70
71 #if defined CONFIG_SYN_INFER_RAM
71 #if defined CONFIG_SYN_INFER_RAM
72 #define CFG_RAM_TECH inferred
72 #define CFG_RAM_TECH inferred
73 #elif defined CONFIG_MEM_UMC
73 #elif defined CONFIG_MEM_UMC
74 #define CFG_RAM_TECH umc
74 #define CFG_RAM_TECH umc
75 #elif defined CONFIG_MEM_RHUMC
75 #elif defined CONFIG_MEM_RHUMC
76 #define CFG_RAM_TECH rhumc
76 #define CFG_RAM_TECH rhumc
77 #elif defined CONFIG_MEM_VIRAGE
77 #elif defined CONFIG_MEM_VIRAGE
78 #define CFG_RAM_TECH memvirage
78 #define CFG_RAM_TECH memvirage
79 #elif defined CONFIG_MEM_ARTISAN
79 #elif defined CONFIG_MEM_ARTISAN
80 #define CFG_RAM_TECH memartisan
80 #define CFG_RAM_TECH memartisan
81 #elif defined CONFIG_MEM_CUSTOM1
81 #elif defined CONFIG_MEM_CUSTOM1
82 #define CFG_RAM_TECH custom1
82 #define CFG_RAM_TECH custom1
83 #elif defined CONFIG_MEM_VIRAGE90
83 #elif defined CONFIG_MEM_VIRAGE90
84 #define CFG_RAM_TECH memvirage90
84 #define CFG_RAM_TECH memvirage90
85 #elif defined CONFIG_MEM_INFERRED
85 #elif defined CONFIG_MEM_INFERRED
86 #define CFG_RAM_TECH inferred
86 #define CFG_RAM_TECH inferred
87 #else
87 #else
88 #define CFG_RAM_TECH CONFIG_SYN_TECH
88 #define CFG_RAM_TECH CONFIG_SYN_TECH
89 #endif
89 #endif
90
90
91 #if defined CONFIG_SYN_INFER_PADS
91 #if defined CONFIG_SYN_INFER_PADS
92 #define CFG_PAD_TECH inferred
92 #define CFG_PAD_TECH inferred
93 #else
93 #else
94 #define CFG_PAD_TECH CONFIG_SYN_TECH
94 #define CFG_PAD_TECH CONFIG_SYN_TECH
95 #endif
95 #endif
96
96
97 #ifndef CONFIG_SYN_NO_ASYNC
97 #ifndef CONFIG_SYN_NO_ASYNC
98 #define CONFIG_SYN_NO_ASYNC 0
98 #define CONFIG_SYN_NO_ASYNC 0
99 #endif
99 #endif
100
100
101 #ifndef CONFIG_SYN_SCAN
101 #ifndef CONFIG_SYN_SCAN
102 #define CONFIG_SYN_SCAN 0
102 #define CONFIG_SYN_SCAN 0
103 #endif
103 #endif
104
104
105
105
106 #if defined CONFIG_CLK_ALTDLL
106 #if defined CONFIG_CLK_ALTDLL
107 #define CFG_CLK_TECH CONFIG_SYN_TECH
107 #define CFG_CLK_TECH CONFIG_SYN_TECH
108 #elif defined CONFIG_CLK_HCLKBUF
108 #elif defined CONFIG_CLK_HCLKBUF
109 #define CFG_CLK_TECH axcel
109 #define CFG_CLK_TECH axcel
110 #elif defined CONFIG_CLK_LATDLL
110 #elif defined CONFIG_CLK_LATDLL
111 #define CFG_CLK_TECH lattice
111 #define CFG_CLK_TECH lattice
112 #elif defined CONFIG_CLK_PRO3PLL
112 #elif defined CONFIG_CLK_PRO3PLL
113 #define CFG_CLK_TECH apa3
113 #define CFG_CLK_TECH apa3
114 #elif defined CONFIG_CLK_CLKDLL
114 #elif defined CONFIG_CLK_CLKDLL
115 #define CFG_CLK_TECH virtex
115 #define CFG_CLK_TECH virtex
116 #elif defined CONFIG_CLK_DCM
116 #elif defined CONFIG_CLK_DCM
117 #define CFG_CLK_TECH CONFIG_SYN_TECH
117 #define CFG_CLK_TECH CONFIG_SYN_TECH
118 #elif defined CONFIG_CLK_LIB18T
118 #elif defined CONFIG_CLK_LIB18T
119 #define CFG_CLK_TECH rhlib18t
119 #define CFG_CLK_TECH rhlib18t
120 #elif defined CONFIG_CLK_RHUMC
120 #elif defined CONFIG_CLK_RHUMC
121 #define CFG_CLK_TECH rhumc
121 #define CFG_CLK_TECH rhumc
122 #else
122 #else
123 #define CFG_CLK_TECH inferred
123 #define CFG_CLK_TECH inferred
124 #endif
124 #endif
125
125
126 #ifndef CONFIG_CLK_MUL
126 #ifndef CONFIG_CLK_MUL
127 #define CONFIG_CLK_MUL 2
127 #define CONFIG_CLK_MUL 2
128 #endif
128 #endif
129
129
130 #ifndef CONFIG_CLK_DIV
130 #ifndef CONFIG_CLK_DIV
131 #define CONFIG_CLK_DIV 2
131 #define CONFIG_CLK_DIV 2
132 #endif
132 #endif
133
133
134 #ifndef CONFIG_OCLK_DIV
134 #ifndef CONFIG_OCLK_DIV
135 #define CONFIG_OCLK_DIV 2
135 #define CONFIG_OCLK_DIV 2
136 #endif
136 #endif
137
137
138 #ifndef CONFIG_PCI_CLKDLL
138 #ifndef CONFIG_PCI_CLKDLL
139 #define CONFIG_PCI_CLKDLL 0
139 #define CONFIG_PCI_CLKDLL 0
140 #endif
140 #endif
141
141
142 #ifndef CONFIG_PCI_SYSCLK
142 #ifndef CONFIG_PCI_SYSCLK
143 #define CONFIG_PCI_SYSCLK 0
143 #define CONFIG_PCI_SYSCLK 0
144 #endif
144 #endif
145
145
146 #ifndef CONFIG_CLK_NOFB
146 #ifndef CONFIG_CLK_NOFB
147 #define CONFIG_CLK_NOFB 0
147 #define CONFIG_CLK_NOFB 0
148 #endif
148 #endif
149 #ifndef CONFIG_LEON3
149 #ifndef CONFIG_LEON3
150 #define CONFIG_LEON3 0
150 #define CONFIG_LEON3 0
151 #endif
151 #endif
152
152
153 #ifndef CONFIG_PROC_NUM
153 #ifndef CONFIG_PROC_NUM
154 #define CONFIG_PROC_NUM 1
154 #define CONFIG_PROC_NUM 1
155 #endif
155 #endif
156
156
157 #ifndef CONFIG_IU_NWINDOWS
157 #ifndef CONFIG_IU_NWINDOWS
158 #define CONFIG_IU_NWINDOWS 8
158 #define CONFIG_IU_NWINDOWS 8
159 #endif
159 #endif
160
160
161 #ifndef CONFIG_IU_RSTADDR
161 #ifndef CONFIG_IU_RSTADDR
162 #define CONFIG_IU_RSTADDR 8
162 #define CONFIG_IU_RSTADDR 8
163 #endif
163 #endif
164
164
165 #ifndef CONFIG_IU_LDELAY
165 #ifndef CONFIG_IU_LDELAY
166 #define CONFIG_IU_LDELAY 1
166 #define CONFIG_IU_LDELAY 1
167 #endif
167 #endif
168
168
169 #ifndef CONFIG_IU_WATCHPOINTS
169 #ifndef CONFIG_IU_WATCHPOINTS
170 #define CONFIG_IU_WATCHPOINTS 0
170 #define CONFIG_IU_WATCHPOINTS 0
171 #endif
171 #endif
172
172
173 #ifdef CONFIG_IU_V8MULDIV
173 #ifdef CONFIG_IU_V8MULDIV
174 #ifdef CONFIG_IU_MUL_LATENCY_4
174 #ifdef CONFIG_IU_MUL_LATENCY_4
175 #define CFG_IU_V8 1
175 #define CFG_IU_V8 1
176 #elif defined CONFIG_IU_MUL_LATENCY_5
176 #elif defined CONFIG_IU_MUL_LATENCY_5
177 #define CFG_IU_V8 2
177 #define CFG_IU_V8 2
178 #elif defined CONFIG_IU_MUL_LATENCY_2
178 #elif defined CONFIG_IU_MUL_LATENCY_2
179 #define CFG_IU_V8 16#32#
179 #define CFG_IU_V8 16#32#
180 #endif
180 #endif
181 #else
181 #else
182 #define CFG_IU_V8 0
182 #define CFG_IU_V8 0
183 #endif
183 #endif
184
184
185 #ifndef CONFIG_PWD
185 #ifndef CONFIG_PWD
186 #define CONFIG_PWD 0
186 #define CONFIG_PWD 0
187 #endif
187 #endif
188
188
189 #ifndef CONFIG_IU_MUL_MAC
189 #ifndef CONFIG_IU_MUL_MAC
190 #define CONFIG_IU_MUL_MAC 0
190 #define CONFIG_IU_MUL_MAC 0
191 #endif
191 #endif
192
192
193 #ifndef CONFIG_IU_SVT
193 #ifndef CONFIG_IU_SVT
194 #define CONFIG_IU_SVT 0
194 #define CONFIG_IU_SVT 0
195 #endif
195 #endif
196
196
197 #if defined CONFIG_FPU_GRFPC1
197 #if defined CONFIG_FPU_GRFPC1
198 #define CONFIG_FPU_GRFPC 1
198 #define CONFIG_FPU_GRFPC 1
199 #elif defined CONFIG_FPU_GRFPC2
199 #elif defined CONFIG_FPU_GRFPC2
200 #define CONFIG_FPU_GRFPC 2
200 #define CONFIG_FPU_GRFPC 2
201 #else
201 #else
202 #define CONFIG_FPU_GRFPC 0
202 #define CONFIG_FPU_GRFPC 0
203 #endif
203 #endif
204
204
205 #if defined CONFIG_FPU_GRFPU_INFMUL
205 #if defined CONFIG_FPU_GRFPU_INFMUL
206 #define CONFIG_FPU_GRFPU_MUL 0
206 #define CONFIG_FPU_GRFPU_MUL 0
207 #elif defined CONFIG_FPU_GRFPU_DWMUL
207 #elif defined CONFIG_FPU_GRFPU_DWMUL
208 #define CONFIG_FPU_GRFPU_MUL 1
208 #define CONFIG_FPU_GRFPU_MUL 1
209 #elif defined CONFIG_FPU_GRFPU_MODGEN
209 #elif defined CONFIG_FPU_GRFPU_MODGEN
210 #define CONFIG_FPU_GRFPU_MUL 2
210 #define CONFIG_FPU_GRFPU_MUL 2
211 #else
211 #else
212 #define CONFIG_FPU_GRFPU_MUL 0
212 #define CONFIG_FPU_GRFPU_MUL 0
213 #endif
213 #endif
214
214
215 #if defined CONFIG_FPU_GRFPU_SH
215 #if defined CONFIG_FPU_GRFPU_SH
216 #define CONFIG_FPU_GRFPU_SHARED 1
216 #define CONFIG_FPU_GRFPU_SHARED 1
217 #else
217 #else
218 #define CONFIG_FPU_GRFPU_SHARED 0
218 #define CONFIG_FPU_GRFPU_SHARED 0
219 #endif
219 #endif
220
220
221 #if defined CONFIG_FPU_GRFPU
221 #if defined CONFIG_FPU_GRFPU
222 #define CONFIG_FPU (1+CONFIG_FPU_GRFPU_MUL)
222 #define CONFIG_FPU (1+CONFIG_FPU_GRFPU_MUL)
223 #elif defined CONFIG_FPU_MEIKO
223 #elif defined CONFIG_FPU_MEIKO
224 #define CONFIG_FPU 15
224 #define CONFIG_FPU 15
225 #elif defined CONFIG_FPU_GRFPULITE
225 #elif defined CONFIG_FPU_GRFPULITE
226 #define CONFIG_FPU (8+CONFIG_FPU_GRFPC)
226 #define CONFIG_FPU (8+CONFIG_FPU_GRFPC)
227 #else
227 #else
228 #define CONFIG_FPU 0
228 #define CONFIG_FPU 0
229 #endif
229 #endif
230
230
231 #ifndef CONFIG_FPU_NETLIST
231 #ifndef CONFIG_FPU_NETLIST
232 #define CONFIG_FPU_NETLIST 0
232 #define CONFIG_FPU_NETLIST 0
233 #endif
233 #endif
234
234
235 #ifndef CONFIG_ICACHE_ENABLE
235 #ifndef CONFIG_ICACHE_ENABLE
236 #define CONFIG_ICACHE_ENABLE 0
236 #define CONFIG_ICACHE_ENABLE 0
237 #endif
237 #endif
238
238
239 #if defined CONFIG_ICACHE_ASSO1
239 #if defined CONFIG_ICACHE_ASSO1
240 #define CFG_IU_ISETS 1
240 #define CFG_IU_ISETS 1
241 #elif defined CONFIG_ICACHE_ASSO2
241 #elif defined CONFIG_ICACHE_ASSO2
242 #define CFG_IU_ISETS 2
242 #define CFG_IU_ISETS 2
243 #elif defined CONFIG_ICACHE_ASSO3
243 #elif defined CONFIG_ICACHE_ASSO3
244 #define CFG_IU_ISETS 3
244 #define CFG_IU_ISETS 3
245 #elif defined CONFIG_ICACHE_ASSO4
245 #elif defined CONFIG_ICACHE_ASSO4
246 #define CFG_IU_ISETS 4
246 #define CFG_IU_ISETS 4
247 #else
247 #else
248 #define CFG_IU_ISETS 1
248 #define CFG_IU_ISETS 1
249 #endif
249 #endif
250
250
251 #if defined CONFIG_ICACHE_SZ1
251 #if defined CONFIG_ICACHE_SZ1
252 #define CFG_ICACHE_SZ 1
252 #define CFG_ICACHE_SZ 1
253 #elif defined CONFIG_ICACHE_SZ2
253 #elif defined CONFIG_ICACHE_SZ2
254 #define CFG_ICACHE_SZ 2
254 #define CFG_ICACHE_SZ 2
255 #elif defined CONFIG_ICACHE_SZ4
255 #elif defined CONFIG_ICACHE_SZ4
256 #define CFG_ICACHE_SZ 4
256 #define CFG_ICACHE_SZ 4
257 #elif defined CONFIG_ICACHE_SZ8
257 #elif defined CONFIG_ICACHE_SZ8
258 #define CFG_ICACHE_SZ 8
258 #define CFG_ICACHE_SZ 8
259 #elif defined CONFIG_ICACHE_SZ16
259 #elif defined CONFIG_ICACHE_SZ16
260 #define CFG_ICACHE_SZ 16
260 #define CFG_ICACHE_SZ 16
261 #elif defined CONFIG_ICACHE_SZ32
261 #elif defined CONFIG_ICACHE_SZ32
262 #define CFG_ICACHE_SZ 32
262 #define CFG_ICACHE_SZ 32
263 #elif defined CONFIG_ICACHE_SZ64
263 #elif defined CONFIG_ICACHE_SZ64
264 #define CFG_ICACHE_SZ 64
264 #define CFG_ICACHE_SZ 64
265 #elif defined CONFIG_ICACHE_SZ128
265 #elif defined CONFIG_ICACHE_SZ128
266 #define CFG_ICACHE_SZ 128
266 #define CFG_ICACHE_SZ 128
267 #elif defined CONFIG_ICACHE_SZ256
267 #elif defined CONFIG_ICACHE_SZ256
268 #define CFG_ICACHE_SZ 256
268 #define CFG_ICACHE_SZ 256
269 #else
269 #else
270 #define CFG_ICACHE_SZ 1
270 #define CFG_ICACHE_SZ 1
271 #endif
271 #endif
272
272
273 #ifdef CONFIG_ICACHE_LZ16
273 #ifdef CONFIG_ICACHE_LZ16
274 #define CFG_ILINE_SZ 4
274 #define CFG_ILINE_SZ 4
275 #else
275 #else
276 #define CFG_ILINE_SZ 8
276 #define CFG_ILINE_SZ 8
277 #endif
277 #endif
278
278
279 #if defined CONFIG_ICACHE_ALGORND
279 #if defined CONFIG_ICACHE_ALGORND
280 #define CFG_ICACHE_ALGORND 2
280 #define CFG_ICACHE_ALGORND 2
281 #elif defined CONFIG_ICACHE_ALGOLRR
281 #elif defined CONFIG_ICACHE_ALGOLRR
282 #define CFG_ICACHE_ALGORND 1
282 #define CFG_ICACHE_ALGORND 1
283 #else
283 #else
284 #define CFG_ICACHE_ALGORND 0
284 #define CFG_ICACHE_ALGORND 0
285 #endif
285 #endif
286
286
287 #ifndef CONFIG_ICACHE_LOCK
287 #ifndef CONFIG_ICACHE_LOCK
288 #define CONFIG_ICACHE_LOCK 0
288 #define CONFIG_ICACHE_LOCK 0
289 #endif
289 #endif
290
290
291 #ifndef CONFIG_ICACHE_LRAM
291 #ifndef CONFIG_ICACHE_LRAM
292 #define CONFIG_ICACHE_LRAM 0
292 #define CONFIG_ICACHE_LRAM 0
293 #endif
293 #endif
294
294
295 #ifndef CONFIG_ICACHE_LRSTART
295 #ifndef CONFIG_ICACHE_LRSTART
296 #define CONFIG_ICACHE_LRSTART 8E
296 #define CONFIG_ICACHE_LRSTART 8E
297 #endif
297 #endif
298
298
299 #if defined CONFIG_ICACHE_LRAM_SZ2
299 #if defined CONFIG_ICACHE_LRAM_SZ2
300 #define CFG_ILRAM_SIZE 2
300 #define CFG_ILRAM_SIZE 2
301 #elif defined CONFIG_ICACHE_LRAM_SZ4
301 #elif defined CONFIG_ICACHE_LRAM_SZ4
302 #define CFG_ILRAM_SIZE 4
302 #define CFG_ILRAM_SIZE 4
303 #elif defined CONFIG_ICACHE_LRAM_SZ8
303 #elif defined CONFIG_ICACHE_LRAM_SZ8
304 #define CFG_ILRAM_SIZE 8
304 #define CFG_ILRAM_SIZE 8
305 #elif defined CONFIG_ICACHE_LRAM_SZ16
305 #elif defined CONFIG_ICACHE_LRAM_SZ16
306 #define CFG_ILRAM_SIZE 16
306 #define CFG_ILRAM_SIZE 16
307 #elif defined CONFIG_ICACHE_LRAM_SZ32
307 #elif defined CONFIG_ICACHE_LRAM_SZ32
308 #define CFG_ILRAM_SIZE 32
308 #define CFG_ILRAM_SIZE 32
309 #elif defined CONFIG_ICACHE_LRAM_SZ64
309 #elif defined CONFIG_ICACHE_LRAM_SZ64
310 #define CFG_ILRAM_SIZE 64
310 #define CFG_ILRAM_SIZE 64
311 #elif defined CONFIG_ICACHE_LRAM_SZ128
311 #elif defined CONFIG_ICACHE_LRAM_SZ128
312 #define CFG_ILRAM_SIZE 128
312 #define CFG_ILRAM_SIZE 128
313 #elif defined CONFIG_ICACHE_LRAM_SZ256
313 #elif defined CONFIG_ICACHE_LRAM_SZ256
314 #define CFG_ILRAM_SIZE 256
314 #define CFG_ILRAM_SIZE 256
315 #else
315 #else
316 #define CFG_ILRAM_SIZE 1
316 #define CFG_ILRAM_SIZE 1
317 #endif
317 #endif
318
318
319
319
320 #ifndef CONFIG_DCACHE_ENABLE
320 #ifndef CONFIG_DCACHE_ENABLE
321 #define CONFIG_DCACHE_ENABLE 0
321 #define CONFIG_DCACHE_ENABLE 0
322 #endif
322 #endif
323
323
324 #if defined CONFIG_DCACHE_ASSO1
324 #if defined CONFIG_DCACHE_ASSO1
325 #define CFG_IU_DSETS 1
325 #define CFG_IU_DSETS 1
326 #elif defined CONFIG_DCACHE_ASSO2
326 #elif defined CONFIG_DCACHE_ASSO2
327 #define CFG_IU_DSETS 2
327 #define CFG_IU_DSETS 2
328 #elif defined CONFIG_DCACHE_ASSO3
328 #elif defined CONFIG_DCACHE_ASSO3
329 #define CFG_IU_DSETS 3
329 #define CFG_IU_DSETS 3
330 #elif defined CONFIG_DCACHE_ASSO4
330 #elif defined CONFIG_DCACHE_ASSO4
331 #define CFG_IU_DSETS 4
331 #define CFG_IU_DSETS 4
332 #else
332 #else
333 #define CFG_IU_DSETS 1
333 #define CFG_IU_DSETS 1
334 #endif
334 #endif
335
335
336 #if defined CONFIG_DCACHE_SZ1
336 #if defined CONFIG_DCACHE_SZ1
337 #define CFG_DCACHE_SZ 1
337 #define CFG_DCACHE_SZ 1
338 #elif defined CONFIG_DCACHE_SZ2
338 #elif defined CONFIG_DCACHE_SZ2
339 #define CFG_DCACHE_SZ 2
339 #define CFG_DCACHE_SZ 2
340 #elif defined CONFIG_DCACHE_SZ4
340 #elif defined CONFIG_DCACHE_SZ4
341 #define CFG_DCACHE_SZ 4
341 #define CFG_DCACHE_SZ 4
342 #elif defined CONFIG_DCACHE_SZ8
342 #elif defined CONFIG_DCACHE_SZ8
343 #define CFG_DCACHE_SZ 8
343 #define CFG_DCACHE_SZ 8
344 #elif defined CONFIG_DCACHE_SZ16
344 #elif defined CONFIG_DCACHE_SZ16
345 #define CFG_DCACHE_SZ 16
345 #define CFG_DCACHE_SZ 16
346 #elif defined CONFIG_DCACHE_SZ32
346 #elif defined CONFIG_DCACHE_SZ32
347 #define CFG_DCACHE_SZ 32
347 #define CFG_DCACHE_SZ 32
348 #elif defined CONFIG_DCACHE_SZ64
348 #elif defined CONFIG_DCACHE_SZ64
349 #define CFG_DCACHE_SZ 64
349 #define CFG_DCACHE_SZ 64
350 #elif defined CONFIG_DCACHE_SZ128
350 #elif defined CONFIG_DCACHE_SZ128
351 #define CFG_DCACHE_SZ 128
351 #define CFG_DCACHE_SZ 128
352 #elif defined CONFIG_DCACHE_SZ256
352 #elif defined CONFIG_DCACHE_SZ256
353 #define CFG_DCACHE_SZ 256
353 #define CFG_DCACHE_SZ 256
354 #else
354 #else
355 #define CFG_DCACHE_SZ 1
355 #define CFG_DCACHE_SZ 1
356 #endif
356 #endif
357
357
358 #ifdef CONFIG_DCACHE_LZ16
358 #ifdef CONFIG_DCACHE_LZ16
359 #define CFG_DLINE_SZ 4
359 #define CFG_DLINE_SZ 4
360 #else
360 #else
361 #define CFG_DLINE_SZ 8
361 #define CFG_DLINE_SZ 8
362 #endif
362 #endif
363
363
364 #if defined CONFIG_DCACHE_ALGORND
364 #if defined CONFIG_DCACHE_ALGORND
365 #define CFG_DCACHE_ALGORND 2
365 #define CFG_DCACHE_ALGORND 2
366 #elif defined CONFIG_DCACHE_ALGOLRR
366 #elif defined CONFIG_DCACHE_ALGOLRR
367 #define CFG_DCACHE_ALGORND 1
367 #define CFG_DCACHE_ALGORND 1
368 #else
368 #else
369 #define CFG_DCACHE_ALGORND 0
369 #define CFG_DCACHE_ALGORND 0
370 #endif
370 #endif
371
371
372 #ifndef CONFIG_DCACHE_LOCK
372 #ifndef CONFIG_DCACHE_LOCK
373 #define CONFIG_DCACHE_LOCK 0
373 #define CONFIG_DCACHE_LOCK 0
374 #endif
374 #endif
375
375
376 #ifndef CONFIG_DCACHE_SNOOP
376 #ifndef CONFIG_DCACHE_SNOOP
377 #define CONFIG_DCACHE_SNOOP 0
377 #define CONFIG_DCACHE_SNOOP 0
378 #endif
378 #endif
379
379
380 #ifndef CONFIG_DCACHE_SNOOP_FAST
380 #ifndef CONFIG_DCACHE_SNOOP_FAST
381 #define CONFIG_DCACHE_SNOOP_FAST 0
381 #define CONFIG_DCACHE_SNOOP_FAST 0
382 #endif
382 #endif
383
383
384 #ifndef CONFIG_DCACHE_SNOOP_SEPTAG
384 #ifndef CONFIG_DCACHE_SNOOP_SEPTAG
385 #define CONFIG_DCACHE_SNOOP_SEPTAG 0
385 #define CONFIG_DCACHE_SNOOP_SEPTAG 0
386 #endif
386 #endif
387
387
388 #ifndef CONFIG_CACHE_FIXED
388 #ifndef CONFIG_CACHE_FIXED
389 #define CONFIG_CACHE_FIXED 0
389 #define CONFIG_CACHE_FIXED 0
390 #endif
390 #endif
391
391
392 #ifndef CONFIG_DCACHE_LRAM
392 #ifndef CONFIG_DCACHE_LRAM
393 #define CONFIG_DCACHE_LRAM 0
393 #define CONFIG_DCACHE_LRAM 0
394 #endif
394 #endif
395
395
396 #ifndef CONFIG_DCACHE_LRSTART
396 #ifndef CONFIG_DCACHE_LRSTART
397 #define CONFIG_DCACHE_LRSTART 8F
397 #define CONFIG_DCACHE_LRSTART 8F
398 #endif
398 #endif
399
399
400 #if defined CONFIG_DCACHE_LRAM_SZ2
400 #if defined CONFIG_DCACHE_LRAM_SZ2
401 #define CFG_DLRAM_SIZE 2
401 #define CFG_DLRAM_SIZE 2
402 #elif defined CONFIG_DCACHE_LRAM_SZ4
402 #elif defined CONFIG_DCACHE_LRAM_SZ4
403 #define CFG_DLRAM_SIZE 4
403 #define CFG_DLRAM_SIZE 4
404 #elif defined CONFIG_DCACHE_LRAM_SZ8
404 #elif defined CONFIG_DCACHE_LRAM_SZ8
405 #define CFG_DLRAM_SIZE 8
405 #define CFG_DLRAM_SIZE 8
406 #elif defined CONFIG_DCACHE_LRAM_SZ16
406 #elif defined CONFIG_DCACHE_LRAM_SZ16
407 #define CFG_DLRAM_SIZE 16
407 #define CFG_DLRAM_SIZE 16
408 #elif defined CONFIG_DCACHE_LRAM_SZ32
408 #elif defined CONFIG_DCACHE_LRAM_SZ32
409 #define CFG_DLRAM_SIZE 32
409 #define CFG_DLRAM_SIZE 32
410 #elif defined CONFIG_DCACHE_LRAM_SZ64
410 #elif defined CONFIG_DCACHE_LRAM_SZ64
411 #define CFG_DLRAM_SIZE 64
411 #define CFG_DLRAM_SIZE 64
412 #elif defined CONFIG_DCACHE_LRAM_SZ128
412 #elif defined CONFIG_DCACHE_LRAM_SZ128
413 #define CFG_DLRAM_SIZE 128
413 #define CFG_DLRAM_SIZE 128
414 #elif defined CONFIG_DCACHE_LRAM_SZ256
414 #elif defined CONFIG_DCACHE_LRAM_SZ256
415 #define CFG_DLRAM_SIZE 256
415 #define CFG_DLRAM_SIZE 256
416 #else
416 #else
417 #define CFG_DLRAM_SIZE 1
417 #define CFG_DLRAM_SIZE 1
418 #endif
418 #endif
419
419
420 #if defined CONFIG_MMU_PAGE_4K
420 #if defined CONFIG_MMU_PAGE_4K
421 #define CONFIG_MMU_PAGE 0
421 #define CONFIG_MMU_PAGE 0
422 #elif defined CONFIG_MMU_PAGE_8K
422 #elif defined CONFIG_MMU_PAGE_8K
423 #define CONFIG_MMU_PAGE 1
423 #define CONFIG_MMU_PAGE 1
424 #elif defined CONFIG_MMU_PAGE_16K
424 #elif defined CONFIG_MMU_PAGE_16K
425 #define CONFIG_MMU_PAGE 2
425 #define CONFIG_MMU_PAGE 2
426 #elif defined CONFIG_MMU_PAGE_32K
426 #elif defined CONFIG_MMU_PAGE_32K
427 #define CONFIG_MMU_PAGE 3
427 #define CONFIG_MMU_PAGE 3
428 #elif defined CONFIG_MMU_PAGE_PROG
428 #elif defined CONFIG_MMU_PAGE_PROG
429 #define CONFIG_MMU_PAGE 4
429 #define CONFIG_MMU_PAGE 4
430 #else
430 #else
431 #define CONFIG_MMU_PAGE 0
431 #define CONFIG_MMU_PAGE 0
432 #endif
432 #endif
433
433
434 #ifdef CONFIG_MMU_ENABLE
434 #ifdef CONFIG_MMU_ENABLE
435 #define CONFIG_MMUEN 1
435 #define CONFIG_MMUEN 1
436
436
437 #ifdef CONFIG_MMU_SPLIT
437 #ifdef CONFIG_MMU_SPLIT
438 #define CONFIG_TLB_TYPE 0
438 #define CONFIG_TLB_TYPE 0
439 #endif
439 #endif
440 #ifdef CONFIG_MMU_COMBINED
440 #ifdef CONFIG_MMU_COMBINED
441 #define CONFIG_TLB_TYPE 1
441 #define CONFIG_TLB_TYPE 1
442 #endif
442 #endif
443
443
444 #ifdef CONFIG_MMU_REPARRAY
444 #ifdef CONFIG_MMU_REPARRAY
445 #define CONFIG_TLB_REP 0
445 #define CONFIG_TLB_REP 0
446 #endif
446 #endif
447 #ifdef CONFIG_MMU_REPINCREMENT
447 #ifdef CONFIG_MMU_REPINCREMENT
448 #define CONFIG_TLB_REP 1
448 #define CONFIG_TLB_REP 1
449 #endif
449 #endif
450
450
451 #ifdef CONFIG_MMU_I2
451 #ifdef CONFIG_MMU_I2
452 #define CONFIG_ITLBNUM 2
452 #define CONFIG_ITLBNUM 2
453 #endif
453 #endif
454 #ifdef CONFIG_MMU_I4
454 #ifdef CONFIG_MMU_I4
455 #define CONFIG_ITLBNUM 4
455 #define CONFIG_ITLBNUM 4
456 #endif
456 #endif
457 #ifdef CONFIG_MMU_I8
457 #ifdef CONFIG_MMU_I8
458 #define CONFIG_ITLBNUM 8
458 #define CONFIG_ITLBNUM 8
459 #endif
459 #endif
460 #ifdef CONFIG_MMU_I16
460 #ifdef CONFIG_MMU_I16
461 #define CONFIG_ITLBNUM 16
461 #define CONFIG_ITLBNUM 16
462 #endif
462 #endif
463 #ifdef CONFIG_MMU_I32
463 #ifdef CONFIG_MMU_I32
464 #define CONFIG_ITLBNUM 32
464 #define CONFIG_ITLBNUM 32
465 #endif
465 #endif
466
466
467 #define CONFIG_DTLBNUM 2
467 #define CONFIG_DTLBNUM 2
468 #ifdef CONFIG_MMU_D2
468 #ifdef CONFIG_MMU_D2
469 #undef CONFIG_DTLBNUM
469 #undef CONFIG_DTLBNUM
470 #define CONFIG_DTLBNUM 2
470 #define CONFIG_DTLBNUM 2
471 #endif
471 #endif
472 #ifdef CONFIG_MMU_D4
472 #ifdef CONFIG_MMU_D4
473 #undef CONFIG_DTLBNUM
473 #undef CONFIG_DTLBNUM
474 #define CONFIG_DTLBNUM 4
474 #define CONFIG_DTLBNUM 4
475 #endif
475 #endif
476 #ifdef CONFIG_MMU_D8
476 #ifdef CONFIG_MMU_D8
477 #undef CONFIG_DTLBNUM
477 #undef CONFIG_DTLBNUM
478 #define CONFIG_DTLBNUM 8
478 #define CONFIG_DTLBNUM 8
479 #endif
479 #endif
480 #ifdef CONFIG_MMU_D16
480 #ifdef CONFIG_MMU_D16
481 #undef CONFIG_DTLBNUM
481 #undef CONFIG_DTLBNUM
482 #define CONFIG_DTLBNUM 16
482 #define CONFIG_DTLBNUM 16
483 #endif
483 #endif
484 #ifdef CONFIG_MMU_D32
484 #ifdef CONFIG_MMU_D32
485 #undef CONFIG_DTLBNUM
485 #undef CONFIG_DTLBNUM
486 #define CONFIG_DTLBNUM 32
486 #define CONFIG_DTLBNUM 32
487 #endif
487 #endif
488 #ifdef CONFIG_MMU_FASTWB
488 #ifdef CONFIG_MMU_FASTWB
489 #define CFG_MMU_FASTWB 1
489 #define CFG_MMU_FASTWB 1
490 #else
490 #else
491 #define CFG_MMU_FASTWB 0
491 #define CFG_MMU_FASTWB 0
492 #endif
492 #endif
493
493
494 #else
494 #else
495 #define CONFIG_MMUEN 0
495 #define CONFIG_MMUEN 0
496 #define CONFIG_ITLBNUM 2
496 #define CONFIG_ITLBNUM 2
497 #define CONFIG_DTLBNUM 2
497 #define CONFIG_DTLBNUM 2
498 #define CONFIG_TLB_TYPE 1
498 #define CONFIG_TLB_TYPE 1
499 #define CONFIG_TLB_REP 1
499 #define CONFIG_TLB_REP 1
500 #define CFG_MMU_FASTWB 0
500 #define CFG_MMU_FASTWB 0
501 #endif
501 #endif
502
502
503 #ifndef CONFIG_DSU_ENABLE
503 #ifndef CONFIG_DSU_ENABLE
504 #define CONFIG_DSU_ENABLE 0
504 #define CONFIG_DSU_ENABLE 0
505 #endif
505 #endif
506
506
507 #if defined CONFIG_DSU_ITRACESZ1
507 #if defined CONFIG_DSU_ITRACESZ1
508 #define CFG_DSU_ITB 1
508 #define CFG_DSU_ITB 1
509 #elif CONFIG_DSU_ITRACESZ2
509 #elif CONFIG_DSU_ITRACESZ2
510 #define CFG_DSU_ITB 2
510 #define CFG_DSU_ITB 2
511 #elif CONFIG_DSU_ITRACESZ4
511 #elif CONFIG_DSU_ITRACESZ4
512 #define CFG_DSU_ITB 4
512 #define CFG_DSU_ITB 4
513 #elif CONFIG_DSU_ITRACESZ8
513 #elif CONFIG_DSU_ITRACESZ8
514 #define CFG_DSU_ITB 8
514 #define CFG_DSU_ITB 8
515 #elif CONFIG_DSU_ITRACESZ16
515 #elif CONFIG_DSU_ITRACESZ16
516 #define CFG_DSU_ITB 16
516 #define CFG_DSU_ITB 16
517 #else
517 #else
518 #define CFG_DSU_ITB 0
518 #define CFG_DSU_ITB 0
519 #endif
519 #endif
520
520
521 #if defined CONFIG_DSU_ATRACESZ1
521 #if defined CONFIG_DSU_ATRACESZ1
522 #define CFG_DSU_ATB 1
522 #define CFG_DSU_ATB 1
523 #elif CONFIG_DSU_ATRACESZ2
523 #elif CONFIG_DSU_ATRACESZ2
524 #define CFG_DSU_ATB 2
524 #define CFG_DSU_ATB 2
525 #elif CONFIG_DSU_ATRACESZ4
525 #elif CONFIG_DSU_ATRACESZ4
526 #define CFG_DSU_ATB 4
526 #define CFG_DSU_ATB 4
527 #elif CONFIG_DSU_ATRACESZ8
527 #elif CONFIG_DSU_ATRACESZ8
528 #define CFG_DSU_ATB 8
528 #define CFG_DSU_ATB 8
529 #elif CONFIG_DSU_ATRACESZ16
529 #elif CONFIG_DSU_ATRACESZ16
530 #define CFG_DSU_ATB 16
530 #define CFG_DSU_ATB 16
531 #else
531 #else
532 #define CFG_DSU_ATB 0
532 #define CFG_DSU_ATB 0
533 #endif
533 #endif
534
534
535 #ifndef CONFIG_LEON3FT_EN
535 #ifndef CONFIG_LEON3FT_EN
536 #define CONFIG_LEON3FT_EN 0
536 #define CONFIG_LEON3FT_EN 0
537 #endif
537 #endif
538
538
539 #if defined CONFIG_IUFT_PAR
539 #if defined CONFIG_IUFT_PAR
540 #define CONFIG_IUFT_EN 1
540 #define CONFIG_IUFT_EN 1
541 #elif defined CONFIG_IUFT_DMR
541 #elif defined CONFIG_IUFT_DMR
542 #define CONFIG_IUFT_EN 2
542 #define CONFIG_IUFT_EN 2
543 #elif defined CONFIG_IUFT_BCH
543 #elif defined CONFIG_IUFT_BCH
544 #define CONFIG_IUFT_EN 3
544 #define CONFIG_IUFT_EN 3
545 #elif defined CONFIG_IUFT_TMR
545 #elif defined CONFIG_IUFT_TMR
546 #define CONFIG_IUFT_EN 4
546 #define CONFIG_IUFT_EN 4
547 #else
547 #else
548 #define CONFIG_IUFT_EN 0
548 #define CONFIG_IUFT_EN 0
549 #endif
549 #endif
550 #ifndef CONFIG_RF_ERRINJ
550 #ifndef CONFIG_RF_ERRINJ
551 #define CONFIG_RF_ERRINJ 0
551 #define CONFIG_RF_ERRINJ 0
552 #endif
552 #endif
553
553
554 #ifndef CONFIG_FPUFT_EN
554 #ifndef CONFIG_FPUFT_EN
555 #define CONFIG_FPUFT 0
555 #define CONFIG_FPUFT 0
556 #else
556 #else
557 #ifdef CONFIG_FPU_GRFPU
557 #ifdef CONFIG_FPU_GRFPU
558 #define CONFIG_FPUFT 2
558 #define CONFIG_FPUFT 2
559 #else
559 #else
560 #define CONFIG_FPUFT 1
560 #define CONFIG_FPUFT 1
561 #endif
561 #endif
562 #endif
562 #endif
563
563
564 #ifndef CONFIG_CACHE_FT_EN
564 #ifndef CONFIG_CACHE_FT_EN
565 #define CONFIG_CACHE_FT_EN 0
565 #define CONFIG_CACHE_FT_EN 0
566 #endif
566 #endif
567 #ifndef CONFIG_CACHE_ERRINJ
567 #ifndef CONFIG_CACHE_ERRINJ
568 #define CONFIG_CACHE_ERRINJ 0
568 #define CONFIG_CACHE_ERRINJ 0
569 #endif
569 #endif
570
570
571 #ifndef CONFIG_LEON3_NETLIST
571 #ifndef CONFIG_LEON3_NETLIST
572 #define CONFIG_LEON3_NETLIST 0
572 #define CONFIG_LEON3_NETLIST 0
573 #endif
573 #endif
574
574
575 #ifdef CONFIG_DEBUG_PC32
575 #ifdef CONFIG_DEBUG_PC32
576 #define CFG_DEBUG_PC32 0
576 #define CFG_DEBUG_PC32 0
577 #else
577 #else
578 #define CFG_DEBUG_PC32 2
578 #define CFG_DEBUG_PC32 2
579 #endif
579 #endif
580 #ifndef CONFIG_IU_DISAS
580 #ifndef CONFIG_IU_DISAS
581 #define CONFIG_IU_DISAS 0
581 #define CONFIG_IU_DISAS 0
582 #endif
582 #endif
583 #ifndef CONFIG_IU_DISAS_NET
583 #ifndef CONFIG_IU_DISAS_NET
584 #define CONFIG_IU_DISAS_NET 0
584 #define CONFIG_IU_DISAS_NET 0
585 #endif
585 #endif
586
586
587
587
588 #ifndef CONFIG_AHB_SPLIT
588 #ifndef CONFIG_AHB_SPLIT
589 #define CONFIG_AHB_SPLIT 0
589 #define CONFIG_AHB_SPLIT 0
590 #endif
590 #endif
591
591
592 #ifndef CONFIG_AHB_RROBIN
592 #ifndef CONFIG_AHB_RROBIN
593 #define CONFIG_AHB_RROBIN 0
593 #define CONFIG_AHB_RROBIN 0
594 #endif
594 #endif
595
595
596 #ifndef CONFIG_AHB_IOADDR
596 #ifndef CONFIG_AHB_IOADDR
597 #define CONFIG_AHB_IOADDR FFF
597 #define CONFIG_AHB_IOADDR FFF
598 #endif
598 #endif
599
599
600 #ifndef CONFIG_APB_HADDR
600 #ifndef CONFIG_APB_HADDR
601 #define CONFIG_APB_HADDR 800
601 #define CONFIG_APB_HADDR 800
602 #endif
602 #endif
603
603
604 #ifndef CONFIG_AHB_MON
604 #ifndef CONFIG_AHB_MON
605 #define CONFIG_AHB_MON 0
605 #define CONFIG_AHB_MON 0
606 #endif
606 #endif
607
607
608 #ifndef CONFIG_AHB_MONERR
608 #ifndef CONFIG_AHB_MONERR
609 #define CONFIG_AHB_MONERR 0
609 #define CONFIG_AHB_MONERR 0
610 #endif
610 #endif
611
611
612 #ifndef CONFIG_AHB_MONWAR
612 #ifndef CONFIG_AHB_MONWAR
613 #define CONFIG_AHB_MONWAR 0
613 #define CONFIG_AHB_MONWAR 0
614 #endif
614 #endif
615
615
616 #ifndef CONFIG_DSU_UART
616 #ifndef CONFIG_DSU_UART
617 #define CONFIG_DSU_UART 0
617 #define CONFIG_DSU_UART 0
618 #endif
618 #endif
619
619
620
620
621 #ifndef CONFIG_DSU_JTAG
621 #ifndef CONFIG_DSU_JTAG
622 #define CONFIG_DSU_JTAG 0
622 #define CONFIG_DSU_JTAG 0
623 #endif
623 #endif
624
624
625 #ifndef CONFIG_DSU_ETH
625 #ifndef CONFIG_DSU_ETH
626 #define CONFIG_DSU_ETH 0
626 #define CONFIG_DSU_ETH 0
627 #endif
627 #endif
628
628
629 #ifndef CONFIG_DSU_IPMSB
629 #ifndef CONFIG_DSU_IPMSB
630 #define CONFIG_DSU_IPMSB C0A8
630 #define CONFIG_DSU_IPMSB C0A8
631 #endif
631 #endif
632
632
633 #ifndef CONFIG_DSU_IPLSB
633 #ifndef CONFIG_DSU_IPLSB
634 #define CONFIG_DSU_IPLSB 0033
634 #define CONFIG_DSU_IPLSB 0033
635 #endif
635 #endif
636
636
637 #ifndef CONFIG_DSU_ETHMSB
637 #ifndef CONFIG_DSU_ETHMSB
638 #define CONFIG_DSU_ETHMSB 020000
638 #define CONFIG_DSU_ETHMSB 020000
639 #endif
639 #endif
640
640
641 #ifndef CONFIG_DSU_ETHLSB
641 #ifndef CONFIG_DSU_ETHLSB
642 #define CONFIG_DSU_ETHLSB 000009
642 #define CONFIG_DSU_ETHLSB 000009
643 #endif
643 #endif
644
644
645 #if defined CONFIG_DSU_ETHSZ1
645 #if defined CONFIG_DSU_ETHSZ1
646 #define CFG_DSU_ETHB 1
646 #define CFG_DSU_ETHB 1
647 #elif CONFIG_DSU_ETHSZ2
647 #elif CONFIG_DSU_ETHSZ2
648 #define CFG_DSU_ETHB 2
648 #define CFG_DSU_ETHB 2
649 #elif CONFIG_DSU_ETHSZ4
649 #elif CONFIG_DSU_ETHSZ4
650 #define CFG_DSU_ETHB 4
650 #define CFG_DSU_ETHB 4
651 #elif CONFIG_DSU_ETHSZ8
651 #elif CONFIG_DSU_ETHSZ8
652 #define CFG_DSU_ETHB 8
652 #define CFG_DSU_ETHB 8
653 #elif CONFIG_DSU_ETHSZ16
653 #elif CONFIG_DSU_ETHSZ16
654 #define CFG_DSU_ETHB 16
654 #define CFG_DSU_ETHB 16
655 #elif CONFIG_DSU_ETHSZ32
655 #elif CONFIG_DSU_ETHSZ32
656 #define CFG_DSU_ETHB 32
656 #define CFG_DSU_ETHB 32
657 #else
657 #else
658 #define CFG_DSU_ETHB 1
658 #define CFG_DSU_ETHB 1
659 #endif
659 #endif
660
660
661 #ifndef CONFIG_DSU_ETH_PROG
661 #ifndef CONFIG_DSU_ETH_PROG
662 #define CONFIG_DSU_ETH_PROG 0
662 #define CONFIG_DSU_ETH_PROG 0
663 #endif
663 #endif
664
664
665
665
666 #ifndef CONFIG_SRCTRL
666 #ifndef CONFIG_SRCTRL
667 #define CONFIG_SRCTRL 0
667 #define CONFIG_SRCTRL 0
668 #endif
668 #endif
669
669
670 #ifndef CONFIG_SRCTRL_PROMWS
670 #ifndef CONFIG_SRCTRL_PROMWS
671 #define CONFIG_SRCTRL_PROMWS 0
671 #define CONFIG_SRCTRL_PROMWS 0
672 #endif
672 #endif
673
673
674 #ifndef CONFIG_SRCTRL_RAMWS
674 #ifndef CONFIG_SRCTRL_RAMWS
675 #define CONFIG_SRCTRL_RAMWS 0
675 #define CONFIG_SRCTRL_RAMWS 0
676 #endif
676 #endif
677
677
678 #ifndef CONFIG_SRCTRL_IOWS
678 #ifndef CONFIG_SRCTRL_IOWS
679 #define CONFIG_SRCTRL_IOWS 0
679 #define CONFIG_SRCTRL_IOWS 0
680 #endif
680 #endif
681
681
682 #ifndef CONFIG_SRCTRL_RMW
682 #ifndef CONFIG_SRCTRL_RMW
683 #define CONFIG_SRCTRL_RMW 0
683 #define CONFIG_SRCTRL_RMW 0
684 #endif
684 #endif
685
685
686 #ifndef CONFIG_SRCTRL_8BIT
686 #ifndef CONFIG_SRCTRL_8BIT
687 #define CONFIG_SRCTRL_8BIT 0
687 #define CONFIG_SRCTRL_8BIT 0
688 #endif
688 #endif
689
689
690
690
691 #ifndef CONFIG_SRCTRL_ROMASEL
691 #ifndef CONFIG_SRCTRL_ROMASEL
692 #define CONFIG_SRCTRL_ROMASEL 0
692 #define CONFIG_SRCTRL_ROMASEL 0
693 #endif
693 #endif
694
694
695 #if defined CONFIG_SRCTRL_SRBANKS1
695 #if defined CONFIG_SRCTRL_SRBANKS1
696 #define CFG_SR_CTRL_SRBANKS 1
696 #define CFG_SR_CTRL_SRBANKS 1
697 #elif defined CONFIG_SRCTRL_SRBANKS2
697 #elif defined CONFIG_SRCTRL_SRBANKS2
698 #define CFG_SR_CTRL_SRBANKS 2
698 #define CFG_SR_CTRL_SRBANKS 2
699 #elif defined CONFIG_SRCTRL_SRBANKS3
699 #elif defined CONFIG_SRCTRL_SRBANKS3
700 #define CFG_SR_CTRL_SRBANKS 3
700 #define CFG_SR_CTRL_SRBANKS 3
701 #elif defined CONFIG_SRCTRL_SRBANKS4
701 #elif defined CONFIG_SRCTRL_SRBANKS4
702 #define CFG_SR_CTRL_SRBANKS 4
702 #define CFG_SR_CTRL_SRBANKS 4
703 #elif defined CONFIG_SRCTRL_SRBANKS5
703 #elif defined CONFIG_SRCTRL_SRBANKS5
704 #define CFG_SR_CTRL_SRBANKS 5
704 #define CFG_SR_CTRL_SRBANKS 5
705 #else
705 #else
706 #define CFG_SR_CTRL_SRBANKS 1
706 #define CFG_SR_CTRL_SRBANKS 1
707 #endif
707 #endif
708
708
709 #if defined CONFIG_SRCTRL_BANKSZ0
709 #if defined CONFIG_SRCTRL_BANKSZ0
710 #define CFG_SR_CTRL_BANKSZ 0
710 #define CFG_SR_CTRL_BANKSZ 0
711 #elif defined CONFIG_SRCTRL_BANKSZ1
711 #elif defined CONFIG_SRCTRL_BANKSZ1
712 #define CFG_SR_CTRL_BANKSZ 1
712 #define CFG_SR_CTRL_BANKSZ 1
713 #elif defined CONFIG_SRCTRL_BANKSZ2
713 #elif defined CONFIG_SRCTRL_BANKSZ2
714 #define CFG_SR_CTRL_BANKSZ 2
714 #define CFG_SR_CTRL_BANKSZ 2
715 #elif defined CONFIG_SRCTRL_BANKSZ3
715 #elif defined CONFIG_SRCTRL_BANKSZ3
716 #define CFG_SR_CTRL_BANKSZ 3
716 #define CFG_SR_CTRL_BANKSZ 3
717 #elif defined CONFIG_SRCTRL_BANKSZ4
717 #elif defined CONFIG_SRCTRL_BANKSZ4
718 #define CFG_SR_CTRL_BANKSZ 4
718 #define CFG_SR_CTRL_BANKSZ 4
719 #elif defined CONFIG_SRCTRL_BANKSZ5
719 #elif defined CONFIG_SRCTRL_BANKSZ5
720 #define CFG_SR_CTRL_BANKSZ 5
720 #define CFG_SR_CTRL_BANKSZ 5
721 #elif defined CONFIG_SRCTRL_BANKSZ6
721 #elif defined CONFIG_SRCTRL_BANKSZ6
722 #define CFG_SR_CTRL_BANKSZ 6
722 #define CFG_SR_CTRL_BANKSZ 6
723 #elif defined CONFIG_SRCTRL_BANKSZ7
723 #elif defined CONFIG_SRCTRL_BANKSZ7
724 #define CFG_SR_CTRL_BANKSZ 7
724 #define CFG_SR_CTRL_BANKSZ 7
725 #elif defined CONFIG_SRCTRL_BANKSZ8
725 #elif defined CONFIG_SRCTRL_BANKSZ8
726 #define CFG_SR_CTRL_BANKSZ 8
726 #define CFG_SR_CTRL_BANKSZ 8
727 #elif defined CONFIG_SRCTRL_BANKSZ9
727 #elif defined CONFIG_SRCTRL_BANKSZ9
728 #define CFG_SR_CTRL_BANKSZ 9
728 #define CFG_SR_CTRL_BANKSZ 9
729 #elif defined CONFIG_SRCTRL_BANKSZ10
729 #elif defined CONFIG_SRCTRL_BANKSZ10
730 #define CFG_SR_CTRL_BANKSZ 10
730 #define CFG_SR_CTRL_BANKSZ 10
731 #elif defined CONFIG_SRCTRL_BANKSZ11
731 #elif defined CONFIG_SRCTRL_BANKSZ11
732 #define CFG_SR_CTRL_BANKSZ 11
732 #define CFG_SR_CTRL_BANKSZ 11
733 #elif defined CONFIG_SRCTRL_BANKSZ12
733 #elif defined CONFIG_SRCTRL_BANKSZ12
734 #define CFG_SR_CTRL_BANKSZ 12
734 #define CFG_SR_CTRL_BANKSZ 12
735 #elif defined CONFIG_SRCTRL_BANKSZ13
735 #elif defined CONFIG_SRCTRL_BANKSZ13
736 #define CFG_SR_CTRL_BANKSZ 13
736 #define CFG_SR_CTRL_BANKSZ 13
737 #else
737 #else
738 #define CFG_SR_CTRL_BANKSZ 0
738 #define CFG_SR_CTRL_BANKSZ 0
739 #endif
739 #endif
740 #ifndef CONFIG_MCTRL_LEON2
740 #ifndef CONFIG_MCTRL_LEON2
741 #define CONFIG_MCTRL_LEON2 0
741 #define CONFIG_MCTRL_LEON2 0
742 #endif
742 #endif
743
743
744 #ifndef CONFIG_MCTRL_SDRAM
744 #ifndef CONFIG_MCTRL_SDRAM
745 #define CONFIG_MCTRL_SDRAM 0
745 #define CONFIG_MCTRL_SDRAM 0
746 #endif
746 #endif
747
747
748 #ifndef CONFIG_MCTRL_SDRAM_SEPBUS
748 #ifndef CONFIG_MCTRL_SDRAM_SEPBUS
749 #define CONFIG_MCTRL_SDRAM_SEPBUS 0
749 #define CONFIG_MCTRL_SDRAM_SEPBUS 0
750 #endif
750 #endif
751
751
752 #ifndef CONFIG_MCTRL_SDRAM_INVCLK
752 #ifndef CONFIG_MCTRL_SDRAM_INVCLK
753 #define CONFIG_MCTRL_SDRAM_INVCLK 0
753 #define CONFIG_MCTRL_SDRAM_INVCLK 0
754 #endif
754 #endif
755
755
756 #ifndef CONFIG_MCTRL_SDRAM_BUS64
756 #ifndef CONFIG_MCTRL_SDRAM_BUS64
757 #define CONFIG_MCTRL_SDRAM_BUS64 0
757 #define CONFIG_MCTRL_SDRAM_BUS64 0
758 #endif
758 #endif
759
759
760 #ifndef CONFIG_MCTRL_8BIT
760 #ifndef CONFIG_MCTRL_8BIT
761 #define CONFIG_MCTRL_8BIT 0
761 #define CONFIG_MCTRL_8BIT 0
762 #endif
762 #endif
763
763
764 #ifndef CONFIG_MCTRL_16BIT
764 #ifndef CONFIG_MCTRL_16BIT
765 #define CONFIG_MCTRL_16BIT 0
765 #define CONFIG_MCTRL_16BIT 0
766 #endif
766 #endif
767
767
768 #ifndef CONFIG_MCTRL_5CS
768 #ifndef CONFIG_MCTRL_5CS
769 #define CONFIG_MCTRL_5CS 0
769 #define CONFIG_MCTRL_5CS 0
770 #endif
770 #endif
771
771
772 #ifndef CONFIG_MCTRL_EDAC
772 #ifndef CONFIG_MCTRL_EDAC
773 #define CONFIG_MCTRL_EDAC 0
773 #define CONFIG_MCTRL_EDAC 0
774 #endif
774 #endif
775
775
776 #ifndef CONFIG_MCTRL_PAGE
776 #ifndef CONFIG_MCTRL_PAGE
777 #define CONFIG_MCTRL_PAGE 0
777 #define CONFIG_MCTRL_PAGE 0
778 #endif
778 #endif
779
779
780 #ifndef CONFIG_MCTRL_PROGPAGE
780 #ifndef CONFIG_MCTRL_PROGPAGE
781 #define CONFIG_MCTRL_PROGPAGE 0
781 #define CONFIG_MCTRL_PROGPAGE 0
782 #endif
782 #endif
783
783
784 #ifndef CONFIG_SDCTRL
784 #ifndef CONFIG_SDCTRL
785 #define CONFIG_SDCTRL 0
785 #define CONFIG_SDCTRL 0
786 #endif
786 #endif
787
787
788 #ifndef CONFIG_SDCTRL_SEPBUS
788 #ifndef CONFIG_SDCTRL_SEPBUS
789 #define CONFIG_SDCTRL_SEPBUS 0
789 #define CONFIG_SDCTRL_SEPBUS 0
790 #endif
790 #endif
791
791
792 #ifndef CONFIG_SDCTRL_INVCLK
792 #ifndef CONFIG_SDCTRL_INVCLK
793 #define CONFIG_SDCTRL_INVCLK 0
793 #define CONFIG_SDCTRL_INVCLK 0
794 #endif
794 #endif
795
795
796 #ifndef CONFIG_SDCTRL_BUS64
796 #ifndef CONFIG_SDCTRL_BUS64
797 #define CONFIG_SDCTRL_BUS64 0
797 #define CONFIG_SDCTRL_BUS64 0
798 #endif
798 #endif
799
799
800 #ifndef CONFIG_SDCTRL_PAGE
800 #ifndef CONFIG_SDCTRL_PAGE
801 #define CONFIG_SDCTRL_PAGE 0
801 #define CONFIG_SDCTRL_PAGE 0
802 #endif
802 #endif
803
803
804 #ifndef CONFIG_SDCTRL_PROGPAGE
804 #ifndef CONFIG_SDCTRL_PROGPAGE
805 #define CONFIG_SDCTRL_PROGPAGE 0
805 #define CONFIG_SDCTRL_PROGPAGE 0
806 #endif
806 #endif
807
807
808 #ifndef CONFIG_AHBROM_ENABLE
808 #ifndef CONFIG_AHBROM_ENABLE
809 #define CONFIG_AHBROM_ENABLE 0
809 #define CONFIG_AHBROM_ENABLE 0
810 #endif
810 #endif
811
811
812 #ifndef CONFIG_AHBROM_START
812 #ifndef CONFIG_AHBROM_START
813 #define CONFIG_AHBROM_START 000
813 #define CONFIG_AHBROM_START 000
814 #endif
814 #endif
815
815
816 #ifndef CONFIG_AHBROM_PIPE
816 #ifndef CONFIG_AHBROM_PIPE
817 #define CONFIG_AHBROM_PIPE 0
817 #define CONFIG_AHBROM_PIPE 0
818 #endif
818 #endif
819
819
820 #if (CONFIG_AHBROM_START == 0) && (CONFIG_AHBROM_ENABLE == 1)
820 #if (CONFIG_AHBROM_START == 0) && (CONFIG_AHBROM_ENABLE == 1)
821 #define CONFIG_ROM_START 100
821 #define CONFIG_ROM_START 100
822 #else
822 #else
823 #define CONFIG_ROM_START 000
823 #define CONFIG_ROM_START 000
824 #endif
824 #endif
825
825
826
826
827 #ifndef CONFIG_AHBRAM_ENABLE
827 #ifndef CONFIG_AHBRAM_ENABLE
828 #define CONFIG_AHBRAM_ENABLE 0
828 #define CONFIG_AHBRAM_ENABLE 0
829 #endif
829 #endif
830
830
831 #ifndef CONFIG_AHBRAM_START
831 #ifndef CONFIG_AHBRAM_START
832 #define CONFIG_AHBRAM_START A00
832 #define CONFIG_AHBRAM_START A00
833 #endif
833 #endif
834
834
835 #if defined CONFIG_AHBRAM_SZ1
835 #if defined CONFIG_AHBRAM_SZ1
836 #define CFG_AHBRAMSZ 1
836 #define CFG_AHBRAMSZ 1
837 #elif CONFIG_AHBRAM_SZ2
837 #elif CONFIG_AHBRAM_SZ2
838 #define CFG_AHBRAMSZ 2
838 #define CFG_AHBRAMSZ 2
839 #elif CONFIG_AHBRAM_SZ4
839 #elif CONFIG_AHBRAM_SZ4
840 #define CFG_AHBRAMSZ 4
840 #define CFG_AHBRAMSZ 4
841 #elif CONFIG_AHBRAM_SZ8
841 #elif CONFIG_AHBRAM_SZ8
842 #define CFG_AHBRAMSZ 8
842 #define CFG_AHBRAMSZ 8
843 #elif CONFIG_AHBRAM_SZ16
843 #elif CONFIG_AHBRAM_SZ16
844 #define CFG_AHBRAMSZ 16
844 #define CFG_AHBRAMSZ 16
845 #elif CONFIG_AHBRAM_SZ32
845 #elif CONFIG_AHBRAM_SZ32
846 #define CFG_AHBRAMSZ 32
846 #define CFG_AHBRAMSZ 32
847 #elif CONFIG_AHBRAM_SZ64
847 #elif CONFIG_AHBRAM_SZ64
848 #define CFG_AHBRAMSZ 64
848 #define CFG_AHBRAMSZ 64
849 #else
849 #else
850 #define CFG_AHBRAMSZ 1
850 #define CFG_AHBRAMSZ 1
851 #endif
851 #endif
852
852
853 #ifndef CONFIG_GRETH_ENABLE
853 #ifndef CONFIG_GRETH_ENABLE
854 #define CONFIG_GRETH_ENABLE 0
854 #define CONFIG_GRETH_ENABLE 0
855 #endif
855 #endif
856
856
857 #ifndef CONFIG_GRETH_GIGA
857 #ifndef CONFIG_GRETH_GIGA
858 #define CONFIG_GRETH_GIGA 0
858 #define CONFIG_GRETH_GIGA 0
859 #endif
859 #endif
860
860
861 #if defined CONFIG_GRETH_FIFO4
861 #if defined CONFIG_GRETH_FIFO4
862 #define CFG_GRETH_FIFO 4
862 #define CFG_GRETH_FIFO 4
863 #elif defined CONFIG_GRETH_FIFO8
863 #elif defined CONFIG_GRETH_FIFO8
864 #define CFG_GRETH_FIFO 8
864 #define CFG_GRETH_FIFO 8
865 #elif defined CONFIG_GRETH_FIFO16
865 #elif defined CONFIG_GRETH_FIFO16
866 #define CFG_GRETH_FIFO 16
866 #define CFG_GRETH_FIFO 16
867 #elif defined CONFIG_GRETH_FIFO32
867 #elif defined CONFIG_GRETH_FIFO32
868 #define CFG_GRETH_FIFO 32
868 #define CFG_GRETH_FIFO 32
869 #elif defined CONFIG_GRETH_FIFO64
869 #elif defined CONFIG_GRETH_FIFO64
870 #define CFG_GRETH_FIFO 64
870 #define CFG_GRETH_FIFO 64
871 #else
871 #else
872 #define CFG_GRETH_FIFO 8
872 #define CFG_GRETH_FIFO 8
873 #endif
873 #endif
874
874
875 #ifndef CONFIG_CAN_ENABLE
875 #ifndef CONFIG_CAN_ENABLE
876 #define CONFIG_CAN_ENABLE 0
876 #define CONFIG_CAN_ENABLE 0
877 #endif
877 #endif
878
878
879 #ifndef CONFIG_CANIO
879 #ifndef CONFIG_CANIO
880 #define CONFIG_CANIO 0
880 #define CONFIG_CANIO 0
881 #endif
881 #endif
882
882
883 #ifndef CONFIG_CANIRQ
883 #ifndef CONFIG_CANIRQ
884 #define CONFIG_CANIRQ 0
884 #define CONFIG_CANIRQ 0
885 #endif
885 #endif
886
886
887 #ifndef CONFIG_CANLOOP
887 #ifndef CONFIG_CANLOOP
888 #define CONFIG_CANLOOP 0
888 #define CONFIG_CANLOOP 0
889 #endif
889 #endif
890
890
891 #ifndef CONFIG_CAN_SYNCRST
891 #ifndef CONFIG_CAN_SYNCRST
892 #define CONFIG_CAN_SYNCRST 0
892 #define CONFIG_CAN_SYNCRST 0
893 #endif
893 #endif
894
894
895
895
896 #ifndef CONFIG_CAN_FT
896 #ifndef CONFIG_CAN_FT
897 #define CONFIG_CAN_FT 0
897 #define CONFIG_CAN_FT 0
898 #endif
898 #endif
899 #if defined CONFIG_PCI_SIMPLE_TARGET
899 #if defined CONFIG_PCI_SIMPLE_TARGET
900 #define CFG_PCITYPE 1
900 #define CFG_PCITYPE 1
901 #elif defined CONFIG_PCI_MASTER_TARGET_DMA
901 #elif defined CONFIG_PCI_MASTER_TARGET_DMA
902 #define CFG_PCITYPE 3
902 #define CFG_PCITYPE 3
903 #elif defined CONFIG_PCI_MASTER_TARGET
903 #elif defined CONFIG_PCI_MASTER_TARGET
904 #define CFG_PCITYPE 2
904 #define CFG_PCITYPE 2
905 #else
905 #else
906 #define CFG_PCITYPE 0
906 #define CFG_PCITYPE 0
907 #endif
907 #endif
908
908
909 #ifndef CONFIG_PCI_VENDORID
909 #ifndef CONFIG_PCI_VENDORID
910 #define CONFIG_PCI_VENDORID 0
910 #define CONFIG_PCI_VENDORID 0
911 #endif
911 #endif
912
912
913 #ifndef CONFIG_PCI_DEVICEID
913 #ifndef CONFIG_PCI_DEVICEID
914 #define CONFIG_PCI_DEVICEID 0
914 #define CONFIG_PCI_DEVICEID 0
915 #endif
915 #endif
916
916
917 #ifndef CONFIG_PCI_REVID
917 #ifndef CONFIG_PCI_REVID
918 #define CONFIG_PCI_REVID 0
918 #define CONFIG_PCI_REVID 0
919 #endif
919 #endif
920
920
921 #if defined CONFIG_PCI_FIFO0
921 #if defined CONFIG_PCI_FIFO0
922 #define CFG_PCIFIFO 8
922 #define CFG_PCIFIFO 8
923 #define CFG_PCI_ENFIFO 0
923 #define CFG_PCI_ENFIFO 0
924 #elif defined CONFIG_PCI_FIFO16
924 #elif defined CONFIG_PCI_FIFO16
925 #define CFG_PCIFIFO 16
925 #define CFG_PCIFIFO 16
926 #elif defined CONFIG_PCI_FIFO32
926 #elif defined CONFIG_PCI_FIFO32
927 #define CFG_PCIFIFO 32
927 #define CFG_PCIFIFO 32
928 #elif defined CONFIG_PCI_FIFO64
928 #elif defined CONFIG_PCI_FIFO64
929 #define CFG_PCIFIFO 64
929 #define CFG_PCIFIFO 64
930 #elif defined CONFIG_PCI_FIFO128
930 #elif defined CONFIG_PCI_FIFO128
931 #define CFG_PCIFIFO 128
931 #define CFG_PCIFIFO 128
932 #elif defined CONFIG_PCI_FIFO256
932 #elif defined CONFIG_PCI_FIFO256
933 #define CFG_PCIFIFO 256
933 #define CFG_PCIFIFO 256
934 #else
934 #else
935 #define CFG_PCIFIFO 8
935 #define CFG_PCIFIFO 8
936 #endif
936 #endif
937
937
938 #ifndef CFG_PCI_ENFIFO
938 #ifndef CFG_PCI_ENFIFO
939 #define CFG_PCI_ENFIFO 1
939 #define CFG_PCI_ENFIFO 1
940 #endif
940 #endif
941
941
942
942
943 #ifndef CONFIG_PCI_ARBITER_APB
943 #ifndef CONFIG_PCI_ARBITER_APB
944 #define CONFIG_PCI_ARBITER_APB 0
944 #define CONFIG_PCI_ARBITER_APB 0
945 #endif
945 #endif
946
946
947 #ifndef CONFIG_PCI_ARBITER
947 #ifndef CONFIG_PCI_ARBITER
948 #define CONFIG_PCI_ARBITER 0
948 #define CONFIG_PCI_ARBITER 0
949 #endif
949 #endif
950
950
951 #ifndef CONFIG_PCI_ARBITER_NREQ
951 #ifndef CONFIG_PCI_ARBITER_NREQ
952 #define CONFIG_PCI_ARBITER_NREQ 4
952 #define CONFIG_PCI_ARBITER_NREQ 4
953 #endif
953 #endif
954
954
955 #ifndef CONFIG_PCI_TRACE
955 #ifndef CONFIG_PCI_TRACE
956 #define CONFIG_PCI_TRACE 0
956 #define CONFIG_PCI_TRACE 0
957 #endif
957 #endif
958
958
959 #if defined CONFIG_PCI_TRACE512
959 #if defined CONFIG_PCI_TRACE512
960 #define CFG_PCI_TRACEBUF 512
960 #define CFG_PCI_TRACEBUF 512
961 #elif defined CONFIG_PCI_TRACE1024
961 #elif defined CONFIG_PCI_TRACE1024
962 #define CFG_PCI_TRACEBUF 1024
962 #define CFG_PCI_TRACEBUF 1024
963 #elif defined CONFIG_PCI_TRACE2048
963 #elif defined CONFIG_PCI_TRACE2048
964 #define CFG_PCI_TRACEBUF 2048
964 #define CFG_PCI_TRACEBUF 2048
965 #elif defined CONFIG_PCI_TRACE4096
965 #elif defined CONFIG_PCI_TRACE4096
966 #define CFG_PCI_TRACEBUF 4096
966 #define CFG_PCI_TRACEBUF 4096
967 #else
967 #else
968 #define CFG_PCI_TRACEBUF 256
968 #define CFG_PCI_TRACEBUF 256
969 #endif
969 #endif
970
970
971
971
972 #ifndef CONFIG_SPW_ENABLE
972 #ifndef CONFIG_SPW_ENABLE
973 #define CONFIG_SPW_ENABLE 0
973 #define CONFIG_SPW_ENABLE 0
974 #endif
974 #endif
975
975
976 #ifndef CONFIG_SPW_NUM
976 #ifndef CONFIG_SPW_NUM
977 #define CONFIG_SPW_NUM 1
977 #define CONFIG_SPW_NUM 1
978 #endif
978 #endif
979
979
980 #if defined CONFIG_SPW_AHBFIFO4
980 #if defined CONFIG_SPW_AHBFIFO4
981 #define CONFIG_SPW_AHBFIFO 4
981 #define CONFIG_SPW_AHBFIFO 4
982 #elif defined CONFIG_SPW_AHBFIFO8
982 #elif defined CONFIG_SPW_AHBFIFO8
983 #define CONFIG_SPW_AHBFIFO 8
983 #define CONFIG_SPW_AHBFIFO 8
984 #elif defined CONFIG_SPW_AHBFIFO16
984 #elif defined CONFIG_SPW_AHBFIFO16
985 #define CONFIG_SPW_AHBFIFO 16
985 #define CONFIG_SPW_AHBFIFO 16
986 #elif defined CONFIG_SPW_AHBFIFO32
986 #elif defined CONFIG_SPW_AHBFIFO32
987 #define CONFIG_SPW_AHBFIFO 32
987 #define CONFIG_SPW_AHBFIFO 32
988 #elif defined CONFIG_SPW_AHBFIFO64
988 #elif defined CONFIG_SPW_AHBFIFO64
989 #define CONFIG_SPW_AHBFIFO 64
989 #define CONFIG_SPW_AHBFIFO 64
990 #else
990 #else
991 #define CONFIG_SPW_AHBFIFO 4
991 #define CONFIG_SPW_AHBFIFO 4
992 #endif
992 #endif
993
993
994 #if defined CONFIG_SPW_RXFIFO16
994 #if defined CONFIG_SPW_RXFIFO16
995 #define CONFIG_SPW_RXFIFO 16
995 #define CONFIG_SPW_RXFIFO 16
996 #elif defined CONFIG_SPW_RXFIFO32
996 #elif defined CONFIG_SPW_RXFIFO32
997 #define CONFIG_SPW_RXFIFO 32
997 #define CONFIG_SPW_RXFIFO 32
998 #elif defined CONFIG_SPW_RXFIFO64
998 #elif defined CONFIG_SPW_RXFIFO64
999 #define CONFIG_SPW_RXFIFO 64
999 #define CONFIG_SPW_RXFIFO 64
1000 #else
1000 #else
1001 #define CONFIG_SPW_RXFIFO 16
1001 #define CONFIG_SPW_RXFIFO 16
1002 #endif
1002 #endif
1003
1003
1004 #ifndef CONFIG_SPW_RMAP
1004 #ifndef CONFIG_SPW_RMAP
1005 #define CONFIG_SPW_RMAP 0
1005 #define CONFIG_SPW_RMAP 0
1006 #endif
1006 #endif
1007
1007
1008 #if defined CONFIG_SPW_RMAPBUF2
1008 #if defined CONFIG_SPW_RMAPBUF2
1009 #define CONFIG_SPW_RMAPBUF 2
1009 #define CONFIG_SPW_RMAPBUF 2
1010 #elif defined CONFIG_SPW_RMAPBUF4
1010 #elif defined CONFIG_SPW_RMAPBUF4
1011 #define CONFIG_SPW_RMAPBUF 4
1011 #define CONFIG_SPW_RMAPBUF 4
1012 #elif defined CONFIG_SPW_RMAPBUF6
1012 #elif defined CONFIG_SPW_RMAPBUF6
1013 #define CONFIG_SPW_RMAPBUF 6
1013 #define CONFIG_SPW_RMAPBUF 6
1014 #elif defined CONFIG_SPW_RMAPBUF8
1014 #elif defined CONFIG_SPW_RMAPBUF8
1015 #define CONFIG_SPW_RMAPBUF 8
1015 #define CONFIG_SPW_RMAPBUF 8
1016 #else
1016 #else
1017 #define CONFIG_SPW_RMAPBUF 4
1017 #define CONFIG_SPW_RMAPBUF 4
1018 #endif
1018 #endif
1019
1019
1020 #ifndef CONFIG_SPW_RMAPCRC
1020 #ifndef CONFIG_SPW_RMAPCRC
1021 #define CONFIG_SPW_RMAPCRC 0
1021 #define CONFIG_SPW_RMAPCRC 0
1022 #endif
1022 #endif
1023
1023
1024 #ifndef CONFIG_SPW_RXUNAL
1024 #ifndef CONFIG_SPW_RXUNAL
1025 #define CONFIG_SPW_RXUNAL 0
1025 #define CONFIG_SPW_RXUNAL 0
1026 #endif
1026 #endif
1027
1027
1028 #ifndef CONFIG_SPW_NETLIST
1028 #ifndef CONFIG_SPW_NETLIST
1029 #define CONFIG_SPW_NETLIST 0
1029 #define CONFIG_SPW_NETLIST 0
1030 #endif
1030 #endif
1031
1031
1032 #ifndef CONFIG_SPW_FT
1032 #ifndef CONFIG_SPW_FT
1033 #define CONFIG_SPW_FT 0
1033 #define CONFIG_SPW_FT 0
1034 #endif
1034 #endif
1035
1035
1036 #if defined CONFIG_SPW_GRSPW1
1036 #if defined CONFIG_SPW_GRSPW1
1037 #define CONFIG_SPW_GRSPW 1
1037 #define CONFIG_SPW_GRSPW 1
1038 #else
1038 #else
1039 #define CONFIG_SPW_GRSPW 2
1039 #define CONFIG_SPW_GRSPW 2
1040 #endif
1040 #endif
1041
1041
1042 #ifndef CONFIG_SPW_DMACHAN
1042 #ifndef CONFIG_SPW_DMACHAN
1043 #define CONFIG_SPW_DMACHAN 1
1043 #define CONFIG_SPW_DMACHAN 1
1044 #endif
1044 #endif
1045
1045
1046 #ifndef CONFIG_SPW_PORTS
1046 #ifndef CONFIG_SPW_PORTS
1047 #define CONFIG_SPW_PORTS 1
1047 #define CONFIG_SPW_PORTS 1
1048 #endif
1048 #endif
1049
1049
1050 #if defined CONFIG_SPW_RX_SDR
1050 #if defined CONFIG_SPW_RX_SDR
1051 #define CONFIG_SPW_INPUT 2
1051 #define CONFIG_SPW_INPUT 2
1052 #elif defined CONFIG_SPW_RX_DDR
1052 #elif defined CONFIG_SPW_RX_DDR
1053 #define CONFIG_SPW_INPUT 3
1053 #define CONFIG_SPW_INPUT 3
1054 #elif defined CONFIG_SPW_RX_XOR
1054 #elif defined CONFIG_SPW_RX_XOR
1055 #define CONFIG_SPW_INPUT 0
1055 #define CONFIG_SPW_INPUT 0
1056 #elif defined CONFIG_SPW_RX_AFLEX
1056 #elif defined CONFIG_SPW_RX_AFLEX
1057 #define CONFIG_SPW_INPUT 1
1057 #define CONFIG_SPW_INPUT 1
1058 #else
1058 #else
1059 #define CONFIG_SPW_INPUT 2
1059 #define CONFIG_SPW_INPUT 2
1060 #endif
1060 #endif
1061
1061
1062 #if defined CONFIG_SPW_TX_SDR
1062 #if defined CONFIG_SPW_TX_SDR
1063 #define CONFIG_SPW_OUTPUT 0
1063 #define CONFIG_SPW_OUTPUT 0
1064 #elif defined CONFIG_SPW_TX_DDR
1064 #elif defined CONFIG_SPW_TX_DDR
1065 #define CONFIG_SPW_OUTPUT 1
1065 #define CONFIG_SPW_OUTPUT 1
1066 #elif defined CONFIG_SPW_TX_AFLEX
1066 #elif defined CONFIG_SPW_TX_AFLEX
1067 #define CONFIG_SPW_OUTPUT 2
1067 #define CONFIG_SPW_OUTPUT 2
1068 #else
1068 #else
1069 #define CONFIG_SPW_OUTPUT 0
1069 #define CONFIG_SPW_OUTPUT 0
1070 #endif
1070 #endif
1071
1071
1072 #ifndef CONFIG_SPW_RTSAME
1072 #ifndef CONFIG_SPW_RTSAME
1073 #define CONFIG_SPW_RTSAME 0
1073 #define CONFIG_SPW_RTSAME 0
1074 #endif
1074 #endif
1075 #ifndef CONFIG_UART1_ENABLE
1075 #ifndef CONFIG_UART1_ENABLE
1076 #define CONFIG_UART1_ENABLE 0
1076 #define CONFIG_UART1_ENABLE 0
1077 #endif
1077 #endif
1078
1078
1079 #if defined CONFIG_UA1_FIFO1
1079 #if defined CONFIG_UA1_FIFO1
1080 #define CFG_UA1_FIFO 1
1080 #define CFG_UA1_FIFO 1
1081 #elif defined CONFIG_UA1_FIFO2
1081 #elif defined CONFIG_UA1_FIFO2
1082 #define CFG_UA1_FIFO 2
1082 #define CFG_UA1_FIFO 2
1083 #elif defined CONFIG_UA1_FIFO4
1083 #elif defined CONFIG_UA1_FIFO4
1084 #define CFG_UA1_FIFO 4
1084 #define CFG_UA1_FIFO 4
1085 #elif defined CONFIG_UA1_FIFO8
1085 #elif defined CONFIG_UA1_FIFO8
1086 #define CFG_UA1_FIFO 8
1086 #define CFG_UA1_FIFO 8
1087 #elif defined CONFIG_UA1_FIFO16
1087 #elif defined CONFIG_UA1_FIFO16
1088 #define CFG_UA1_FIFO 16
1088 #define CFG_UA1_FIFO 16
1089 #elif defined CONFIG_UA1_FIFO32
1089 #elif defined CONFIG_UA1_FIFO32
1090 #define CFG_UA1_FIFO 32
1090 #define CFG_UA1_FIFO 32
1091 #else
1091 #else
1092 #define CFG_UA1_FIFO 1
1092 #define CFG_UA1_FIFO 1
1093 #endif
1093 #endif
1094
1094
1095 #ifndef CONFIG_UART2_ENABLE
1095 #ifndef CONFIG_UART2_ENABLE
1096 #define CONFIG_UART2_ENABLE 0
1096 #define CONFIG_UART2_ENABLE 0
1097 #endif
1097 #endif
1098
1098
1099 #if defined CONFIG_UA2_FIFO1
1099 #if defined CONFIG_UA2_FIFO1
1100 #define CFG_UA2_FIFO 1
1100 #define CFG_UA2_FIFO 1
1101 #elif defined CONFIG_UA2_FIFO2
1101 #elif defined CONFIG_UA2_FIFO2
1102 #define CFG_UA2_FIFO 2
1102 #define CFG_UA2_FIFO 2
1103 #elif defined CONFIG_UA2_FIFO4
1103 #elif defined CONFIG_UA2_FIFO4
1104 #define CFG_UA2_FIFO 4
1104 #define CFG_UA2_FIFO 4
1105 #elif defined CONFIG_UA2_FIFO8
1105 #elif defined CONFIG_UA2_FIFO8
1106 #define CFG_UA2_FIFO 8
1106 #define CFG_UA2_FIFO 8
1107 #elif defined CONFIG_UA2_FIFO16
1107 #elif defined CONFIG_UA2_FIFO16
1108 #define CFG_UA2_FIFO 16
1108 #define CFG_UA2_FIFO 16
1109 #elif defined CONFIG_UA2_FIFO32
1109 #elif defined CONFIG_UA2_FIFO32
1110 #define CFG_UA2_FIFO 32
1110 #define CFG_UA2_FIFO 32
1111 #else
1111 #else
1112 #define CFG_UA2_FIFO 1
1112 #define CFG_UA2_FIFO 1
1113 #endif
1113 #endif
1114
1114
1115 #ifndef CONFIG_IRQ3_ENABLE
1115 #ifndef CONFIG_IRQ3_ENABLE
1116 #define CONFIG_IRQ3_ENABLE 0
1116 #define CONFIG_IRQ3_ENABLE 0
1117 #endif
1117 #endif
1118 #ifndef CONFIG_IRQ3_NSEC
1118 #ifndef CONFIG_IRQ3_NSEC
1119 #define CONFIG_IRQ3_NSEC 0
1119 #define CONFIG_IRQ3_NSEC 0
1120 #endif
1120 #endif
1121 #ifndef CONFIG_GPT_ENABLE
1121 #ifndef CONFIG_GPT_ENABLE
1122 #define CONFIG_GPT_ENABLE 0
1122 #define CONFIG_GPT_ENABLE 0
1123 #endif
1123 #endif
1124
1124
1125 #ifndef CONFIG_GPT_NTIM
1125 #ifndef CONFIG_GPT_NTIM
1126 #define CONFIG_GPT_NTIM 1
1126 #define CONFIG_GPT_NTIM 1
1127 #endif
1127 #endif
1128
1128
1129 #ifndef CONFIG_GPT_SW
1129 #ifndef CONFIG_GPT_SW
1130 #define CONFIG_GPT_SW 8
1130 #define CONFIG_GPT_SW 8
1131 #endif
1131 #endif
1132
1132
1133 #ifndef CONFIG_GPT_TW
1133 #ifndef CONFIG_GPT_TW
1134 #define CONFIG_GPT_TW 8
1134 #define CONFIG_GPT_TW 8
1135 #endif
1135 #endif
1136
1136
1137 #ifndef CONFIG_GPT_IRQ
1137 #ifndef CONFIG_GPT_IRQ
1138 #define CONFIG_GPT_IRQ 8
1138 #define CONFIG_GPT_IRQ 8
1139 #endif
1139 #endif
1140
1140
1141 #ifndef CONFIG_GPT_SEPIRQ
1141 #ifndef CONFIG_GPT_SEPIRQ
1142 #define CONFIG_GPT_SEPIRQ 0
1142 #define CONFIG_GPT_SEPIRQ 0
1143 #endif
1143 #endif
1144 #ifndef CONFIG_GPT_ENABLE
1144 #ifndef CONFIG_GPT_ENABLE
1145 #define CONFIG_GPT_ENABLE 0
1145 #define CONFIG_GPT_ENABLE 0
1146 #endif
1146 #endif
1147
1147
1148 #ifndef CONFIG_GPT_NTIM
1148 #ifndef CONFIG_GPT_NTIM
1149 #define CONFIG_GPT_NTIM 1
1149 #define CONFIG_GPT_NTIM 1
1150 #endif
1150 #endif
1151
1151
1152 #ifndef CONFIG_GPT_SW
1152 #ifndef CONFIG_GPT_SW
1153 #define CONFIG_GPT_SW 8
1153 #define CONFIG_GPT_SW 8
1154 #endif
1154 #endif
1155
1155
1156 #ifndef CONFIG_GPT_TW
1156 #ifndef CONFIG_GPT_TW
1157 #define CONFIG_GPT_TW 8
1157 #define CONFIG_GPT_TW 8
1158 #endif
1158 #endif
1159
1159
1160 #ifndef CONFIG_GPT_IRQ
1160 #ifndef CONFIG_GPT_IRQ
1161 #define CONFIG_GPT_IRQ 8
1161 #define CONFIG_GPT_IRQ 8
1162 #endif
1162 #endif
1163
1163
1164 #ifndef CONFIG_GPT_SEPIRQ
1164 #ifndef CONFIG_GPT_SEPIRQ
1165 #define CONFIG_GPT_SEPIRQ 0
1165 #define CONFIG_GPT_SEPIRQ 0
1166 #endif
1166 #endif
1167
1167
1168 #ifndef CONFIG_GPT_WDOGEN
1168 #ifndef CONFIG_GPT_WDOGEN
1169 #define CONFIG_GPT_WDOGEN 0
1169 #define CONFIG_GPT_WDOGEN 0
1170 #endif
1170 #endif
1171
1171
1172 #ifndef CONFIG_GPT_WDOG
1172 #ifndef CONFIG_GPT_WDOG
1173 #define CONFIG_GPT_WDOG 0
1173 #define CONFIG_GPT_WDOG 0
1174 #endif
1174 #endif
1175
1175
1176 #ifndef CONFIG_GRGPIO_ENABLE
1176 #ifndef CONFIG_GRGPIO_ENABLE
1177 #define CONFIG_GRGPIO_ENABLE 0
1177 #define CONFIG_GRGPIO_ENABLE 0
1178 #endif
1178 #endif
1179 #ifndef CONFIG_GRGPIO_IMASK
1179 #ifndef CONFIG_GRGPIO_IMASK
1180 #define CONFIG_GRGPIO_IMASK 0000
1180 #define CONFIG_GRGPIO_IMASK 0000
1181 #endif
1181 #endif
1182 #ifndef CONFIG_GRGPIO_WIDTH
1182 #ifndef CONFIG_GRGPIO_WIDTH
1183 #define CONFIG_GRGPIO_WIDTH 1
1183 #define CONFIG_GRGPIO_WIDTH 1
1184 #endif
1184 #endif
1185
1185
1186
1186
1187 #ifndef CONFIG_DEBUG_UART
1187 #ifndef CONFIG_DEBUG_UART
1188 #define CONFIG_DEBUG_UART 0
1188 #define CONFIG_DEBUG_UART 0
1189 #endif
1189 #endif
Show file before | Show file after | Hide comments
@@ -1,209 +1,209
1 This leon3 design is tailored to the Xilinx SP605 Spartan6 board
1 This leon3 design is tailored to the Xilinx SP605 Spartan6 board
2
2
3 Simulation and synthesis
3 Simulation and synthesis
4 ------------------------
4 ------------------------
5
5
6 The design uses the Xilinx MIG memory interface with an AHB-2.0
6 The design uses the Xilinx MIG memory interface with an AHB-2.0
7 interface. The MIG source code cannot be distributed due to the
7 interface. The MIG source code cannot be distributed due to the
8 prohibitive Xilinx license, so the MIG must be re-generated with
8 prohibitive Xilinx license, so the MIG must be re-generated with
9 coregen before simulation and synthesis can be done.
9 coregen before simulation and synthesis can be done.
10
10
11 To generate the MIG and install tne Xilinx unisim simulation
11 To generate the MIG and install tne Xilinx unisim simulation
12 library, do as follows:
12 library, do as follows:
13
13
14 make mig
14 make mig
15 make install-secureip
15 make install-secureip
16
16
17 This will ONLY work with ISE-13.2 installed, and the XILINX variable
17 This will ONLY work with ISE-13.2 installed, and the XILINX variable
18 properly set in the shell. To synthesize the design, do
18 properly set in the shell. To synthesize the design, do
19
19
20 make ise
20 make ise
21
21
22 and then
22 and then
23
23
24 make ise-prog-fpga
24 make ise-prog-fpga
25
25
26 to program the FPGA.
26 to program the FPGA.
27
27
28 Design specifics
28 Design specifics
29 ----------------
29 ----------------
30
30
31 * System reset is mapped to the CPU RESET button
31 * System reset is mapped to the CPU RESET button
32
32
33 * The AHB and processor is clocked by a 60 MHz clock, generated
33 * The AHB and processor is clocked by a 60 MHz clock, generated
34 from the 33 MHz SYSACE clock using a DCM. You can change the frequency
34 from the 33 MHz SYSACE clock using a DCM. You can change the frequency
35 generation in the clocks menu of xconfig. The DDR3 (MIG) controller
35 generation in the clocks menu of xconfig. The DDR3 (MIG) controller
36 runs at 667 MHz.
36 runs at 667 MHz.
37
37
38 * The GRETH core is enabled and runs without problems at 100 Mbit.
38 * The GRETH core is enabled and runs without problems at 100 Mbit.
39 Ethernet debug link is enabled and has IP 192.168.0.51.
39 Ethernet debug link is enabled and has IP 192.168.0.51.
40 1 Gbit operation is also possible (requires grlib com release),
40 1 Gbit operation is also possible (requires grlib com release),
41 uncomment related timing constraints in the leon3mp.ucf first.
41 uncomment related timing constraints in the leon3mp.ucf first.
42
42
43 * 16-bit flash prom can be read at address 0. It can be programmed
43 * 16-bit flash prom can be read at address 0. It can be programmed
44 with GRMON version 1.1.16 or later.
44 with GRMON version 1.1.16 or later.
45
45
46 * DDR3 is working with the provided Xilinx MIG DDR3 controller.
46 * DDR3 is working with the provided Xilinx MIG DDR3 controller.
47 If you want to simulate this design, first install the secure
47 If you want to simulate this design, first install the secure
48 IP models with:
48 IP models with:
49
49
50 make install-secureip
50 make install-secureip
51
51
52 Then rebuild the scripts and simulation model:
52 Then rebuild the scripts and simulation model:
53
53
54 make distclean vsim
54 make distclean vsim
55
55
56 Modelsim v6.6e or newer is required to build the secure IP models.
56 Modelsim v6.6e or newer is required to build the secure IP models.
57 Note that the regular leon3 test bench cannot be run in simulation
57 Note that the regular leon3 test bench cannot be run in simulation
58 as the DDR3 model lacks data pre-load.
58 as the DDR3 model lacks data pre-load.
59
59
60 * The application UART1 is connected to the USB/UART connector
60 * The application UART1 is connected to the USB/UART connector
61
61
62 * The SVGA frame buffer uses a separate port on the DDR3 controller,
62 * The SVGA frame buffer uses a separate port on the DDR3 controller,
63 and therefore does not noticeably affect the performance of the processor.
63 and therefore does not noticeably affect the performance of the processor.
64 Default output is analog VGA, to switch to DVI mode execute this
64 Default output is analog VGA, to switch to DVI mode execute this
65 command in grmon:
65 command in grmon:
66
66
67 i2c dvi init_l4itx_vga
67 i2c dvi init_l4itx_vga
68
68
69 * The JTAG DSU interface is enabled and accesible via the USB/JTAG port.
69 * The JTAG DSU interface is enabled and accesible via the USB/JTAG port.
70 Start grmon with -xilusb to connect.
70 Start grmon with -xilusb to connect.
71
71
72 * Output from GRMON is:
72 * Output from GRMON is:
73
73
74 $ grmon -xilusb -u
74 $ grmon -xilusb -u
75
75
76 GRMON LEON debug monitor v1.1.51 professional version (debug)
76 GRMON LEON debug monitor v1.1.51 professional version (debug)
77
77
78 Copyright (C) 2004-2011 Aeroflex Gaisler - all rights reserved.
78 Copyright (C) 2004-2011 Aeroflex Gaisler - all rights reserved.
79 For latest updates, go to http://www.gaisler.com/
79 For latest updates, go to http://www.gaisler.com/
80 Comments or bug-reports to support@gaisler.com
80 Comments or bug-reports to support@gaisler.com
81
81
82 Xilinx cable: Cable type/rev : 0x3
82 Xilinx cable: Cable type/rev : 0x3
83 JTAG chain: xc6slx45t xccace
83 JTAG chain: xc6slx45t xccace
84
84
85 GRLIB build version: 4111
85 GRLIB build version: 4111
86
86
87 initialising ...............
87 initialising ...............
88 detected frequency: 50 MHz
88 detected frequency: 50 MHz
89 SRAM waitstates: 1
89 SRAM waitstates: 1
90
90
91 Component Vendor
91 Component Vendor
92 LEON3 SPARC V8 Processor Gaisler Research
92 LEON3 SPARC V8 Processor Gaisler Research
93 AHB Debug JTAG TAP Gaisler Research
93 AHB Debug JTAG TAP Gaisler Research
94 GR Ethernet MAC Gaisler Research
94 GR Ethernet MAC Gaisler Research
95 LEON2 Memory Controller European Space Agency
95 LEON2 Memory Controller European Space Agency
96 AHB/APB Bridge Gaisler Research
96 AHB/APB Bridge Gaisler Research
97 LEON3 Debug Support Unit Gaisler Research
97 LEON3 Debug Support Unit Gaisler Research
98 Xilinx MIG DDR2 controller Gaisler Research
98 Xilinx MIG DDR2 controller Gaisler Research
99 AHB/APB Bridge Gaisler Research
99 AHB/APB Bridge Gaisler Research
100 Generic APB UART Gaisler Research
100 Generic APB UART Gaisler Research
101 Multi-processor Interrupt Ctrl Gaisler Research
101 Multi-processor Interrupt Ctrl Gaisler Research
102 Modular Timer Unit Gaisler Research
102 Modular Timer Unit Gaisler Research
103 SVGA Controller Gaisler Research
103 SVGA Controller Gaisler Research
104 AMBA Wrapper for OC I2C-master Gaisler Research
104 AMBA Wrapper for OC I2C-master Gaisler Research
105 General purpose I/O port Gaisler Research
105 General purpose I/O port Gaisler Research
106 AHB status register Gaisler Research
106 AHB status register Gaisler Research
107
107
108 Use command 'info sys' to print a detailed report of attached cores
108 Use command 'info sys' to print a detailed report of attached cores
109
109
110 grlib> inf sys
110 grlib> inf sys
111 00.01:003 Gaisler Research LEON3 SPARC V8 Processor (ver 0x0)
111 00.01:003 Gaisler Research LEON3 SPARC V8 Processor (ver 0x0)
112 ahb master 0
112 ahb master 0
113 01.01:01c Gaisler Research AHB Debug JTAG TAP (ver 0x1)
113 01.01:01c Gaisler Research AHB Debug JTAG TAP (ver 0x1)
114 ahb master 1
114 ahb master 1
115 02.01:01d Gaisler Research GR Ethernet MAC (ver 0x0)
115 02.01:01d Gaisler Research GR Ethernet MAC (ver 0x0)
116 ahb master 2, irq 12
116 ahb master 2, irq 12
117 apb: 80000e00 - 80000f00
117 apb: 80000e00 - 80000f00
118 Device index: dev0
118 Device index: dev0
119 edcl ip 192.168.1.51, buffer 2 kbyte
119 edcl ip 192.168.1.51, buffer 2 kbyte
120 00.04:00f European Space Agency LEON2 Memory Controller (ver 0x1)
120 00.04:00f European Space Agency LEON2 Memory Controller (ver 0x1)
121 ahb: 00000000 - 20000000
121 ahb: 00000000 - 20000000
122 apb: 80000000 - 80000100
122 apb: 80000000 - 80000100
123 16-bit prom @ 0x00000000
123 16-bit prom @ 0x00000000
124 01.01:006 Gaisler Research AHB/APB Bridge (ver 0x0)
124 01.01:006 Gaisler Research AHB/APB Bridge (ver 0x0)
125 ahb: 80000000 - 80100000
125 ahb: 80000000 - 80100000
126 02.01:004 Gaisler Research LEON3 Debug Support Unit (ver 0x1)
126 02.01:004 Gaisler Research LEON3 Debug Support Unit (ver 0x1)
127 ahb: 90000000 - a0000000
127 ahb: 90000000 - a0000000
128 AHB trace 256 lines, 32-bit bus, stack pointer 0x47fffff0
128 AHB trace 256 lines, 32-bit bus, stack pointer 0x47fffff0
129 CPU#0 win 8, hwbp 2, itrace 256, V8 mul/div, srmmu, lddel 1
129 CPU#0 win 8, hwbp 2, itrace 256, V8 mul/div, srmmu, lddel 1
130 icache 2 * 8 kbyte, 32 byte/line rnd
130 icache 2 * 8 kbyte, 32 byte/line rnd
131 dcache 2 * 4 kbyte, 16 byte/line rnd
131 dcache 2 * 4 kbyte, 16 byte/line rnd
132 04.01:06b Gaisler Research Xilinx MIG DDR2 controller (ver 0x0)
132 04.01:06b Gaisler Research Xilinx MIG DDR2 controller (ver 0x0)
133 ahb: 40000000 - 48000000
133 ahb: 40000000 - 48000000
134 apb: 80100000 - 80100100
134 apb: 80100000 - 80100100
135 DDR2: 128 Mbyte
135 DDR2: 128 Mbyte
136 0d.01:006 Gaisler Research AHB/APB Bridge (ver 0x0)
136 0d.01:006 Gaisler Research AHB/APB Bridge (ver 0x0)
137 ahb: 80100000 - 80200000
137 ahb: 80100000 - 80200000
138 01.01:00c Gaisler Research Generic APB UART (ver 0x1)
138 01.01:00c Gaisler Research Generic APB UART (ver 0x1)
139 irq 2
139 irq 2
140 apb: 80000100 - 80000200
140 apb: 80000100 - 80000200
141 baud rate 38343, DSU mode (FIFO debug)
141 baud rate 38343, DSU mode (FIFO debug)
142 02.01:00d Gaisler Research Multi-processor Interrupt Ctrl (ver 0x3)
142 02.01:00d Gaisler Research Multi-processor Interrupt Ctrl (ver 0x3)
143 apb: 80000200 - 80000300
143 apb: 80000200 - 80000300
144 03.01:011 Gaisler Research Modular Timer Unit (ver 0x0)
144 03.01:011 Gaisler Research Modular Timer Unit (ver 0x0)
145 irq 8
145 irq 8
146 apb: 80000300 - 80000400
146 apb: 80000300 - 80000400
147 8-bit scaler, 2 * 32-bit timers, divisor 50
147 8-bit scaler, 2 * 32-bit timers, divisor 50
148 06.01:063 Gaisler Research SVGA Controller (ver 0x0)
148 06.01:063 Gaisler Research SVGA Controller (ver 0x0)
149 apb: 80000600 - 80000700
149 apb: 80000600 - 80000700
150 clk0: 50.00 MHz
150 clk0: 50.00 MHz
151 09.01:028 Gaisler Research AMBA Wrapper for OC I2C-master (ver 0x3)
151 09.01:028 Gaisler Research AMBA Wrapper for OC I2C-master (ver 0x3)
152 irq 14
152 irq 14
153 apb: 80000900 - 80000a00
153 apb: 80000900 - 80000a00
154 0a.01:01a Gaisler Research General purpose I/O port (ver 0x1)
154 0a.01:01a Gaisler Research General purpose I/O port (ver 0x1)
155 apb: 80000a00 - 80000b00
155 apb: 80000a00 - 80000b00
156 0f.01:052 Gaisler Research AHB status register (ver 0x0)
156 0f.01:052 Gaisler Research AHB status register (ver 0x0)
157 irq 7
157 irq 7
158 apb: 80000f00 - 80001000
158 apb: 80000f00 - 80001000
159 grlib> fla
159 grlib> fla
160
160
161 Intel-style 16-bit flash on D[31:16]
161 Intel-style 16-bit flash on D[31:16]
162
162
163 Manuf. Intel
163 Manuf. Intel
164 Device Strataflash P30
164 Device Strataflash P30
165
165
166 Device ID 02e44603e127ffff
166 Device ID 02e44603e127ffff
167 User ID ffffffffffffffff
167 User ID ffffffffffffffff
168
168
169
169
170 1 x 32 Mbyte = 32 Mbyte total @ 0x00000000
170 1 x 32 Mbyte = 32 Mbyte total @ 0x00000000
171
171
172
172
173 CFI info
173 CFI info
174 flash family : 1
174 flash family : 1
175 flash size : 256 Mbit
175 flash size : 256 Mbit
176 erase regions : 2
176 erase regions : 2
177 erase blocks : 259
177 erase blocks : 259
178 write buffer : 1024 bytes
178 write buffer : 1024 bytes
179 lock-down : yes
179 lock-down : yes
180 region 0 : 255 blocks of 128 Kbytes
180 region 0 : 255 blocks of 128 Kbytes
181 region 1 : 4 blocks of 32 Kbytes
181 region 1 : 4 blocks of 32 Kbytes
182
182
183 grlib> lo ~/ibm/src/bench/leonbench/coremark.exe
183 grlib> lo ~/ibm/src/bench/leonbench/coremark.exe
184 section: .text at 0x40000000, size 102544 bytes
184 section: .text at 0x40000000, size 102544 bytes
185 section: .data at 0x40019090, size 2788 bytes
185 section: .data at 0x40019090, size 2788 bytes
186 total size: 105332 bytes (1.2 Mbit/s)
186 total size: 105332 bytes (1.2 Mbit/s)
187 read 272 symbols
187 read 272 symbols
188 entry point: 0x40000000
188 entry point: 0x40000000
189 grlib> run
189 grlib> run
190 2K performance run parameters for coremark.
190 2K performance run parameters for coremark.
191 CoreMark Size : 666
191 CoreMark Size : 666
192 Total ticks : 19945918
192 Total ticks : 19945918
193 Total time (secs): 19.945918
193 Total time (secs): 19.945918
194 Iterations/Sec : 100.271143
194 Iterations/Sec : 100.271143
195 Iterations : 2000
195 Iterations : 2000
196 Compiler version : GCC4.4.2
196 Compiler version : GCC4.4.2
197 Compiler flags : -O3 -mv8 -funroll-loops -fgcse-sm -combine -DPERFORMANCE_RUN=1 -mcpu=v8 -msoft-float
197 Compiler flags : -O3 -mv8 -funroll-loops -fgcse-sm -combine -DPERFORMANCE_RUN=1 -mcpu=v8 -msoft-float
198 Memory location : STACK
198 Memory location : STACK
199 seedcrc : 0xe9f5
199 seedcrc : 0xe9f5
200 [0]crclist : 0xe714
200 [0]crclist : 0xe714
201 [0]crcmatrix : 0x1fd7
201 [0]crcmatrix : 0x1fd7
202 [0]crcstate : 0x8e3a
202 [0]crcstate : 0x8e3a
203 [0]crcfinal : 0x4983
203 [0]crcfinal : 0x4983
204 Correct operation validated. See readme.txt for run and reporting rules.
204 Correct operation validated. See readme.txt for run and reporting rules.
205 CoreMark 1.0 : 100.271143 / GCC4.4.2 -O3 -mv8 -funroll-loops -fgcse-sm -combine -DPERFORMANCE_RUN=1 -mcpu=v8 -msoft-float / Stack
205 CoreMark 1.0 : 100.271143 / GCC4.4.2 -O3 -mv8 -funroll-loops -fgcse-sm -combine -DPERFORMANCE_RUN=1 -mcpu=v8 -msoft-float / Stack
206
206
207 Program exited normally.
207 Program exited normally.
208 grlib>
208 grlib>
209
209
Show file before | Show file after | Hide comments
@@ -1,190 +1,190
1 -- Technology and synthesis options
1 -- Technology and synthesis options
2 constant CFG_FABTECH : integer := CONFIG_SYN_TECH;
2 constant CFG_FABTECH : integer := CONFIG_SYN_TECH;
3 constant CFG_MEMTECH : integer := CFG_RAM_TECH;
3 constant CFG_MEMTECH : integer := CFG_RAM_TECH;
4 constant CFG_PADTECH : integer := CFG_PAD_TECH;
4 constant CFG_PADTECH : integer := CFG_PAD_TECH;
5 constant CFG_NOASYNC : integer := CONFIG_SYN_NO_ASYNC;
5 constant CFG_NOASYNC : integer := CONFIG_SYN_NO_ASYNC;
6 constant CFG_SCAN : integer := CONFIG_SYN_SCAN;
6 constant CFG_SCAN : integer := CONFIG_SYN_SCAN;
7
7
8 -- Clock generator
8 -- Clock generator
9 constant CFG_CLKTECH : integer := CFG_CLK_TECH;
9 constant CFG_CLKTECH : integer := CFG_CLK_TECH;
10 constant CFG_CLKMUL : integer := CONFIG_CLK_MUL;
10 constant CFG_CLKMUL : integer := CONFIG_CLK_MUL;
11 constant CFG_CLKDIV : integer := CONFIG_CLK_DIV;
11 constant CFG_CLKDIV : integer := CONFIG_CLK_DIV;
12 constant CFG_OCLKDIV : integer := CONFIG_OCLK_DIV;
12 constant CFG_OCLKDIV : integer := CONFIG_OCLK_DIV;
13 constant CFG_OCLKBDIV : integer := CONFIG_OCLKB_DIV;
13 constant CFG_OCLKBDIV : integer := CONFIG_OCLKB_DIV;
14 constant CFG_OCLKCDIV : integer := CONFIG_OCLKC_DIV;
14 constant CFG_OCLKCDIV : integer := CONFIG_OCLKC_DIV;
15 constant CFG_PCIDLL : integer := CONFIG_PCI_CLKDLL;
15 constant CFG_PCIDLL : integer := CONFIG_PCI_CLKDLL;
16 constant CFG_PCISYSCLK: integer := CONFIG_PCI_SYSCLK;
16 constant CFG_PCISYSCLK: integer := CONFIG_PCI_SYSCLK;
17 constant CFG_CLK_NOFB : integer := CONFIG_CLK_NOFB;
17 constant CFG_CLK_NOFB : integer := CONFIG_CLK_NOFB;
18
18
19 -- LEON3 processor core
19 -- LEON3 processor core
20 constant CFG_LEON3 : integer := CONFIG_LEON3;
20 constant CFG_LEON3 : integer := CONFIG_LEON3;
21 constant CFG_NCPU : integer := CONFIG_PROC_NUM;
21 constant CFG_NCPU : integer := CONFIG_PROC_NUM;
22 constant CFG_NWIN : integer := CONFIG_IU_NWINDOWS;
22 constant CFG_NWIN : integer := CONFIG_IU_NWINDOWS;
23 constant CFG_V8 : integer := CFG_IU_V8 + 4*CFG_IU_MUL_STRUCT;
23 constant CFG_V8 : integer := CFG_IU_V8 + 4*CFG_IU_MUL_STRUCT;
24 constant CFG_MAC : integer := CONFIG_IU_MUL_MAC;
24 constant CFG_MAC : integer := CONFIG_IU_MUL_MAC;
25 constant CFG_BP : integer := CONFIG_IU_BP;
25 constant CFG_BP : integer := CONFIG_IU_BP;
26 constant CFG_SVT : integer := CONFIG_IU_SVT;
26 constant CFG_SVT : integer := CONFIG_IU_SVT;
27 constant CFG_RSTADDR : integer := 16#CONFIG_IU_RSTADDR#;
27 constant CFG_RSTADDR : integer := 16#CONFIG_IU_RSTADDR#;
28 constant CFG_LDDEL : integer := CONFIG_IU_LDELAY;
28 constant CFG_LDDEL : integer := CONFIG_IU_LDELAY;
29 constant CFG_NOTAG : integer := CONFIG_NOTAG;
29 constant CFG_NOTAG : integer := CONFIG_NOTAG;
30 constant CFG_NWP : integer := CONFIG_IU_WATCHPOINTS;
30 constant CFG_NWP : integer := CONFIG_IU_WATCHPOINTS;
31 constant CFG_PWD : integer := CONFIG_PWD*2;
31 constant CFG_PWD : integer := CONFIG_PWD*2;
32 constant CFG_FPU : integer := CONFIG_FPU + 16*CONFIG_FPU_NETLIST + 32*CONFIG_FPU_GRFPU_SHARED;
32 constant CFG_FPU : integer := CONFIG_FPU + 16*CONFIG_FPU_NETLIST + 32*CONFIG_FPU_GRFPU_SHARED;
33 constant CFG_GRFPUSH : integer := CONFIG_FPU_GRFPU_SHARED;
33 constant CFG_GRFPUSH : integer := CONFIG_FPU_GRFPU_SHARED;
34 constant CFG_ICEN : integer := CONFIG_ICACHE_ENABLE;
34 constant CFG_ICEN : integer := CONFIG_ICACHE_ENABLE;
35 constant CFG_ISETS : integer := CFG_IU_ISETS;
35 constant CFG_ISETS : integer := CFG_IU_ISETS;
36 constant CFG_ISETSZ : integer := CFG_ICACHE_SZ;
36 constant CFG_ISETSZ : integer := CFG_ICACHE_SZ;
37 constant CFG_ILINE : integer := CFG_ILINE_SZ;
37 constant CFG_ILINE : integer := CFG_ILINE_SZ;
38 constant CFG_IREPL : integer := CFG_ICACHE_ALGORND;
38 constant CFG_IREPL : integer := CFG_ICACHE_ALGORND;
39 constant CFG_ILOCK : integer := CONFIG_ICACHE_LOCK;
39 constant CFG_ILOCK : integer := CONFIG_ICACHE_LOCK;
40 constant CFG_ILRAMEN : integer := CONFIG_ICACHE_LRAM;
40 constant CFG_ILRAMEN : integer := CONFIG_ICACHE_LRAM;
41 constant CFG_ILRAMADDR: integer := 16#CONFIG_ICACHE_LRSTART#;
41 constant CFG_ILRAMADDR: integer := 16#CONFIG_ICACHE_LRSTART#;
42 constant CFG_ILRAMSZ : integer := CFG_ILRAM_SIZE;
42 constant CFG_ILRAMSZ : integer := CFG_ILRAM_SIZE;
43 constant CFG_DCEN : integer := CONFIG_DCACHE_ENABLE;
43 constant CFG_DCEN : integer := CONFIG_DCACHE_ENABLE;
44 constant CFG_DSETS : integer := CFG_IU_DSETS;
44 constant CFG_DSETS : integer := CFG_IU_DSETS;
45 constant CFG_DSETSZ : integer := CFG_DCACHE_SZ;
45 constant CFG_DSETSZ : integer := CFG_DCACHE_SZ;
46 constant CFG_DLINE : integer := CFG_DLINE_SZ;
46 constant CFG_DLINE : integer := CFG_DLINE_SZ;
47 constant CFG_DREPL : integer := CFG_DCACHE_ALGORND;
47 constant CFG_DREPL : integer := CFG_DCACHE_ALGORND;
48 constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK;
48 constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK;
49 constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG;
49 constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG;
50 constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#;
50 constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#;
51 constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM;
51 constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM;
52 constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#;
52 constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#;
53 constant CFG_DLRAMSZ : integer := CFG_DLRAM_SIZE;
53 constant CFG_DLRAMSZ : integer := CFG_DLRAM_SIZE;
54 constant CFG_MMUEN : integer := CONFIG_MMUEN;
54 constant CFG_MMUEN : integer := CONFIG_MMUEN;
55 constant CFG_ITLBNUM : integer := CONFIG_ITLBNUM;
55 constant CFG_ITLBNUM : integer := CONFIG_ITLBNUM;
56 constant CFG_DTLBNUM : integer := CONFIG_DTLBNUM;
56 constant CFG_DTLBNUM : integer := CONFIG_DTLBNUM;
57 constant CFG_TLB_TYPE : integer := CONFIG_TLB_TYPE + CFG_MMU_FASTWB*2;
57 constant CFG_TLB_TYPE : integer := CONFIG_TLB_TYPE + CFG_MMU_FASTWB*2;
58 constant CFG_TLB_REP : integer := CONFIG_TLB_REP;
58 constant CFG_TLB_REP : integer := CONFIG_TLB_REP;
59 constant CFG_MMU_PAGE : integer := CONFIG_MMU_PAGE;
59 constant CFG_MMU_PAGE : integer := CONFIG_MMU_PAGE;
60 constant CFG_DSU : integer := CONFIG_DSU_ENABLE;
60 constant CFG_DSU : integer := CONFIG_DSU_ENABLE;
61 constant CFG_ITBSZ : integer := CFG_DSU_ITB;
61 constant CFG_ITBSZ : integer := CFG_DSU_ITB;
62 constant CFG_ATBSZ : integer := CFG_DSU_ATB;
62 constant CFG_ATBSZ : integer := CFG_DSU_ATB;
63 constant CFG_LEON3FT_EN : integer := CONFIG_LEON3FT_EN;
63 constant CFG_LEON3FT_EN : integer := CONFIG_LEON3FT_EN;
64 constant CFG_IUFT_EN : integer := CONFIG_IUFT_EN;
64 constant CFG_IUFT_EN : integer := CONFIG_IUFT_EN;
65 constant CFG_FPUFT_EN : integer := CONFIG_FPUFT;
65 constant CFG_FPUFT_EN : integer := CONFIG_FPUFT;
66 constant CFG_RF_ERRINJ : integer := CONFIG_RF_ERRINJ;
66 constant CFG_RF_ERRINJ : integer := CONFIG_RF_ERRINJ;
67 constant CFG_CACHE_FT_EN : integer := CONFIG_CACHE_FT_EN;
67 constant CFG_CACHE_FT_EN : integer := CONFIG_CACHE_FT_EN;
68 constant CFG_CACHE_ERRINJ : integer := CONFIG_CACHE_ERRINJ;
68 constant CFG_CACHE_ERRINJ : integer := CONFIG_CACHE_ERRINJ;
69 constant CFG_LEON3_NETLIST: integer := CONFIG_LEON3_NETLIST;
69 constant CFG_LEON3_NETLIST: integer := CONFIG_LEON3_NETLIST;
70 constant CFG_DISAS : integer := CONFIG_IU_DISAS + CONFIG_IU_DISAS_NET;
70 constant CFG_DISAS : integer := CONFIG_IU_DISAS + CONFIG_IU_DISAS_NET;
71 constant CFG_PCLOW : integer := CFG_DEBUG_PC32;
71 constant CFG_PCLOW : integer := CFG_DEBUG_PC32;
72
72
73 -- AMBA settings
73 -- AMBA settings
74 constant CFG_DEFMST : integer := CONFIG_AHB_DEFMST;
74 constant CFG_DEFMST : integer := CONFIG_AHB_DEFMST;
75 constant CFG_RROBIN : integer := CONFIG_AHB_RROBIN;
75 constant CFG_RROBIN : integer := CONFIG_AHB_RROBIN;
76 constant CFG_SPLIT : integer := CONFIG_AHB_SPLIT;
76 constant CFG_SPLIT : integer := CONFIG_AHB_SPLIT;
77 constant CFG_AHBIO : integer := 16#CONFIG_AHB_IOADDR#;
77 constant CFG_AHBIO : integer := 16#CONFIG_AHB_IOADDR#;
78 constant CFG_APBADDR : integer := 16#CONFIG_APB_HADDR#;
78 constant CFG_APBADDR : integer := 16#CONFIG_APB_HADDR#;
79 constant CFG_AHB_MON : integer := CONFIG_AHB_MON;
79 constant CFG_AHB_MON : integer := CONFIG_AHB_MON;
80 constant CFG_AHB_MONERR : integer := CONFIG_AHB_MONERR;
80 constant CFG_AHB_MONERR : integer := CONFIG_AHB_MONERR;
81 constant CFG_AHB_MONWAR : integer := CONFIG_AHB_MONWAR;
81 constant CFG_AHB_MONWAR : integer := CONFIG_AHB_MONWAR;
82 constant CFG_AHB_DTRACE : integer := CONFIG_AHB_DTRACE;
82 constant CFG_AHB_DTRACE : integer := CONFIG_AHB_DTRACE;
83
83
84 -- JTAG based DSU interface
84 -- JTAG based DSU interface
85 constant CFG_AHB_JTAG : integer := CONFIG_DSU_JTAG;
85 constant CFG_AHB_JTAG : integer := CONFIG_DSU_JTAG;
86
86
87 -- Ethernet DSU
87 -- Ethernet DSU
88 constant CFG_DSU_ETH : integer := CONFIG_DSU_ETH + CONFIG_DSU_ETH_PROG + CONFIG_DSU_ETH_DIS;
88 constant CFG_DSU_ETH : integer := CONFIG_DSU_ETH + CONFIG_DSU_ETH_PROG + CONFIG_DSU_ETH_DIS;
89 constant CFG_ETH_BUF : integer := CFG_DSU_ETHB;
89 constant CFG_ETH_BUF : integer := CFG_DSU_ETHB;
90 constant CFG_ETH_IPM : integer := 16#CONFIG_DSU_IPMSB#;
90 constant CFG_ETH_IPM : integer := 16#CONFIG_DSU_IPMSB#;
91 constant CFG_ETH_IPL : integer := 16#CONFIG_DSU_IPLSB#;
91 constant CFG_ETH_IPL : integer := 16#CONFIG_DSU_IPLSB#;
92 constant CFG_ETH_ENM : integer := 16#CONFIG_DSU_ETHMSB#;
92 constant CFG_ETH_ENM : integer := 16#CONFIG_DSU_ETHMSB#;
93 constant CFG_ETH_ENL : integer := 16#CONFIG_DSU_ETHLSB#;
93 constant CFG_ETH_ENL : integer := 16#CONFIG_DSU_ETHLSB#;
94
94
95 -- LEON2 memory controller
95 -- LEON2 memory controller
96 constant CFG_MCTRL_LEON2 : integer := CONFIG_MCTRL_LEON2;
96 constant CFG_MCTRL_LEON2 : integer := CONFIG_MCTRL_LEON2;
97 constant CFG_MCTRL_RAM8BIT : integer := CONFIG_MCTRL_8BIT;
97 constant CFG_MCTRL_RAM8BIT : integer := CONFIG_MCTRL_8BIT;
98 constant CFG_MCTRL_RAM16BIT : integer := CONFIG_MCTRL_16BIT;
98 constant CFG_MCTRL_RAM16BIT : integer := CONFIG_MCTRL_16BIT;
99 constant CFG_MCTRL_5CS : integer := CONFIG_MCTRL_5CS;
99 constant CFG_MCTRL_5CS : integer := CONFIG_MCTRL_5CS;
100 constant CFG_MCTRL_SDEN : integer := CONFIG_MCTRL_SDRAM;
100 constant CFG_MCTRL_SDEN : integer := CONFIG_MCTRL_SDRAM;
101 constant CFG_MCTRL_SEPBUS : integer := CONFIG_MCTRL_SDRAM_SEPBUS;
101 constant CFG_MCTRL_SEPBUS : integer := CONFIG_MCTRL_SDRAM_SEPBUS;
102 constant CFG_MCTRL_INVCLK : integer := CONFIG_MCTRL_SDRAM_INVCLK;
102 constant CFG_MCTRL_INVCLK : integer := CONFIG_MCTRL_SDRAM_INVCLK;
103 constant CFG_MCTRL_SD64 : integer := CONFIG_MCTRL_SDRAM_BUS64;
103 constant CFG_MCTRL_SD64 : integer := CONFIG_MCTRL_SDRAM_BUS64;
104 constant CFG_MCTRL_PAGE : integer := CONFIG_MCTRL_PAGE + CONFIG_MCTRL_PROGPAGE;
104 constant CFG_MCTRL_PAGE : integer := CONFIG_MCTRL_PAGE + CONFIG_MCTRL_PROGPAGE;
105
105
106 -- Xilinx MIG
106 -- Xilinx MIG
107 constant CFG_MIG_DDR2 : integer := CONFIG_MIG_DDR2;
107 constant CFG_MIG_DDR2 : integer := CONFIG_MIG_DDR2;
108 constant CFG_MIG_RANKS : integer := CONFIG_MIG_RANKS;
108 constant CFG_MIG_RANKS : integer := CONFIG_MIG_RANKS;
109 constant CFG_MIG_COLBITS : integer := CONFIG_MIG_COLBITS;
109 constant CFG_MIG_COLBITS : integer := CONFIG_MIG_COLBITS;
110 constant CFG_MIG_ROWBITS : integer := CONFIG_MIG_ROWBITS;
110 constant CFG_MIG_ROWBITS : integer := CONFIG_MIG_ROWBITS;
111 constant CFG_MIG_BANKBITS: integer := CONFIG_MIG_BANKBITS;
111 constant CFG_MIG_BANKBITS: integer := CONFIG_MIG_BANKBITS;
112 constant CFG_MIG_HMASK : integer := 16#CONFIG_MIG_HMASK#;
112 constant CFG_MIG_HMASK : integer := 16#CONFIG_MIG_HMASK#;
113
113
114
114
115 -- AHB status register
115 -- AHB status register
116 constant CFG_AHBSTAT : integer := CONFIG_AHBSTAT_ENABLE;
116 constant CFG_AHBSTAT : integer := CONFIG_AHBSTAT_ENABLE;
117 constant CFG_AHBSTATN : integer := CONFIG_AHBSTAT_NFTSLV;
117 constant CFG_AHBSTATN : integer := CONFIG_AHBSTAT_NFTSLV;
118
118
119 -- AHB ROM
119 -- AHB ROM
120 constant CFG_AHBROMEN : integer := CONFIG_AHBROM_ENABLE;
120 constant CFG_AHBROMEN : integer := CONFIG_AHBROM_ENABLE;
121 constant CFG_AHBROPIP : integer := CONFIG_AHBROM_PIPE;
121 constant CFG_AHBROPIP : integer := CONFIG_AHBROM_PIPE;
122 constant CFG_AHBRODDR : integer := 16#CONFIG_AHBROM_START#;
122 constant CFG_AHBRODDR : integer := 16#CONFIG_AHBROM_START#;
123 constant CFG_ROMADDR : integer := 16#CONFIG_ROM_START#;
123 constant CFG_ROMADDR : integer := 16#CONFIG_ROM_START#;
124 constant CFG_ROMMASK : integer := 16#E00# + 16#CONFIG_ROM_START#;
124 constant CFG_ROMMASK : integer := 16#E00# + 16#CONFIG_ROM_START#;
125
125
126 -- AHB RAM
126 -- AHB RAM
127 constant CFG_AHBRAMEN : integer := CONFIG_AHBRAM_ENABLE;
127 constant CFG_AHBRAMEN : integer := CONFIG_AHBRAM_ENABLE;
128 constant CFG_AHBRSZ : integer := CFG_AHBRAMSZ;
128 constant CFG_AHBRSZ : integer := CFG_AHBRAMSZ;
129 constant CFG_AHBRADDR : integer := 16#CONFIG_AHBRAM_START#;
129 constant CFG_AHBRADDR : integer := 16#CONFIG_AHBRAM_START#;
130
130
131 -- Gaisler Ethernet core
131 -- Gaisler Ethernet core
132 constant CFG_GRETH : integer := CONFIG_GRETH_ENABLE;
132 constant CFG_GRETH : integer := CONFIG_GRETH_ENABLE;
133 constant CFG_GRETH1G : integer := CONFIG_GRETH_GIGA;
133 constant CFG_GRETH1G : integer := CONFIG_GRETH_GIGA;
134 constant CFG_ETH_FIFO : integer := CFG_GRETH_FIFO;
134 constant CFG_ETH_FIFO : integer := CFG_GRETH_FIFO;
135
135
136 -- UART 1
136 -- UART 1
137 constant CFG_UART1_ENABLE : integer := CONFIG_UART1_ENABLE;
137 constant CFG_UART1_ENABLE : integer := CONFIG_UART1_ENABLE;
138 constant CFG_UART1_FIFO : integer := CFG_UA1_FIFO;
138 constant CFG_UART1_FIFO : integer := CFG_UA1_FIFO;
139
139
140 -- LEON3 interrupt controller
140 -- LEON3 interrupt controller
141 constant CFG_IRQ3_ENABLE : integer := CONFIG_IRQ3_ENABLE;
141 constant CFG_IRQ3_ENABLE : integer := CONFIG_IRQ3_ENABLE;
142 constant CFG_IRQ3_NSEC : integer := CONFIG_IRQ3_NSEC;
142 constant CFG_IRQ3_NSEC : integer := CONFIG_IRQ3_NSEC;
143
143
144 -- Modular timer
144 -- Modular timer
145 constant CFG_GPT_ENABLE : integer := CONFIG_GPT_ENABLE;
145 constant CFG_GPT_ENABLE : integer := CONFIG_GPT_ENABLE;
146 constant CFG_GPT_NTIM : integer := CONFIG_GPT_NTIM;
146 constant CFG_GPT_NTIM : integer := CONFIG_GPT_NTIM;
147 constant CFG_GPT_SW : integer := CONFIG_GPT_SW;
147 constant CFG_GPT_SW : integer := CONFIG_GPT_SW;
148 constant CFG_GPT_TW : integer := CONFIG_GPT_TW;
148 constant CFG_GPT_TW : integer := CONFIG_GPT_TW;
149 constant CFG_GPT_IRQ : integer := CONFIG_GPT_IRQ;
149 constant CFG_GPT_IRQ : integer := CONFIG_GPT_IRQ;
150 constant CFG_GPT_SEPIRQ : integer := CONFIG_GPT_SEPIRQ;
150 constant CFG_GPT_SEPIRQ : integer := CONFIG_GPT_SEPIRQ;
151 constant CFG_GPT_WDOGEN : integer := CONFIG_GPT_WDOGEN;
151 constant CFG_GPT_WDOGEN : integer := CONFIG_GPT_WDOGEN;
152 constant CFG_GPT_WDOG : integer := 16#CONFIG_GPT_WDOG#;
152 constant CFG_GPT_WDOG : integer := 16#CONFIG_GPT_WDOG#;
153
153
154 -- GPIO port
154 -- GPIO port
155 constant CFG_GRGPIO_ENABLE : integer := CONFIG_GRGPIO_ENABLE;
155 constant CFG_GRGPIO_ENABLE : integer := CONFIG_GRGPIO_ENABLE;
156 constant CFG_GRGPIO_IMASK : integer := 16#CONFIG_GRGPIO_IMASK#;
156 constant CFG_GRGPIO_IMASK : integer := 16#CONFIG_GRGPIO_IMASK#;
157 constant CFG_GRGPIO_WIDTH : integer := CONFIG_GRGPIO_WIDTH;
157 constant CFG_GRGPIO_WIDTH : integer := CONFIG_GRGPIO_WIDTH;
158
158
159 -- VGA and PS2/ interface
159 -- VGA and PS2/ interface
160 constant CFG_KBD_ENABLE : integer := CONFIG_KBD_ENABLE;
160 constant CFG_KBD_ENABLE : integer := CONFIG_KBD_ENABLE;
161 constant CFG_VGA_ENABLE : integer := CONFIG_VGA_ENABLE;
161 constant CFG_VGA_ENABLE : integer := CONFIG_VGA_ENABLE;
162 constant CFG_SVGA_ENABLE : integer := CONFIG_SVGA_ENABLE;
162 constant CFG_SVGA_ENABLE : integer := CONFIG_SVGA_ENABLE;
163
163
164 -- SPI memory controller
164 -- SPI memory controller
165 constant CFG_SPIMCTRL : integer := CONFIG_SPIMCTRL;
165 constant CFG_SPIMCTRL : integer := CONFIG_SPIMCTRL;
166 constant CFG_SPIMCTRL_SDCARD : integer := CONFIG_SPIMCTRL_SDCARD;
166 constant CFG_SPIMCTRL_SDCARD : integer := CONFIG_SPIMCTRL_SDCARD;
167 constant CFG_SPIMCTRL_READCMD : integer := 16#CONFIG_SPIMCTRL_READCMD#;
167 constant CFG_SPIMCTRL_READCMD : integer := 16#CONFIG_SPIMCTRL_READCMD#;
168 constant CFG_SPIMCTRL_DUMMYBYTE : integer := CONFIG_SPIMCTRL_DUMMYBYTE;
168 constant CFG_SPIMCTRL_DUMMYBYTE : integer := CONFIG_SPIMCTRL_DUMMYBYTE;
169 constant CFG_SPIMCTRL_DUALOUTPUT : integer := CONFIG_SPIMCTRL_DUALOUTPUT;
169 constant CFG_SPIMCTRL_DUALOUTPUT : integer := CONFIG_SPIMCTRL_DUALOUTPUT;
170 constant CFG_SPIMCTRL_SCALER : integer := CONFIG_SPIMCTRL_SCALER;
170 constant CFG_SPIMCTRL_SCALER : integer := CONFIG_SPIMCTRL_SCALER;
171 constant CFG_SPIMCTRL_ASCALER : integer := CONFIG_SPIMCTRL_ASCALER;
171 constant CFG_SPIMCTRL_ASCALER : integer := CONFIG_SPIMCTRL_ASCALER;
172 constant CFG_SPIMCTRL_PWRUPCNT : integer := CONFIG_SPIMCTRL_PWRUPCNT;
172 constant CFG_SPIMCTRL_PWRUPCNT : integer := CONFIG_SPIMCTRL_PWRUPCNT;
173
173
174 -- SPI controller
174 -- SPI controller
175 constant CFG_SPICTRL_ENABLE : integer := CONFIG_SPICTRL_ENABLE;
175 constant CFG_SPICTRL_ENABLE : integer := CONFIG_SPICTRL_ENABLE;
176 constant CFG_SPICTRL_NUM : integer := CONFIG_SPICTRL_NUM;
176 constant CFG_SPICTRL_NUM : integer := CONFIG_SPICTRL_NUM;
177 constant CFG_SPICTRL_SLVS : integer := CONFIG_SPICTRL_SLVS;
177 constant CFG_SPICTRL_SLVS : integer := CONFIG_SPICTRL_SLVS;
178 constant CFG_SPICTRL_FIFO : integer := CONFIG_SPICTRL_FIFO;
178 constant CFG_SPICTRL_FIFO : integer := CONFIG_SPICTRL_FIFO;
179 constant CFG_SPICTRL_SLVREG : integer := CONFIG_SPICTRL_SLVREG;
179 constant CFG_SPICTRL_SLVREG : integer := CONFIG_SPICTRL_SLVREG;
180 constant CFG_SPICTRL_ODMODE : integer := CONFIG_SPICTRL_ODMODE;
180 constant CFG_SPICTRL_ODMODE : integer := CONFIG_SPICTRL_ODMODE;
181 constant CFG_SPICTRL_AM : integer := CONFIG_SPICTRL_AM;
181 constant CFG_SPICTRL_AM : integer := CONFIG_SPICTRL_AM;
182 constant CFG_SPICTRL_ASEL : integer := CONFIG_SPICTRL_ASEL;
182 constant CFG_SPICTRL_ASEL : integer := CONFIG_SPICTRL_ASEL;
183 constant CFG_SPICTRL_TWEN : integer := CONFIG_SPICTRL_TWEN;
183 constant CFG_SPICTRL_TWEN : integer := CONFIG_SPICTRL_TWEN;
184 constant CFG_SPICTRL_MAXWLEN : integer := CONFIG_SPICTRL_MAXWLEN;
184 constant CFG_SPICTRL_MAXWLEN : integer := CONFIG_SPICTRL_MAXWLEN;
185 constant CFG_SPICTRL_SYNCRAM : integer := CONFIG_SPICTRL_SYNCRAM;
185 constant CFG_SPICTRL_SYNCRAM : integer := CONFIG_SPICTRL_SYNCRAM;
186 constant CFG_SPICTRL_FT : integer := CONFIG_SPICTRL_FT;
186 constant CFG_SPICTRL_FT : integer := CONFIG_SPICTRL_FT;
187
187
188 -- GRLIB debugging
188 -- GRLIB debugging
189 constant CFG_DUART : integer := CONFIG_DEBUG_UART;
189 constant CFG_DUART : integer := CONFIG_DEBUG_UART;
190
190
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@@ -1,18 +1,18
1
1
2 main()
2 main()
3
3
4 {
4 {
5 report_start();
5 report_start();
6
6
7
7
8 // svgactrl_test(0x80000600, 1, 0, 0x40200000, -1, 0, 0);
8 // svgactrl_test(0x80000600, 1, 0, 0x40200000, -1, 0, 0);
9 base_test();
9 base_test();
10 /*
10 /*
11 greth_test(0x80000e00);
11 greth_test(0x80000e00);
12 spw_test(0x80100A00);
12 spw_test(0x80100A00);
13 spw_test(0x80100B00);
13 spw_test(0x80100B00);
14 spw_test(0x80100C00);
14 spw_test(0x80100C00);
15 svgactrl_test(0x80000600, 1, 0, 0x40200000, -1, 0, 0);
15 svgactrl_test(0x80000600, 1, 0, 0x40200000, -1, 0, 0);
16 */
16 */
17 report_end();
17 report_end();
18 }
18 }
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This diff has been collapsed as it changes many lines, (2102 lines changed) Show them Hide them
@@ -1,1051 +1,1051
1 #if defined CONFIG_SYN_INFERRED
1 #if defined CONFIG_SYN_INFERRED
2 #define CONFIG_SYN_TECH inferred
2 #define CONFIG_SYN_TECH inferred
3 #elif defined CONFIG_SYN_UMC
3 #elif defined CONFIG_SYN_UMC
4 #define CONFIG_SYN_TECH umc
4 #define CONFIG_SYN_TECH umc
5 #elif defined CONFIG_SYN_RHUMC
5 #elif defined CONFIG_SYN_RHUMC
6 #define CONFIG_SYN_TECH rhumc
6 #define CONFIG_SYN_TECH rhumc
7 #elif defined CONFIG_SYN_ATC18
7 #elif defined CONFIG_SYN_ATC18
8 #define CONFIG_SYN_TECH atc18s
8 #define CONFIG_SYN_TECH atc18s
9 #elif defined CONFIG_SYN_ATC18RHA
9 #elif defined CONFIG_SYN_ATC18RHA
10 #define CONFIG_SYN_TECH atc18rha
10 #define CONFIG_SYN_TECH atc18rha
11 #elif defined CONFIG_SYN_AXCEL
11 #elif defined CONFIG_SYN_AXCEL
12 #define CONFIG_SYN_TECH axcel
12 #define CONFIG_SYN_TECH axcel
13 #elif defined CONFIG_SYN_AXDSP
13 #elif defined CONFIG_SYN_AXDSP
14 #define CONFIG_SYN_TECH axdsp
14 #define CONFIG_SYN_TECH axdsp
15 #elif defined CONFIG_SYN_PROASICPLUS
15 #elif defined CONFIG_SYN_PROASICPLUS
16 #define CONFIG_SYN_TECH proasic
16 #define CONFIG_SYN_TECH proasic
17 #elif defined CONFIG_SYN_ALTERA
17 #elif defined CONFIG_SYN_ALTERA
18 #define CONFIG_SYN_TECH altera
18 #define CONFIG_SYN_TECH altera
19 #elif defined CONFIG_SYN_STRATIX
19 #elif defined CONFIG_SYN_STRATIX
20 #define CONFIG_SYN_TECH stratix1
20 #define CONFIG_SYN_TECH stratix1
21 #elif defined CONFIG_SYN_STRATIXII
21 #elif defined CONFIG_SYN_STRATIXII
22 #define CONFIG_SYN_TECH stratix2
22 #define CONFIG_SYN_TECH stratix2
23 #elif defined CONFIG_SYN_STRATIXIII
23 #elif defined CONFIG_SYN_STRATIXIII
24 #define CONFIG_SYN_TECH stratix3
24 #define CONFIG_SYN_TECH stratix3
25 #elif defined CONFIG_SYN_CYCLONEIII
25 #elif defined CONFIG_SYN_CYCLONEIII
26 #define CONFIG_SYN_TECH cyclone3
26 #define CONFIG_SYN_TECH cyclone3
27 #elif defined CONFIG_SYN_EASIC45
27 #elif defined CONFIG_SYN_EASIC45
28 #define CONFIG_SYN_TECH easic45
28 #define CONFIG_SYN_TECH easic45
29 #elif defined CONFIG_SYN_EASIC90
29 #elif defined CONFIG_SYN_EASIC90
30 #define CONFIG_SYN_TECH easic90
30 #define CONFIG_SYN_TECH easic90
31 #elif defined CONFIG_SYN_IHP25
31 #elif defined CONFIG_SYN_IHP25
32 #define CONFIG_SYN_TECH ihp25
32 #define CONFIG_SYN_TECH ihp25
33 #elif defined CONFIG_SYN_IHP25RH
33 #elif defined CONFIG_SYN_IHP25RH
34 #define CONFIG_SYN_TECH ihp25rh
34 #define CONFIG_SYN_TECH ihp25rh
35 #elif defined CONFIG_SYN_CMOS9SF
35 #elif defined CONFIG_SYN_CMOS9SF
36 #define CONFIG_SYN_TECH cmos9sf
36 #define CONFIG_SYN_TECH cmos9sf
37 #elif defined CONFIG_SYN_LATTICE
37 #elif defined CONFIG_SYN_LATTICE
38 #define CONFIG_SYN_TECH lattice
38 #define CONFIG_SYN_TECH lattice
39 #elif defined CONFIG_SYN_ECLIPSE
39 #elif defined CONFIG_SYN_ECLIPSE
40 #define CONFIG_SYN_TECH eclipse
40 #define CONFIG_SYN_TECH eclipse
41 #elif defined CONFIG_SYN_PEREGRINE
41 #elif defined CONFIG_SYN_PEREGRINE
42 #define CONFIG_SYN_TECH peregrine
42 #define CONFIG_SYN_TECH peregrine
43 #elif defined CONFIG_SYN_PROASIC
43 #elif defined CONFIG_SYN_PROASIC
44 #define CONFIG_SYN_TECH proasic
44 #define CONFIG_SYN_TECH proasic
45 #elif defined CONFIG_SYN_PROASIC3
45 #elif defined CONFIG_SYN_PROASIC3
46 #define CONFIG_SYN_TECH apa3
46 #define CONFIG_SYN_TECH apa3
47 #elif defined CONFIG_SYN_PROASIC3E
47 #elif defined CONFIG_SYN_PROASIC3E
48 #define CONFIG_SYN_TECH apa3e
48 #define CONFIG_SYN_TECH apa3e
49 #elif defined CONFIG_SYN_PROASIC3L
49 #elif defined CONFIG_SYN_PROASIC3L
50 #define CONFIG_SYN_TECH apa3l
50 #define CONFIG_SYN_TECH apa3l
51 #elif defined CONFIG_SYN_IGLOO
51 #elif defined CONFIG_SYN_IGLOO
52 #define CONFIG_SYN_TECH apa3
52 #define CONFIG_SYN_TECH apa3
53 #elif defined CONFIG_SYN_FUSION
53 #elif defined CONFIG_SYN_FUSION
54 #define CONFIG_SYN_TECH actfus
54 #define CONFIG_SYN_TECH actfus
55 #elif defined CONFIG_SYN_SPARTAN2
55 #elif defined CONFIG_SYN_SPARTAN2
56 #define CONFIG_SYN_TECH virtex
56 #define CONFIG_SYN_TECH virtex
57 #elif defined CONFIG_SYN_VIRTEX
57 #elif defined CONFIG_SYN_VIRTEX
58 #define CONFIG_SYN_TECH virtex
58 #define CONFIG_SYN_TECH virtex
59 #elif defined CONFIG_SYN_VIRTEXE
59 #elif defined CONFIG_SYN_VIRTEXE
60 #define CONFIG_SYN_TECH virtex
60 #define CONFIG_SYN_TECH virtex
61 #elif defined CONFIG_SYN_SPARTAN3
61 #elif defined CONFIG_SYN_SPARTAN3
62 #define CONFIG_SYN_TECH spartan3
62 #define CONFIG_SYN_TECH spartan3
63 #elif defined CONFIG_SYN_SPARTAN3E
63 #elif defined CONFIG_SYN_SPARTAN3E
64 #define CONFIG_SYN_TECH spartan3e
64 #define CONFIG_SYN_TECH spartan3e
65 #elif defined CONFIG_SYN_SPARTAN6
65 #elif defined CONFIG_SYN_SPARTAN6
66 #define CONFIG_SYN_TECH spartan6
66 #define CONFIG_SYN_TECH spartan6
67 #elif defined CONFIG_SYN_VIRTEX2
67 #elif defined CONFIG_SYN_VIRTEX2
68 #define CONFIG_SYN_TECH virtex2
68 #define CONFIG_SYN_TECH virtex2
69 #elif defined CONFIG_SYN_VIRTEX4
69 #elif defined CONFIG_SYN_VIRTEX4
70 #define CONFIG_SYN_TECH virtex4
70 #define CONFIG_SYN_TECH virtex4
71 #elif defined CONFIG_SYN_VIRTEX5
71 #elif defined CONFIG_SYN_VIRTEX5
72 #define CONFIG_SYN_TECH virtex5
72 #define CONFIG_SYN_TECH virtex5
73 #elif defined CONFIG_SYN_VIRTEX6
73 #elif defined CONFIG_SYN_VIRTEX6
74 #define CONFIG_SYN_TECH virtex6
74 #define CONFIG_SYN_TECH virtex6
75 #elif defined CONFIG_SYN_RH_LIB18T
75 #elif defined CONFIG_SYN_RH_LIB18T
76 #define CONFIG_SYN_TECH rhlib18t
76 #define CONFIG_SYN_TECH rhlib18t
77 #elif defined CONFIG_SYN_SMIC13
77 #elif defined CONFIG_SYN_SMIC13
78 #define CONFIG_SYN_TECH smic013
78 #define CONFIG_SYN_TECH smic013
79 #elif defined CONFIG_SYN_UT025CRH
79 #elif defined CONFIG_SYN_UT025CRH
80 #define CONFIG_SYN_TECH ut25
80 #define CONFIG_SYN_TECH ut25
81 #elif defined CONFIG_SYN_UT130HBD
81 #elif defined CONFIG_SYN_UT130HBD
82 #define CONFIG_SYN_TECH ut130
82 #define CONFIG_SYN_TECH ut130
83 #elif defined CONFIG_SYN_UT90NHBD
83 #elif defined CONFIG_SYN_UT90NHBD
84 #define CONFIG_SYN_TECH ut90
84 #define CONFIG_SYN_TECH ut90
85 #elif defined CONFIG_SYN_TSMC90
85 #elif defined CONFIG_SYN_TSMC90
86 #define CONFIG_SYN_TECH tsmc90
86 #define CONFIG_SYN_TECH tsmc90
87 #elif defined CONFIG_SYN_TM65GPLUS
87 #elif defined CONFIG_SYN_TM65GPLUS
88 #define CONFIG_SYN_TECH tm65gpl
88 #define CONFIG_SYN_TECH tm65gpl
89 #elif defined CONFIG_SYN_CUSTOM1
89 #elif defined CONFIG_SYN_CUSTOM1
90 #define CONFIG_SYN_TECH custom1
90 #define CONFIG_SYN_TECH custom1
91 #else
91 #else
92 #error "unknown target technology"
92 #error "unknown target technology"
93 #endif
93 #endif
94
94
95 #if defined CONFIG_SYN_INFER_RAM
95 #if defined CONFIG_SYN_INFER_RAM
96 #define CFG_RAM_TECH inferred
96 #define CFG_RAM_TECH inferred
97 #elif defined CONFIG_MEM_UMC
97 #elif defined CONFIG_MEM_UMC
98 #define CFG_RAM_TECH umc
98 #define CFG_RAM_TECH umc
99 #elif defined CONFIG_MEM_RHUMC
99 #elif defined CONFIG_MEM_RHUMC
100 #define CFG_RAM_TECH rhumc
100 #define CFG_RAM_TECH rhumc
101 #elif defined CONFIG_MEM_VIRAGE
101 #elif defined CONFIG_MEM_VIRAGE
102 #define CFG_RAM_TECH memvirage
102 #define CFG_RAM_TECH memvirage
103 #elif defined CONFIG_MEM_ARTISAN
103 #elif defined CONFIG_MEM_ARTISAN
104 #define CFG_RAM_TECH memartisan
104 #define CFG_RAM_TECH memartisan
105 #elif defined CONFIG_MEM_CUSTOM1
105 #elif defined CONFIG_MEM_CUSTOM1
106 #define CFG_RAM_TECH custom1
106 #define CFG_RAM_TECH custom1
107 #elif defined CONFIG_MEM_VIRAGE90
107 #elif defined CONFIG_MEM_VIRAGE90
108 #define CFG_RAM_TECH memvirage90
108 #define CFG_RAM_TECH memvirage90
109 #elif defined CONFIG_MEM_INFERRED
109 #elif defined CONFIG_MEM_INFERRED
110 #define CFG_RAM_TECH inferred
110 #define CFG_RAM_TECH inferred
111 #else
111 #else
112 #define CFG_RAM_TECH CONFIG_SYN_TECH
112 #define CFG_RAM_TECH CONFIG_SYN_TECH
113 #endif
113 #endif
114
114
115 #if defined CONFIG_SYN_INFER_PADS
115 #if defined CONFIG_SYN_INFER_PADS
116 #define CFG_PAD_TECH inferred
116 #define CFG_PAD_TECH inferred
117 #else
117 #else
118 #define CFG_PAD_TECH CONFIG_SYN_TECH
118 #define CFG_PAD_TECH CONFIG_SYN_TECH
119 #endif
119 #endif
120
120
121 #ifndef CONFIG_SYN_NO_ASYNC
121 #ifndef CONFIG_SYN_NO_ASYNC
122 #define CONFIG_SYN_NO_ASYNC 0
122 #define CONFIG_SYN_NO_ASYNC 0
123 #endif
123 #endif
124
124
125 #ifndef CONFIG_SYN_SCAN
125 #ifndef CONFIG_SYN_SCAN
126 #define CONFIG_SYN_SCAN 0
126 #define CONFIG_SYN_SCAN 0
127 #endif
127 #endif
128
128
129
129
130 #if defined CONFIG_CLK_ALTDLL
130 #if defined CONFIG_CLK_ALTDLL
131 #define CFG_CLK_TECH CONFIG_SYN_TECH
131 #define CFG_CLK_TECH CONFIG_SYN_TECH
132 #elif defined CONFIG_CLK_HCLKBUF
132 #elif defined CONFIG_CLK_HCLKBUF
133 #define CFG_CLK_TECH axcel
133 #define CFG_CLK_TECH axcel
134 #elif defined CONFIG_CLK_LATDLL
134 #elif defined CONFIG_CLK_LATDLL
135 #define CFG_CLK_TECH lattice
135 #define CFG_CLK_TECH lattice
136 #elif defined CONFIG_CLK_PRO3PLL
136 #elif defined CONFIG_CLK_PRO3PLL
137 #define CFG_CLK_TECH apa3
137 #define CFG_CLK_TECH apa3
138 #elif defined CONFIG_CLK_PRO3EPLL
138 #elif defined CONFIG_CLK_PRO3EPLL
139 #define CFG_CLK_TECH apa3e
139 #define CFG_CLK_TECH apa3e
140 #elif defined CONFIG_CLK_PRO3LPLL
140 #elif defined CONFIG_CLK_PRO3LPLL
141 #define CFG_CLK_TECH apa3l
141 #define CFG_CLK_TECH apa3l
142 #elif defined CONFIG_CLK_FUSPLL
142 #elif defined CONFIG_CLK_FUSPLL
143 #define CFG_CLK_TECH actfus
143 #define CFG_CLK_TECH actfus
144 #elif defined CONFIG_CLK_CLKDLL
144 #elif defined CONFIG_CLK_CLKDLL
145 #define CFG_CLK_TECH virtex
145 #define CFG_CLK_TECH virtex
146 #elif defined CONFIG_CLK_DCM
146 #elif defined CONFIG_CLK_DCM
147 #define CFG_CLK_TECH CONFIG_SYN_TECH
147 #define CFG_CLK_TECH CONFIG_SYN_TECH
148 #elif defined CONFIG_CLK_LIB18T
148 #elif defined CONFIG_CLK_LIB18T
149 #define CFG_CLK_TECH rhlib18t
149 #define CFG_CLK_TECH rhlib18t
150 #elif defined CONFIG_CLK_RHUMC
150 #elif defined CONFIG_CLK_RHUMC
151 #define CFG_CLK_TECH rhumc
151 #define CFG_CLK_TECH rhumc
152 #elif defined CONFIG_CLK_UT130HBD
152 #elif defined CONFIG_CLK_UT130HBD
153 #define CFG_CLK_TECH ut130
153 #define CFG_CLK_TECH ut130
154 #else
154 #else
155 #define CFG_CLK_TECH inferred
155 #define CFG_CLK_TECH inferred
156 #endif
156 #endif
157
157
158 #ifndef CONFIG_CLK_MUL
158 #ifndef CONFIG_CLK_MUL
159 #define CONFIG_CLK_MUL 2
159 #define CONFIG_CLK_MUL 2
160 #endif
160 #endif
161
161
162 #ifndef CONFIG_CLK_DIV
162 #ifndef CONFIG_CLK_DIV
163 #define CONFIG_CLK_DIV 2
163 #define CONFIG_CLK_DIV 2
164 #endif
164 #endif
165
165
166 #ifndef CONFIG_OCLK_DIV
166 #ifndef CONFIG_OCLK_DIV
167 #define CONFIG_OCLK_DIV 1
167 #define CONFIG_OCLK_DIV 1
168 #endif
168 #endif
169
169
170 #ifndef CONFIG_OCLKB_DIV
170 #ifndef CONFIG_OCLKB_DIV
171 #define CONFIG_OCLKB_DIV 0
171 #define CONFIG_OCLKB_DIV 0
172 #endif
172 #endif
173
173
174 #ifndef CONFIG_OCLKC_DIV
174 #ifndef CONFIG_OCLKC_DIV
175 #define CONFIG_OCLKC_DIV 0
175 #define CONFIG_OCLKC_DIV 0
176 #endif
176 #endif
177
177
178 #ifndef CONFIG_PCI_CLKDLL
178 #ifndef CONFIG_PCI_CLKDLL
179 #define CONFIG_PCI_CLKDLL 0
179 #define CONFIG_PCI_CLKDLL 0
180 #endif
180 #endif
181
181
182 #ifndef CONFIG_PCI_SYSCLK
182 #ifndef CONFIG_PCI_SYSCLK
183 #define CONFIG_PCI_SYSCLK 0
183 #define CONFIG_PCI_SYSCLK 0
184 #endif
184 #endif
185
185
186 #ifndef CONFIG_CLK_NOFB
186 #ifndef CONFIG_CLK_NOFB
187 #define CONFIG_CLK_NOFB 0
187 #define CONFIG_CLK_NOFB 0
188 #endif
188 #endif
189 #ifndef CONFIG_LEON3
189 #ifndef CONFIG_LEON3
190 #define CONFIG_LEON3 0
190 #define CONFIG_LEON3 0
191 #endif
191 #endif
192
192
193 #ifndef CONFIG_PROC_NUM
193 #ifndef CONFIG_PROC_NUM
194 #define CONFIG_PROC_NUM 1
194 #define CONFIG_PROC_NUM 1
195 #endif
195 #endif
196
196
197 #ifndef CONFIG_IU_NWINDOWS
197 #ifndef CONFIG_IU_NWINDOWS
198 #define CONFIG_IU_NWINDOWS 8
198 #define CONFIG_IU_NWINDOWS 8
199 #endif
199 #endif
200
200
201 #ifndef CONFIG_IU_RSTADDR
201 #ifndef CONFIG_IU_RSTADDR
202 #define CONFIG_IU_RSTADDR 8
202 #define CONFIG_IU_RSTADDR 8
203 #endif
203 #endif
204
204
205 #ifndef CONFIG_IU_LDELAY
205 #ifndef CONFIG_IU_LDELAY
206 #define CONFIG_IU_LDELAY 1
206 #define CONFIG_IU_LDELAY 1
207 #endif
207 #endif
208
208
209 #ifndef CONFIG_IU_WATCHPOINTS
209 #ifndef CONFIG_IU_WATCHPOINTS
210 #define CONFIG_IU_WATCHPOINTS 0
210 #define CONFIG_IU_WATCHPOINTS 0
211 #endif
211 #endif
212
212
213 #ifdef CONFIG_IU_V8MULDIV
213 #ifdef CONFIG_IU_V8MULDIV
214 #ifdef CONFIG_IU_MUL_LATENCY_4
214 #ifdef CONFIG_IU_MUL_LATENCY_4
215 #define CFG_IU_V8 1
215 #define CFG_IU_V8 1
216 #elif defined CONFIG_IU_MUL_LATENCY_5
216 #elif defined CONFIG_IU_MUL_LATENCY_5
217 #define CFG_IU_V8 2
217 #define CFG_IU_V8 2
218 #elif defined CONFIG_IU_MUL_LATENCY_2
218 #elif defined CONFIG_IU_MUL_LATENCY_2
219 #define CFG_IU_V8 16#32#
219 #define CFG_IU_V8 16#32#
220 #endif
220 #endif
221 #else
221 #else
222 #define CFG_IU_V8 0
222 #define CFG_IU_V8 0
223 #endif
223 #endif
224
224
225 #ifdef CONFIG_IU_MUL_MODGEN
225 #ifdef CONFIG_IU_MUL_MODGEN
226 #define CFG_IU_MUL_STRUCT 1
226 #define CFG_IU_MUL_STRUCT 1
227 #elif defined CONFIG_IU_MUL_TECHSPEC
227 #elif defined CONFIG_IU_MUL_TECHSPEC
228 #define CFG_IU_MUL_STRUCT 2
228 #define CFG_IU_MUL_STRUCT 2
229 #elif defined CONFIG_IU_MUL_DW
229 #elif defined CONFIG_IU_MUL_DW
230 #define CFG_IU_MUL_STRUCT 3
230 #define CFG_IU_MUL_STRUCT 3
231 #else
231 #else
232 #define CFG_IU_MUL_STRUCT 0
232 #define CFG_IU_MUL_STRUCT 0
233 #endif
233 #endif
234
234
235 #ifndef CONFIG_PWD
235 #ifndef CONFIG_PWD
236 #define CONFIG_PWD 0
236 #define CONFIG_PWD 0
237 #endif
237 #endif
238
238
239 #ifndef CONFIG_IU_MUL_MAC
239 #ifndef CONFIG_IU_MUL_MAC
240 #define CONFIG_IU_MUL_MAC 0
240 #define CONFIG_IU_MUL_MAC 0
241 #endif
241 #endif
242
242
243 #ifndef CONFIG_IU_BP
243 #ifndef CONFIG_IU_BP
244 #define CONFIG_IU_BP 0
244 #define CONFIG_IU_BP 0
245 #endif
245 #endif
246
246
247 #ifndef CONFIG_NOTAG
247 #ifndef CONFIG_NOTAG
248 #define CONFIG_NOTAG 0
248 #define CONFIG_NOTAG 0
249 #endif
249 #endif
250
250
251 #ifndef CONFIG_IU_SVT
251 #ifndef CONFIG_IU_SVT
252 #define CONFIG_IU_SVT 0
252 #define CONFIG_IU_SVT 0
253 #endif
253 #endif
254
254
255 #if defined CONFIG_FPU_GRFPC1
255 #if defined CONFIG_FPU_GRFPC1
256 #define CONFIG_FPU_GRFPC 1
256 #define CONFIG_FPU_GRFPC 1
257 #elif defined CONFIG_FPU_GRFPC2
257 #elif defined CONFIG_FPU_GRFPC2
258 #define CONFIG_FPU_GRFPC 2
258 #define CONFIG_FPU_GRFPC 2
259 #else
259 #else
260 #define CONFIG_FPU_GRFPC 0
260 #define CONFIG_FPU_GRFPC 0
261 #endif
261 #endif
262
262
263 #if defined CONFIG_FPU_GRFPU_INFMUL
263 #if defined CONFIG_FPU_GRFPU_INFMUL
264 #define CONFIG_FPU_GRFPU_MUL 0
264 #define CONFIG_FPU_GRFPU_MUL 0
265 #elif defined CONFIG_FPU_GRFPU_DWMUL
265 #elif defined CONFIG_FPU_GRFPU_DWMUL
266 #define CONFIG_FPU_GRFPU_MUL 1
266 #define CONFIG_FPU_GRFPU_MUL 1
267 #elif defined CONFIG_FPU_GRFPU_MODGEN
267 #elif defined CONFIG_FPU_GRFPU_MODGEN
268 #define CONFIG_FPU_GRFPU_MUL 2
268 #define CONFIG_FPU_GRFPU_MUL 2
269 #elif defined CONFIG_FPU_GRFPU_TECHSPEC
269 #elif defined CONFIG_FPU_GRFPU_TECHSPEC
270 #define CONFIG_FPU_GRFPU_MUL 3
270 #define CONFIG_FPU_GRFPU_MUL 3
271 #else
271 #else
272 #define CONFIG_FPU_GRFPU_MUL 0
272 #define CONFIG_FPU_GRFPU_MUL 0
273 #endif
273 #endif
274
274
275 #if defined CONFIG_FPU_GRFPU_SH
275 #if defined CONFIG_FPU_GRFPU_SH
276 #define CONFIG_FPU_GRFPU_SHARED 1
276 #define CONFIG_FPU_GRFPU_SHARED 1
277 #else
277 #else
278 #define CONFIG_FPU_GRFPU_SHARED 0
278 #define CONFIG_FPU_GRFPU_SHARED 0
279 #endif
279 #endif
280
280
281 #if defined CONFIG_FPU_GRFPU
281 #if defined CONFIG_FPU_GRFPU
282 #define CONFIG_FPU (1+CONFIG_FPU_GRFPU_MUL)
282 #define CONFIG_FPU (1+CONFIG_FPU_GRFPU_MUL)
283 #elif defined CONFIG_FPU_MEIKO
283 #elif defined CONFIG_FPU_MEIKO
284 #define CONFIG_FPU 15
284 #define CONFIG_FPU 15
285 #elif defined CONFIG_FPU_GRFPULITE
285 #elif defined CONFIG_FPU_GRFPULITE
286 #define CONFIG_FPU (8+CONFIG_FPU_GRFPC)
286 #define CONFIG_FPU (8+CONFIG_FPU_GRFPC)
287 #else
287 #else
288 #define CONFIG_FPU 0
288 #define CONFIG_FPU 0
289 #endif
289 #endif
290
290
291 #ifndef CONFIG_FPU_NETLIST
291 #ifndef CONFIG_FPU_NETLIST
292 #define CONFIG_FPU_NETLIST 0
292 #define CONFIG_FPU_NETLIST 0
293 #endif
293 #endif
294
294
295 #ifndef CONFIG_ICACHE_ENABLE
295 #ifndef CONFIG_ICACHE_ENABLE
296 #define CONFIG_ICACHE_ENABLE 0
296 #define CONFIG_ICACHE_ENABLE 0
297 #endif
297 #endif
298
298
299 #if defined CONFIG_ICACHE_ASSO1
299 #if defined CONFIG_ICACHE_ASSO1
300 #define CFG_IU_ISETS 1
300 #define CFG_IU_ISETS 1
301 #elif defined CONFIG_ICACHE_ASSO2
301 #elif defined CONFIG_ICACHE_ASSO2
302 #define CFG_IU_ISETS 2
302 #define CFG_IU_ISETS 2
303 #elif defined CONFIG_ICACHE_ASSO3
303 #elif defined CONFIG_ICACHE_ASSO3
304 #define CFG_IU_ISETS 3
304 #define CFG_IU_ISETS 3
305 #elif defined CONFIG_ICACHE_ASSO4
305 #elif defined CONFIG_ICACHE_ASSO4
306 #define CFG_IU_ISETS 4
306 #define CFG_IU_ISETS 4
307 #else
307 #else
308 #define CFG_IU_ISETS 1
308 #define CFG_IU_ISETS 1
309 #endif
309 #endif
310
310
311 #if defined CONFIG_ICACHE_SZ1
311 #if defined CONFIG_ICACHE_SZ1
312 #define CFG_ICACHE_SZ 1
312 #define CFG_ICACHE_SZ 1
313 #elif defined CONFIG_ICACHE_SZ2
313 #elif defined CONFIG_ICACHE_SZ2
314 #define CFG_ICACHE_SZ 2
314 #define CFG_ICACHE_SZ 2
315 #elif defined CONFIG_ICACHE_SZ4
315 #elif defined CONFIG_ICACHE_SZ4
316 #define CFG_ICACHE_SZ 4
316 #define CFG_ICACHE_SZ 4
317 #elif defined CONFIG_ICACHE_SZ8
317 #elif defined CONFIG_ICACHE_SZ8
318 #define CFG_ICACHE_SZ 8
318 #define CFG_ICACHE_SZ 8
319 #elif defined CONFIG_ICACHE_SZ16
319 #elif defined CONFIG_ICACHE_SZ16
320 #define CFG_ICACHE_SZ 16
320 #define CFG_ICACHE_SZ 16
321 #elif defined CONFIG_ICACHE_SZ32
321 #elif defined CONFIG_ICACHE_SZ32
322 #define CFG_ICACHE_SZ 32
322 #define CFG_ICACHE_SZ 32
323 #elif defined CONFIG_ICACHE_SZ64
323 #elif defined CONFIG_ICACHE_SZ64
324 #define CFG_ICACHE_SZ 64
324 #define CFG_ICACHE_SZ 64
325 #elif defined CONFIG_ICACHE_SZ128
325 #elif defined CONFIG_ICACHE_SZ128
326 #define CFG_ICACHE_SZ 128
326 #define CFG_ICACHE_SZ 128
327 #elif defined CONFIG_ICACHE_SZ256
327 #elif defined CONFIG_ICACHE_SZ256
328 #define CFG_ICACHE_SZ 256
328 #define CFG_ICACHE_SZ 256
329 #else
329 #else
330 #define CFG_ICACHE_SZ 1
330 #define CFG_ICACHE_SZ 1
331 #endif
331 #endif
332
332
333 #ifdef CONFIG_ICACHE_LZ16
333 #ifdef CONFIG_ICACHE_LZ16
334 #define CFG_ILINE_SZ 4
334 #define CFG_ILINE_SZ 4
335 #else
335 #else
336 #define CFG_ILINE_SZ 8
336 #define CFG_ILINE_SZ 8
337 #endif
337 #endif
338
338
339 #if defined CONFIG_ICACHE_ALGODIR
339 #if defined CONFIG_ICACHE_ALGODIR
340 #define CFG_ICACHE_ALGORND 3
340 #define CFG_ICACHE_ALGORND 3
341 #elif defined CONFIG_ICACHE_ALGORND
341 #elif defined CONFIG_ICACHE_ALGORND
342 #define CFG_ICACHE_ALGORND 2
342 #define CFG_ICACHE_ALGORND 2
343 #elif defined CONFIG_ICACHE_ALGOLRR
343 #elif defined CONFIG_ICACHE_ALGOLRR
344 #define CFG_ICACHE_ALGORND 1
344 #define CFG_ICACHE_ALGORND 1
345 #else
345 #else
346 #define CFG_ICACHE_ALGORND 0
346 #define CFG_ICACHE_ALGORND 0
347 #endif
347 #endif
348
348
349 #ifndef CONFIG_ICACHE_LOCK
349 #ifndef CONFIG_ICACHE_LOCK
350 #define CONFIG_ICACHE_LOCK 0
350 #define CONFIG_ICACHE_LOCK 0
351 #endif
351 #endif
352
352
353 #ifndef CONFIG_ICACHE_LRAM
353 #ifndef CONFIG_ICACHE_LRAM
354 #define CONFIG_ICACHE_LRAM 0
354 #define CONFIG_ICACHE_LRAM 0
355 #endif
355 #endif
356
356
357 #ifndef CONFIG_ICACHE_LRSTART
357 #ifndef CONFIG_ICACHE_LRSTART
358 #define CONFIG_ICACHE_LRSTART 8E
358 #define CONFIG_ICACHE_LRSTART 8E
359 #endif
359 #endif
360
360
361 #if defined CONFIG_ICACHE_LRAM_SZ2
361 #if defined CONFIG_ICACHE_LRAM_SZ2
362 #define CFG_ILRAM_SIZE 2
362 #define CFG_ILRAM_SIZE 2
363 #elif defined CONFIG_ICACHE_LRAM_SZ4
363 #elif defined CONFIG_ICACHE_LRAM_SZ4
364 #define CFG_ILRAM_SIZE 4
364 #define CFG_ILRAM_SIZE 4
365 #elif defined CONFIG_ICACHE_LRAM_SZ8
365 #elif defined CONFIG_ICACHE_LRAM_SZ8
366 #define CFG_ILRAM_SIZE 8
366 #define CFG_ILRAM_SIZE 8
367 #elif defined CONFIG_ICACHE_LRAM_SZ16
367 #elif defined CONFIG_ICACHE_LRAM_SZ16
368 #define CFG_ILRAM_SIZE 16
368 #define CFG_ILRAM_SIZE 16
369 #elif defined CONFIG_ICACHE_LRAM_SZ32
369 #elif defined CONFIG_ICACHE_LRAM_SZ32
370 #define CFG_ILRAM_SIZE 32
370 #define CFG_ILRAM_SIZE 32
371 #elif defined CONFIG_ICACHE_LRAM_SZ64
371 #elif defined CONFIG_ICACHE_LRAM_SZ64
372 #define CFG_ILRAM_SIZE 64
372 #define CFG_ILRAM_SIZE 64
373 #elif defined CONFIG_ICACHE_LRAM_SZ128
373 #elif defined CONFIG_ICACHE_LRAM_SZ128
374 #define CFG_ILRAM_SIZE 128
374 #define CFG_ILRAM_SIZE 128
375 #elif defined CONFIG_ICACHE_LRAM_SZ256
375 #elif defined CONFIG_ICACHE_LRAM_SZ256
376 #define CFG_ILRAM_SIZE 256
376 #define CFG_ILRAM_SIZE 256
377 #else
377 #else
378 #define CFG_ILRAM_SIZE 1
378 #define CFG_ILRAM_SIZE 1
379 #endif
379 #endif
380
380
381
381
382 #ifndef CONFIG_DCACHE_ENABLE
382 #ifndef CONFIG_DCACHE_ENABLE
383 #define CONFIG_DCACHE_ENABLE 0
383 #define CONFIG_DCACHE_ENABLE 0
384 #endif
384 #endif
385
385
386 #if defined CONFIG_DCACHE_ASSO1
386 #if defined CONFIG_DCACHE_ASSO1
387 #define CFG_IU_DSETS 1
387 #define CFG_IU_DSETS 1
388 #elif defined CONFIG_DCACHE_ASSO2
388 #elif defined CONFIG_DCACHE_ASSO2
389 #define CFG_IU_DSETS 2
389 #define CFG_IU_DSETS 2
390 #elif defined CONFIG_DCACHE_ASSO3
390 #elif defined CONFIG_DCACHE_ASSO3
391 #define CFG_IU_DSETS 3
391 #define CFG_IU_DSETS 3
392 #elif defined CONFIG_DCACHE_ASSO4
392 #elif defined CONFIG_DCACHE_ASSO4
393 #define CFG_IU_DSETS 4
393 #define CFG_IU_DSETS 4
394 #else
394 #else
395 #define CFG_IU_DSETS 1
395 #define CFG_IU_DSETS 1
396 #endif
396 #endif
397
397
398 #if defined CONFIG_DCACHE_SZ1
398 #if defined CONFIG_DCACHE_SZ1
399 #define CFG_DCACHE_SZ 1
399 #define CFG_DCACHE_SZ 1
400 #elif defined CONFIG_DCACHE_SZ2
400 #elif defined CONFIG_DCACHE_SZ2
401 #define CFG_DCACHE_SZ 2
401 #define CFG_DCACHE_SZ 2
402 #elif defined CONFIG_DCACHE_SZ4
402 #elif defined CONFIG_DCACHE_SZ4
403 #define CFG_DCACHE_SZ 4
403 #define CFG_DCACHE_SZ 4
404 #elif defined CONFIG_DCACHE_SZ8
404 #elif defined CONFIG_DCACHE_SZ8
405 #define CFG_DCACHE_SZ 8
405 #define CFG_DCACHE_SZ 8
406 #elif defined CONFIG_DCACHE_SZ16
406 #elif defined CONFIG_DCACHE_SZ16
407 #define CFG_DCACHE_SZ 16
407 #define CFG_DCACHE_SZ 16
408 #elif defined CONFIG_DCACHE_SZ32
408 #elif defined CONFIG_DCACHE_SZ32
409 #define CFG_DCACHE_SZ 32
409 #define CFG_DCACHE_SZ 32
410 #elif defined CONFIG_DCACHE_SZ64
410 #elif defined CONFIG_DCACHE_SZ64
411 #define CFG_DCACHE_SZ 64
411 #define CFG_DCACHE_SZ 64
412 #elif defined CONFIG_DCACHE_SZ128
412 #elif defined CONFIG_DCACHE_SZ128
413 #define CFG_DCACHE_SZ 128
413 #define CFG_DCACHE_SZ 128
414 #elif defined CONFIG_DCACHE_SZ256
414 #elif defined CONFIG_DCACHE_SZ256
415 #define CFG_DCACHE_SZ 256
415 #define CFG_DCACHE_SZ 256
416 #else
416 #else
417 #define CFG_DCACHE_SZ 1
417 #define CFG_DCACHE_SZ 1
418 #endif
418 #endif
419
419
420 #ifdef CONFIG_DCACHE_LZ16
420 #ifdef CONFIG_DCACHE_LZ16
421 #define CFG_DLINE_SZ 4
421 #define CFG_DLINE_SZ 4
422 #else
422 #else
423 #define CFG_DLINE_SZ 8
423 #define CFG_DLINE_SZ 8
424 #endif
424 #endif
425
425
426 #if defined CONFIG_DCACHE_ALGODIR
426 #if defined CONFIG_DCACHE_ALGODIR
427 #define CFG_DCACHE_ALGORND 3
427 #define CFG_DCACHE_ALGORND 3
428 #elif defined CONFIG_DCACHE_ALGORND
428 #elif defined CONFIG_DCACHE_ALGORND
429 #define CFG_DCACHE_ALGORND 2
429 #define CFG_DCACHE_ALGORND 2
430 #elif defined CONFIG_DCACHE_ALGOLRR
430 #elif defined CONFIG_DCACHE_ALGOLRR
431 #define CFG_DCACHE_ALGORND 1
431 #define CFG_DCACHE_ALGORND 1
432 #else
432 #else
433 #define CFG_DCACHE_ALGORND 0
433 #define CFG_DCACHE_ALGORND 0
434 #endif
434 #endif
435
435
436 #ifndef CONFIG_DCACHE_LOCK
436 #ifndef CONFIG_DCACHE_LOCK
437 #define CONFIG_DCACHE_LOCK 0
437 #define CONFIG_DCACHE_LOCK 0
438 #endif
438 #endif
439
439
440 #ifndef CONFIG_DCACHE_SNOOP
440 #ifndef CONFIG_DCACHE_SNOOP
441 #define CONFIG_DCACHE_SNOOP 0
441 #define CONFIG_DCACHE_SNOOP 0
442 #endif
442 #endif
443
443
444 #ifndef CONFIG_DCACHE_SNOOP_FAST
444 #ifndef CONFIG_DCACHE_SNOOP_FAST
445 #define CONFIG_DCACHE_SNOOP_FAST 0
445 #define CONFIG_DCACHE_SNOOP_FAST 0
446 #endif
446 #endif
447
447
448 #ifndef CONFIG_DCACHE_SNOOP_SEPTAG
448 #ifndef CONFIG_DCACHE_SNOOP_SEPTAG
449 #define CONFIG_DCACHE_SNOOP_SEPTAG 0
449 #define CONFIG_DCACHE_SNOOP_SEPTAG 0
450 #endif
450 #endif
451
451
452 #ifndef CONFIG_CACHE_FIXED
452 #ifndef CONFIG_CACHE_FIXED
453 #define CONFIG_CACHE_FIXED 0
453 #define CONFIG_CACHE_FIXED 0
454 #endif
454 #endif
455
455
456 #ifndef CONFIG_DCACHE_LRAM
456 #ifndef CONFIG_DCACHE_LRAM
457 #define CONFIG_DCACHE_LRAM 0
457 #define CONFIG_DCACHE_LRAM 0
458 #endif
458 #endif
459
459
460 #ifndef CONFIG_DCACHE_LRSTART
460 #ifndef CONFIG_DCACHE_LRSTART
461 #define CONFIG_DCACHE_LRSTART 8F
461 #define CONFIG_DCACHE_LRSTART 8F
462 #endif
462 #endif
463
463
464 #if defined CONFIG_DCACHE_LRAM_SZ2
464 #if defined CONFIG_DCACHE_LRAM_SZ2
465 #define CFG_DLRAM_SIZE 2
465 #define CFG_DLRAM_SIZE 2
466 #elif defined CONFIG_DCACHE_LRAM_SZ4
466 #elif defined CONFIG_DCACHE_LRAM_SZ4
467 #define CFG_DLRAM_SIZE 4
467 #define CFG_DLRAM_SIZE 4
468 #elif defined CONFIG_DCACHE_LRAM_SZ8
468 #elif defined CONFIG_DCACHE_LRAM_SZ8
469 #define CFG_DLRAM_SIZE 8
469 #define CFG_DLRAM_SIZE 8
470 #elif defined CONFIG_DCACHE_LRAM_SZ16
470 #elif defined CONFIG_DCACHE_LRAM_SZ16
471 #define CFG_DLRAM_SIZE 16
471 #define CFG_DLRAM_SIZE 16
472 #elif defined CONFIG_DCACHE_LRAM_SZ32
472 #elif defined CONFIG_DCACHE_LRAM_SZ32
473 #define CFG_DLRAM_SIZE 32
473 #define CFG_DLRAM_SIZE 32
474 #elif defined CONFIG_DCACHE_LRAM_SZ64
474 #elif defined CONFIG_DCACHE_LRAM_SZ64
475 #define CFG_DLRAM_SIZE 64
475 #define CFG_DLRAM_SIZE 64
476 #elif defined CONFIG_DCACHE_LRAM_SZ128
476 #elif defined CONFIG_DCACHE_LRAM_SZ128
477 #define CFG_DLRAM_SIZE 128
477 #define CFG_DLRAM_SIZE 128
478 #elif defined CONFIG_DCACHE_LRAM_SZ256
478 #elif defined CONFIG_DCACHE_LRAM_SZ256
479 #define CFG_DLRAM_SIZE 256
479 #define CFG_DLRAM_SIZE 256
480 #else
480 #else
481 #define CFG_DLRAM_SIZE 1
481 #define CFG_DLRAM_SIZE 1
482 #endif
482 #endif
483
483
484 #if defined CONFIG_MMU_PAGE_4K
484 #if defined CONFIG_MMU_PAGE_4K
485 #define CONFIG_MMU_PAGE 0
485 #define CONFIG_MMU_PAGE 0
486 #elif defined CONFIG_MMU_PAGE_8K
486 #elif defined CONFIG_MMU_PAGE_8K
487 #define CONFIG_MMU_PAGE 1
487 #define CONFIG_MMU_PAGE 1
488 #elif defined CONFIG_MMU_PAGE_16K
488 #elif defined CONFIG_MMU_PAGE_16K
489 #define CONFIG_MMU_PAGE 2
489 #define CONFIG_MMU_PAGE 2
490 #elif defined CONFIG_MMU_PAGE_32K
490 #elif defined CONFIG_MMU_PAGE_32K
491 #define CONFIG_MMU_PAGE 3
491 #define CONFIG_MMU_PAGE 3
492 #elif defined CONFIG_MMU_PAGE_PROG
492 #elif defined CONFIG_MMU_PAGE_PROG
493 #define CONFIG_MMU_PAGE 4
493 #define CONFIG_MMU_PAGE 4
494 #else
494 #else
495 #define CONFIG_MMU_PAGE 0
495 #define CONFIG_MMU_PAGE 0
496 #endif
496 #endif
497
497
498 #ifdef CONFIG_MMU_ENABLE
498 #ifdef CONFIG_MMU_ENABLE
499 #define CONFIG_MMUEN 1
499 #define CONFIG_MMUEN 1
500
500
501 #ifdef CONFIG_MMU_SPLIT
501 #ifdef CONFIG_MMU_SPLIT
502 #define CONFIG_TLB_TYPE 0
502 #define CONFIG_TLB_TYPE 0
503 #endif
503 #endif
504 #ifdef CONFIG_MMU_COMBINED
504 #ifdef CONFIG_MMU_COMBINED
505 #define CONFIG_TLB_TYPE 1
505 #define CONFIG_TLB_TYPE 1
506 #endif
506 #endif
507
507
508 #ifdef CONFIG_MMU_REPARRAY
508 #ifdef CONFIG_MMU_REPARRAY
509 #define CONFIG_TLB_REP 0
509 #define CONFIG_TLB_REP 0
510 #endif
510 #endif
511 #ifdef CONFIG_MMU_REPINCREMENT
511 #ifdef CONFIG_MMU_REPINCREMENT
512 #define CONFIG_TLB_REP 1
512 #define CONFIG_TLB_REP 1
513 #endif
513 #endif
514
514
515 #ifdef CONFIG_MMU_I2
515 #ifdef CONFIG_MMU_I2
516 #define CONFIG_ITLBNUM 2
516 #define CONFIG_ITLBNUM 2
517 #endif
517 #endif
518 #ifdef CONFIG_MMU_I4
518 #ifdef CONFIG_MMU_I4
519 #define CONFIG_ITLBNUM 4
519 #define CONFIG_ITLBNUM 4
520 #endif
520 #endif
521 #ifdef CONFIG_MMU_I8
521 #ifdef CONFIG_MMU_I8
522 #define CONFIG_ITLBNUM 8
522 #define CONFIG_ITLBNUM 8
523 #endif
523 #endif
524 #ifdef CONFIG_MMU_I16
524 #ifdef CONFIG_MMU_I16
525 #define CONFIG_ITLBNUM 16
525 #define CONFIG_ITLBNUM 16
526 #endif
526 #endif
527 #ifdef CONFIG_MMU_I32
527 #ifdef CONFIG_MMU_I32
528 #define CONFIG_ITLBNUM 32
528 #define CONFIG_ITLBNUM 32
529 #endif
529 #endif
530
530
531 #define CONFIG_DTLBNUM 2
531 #define CONFIG_DTLBNUM 2
532 #ifdef CONFIG_MMU_D2
532 #ifdef CONFIG_MMU_D2
533 #undef CONFIG_DTLBNUM
533 #undef CONFIG_DTLBNUM
534 #define CONFIG_DTLBNUM 2
534 #define CONFIG_DTLBNUM 2
535 #endif
535 #endif
536 #ifdef CONFIG_MMU_D4
536 #ifdef CONFIG_MMU_D4
537 #undef CONFIG_DTLBNUM
537 #undef CONFIG_DTLBNUM
538 #define CONFIG_DTLBNUM 4
538 #define CONFIG_DTLBNUM 4
539 #endif
539 #endif
540 #ifdef CONFIG_MMU_D8
540 #ifdef CONFIG_MMU_D8
541 #undef CONFIG_DTLBNUM
541 #undef CONFIG_DTLBNUM
542 #define CONFIG_DTLBNUM 8
542 #define CONFIG_DTLBNUM 8
543 #endif
543 #endif
544 #ifdef CONFIG_MMU_D16
544 #ifdef CONFIG_MMU_D16
545 #undef CONFIG_DTLBNUM
545 #undef CONFIG_DTLBNUM
546 #define CONFIG_DTLBNUM 16
546 #define CONFIG_DTLBNUM 16
547 #endif
547 #endif
548 #ifdef CONFIG_MMU_D32
548 #ifdef CONFIG_MMU_D32
549 #undef CONFIG_DTLBNUM
549 #undef CONFIG_DTLBNUM
550 #define CONFIG_DTLBNUM 32
550 #define CONFIG_DTLBNUM 32
551 #endif
551 #endif
552 #ifdef CONFIG_MMU_FASTWB
552 #ifdef CONFIG_MMU_FASTWB
553 #define CFG_MMU_FASTWB 1
553 #define CFG_MMU_FASTWB 1
554 #else
554 #else
555 #define CFG_MMU_FASTWB 0
555 #define CFG_MMU_FASTWB 0
556 #endif
556 #endif
557
557
558 #else
558 #else
559 #define CONFIG_MMUEN 0
559 #define CONFIG_MMUEN 0
560 #define CONFIG_ITLBNUM 2
560 #define CONFIG_ITLBNUM 2
561 #define CONFIG_DTLBNUM 2
561 #define CONFIG_DTLBNUM 2
562 #define CONFIG_TLB_TYPE 1
562 #define CONFIG_TLB_TYPE 1
563 #define CONFIG_TLB_REP 1
563 #define CONFIG_TLB_REP 1
564 #define CFG_MMU_FASTWB 0
564 #define CFG_MMU_FASTWB 0
565 #endif
565 #endif
566
566
567 #ifndef CONFIG_DSU_ENABLE
567 #ifndef CONFIG_DSU_ENABLE
568 #define CONFIG_DSU_ENABLE 0
568 #define CONFIG_DSU_ENABLE 0
569 #endif
569 #endif
570
570
571 #if defined CONFIG_DSU_ITRACESZ1
571 #if defined CONFIG_DSU_ITRACESZ1
572 #define CFG_DSU_ITB 1
572 #define CFG_DSU_ITB 1
573 #elif CONFIG_DSU_ITRACESZ2
573 #elif CONFIG_DSU_ITRACESZ2
574 #define CFG_DSU_ITB 2
574 #define CFG_DSU_ITB 2
575 #elif CONFIG_DSU_ITRACESZ4
575 #elif CONFIG_DSU_ITRACESZ4
576 #define CFG_DSU_ITB 4
576 #define CFG_DSU_ITB 4
577 #elif CONFIG_DSU_ITRACESZ8
577 #elif CONFIG_DSU_ITRACESZ8
578 #define CFG_DSU_ITB 8
578 #define CFG_DSU_ITB 8
579 #elif CONFIG_DSU_ITRACESZ16
579 #elif CONFIG_DSU_ITRACESZ16
580 #define CFG_DSU_ITB 16
580 #define CFG_DSU_ITB 16
581 #else
581 #else
582 #define CFG_DSU_ITB 0
582 #define CFG_DSU_ITB 0
583 #endif
583 #endif
584
584
585 #if defined CONFIG_DSU_ATRACESZ1
585 #if defined CONFIG_DSU_ATRACESZ1
586 #define CFG_DSU_ATB 1
586 #define CFG_DSU_ATB 1
587 #elif CONFIG_DSU_ATRACESZ2
587 #elif CONFIG_DSU_ATRACESZ2
588 #define CFG_DSU_ATB 2
588 #define CFG_DSU_ATB 2
589 #elif CONFIG_DSU_ATRACESZ4
589 #elif CONFIG_DSU_ATRACESZ4
590 #define CFG_DSU_ATB 4
590 #define CFG_DSU_ATB 4
591 #elif CONFIG_DSU_ATRACESZ8
591 #elif CONFIG_DSU_ATRACESZ8
592 #define CFG_DSU_ATB 8
592 #define CFG_DSU_ATB 8
593 #elif CONFIG_DSU_ATRACESZ16
593 #elif CONFIG_DSU_ATRACESZ16
594 #define CFG_DSU_ATB 16
594 #define CFG_DSU_ATB 16
595 #else
595 #else
596 #define CFG_DSU_ATB 0
596 #define CFG_DSU_ATB 0
597 #endif
597 #endif
598
598
599 #ifndef CONFIG_LEON3FT_EN
599 #ifndef CONFIG_LEON3FT_EN
600 #define CONFIG_LEON3FT_EN 0
600 #define CONFIG_LEON3FT_EN 0
601 #endif
601 #endif
602
602
603 #if defined CONFIG_IUFT_PAR
603 #if defined CONFIG_IUFT_PAR
604 #define CONFIG_IUFT_EN 1
604 #define CONFIG_IUFT_EN 1
605 #elif defined CONFIG_IUFT_DMR
605 #elif defined CONFIG_IUFT_DMR
606 #define CONFIG_IUFT_EN 2
606 #define CONFIG_IUFT_EN 2
607 #elif defined CONFIG_IUFT_BCH
607 #elif defined CONFIG_IUFT_BCH
608 #define CONFIG_IUFT_EN 3
608 #define CONFIG_IUFT_EN 3
609 #elif defined CONFIG_IUFT_TMR
609 #elif defined CONFIG_IUFT_TMR
610 #define CONFIG_IUFT_EN 4
610 #define CONFIG_IUFT_EN 4
611 #else
611 #else
612 #define CONFIG_IUFT_EN 0
612 #define CONFIG_IUFT_EN 0
613 #endif
613 #endif
614 #ifndef CONFIG_RF_ERRINJ
614 #ifndef CONFIG_RF_ERRINJ
615 #define CONFIG_RF_ERRINJ 0
615 #define CONFIG_RF_ERRINJ 0
616 #endif
616 #endif
617
617
618 #ifndef CONFIG_FPUFT_EN
618 #ifndef CONFIG_FPUFT_EN
619 #define CONFIG_FPUFT 0
619 #define CONFIG_FPUFT 0
620 #else
620 #else
621 #ifdef CONFIG_FPU_GRFPU
621 #ifdef CONFIG_FPU_GRFPU
622 #define CONFIG_FPUFT 2
622 #define CONFIG_FPUFT 2
623 #else
623 #else
624 #define CONFIG_FPUFT 1
624 #define CONFIG_FPUFT 1
625 #endif
625 #endif
626 #endif
626 #endif
627
627
628 #ifndef CONFIG_CACHE_FT_EN
628 #ifndef CONFIG_CACHE_FT_EN
629 #define CONFIG_CACHE_FT_EN 0
629 #define CONFIG_CACHE_FT_EN 0
630 #endif
630 #endif
631 #ifndef CONFIG_CACHE_ERRINJ
631 #ifndef CONFIG_CACHE_ERRINJ
632 #define CONFIG_CACHE_ERRINJ 0
632 #define CONFIG_CACHE_ERRINJ 0
633 #endif
633 #endif
634
634
635 #ifndef CONFIG_LEON3_NETLIST
635 #ifndef CONFIG_LEON3_NETLIST
636 #define CONFIG_LEON3_NETLIST 0
636 #define CONFIG_LEON3_NETLIST 0
637 #endif
637 #endif
638
638
639 #ifdef CONFIG_DEBUG_PC32
639 #ifdef CONFIG_DEBUG_PC32
640 #define CFG_DEBUG_PC32 0
640 #define CFG_DEBUG_PC32 0
641 #else
641 #else
642 #define CFG_DEBUG_PC32 2
642 #define CFG_DEBUG_PC32 2
643 #endif
643 #endif
644 #ifndef CONFIG_IU_DISAS
644 #ifndef CONFIG_IU_DISAS
645 #define CONFIG_IU_DISAS 0
645 #define CONFIG_IU_DISAS 0
646 #endif
646 #endif
647 #ifndef CONFIG_IU_DISAS_NET
647 #ifndef CONFIG_IU_DISAS_NET
648 #define CONFIG_IU_DISAS_NET 0
648 #define CONFIG_IU_DISAS_NET 0
649 #endif
649 #endif
650
650
651
651
652 #ifndef CONFIG_AHB_SPLIT
652 #ifndef CONFIG_AHB_SPLIT
653 #define CONFIG_AHB_SPLIT 0
653 #define CONFIG_AHB_SPLIT 0
654 #endif
654 #endif
655
655
656 #ifndef CONFIG_AHB_RROBIN
656 #ifndef CONFIG_AHB_RROBIN
657 #define CONFIG_AHB_RROBIN 0
657 #define CONFIG_AHB_RROBIN 0
658 #endif
658 #endif
659
659
660 #ifndef CONFIG_AHB_IOADDR
660 #ifndef CONFIG_AHB_IOADDR
661 #define CONFIG_AHB_IOADDR FFF
661 #define CONFIG_AHB_IOADDR FFF
662 #endif
662 #endif
663
663
664 #ifndef CONFIG_APB_HADDR
664 #ifndef CONFIG_APB_HADDR
665 #define CONFIG_APB_HADDR 800
665 #define CONFIG_APB_HADDR 800
666 #endif
666 #endif
667
667
668 #ifndef CONFIG_AHB_MON
668 #ifndef CONFIG_AHB_MON
669 #define CONFIG_AHB_MON 0
669 #define CONFIG_AHB_MON 0
670 #endif
670 #endif
671
671
672 #ifndef CONFIG_AHB_MONERR
672 #ifndef CONFIG_AHB_MONERR
673 #define CONFIG_AHB_MONERR 0
673 #define CONFIG_AHB_MONERR 0
674 #endif
674 #endif
675
675
676 #ifndef CONFIG_AHB_MONWAR
676 #ifndef CONFIG_AHB_MONWAR
677 #define CONFIG_AHB_MONWAR 0
677 #define CONFIG_AHB_MONWAR 0
678 #endif
678 #endif
679
679
680 #ifndef CONFIG_AHB_DTRACE
680 #ifndef CONFIG_AHB_DTRACE
681 #define CONFIG_AHB_DTRACE 0
681 #define CONFIG_AHB_DTRACE 0
682 #endif
682 #endif
683
683
684 #ifndef CONFIG_DSU_JTAG
684 #ifndef CONFIG_DSU_JTAG
685 #define CONFIG_DSU_JTAG 0
685 #define CONFIG_DSU_JTAG 0
686 #endif
686 #endif
687
687
688 #ifndef CONFIG_DSU_ETH
688 #ifndef CONFIG_DSU_ETH
689 #define CONFIG_DSU_ETH 0
689 #define CONFIG_DSU_ETH 0
690 #endif
690 #endif
691
691
692 #ifndef CONFIG_DSU_IPMSB
692 #ifndef CONFIG_DSU_IPMSB
693 #define CONFIG_DSU_IPMSB C0A8
693 #define CONFIG_DSU_IPMSB C0A8
694 #endif
694 #endif
695
695
696 #ifndef CONFIG_DSU_IPLSB
696 #ifndef CONFIG_DSU_IPLSB
697 #define CONFIG_DSU_IPLSB 0033
697 #define CONFIG_DSU_IPLSB 0033
698 #endif
698 #endif
699
699
700 #ifndef CONFIG_DSU_ETHMSB
700 #ifndef CONFIG_DSU_ETHMSB
701 #define CONFIG_DSU_ETHMSB 020000
701 #define CONFIG_DSU_ETHMSB 020000
702 #endif
702 #endif
703
703
704 #ifndef CONFIG_DSU_ETHLSB
704 #ifndef CONFIG_DSU_ETHLSB
705 #define CONFIG_DSU_ETHLSB 000009
705 #define CONFIG_DSU_ETHLSB 000009
706 #endif
706 #endif
707
707
708 #if defined CONFIG_DSU_ETHSZ1
708 #if defined CONFIG_DSU_ETHSZ1
709 #define CFG_DSU_ETHB 1
709 #define CFG_DSU_ETHB 1
710 #elif CONFIG_DSU_ETHSZ2
710 #elif CONFIG_DSU_ETHSZ2
711 #define CFG_DSU_ETHB 2
711 #define CFG_DSU_ETHB 2
712 #elif CONFIG_DSU_ETHSZ4
712 #elif CONFIG_DSU_ETHSZ4
713 #define CFG_DSU_ETHB 4
713 #define CFG_DSU_ETHB 4
714 #elif CONFIG_DSU_ETHSZ8
714 #elif CONFIG_DSU_ETHSZ8
715 #define CFG_DSU_ETHB 8
715 #define CFG_DSU_ETHB 8
716 #elif CONFIG_DSU_ETHSZ16
716 #elif CONFIG_DSU_ETHSZ16
717 #define CFG_DSU_ETHB 16
717 #define CFG_DSU_ETHB 16
718 #elif CONFIG_DSU_ETHSZ32
718 #elif CONFIG_DSU_ETHSZ32
719 #define CFG_DSU_ETHB 32
719 #define CFG_DSU_ETHB 32
720 #else
720 #else
721 #define CFG_DSU_ETHB 1
721 #define CFG_DSU_ETHB 1
722 #endif
722 #endif
723
723
724 #ifndef CONFIG_DSU_ETH_PROG
724 #ifndef CONFIG_DSU_ETH_PROG
725 #define CONFIG_DSU_ETH_PROG 0
725 #define CONFIG_DSU_ETH_PROG 0
726 #endif
726 #endif
727
727
728 #ifndef CONFIG_DSU_ETH_DIS
728 #ifndef CONFIG_DSU_ETH_DIS
729 #define CONFIG_DSU_ETH_DIS 0
729 #define CONFIG_DSU_ETH_DIS 0
730 #endif
730 #endif
731
731
732 #ifndef CONFIG_MCTRL_LEON2
732 #ifndef CONFIG_MCTRL_LEON2
733 #define CONFIG_MCTRL_LEON2 0
733 #define CONFIG_MCTRL_LEON2 0
734 #endif
734 #endif
735
735
736 #ifndef CONFIG_MCTRL_SDRAM
736 #ifndef CONFIG_MCTRL_SDRAM
737 #define CONFIG_MCTRL_SDRAM 0
737 #define CONFIG_MCTRL_SDRAM 0
738 #endif
738 #endif
739
739
740 #ifndef CONFIG_MCTRL_SDRAM_SEPBUS
740 #ifndef CONFIG_MCTRL_SDRAM_SEPBUS
741 #define CONFIG_MCTRL_SDRAM_SEPBUS 0
741 #define CONFIG_MCTRL_SDRAM_SEPBUS 0
742 #endif
742 #endif
743
743
744 #ifndef CONFIG_MCTRL_SDRAM_INVCLK
744 #ifndef CONFIG_MCTRL_SDRAM_INVCLK
745 #define CONFIG_MCTRL_SDRAM_INVCLK 0
745 #define CONFIG_MCTRL_SDRAM_INVCLK 0
746 #endif
746 #endif
747
747
748 #ifndef CONFIG_MCTRL_SDRAM_BUS64
748 #ifndef CONFIG_MCTRL_SDRAM_BUS64
749 #define CONFIG_MCTRL_SDRAM_BUS64 0
749 #define CONFIG_MCTRL_SDRAM_BUS64 0
750 #endif
750 #endif
751
751
752 #ifndef CONFIG_MCTRL_8BIT
752 #ifndef CONFIG_MCTRL_8BIT
753 #define CONFIG_MCTRL_8BIT 0
753 #define CONFIG_MCTRL_8BIT 0
754 #endif
754 #endif
755
755
756 #ifndef CONFIG_MCTRL_16BIT
756 #ifndef CONFIG_MCTRL_16BIT
757 #define CONFIG_MCTRL_16BIT 0
757 #define CONFIG_MCTRL_16BIT 0
758 #endif
758 #endif
759
759
760 #ifndef CONFIG_MCTRL_5CS
760 #ifndef CONFIG_MCTRL_5CS
761 #define CONFIG_MCTRL_5CS 0
761 #define CONFIG_MCTRL_5CS 0
762 #endif
762 #endif
763
763
764 #ifndef CONFIG_MCTRL_EDAC
764 #ifndef CONFIG_MCTRL_EDAC
765 #define CONFIG_MCTRL_EDAC 0
765 #define CONFIG_MCTRL_EDAC 0
766 #endif
766 #endif
767
767
768 #ifndef CONFIG_MCTRL_PAGE
768 #ifndef CONFIG_MCTRL_PAGE
769 #define CONFIG_MCTRL_PAGE 0
769 #define CONFIG_MCTRL_PAGE 0
770 #endif
770 #endif
771
771
772 #ifndef CONFIG_MCTRL_PROGPAGE
772 #ifndef CONFIG_MCTRL_PROGPAGE
773 #define CONFIG_MCTRL_PROGPAGE 0
773 #define CONFIG_MCTRL_PROGPAGE 0
774 #endif
774 #endif
775
775
776
776
777 #ifndef CONFIG_MIG_DDR2
777 #ifndef CONFIG_MIG_DDR2
778 #define CONFIG_MIG_DDR2 0
778 #define CONFIG_MIG_DDR2 0
779 #endif
779 #endif
780
780
781 #ifndef CONFIG_MIG_RANKS
781 #ifndef CONFIG_MIG_RANKS
782 #define CONFIG_MIG_RANKS 1
782 #define CONFIG_MIG_RANKS 1
783 #endif
783 #endif
784
784
785 #ifndef CONFIG_MIG_COLBITS
785 #ifndef CONFIG_MIG_COLBITS
786 #define CONFIG_MIG_COLBITS 10
786 #define CONFIG_MIG_COLBITS 10
787 #endif
787 #endif
788
788
789 #ifndef CONFIG_MIG_ROWBITS
789 #ifndef CONFIG_MIG_ROWBITS
790 #define CONFIG_MIG_ROWBITS 13
790 #define CONFIG_MIG_ROWBITS 13
791 #endif
791 #endif
792
792
793 #ifndef CONFIG_MIG_BANKBITS
793 #ifndef CONFIG_MIG_BANKBITS
794 #define CONFIG_MIG_BANKBITS 2
794 #define CONFIG_MIG_BANKBITS 2
795 #endif
795 #endif
796
796
797 #ifndef CONFIG_MIG_HMASK
797 #ifndef CONFIG_MIG_HMASK
798 #define CONFIG_MIG_HMASK F00
798 #define CONFIG_MIG_HMASK F00
799 #endif
799 #endif
800 #ifndef CONFIG_AHBSTAT_ENABLE
800 #ifndef CONFIG_AHBSTAT_ENABLE
801 #define CONFIG_AHBSTAT_ENABLE 0
801 #define CONFIG_AHBSTAT_ENABLE 0
802 #endif
802 #endif
803
803
804 #ifndef CONFIG_AHBSTAT_NFTSLV
804 #ifndef CONFIG_AHBSTAT_NFTSLV
805 #define CONFIG_AHBSTAT_NFTSLV 1
805 #define CONFIG_AHBSTAT_NFTSLV 1
806 #endif
806 #endif
807
807
808 #ifndef CONFIG_AHBROM_ENABLE
808 #ifndef CONFIG_AHBROM_ENABLE
809 #define CONFIG_AHBROM_ENABLE 0
809 #define CONFIG_AHBROM_ENABLE 0
810 #endif
810 #endif
811
811
812 #ifndef CONFIG_AHBROM_START
812 #ifndef CONFIG_AHBROM_START
813 #define CONFIG_AHBROM_START 000
813 #define CONFIG_AHBROM_START 000
814 #endif
814 #endif
815
815
816 #ifndef CONFIG_AHBROM_PIPE
816 #ifndef CONFIG_AHBROM_PIPE
817 #define CONFIG_AHBROM_PIPE 0
817 #define CONFIG_AHBROM_PIPE 0
818 #endif
818 #endif
819
819
820 #if (CONFIG_AHBROM_START == 0) && (CONFIG_AHBROM_ENABLE == 1)
820 #if (CONFIG_AHBROM_START == 0) && (CONFIG_AHBROM_ENABLE == 1)
821 #define CONFIG_ROM_START 100
821 #define CONFIG_ROM_START 100
822 #else
822 #else
823 #define CONFIG_ROM_START 000
823 #define CONFIG_ROM_START 000
824 #endif
824 #endif
825
825
826
826
827 #ifndef CONFIG_AHBRAM_ENABLE
827 #ifndef CONFIG_AHBRAM_ENABLE
828 #define CONFIG_AHBRAM_ENABLE 0
828 #define CONFIG_AHBRAM_ENABLE 0
829 #endif
829 #endif
830
830
831 #ifndef CONFIG_AHBRAM_START
831 #ifndef CONFIG_AHBRAM_START
832 #define CONFIG_AHBRAM_START A00
832 #define CONFIG_AHBRAM_START A00
833 #endif
833 #endif
834
834
835 #if defined CONFIG_AHBRAM_SZ1
835 #if defined CONFIG_AHBRAM_SZ1
836 #define CFG_AHBRAMSZ 1
836 #define CFG_AHBRAMSZ 1
837 #elif CONFIG_AHBRAM_SZ2
837 #elif CONFIG_AHBRAM_SZ2
838 #define CFG_AHBRAMSZ 2
838 #define CFG_AHBRAMSZ 2
839 #elif CONFIG_AHBRAM_SZ4
839 #elif CONFIG_AHBRAM_SZ4
840 #define CFG_AHBRAMSZ 4
840 #define CFG_AHBRAMSZ 4
841 #elif CONFIG_AHBRAM_SZ8
841 #elif CONFIG_AHBRAM_SZ8
842 #define CFG_AHBRAMSZ 8
842 #define CFG_AHBRAMSZ 8
843 #elif CONFIG_AHBRAM_SZ16
843 #elif CONFIG_AHBRAM_SZ16
844 #define CFG_AHBRAMSZ 16
844 #define CFG_AHBRAMSZ 16
845 #elif CONFIG_AHBRAM_SZ32
845 #elif CONFIG_AHBRAM_SZ32
846 #define CFG_AHBRAMSZ 32
846 #define CFG_AHBRAMSZ 32
847 #elif CONFIG_AHBRAM_SZ64
847 #elif CONFIG_AHBRAM_SZ64
848 #define CFG_AHBRAMSZ 64
848 #define CFG_AHBRAMSZ 64
849 #else
849 #else
850 #define CFG_AHBRAMSZ 1
850 #define CFG_AHBRAMSZ 1
851 #endif
851 #endif
852
852
853 #ifndef CONFIG_GRETH_ENABLE
853 #ifndef CONFIG_GRETH_ENABLE
854 #define CONFIG_GRETH_ENABLE 0
854 #define CONFIG_GRETH_ENABLE 0
855 #endif
855 #endif
856
856
857 #ifndef CONFIG_GRETH_GIGA
857 #ifndef CONFIG_GRETH_GIGA
858 #define CONFIG_GRETH_GIGA 0
858 #define CONFIG_GRETH_GIGA 0
859 #endif
859 #endif
860
860
861 #if defined CONFIG_GRETH_FIFO4
861 #if defined CONFIG_GRETH_FIFO4
862 #define CFG_GRETH_FIFO 4
862 #define CFG_GRETH_FIFO 4
863 #elif defined CONFIG_GRETH_FIFO8
863 #elif defined CONFIG_GRETH_FIFO8
864 #define CFG_GRETH_FIFO 8
864 #define CFG_GRETH_FIFO 8
865 #elif defined CONFIG_GRETH_FIFO16
865 #elif defined CONFIG_GRETH_FIFO16
866 #define CFG_GRETH_FIFO 16
866 #define CFG_GRETH_FIFO 16
867 #elif defined CONFIG_GRETH_FIFO32
867 #elif defined CONFIG_GRETH_FIFO32
868 #define CFG_GRETH_FIFO 32
868 #define CFG_GRETH_FIFO 32
869 #elif defined CONFIG_GRETH_FIFO64
869 #elif defined CONFIG_GRETH_FIFO64
870 #define CFG_GRETH_FIFO 64
870 #define CFG_GRETH_FIFO 64
871 #else
871 #else
872 #define CFG_GRETH_FIFO 8
872 #define CFG_GRETH_FIFO 8
873 #endif
873 #endif
874
874
875 #ifndef CONFIG_UART1_ENABLE
875 #ifndef CONFIG_UART1_ENABLE
876 #define CONFIG_UART1_ENABLE 0
876 #define CONFIG_UART1_ENABLE 0
877 #endif
877 #endif
878
878
879 #if defined CONFIG_UA1_FIFO1
879 #if defined CONFIG_UA1_FIFO1
880 #define CFG_UA1_FIFO 1
880 #define CFG_UA1_FIFO 1
881 #elif defined CONFIG_UA1_FIFO2
881 #elif defined CONFIG_UA1_FIFO2
882 #define CFG_UA1_FIFO 2
882 #define CFG_UA1_FIFO 2
883 #elif defined CONFIG_UA1_FIFO4
883 #elif defined CONFIG_UA1_FIFO4
884 #define CFG_UA1_FIFO 4
884 #define CFG_UA1_FIFO 4
885 #elif defined CONFIG_UA1_FIFO8
885 #elif defined CONFIG_UA1_FIFO8
886 #define CFG_UA1_FIFO 8
886 #define CFG_UA1_FIFO 8
887 #elif defined CONFIG_UA1_FIFO16
887 #elif defined CONFIG_UA1_FIFO16
888 #define CFG_UA1_FIFO 16
888 #define CFG_UA1_FIFO 16
889 #elif defined CONFIG_UA1_FIFO32
889 #elif defined CONFIG_UA1_FIFO32
890 #define CFG_UA1_FIFO 32
890 #define CFG_UA1_FIFO 32
891 #else
891 #else
892 #define CFG_UA1_FIFO 1
892 #define CFG_UA1_FIFO 1
893 #endif
893 #endif
894
894
895 #ifndef CONFIG_IRQ3_ENABLE
895 #ifndef CONFIG_IRQ3_ENABLE
896 #define CONFIG_IRQ3_ENABLE 0
896 #define CONFIG_IRQ3_ENABLE 0
897 #endif
897 #endif
898 #ifndef CONFIG_IRQ3_NSEC
898 #ifndef CONFIG_IRQ3_NSEC
899 #define CONFIG_IRQ3_NSEC 0
899 #define CONFIG_IRQ3_NSEC 0
900 #endif
900 #endif
901 #ifndef CONFIG_GPT_ENABLE
901 #ifndef CONFIG_GPT_ENABLE
902 #define CONFIG_GPT_ENABLE 0
902 #define CONFIG_GPT_ENABLE 0
903 #endif
903 #endif
904
904
905 #ifndef CONFIG_GPT_NTIM
905 #ifndef CONFIG_GPT_NTIM
906 #define CONFIG_GPT_NTIM 1
906 #define CONFIG_GPT_NTIM 1
907 #endif
907 #endif
908
908
909 #ifndef CONFIG_GPT_SW
909 #ifndef CONFIG_GPT_SW
910 #define CONFIG_GPT_SW 8
910 #define CONFIG_GPT_SW 8
911 #endif
911 #endif
912
912
913 #ifndef CONFIG_GPT_TW
913 #ifndef CONFIG_GPT_TW
914 #define CONFIG_GPT_TW 8
914 #define CONFIG_GPT_TW 8
915 #endif
915 #endif
916
916
917 #ifndef CONFIG_GPT_IRQ
917 #ifndef CONFIG_GPT_IRQ
918 #define CONFIG_GPT_IRQ 8
918 #define CONFIG_GPT_IRQ 8
919 #endif
919 #endif
920
920
921 #ifndef CONFIG_GPT_SEPIRQ
921 #ifndef CONFIG_GPT_SEPIRQ
922 #define CONFIG_GPT_SEPIRQ 0
922 #define CONFIG_GPT_SEPIRQ 0
923 #endif
923 #endif
924 #ifndef CONFIG_GPT_ENABLE
924 #ifndef CONFIG_GPT_ENABLE
925 #define CONFIG_GPT_ENABLE 0
925 #define CONFIG_GPT_ENABLE 0
926 #endif
926 #endif
927
927
928 #ifndef CONFIG_GPT_NTIM
928 #ifndef CONFIG_GPT_NTIM
929 #define CONFIG_GPT_NTIM 1
929 #define CONFIG_GPT_NTIM 1
930 #endif
930 #endif
931
931
932 #ifndef CONFIG_GPT_SW
932 #ifndef CONFIG_GPT_SW
933 #define CONFIG_GPT_SW 8
933 #define CONFIG_GPT_SW 8
934 #endif
934 #endif
935
935
936 #ifndef CONFIG_GPT_TW
936 #ifndef CONFIG_GPT_TW
937 #define CONFIG_GPT_TW 8
937 #define CONFIG_GPT_TW 8
938 #endif
938 #endif
939
939
940 #ifndef CONFIG_GPT_IRQ
940 #ifndef CONFIG_GPT_IRQ
941 #define CONFIG_GPT_IRQ 8
941 #define CONFIG_GPT_IRQ 8
942 #endif
942 #endif
943
943
944 #ifndef CONFIG_GPT_SEPIRQ
944 #ifndef CONFIG_GPT_SEPIRQ
945 #define CONFIG_GPT_SEPIRQ 0
945 #define CONFIG_GPT_SEPIRQ 0
946 #endif
946 #endif
947
947
948 #ifndef CONFIG_GPT_WDOGEN
948 #ifndef CONFIG_GPT_WDOGEN
949 #define CONFIG_GPT_WDOGEN 0
949 #define CONFIG_GPT_WDOGEN 0
950 #endif
950 #endif
951
951
952 #ifndef CONFIG_GPT_WDOG
952 #ifndef CONFIG_GPT_WDOG
953 #define CONFIG_GPT_WDOG 0
953 #define CONFIG_GPT_WDOG 0
954 #endif
954 #endif
955
955
956 #ifndef CONFIG_GRGPIO_ENABLE
956 #ifndef CONFIG_GRGPIO_ENABLE
957 #define CONFIG_GRGPIO_ENABLE 0
957 #define CONFIG_GRGPIO_ENABLE 0
958 #endif
958 #endif
959 #ifndef CONFIG_GRGPIO_IMASK
959 #ifndef CONFIG_GRGPIO_IMASK
960 #define CONFIG_GRGPIO_IMASK 0000
960 #define CONFIG_GRGPIO_IMASK 0000
961 #endif
961 #endif
962 #ifndef CONFIG_GRGPIO_WIDTH
962 #ifndef CONFIG_GRGPIO_WIDTH
963 #define CONFIG_GRGPIO_WIDTH 1
963 #define CONFIG_GRGPIO_WIDTH 1
964 #endif
964 #endif
965
965
966 #ifndef CONFIG_VGA_ENABLE
966 #ifndef CONFIG_VGA_ENABLE
967 #define CONFIG_VGA_ENABLE 0
967 #define CONFIG_VGA_ENABLE 0
968 #endif
968 #endif
969 #ifndef CONFIG_SVGA_ENABLE
969 #ifndef CONFIG_SVGA_ENABLE
970 #define CONFIG_SVGA_ENABLE 0
970 #define CONFIG_SVGA_ENABLE 0
971 #endif
971 #endif
972 #ifndef CONFIG_KBD_ENABLE
972 #ifndef CONFIG_KBD_ENABLE
973 #define CONFIG_KBD_ENABLE 0
973 #define CONFIG_KBD_ENABLE 0
974 #endif
974 #endif
975
975
976
976
977 #ifndef CONFIG_SPIMCTRL
977 #ifndef CONFIG_SPIMCTRL
978 #define CONFIG_SPIMCTRL 0
978 #define CONFIG_SPIMCTRL 0
979 #endif
979 #endif
980
980
981 #ifndef CONFIG_SPIMCTRL_SDCARD
981 #ifndef CONFIG_SPIMCTRL_SDCARD
982 #define CONFIG_SPIMCTRL_SDCARD 0
982 #define CONFIG_SPIMCTRL_SDCARD 0
983 #endif
983 #endif
984
984
985 #ifndef CONFIG_SPIMCTRL_READCMD
985 #ifndef CONFIG_SPIMCTRL_READCMD
986 #define CONFIG_SPIMCTRL_READCMD 0
986 #define CONFIG_SPIMCTRL_READCMD 0
987 #endif
987 #endif
988
988
989 #ifndef CONFIG_SPIMCTRL_DUMMYBYTE
989 #ifndef CONFIG_SPIMCTRL_DUMMYBYTE
990 #define CONFIG_SPIMCTRL_DUMMYBYTE 0
990 #define CONFIG_SPIMCTRL_DUMMYBYTE 0
991 #endif
991 #endif
992
992
993 #ifndef CONFIG_SPIMCTRL_DUALOUTPUT
993 #ifndef CONFIG_SPIMCTRL_DUALOUTPUT
994 #define CONFIG_SPIMCTRL_DUALOUTPUT 0
994 #define CONFIG_SPIMCTRL_DUALOUTPUT 0
995 #endif
995 #endif
996
996
997 #ifndef CONFIG_SPIMCTRL_SCALER
997 #ifndef CONFIG_SPIMCTRL_SCALER
998 #define CONFIG_SPIMCTRL_SCALER 1
998 #define CONFIG_SPIMCTRL_SCALER 1
999 #endif
999 #endif
1000
1000
1001 #ifndef CONFIG_SPIMCTRL_ASCALER
1001 #ifndef CONFIG_SPIMCTRL_ASCALER
1002 #define CONFIG_SPIMCTRL_ASCALER 1
1002 #define CONFIG_SPIMCTRL_ASCALER 1
1003 #endif
1003 #endif
1004
1004
1005 #ifndef CONFIG_SPIMCTRL_PWRUPCNT
1005 #ifndef CONFIG_SPIMCTRL_PWRUPCNT
1006 #define CONFIG_SPIMCTRL_PWRUPCNT 0
1006 #define CONFIG_SPIMCTRL_PWRUPCNT 0
1007 #endif
1007 #endif
1008 #ifndef CONFIG_SPICTRL_ENABLE
1008 #ifndef CONFIG_SPICTRL_ENABLE
1009 #define CONFIG_SPICTRL_ENABLE 0
1009 #define CONFIG_SPICTRL_ENABLE 0
1010 #endif
1010 #endif
1011 #ifndef CONFIG_SPICTRL_NUM
1011 #ifndef CONFIG_SPICTRL_NUM
1012 #define CONFIG_SPICTRL_NUM 1
1012 #define CONFIG_SPICTRL_NUM 1
1013 #endif
1013 #endif
1014 #ifndef CONFIG_SPICTRL_SLVS
1014 #ifndef CONFIG_SPICTRL_SLVS
1015 #define CONFIG_SPICTRL_SLVS 1
1015 #define CONFIG_SPICTRL_SLVS 1
1016 #endif
1016 #endif
1017 #ifndef CONFIG_SPICTRL_FIFO
1017 #ifndef CONFIG_SPICTRL_FIFO
1018 #define CONFIG_SPICTRL_FIFO 1
1018 #define CONFIG_SPICTRL_FIFO 1
1019 #endif
1019 #endif
1020 #ifndef CONFIG_SPICTRL_SLVREG
1020 #ifndef CONFIG_SPICTRL_SLVREG
1021 #define CONFIG_SPICTRL_SLVREG 0
1021 #define CONFIG_SPICTRL_SLVREG 0
1022 #endif
1022 #endif
1023 #ifndef CONFIG_SPICTRL_ODMODE
1023 #ifndef CONFIG_SPICTRL_ODMODE
1024 #define CONFIG_SPICTRL_ODMODE 0
1024 #define CONFIG_SPICTRL_ODMODE 0
1025 #endif
1025 #endif
1026 #ifndef CONFIG_SPICTRL_AM
1026 #ifndef CONFIG_SPICTRL_AM
1027 #define CONFIG_SPICTRL_AM 0
1027 #define CONFIG_SPICTRL_AM 0
1028 #endif
1028 #endif
1029 #ifndef CONFIG_SPICTRL_ASEL
1029 #ifndef CONFIG_SPICTRL_ASEL
1030 #define CONFIG_SPICTRL_ASEL 0
1030 #define CONFIG_SPICTRL_ASEL 0
1031 #endif
1031 #endif
1032 #ifndef CONFIG_SPICTRL_TWEN
1032 #ifndef CONFIG_SPICTRL_TWEN
1033 #define CONFIG_SPICTRL_TWEN 0
1033 #define CONFIG_SPICTRL_TWEN 0
1034 #endif
1034 #endif
1035 #ifndef CONFIG_SPICTRL_MAXWLEN
1035 #ifndef CONFIG_SPICTRL_MAXWLEN
1036 #define CONFIG_SPICTRL_MAXWLEN 0
1036 #define CONFIG_SPICTRL_MAXWLEN 0
1037 #endif
1037 #endif
1038 #ifndef CONFIG_SPICTRL_SYNCRAM
1038 #ifndef CONFIG_SPICTRL_SYNCRAM
1039 #define CONFIG_SPICTRL_SYNCRAM 0
1039 #define CONFIG_SPICTRL_SYNCRAM 0
1040 #endif
1040 #endif
1041 #if defined(CONFIG_SPICTRL_DMRFT)
1041 #if defined(CONFIG_SPICTRL_DMRFT)
1042 #define CONFIG_SPICTRL_FT 1
1042 #define CONFIG_SPICTRL_FT 1
1043 #elif defined(CONFIG_SPICTRL_TMRFT)
1043 #elif defined(CONFIG_SPICTRL_TMRFT)
1044 #define CONFIG_SPICTRL_FT 2
1044 #define CONFIG_SPICTRL_FT 2
1045 #else
1045 #else
1046 #define CONFIG_SPICTRL_FT 0
1046 #define CONFIG_SPICTRL_FT 0
1047 #endif
1047 #endif
1048
1048
1049 #ifndef CONFIG_DEBUG_UART
1049 #ifndef CONFIG_DEBUG_UART
1050 #define CONFIG_DEBUG_UART 0
1050 #define CONFIG_DEBUG_UART 0
1051 #endif
1051 #endif
Show file before | Show file after | Hide comments
@@ -1,209 +1,209
1 This leon3 design is tailored to the Xilinx SP605 Spartan6 board
1 This leon3 design is tailored to the Xilinx SP605 Spartan6 board
2
2
3 Simulation and synthesis
3 Simulation and synthesis
4 ------------------------
4 ------------------------
5
5
6 The design uses the Xilinx MIG memory interface with an AHB-2.0
6 The design uses the Xilinx MIG memory interface with an AHB-2.0
7 interface. The MIG source code cannot be distributed due to the
7 interface. The MIG source code cannot be distributed due to the
8 prohibitive Xilinx license, so the MIG must be re-generated with
8 prohibitive Xilinx license, so the MIG must be re-generated with
9 coregen before simulation and synthesis can be done.
9 coregen before simulation and synthesis can be done.
10
10
11 To generate the MIG and install tne Xilinx unisim simulation
11 To generate the MIG and install tne Xilinx unisim simulation
12 library, do as follows:
12 library, do as follows:
13
13
14 make mig
14 make mig
15 make install-secureip
15 make install-secureip
16
16
17 This will ONLY work with ISE-13.2 installed, and the XILINX variable
17 This will ONLY work with ISE-13.2 installed, and the XILINX variable
18 properly set in the shell. To synthesize the design, do
18 properly set in the shell. To synthesize the design, do
19
19
20 make ise
20 make ise
21
21
22 and then
22 and then
23
23
24 make ise-prog-fpga
24 make ise-prog-fpga
25
25
26 to program the FPGA.
26 to program the FPGA.
27
27
28 Design specifics
28 Design specifics
29 ----------------
29 ----------------
30
30
31 * System reset is mapped to the CPU RESET button
31 * System reset is mapped to the CPU RESET button
32
32
33 * The AHB and processor is clocked by a 60 MHz clock, generated
33 * The AHB and processor is clocked by a 60 MHz clock, generated
34 from the 33 MHz SYSACE clock using a DCM. You can change the frequency
34 from the 33 MHz SYSACE clock using a DCM. You can change the frequency
35 generation in the clocks menu of xconfig. The DDR3 (MIG) controller
35 generation in the clocks menu of xconfig. The DDR3 (MIG) controller
36 runs at 667 MHz.
36 runs at 667 MHz.
37
37
38 * The GRETH core is enabled and runs without problems at 100 Mbit.
38 * The GRETH core is enabled and runs without problems at 100 Mbit.
39 Ethernet debug link is enabled and has IP 192.168.0.51.
39 Ethernet debug link is enabled and has IP 192.168.0.51.
40 1 Gbit operation is also possible (requires grlib com release),
40 1 Gbit operation is also possible (requires grlib com release),
41 uncomment related timing constraints in the leon3mp.ucf first.
41 uncomment related timing constraints in the leon3mp.ucf first.
42
42
43 * 16-bit flash prom can be read at address 0. It can be programmed
43 * 16-bit flash prom can be read at address 0. It can be programmed
44 with GRMON version 1.1.16 or later.
44 with GRMON version 1.1.16 or later.
45
45
46 * DDR3 is working with the provided Xilinx MIG DDR3 controller.
46 * DDR3 is working with the provided Xilinx MIG DDR3 controller.
47 If you want to simulate this design, first install the secure
47 If you want to simulate this design, first install the secure
48 IP models with:
48 IP models with:
49
49
50 make install-secureip
50 make install-secureip
51
51
52 Then rebuild the scripts and simulation model:
52 Then rebuild the scripts and simulation model:
53
53
54 make distclean vsim
54 make distclean vsim
55
55
56 Modelsim v6.6e or newer is required to build the secure IP models.
56 Modelsim v6.6e or newer is required to build the secure IP models.
57 Note that the regular leon3 test bench cannot be run in simulation
57 Note that the regular leon3 test bench cannot be run in simulation
58 as the DDR3 model lacks data pre-load.
58 as the DDR3 model lacks data pre-load.
59
59
60 * The application UART1 is connected to the USB/UART connector
60 * The application UART1 is connected to the USB/UART connector
61
61
62 * The SVGA frame buffer uses a separate port on the DDR3 controller,
62 * The SVGA frame buffer uses a separate port on the DDR3 controller,
63 and therefore does not noticeably affect the performance of the processor.
63 and therefore does not noticeably affect the performance of the processor.
64 Default output is analog VGA, to switch to DVI mode execute this
64 Default output is analog VGA, to switch to DVI mode execute this
65 command in grmon:
65 command in grmon:
66
66
67 i2c dvi init_l4itx_vga
67 i2c dvi init_l4itx_vga
68
68
69 * The JTAG DSU interface is enabled and accesible via the USB/JTAG port.
69 * The JTAG DSU interface is enabled and accesible via the USB/JTAG port.
70 Start grmon with -xilusb to connect.
70 Start grmon with -xilusb to connect.
71
71
72 * Output from GRMON is:
72 * Output from GRMON is:
73
73
74 $ grmon -xilusb -u
74 $ grmon -xilusb -u
75
75
76 GRMON LEON debug monitor v1.1.51 professional version (debug)
76 GRMON LEON debug monitor v1.1.51 professional version (debug)
77
77
78 Copyright (C) 2004-2011 Aeroflex Gaisler - all rights reserved.
78 Copyright (C) 2004-2011 Aeroflex Gaisler - all rights reserved.
79 For latest updates, go to http://www.gaisler.com/
79 For latest updates, go to http://www.gaisler.com/
80 Comments or bug-reports to support@gaisler.com
80 Comments or bug-reports to support@gaisler.com
81
81
82 Xilinx cable: Cable type/rev : 0x3
82 Xilinx cable: Cable type/rev : 0x3
83 JTAG chain: xc6slx45t xccace
83 JTAG chain: xc6slx45t xccace
84
84
85 GRLIB build version: 4111
85 GRLIB build version: 4111
86
86
87 initialising ...............
87 initialising ...............
88 detected frequency: 50 MHz
88 detected frequency: 50 MHz
89 SRAM waitstates: 1
89 SRAM waitstates: 1
90
90
91 Component Vendor
91 Component Vendor
92 LEON3 SPARC V8 Processor Gaisler Research
92 LEON3 SPARC V8 Processor Gaisler Research
93 AHB Debug JTAG TAP Gaisler Research
93 AHB Debug JTAG TAP Gaisler Research
94 GR Ethernet MAC Gaisler Research
94 GR Ethernet MAC Gaisler Research
95 LEON2 Memory Controller European Space Agency
95 LEON2 Memory Controller European Space Agency
96 AHB/APB Bridge Gaisler Research
96 AHB/APB Bridge Gaisler Research
97 LEON3 Debug Support Unit Gaisler Research
97 LEON3 Debug Support Unit Gaisler Research
98 Xilinx MIG DDR2 controller Gaisler Research
98 Xilinx MIG DDR2 controller Gaisler Research
99 AHB/APB Bridge Gaisler Research
99 AHB/APB Bridge Gaisler Research
100 Generic APB UART Gaisler Research
100 Generic APB UART Gaisler Research
101 Multi-processor Interrupt Ctrl Gaisler Research
101 Multi-processor Interrupt Ctrl Gaisler Research
102 Modular Timer Unit Gaisler Research
102 Modular Timer Unit Gaisler Research
103 SVGA Controller Gaisler Research
103 SVGA Controller Gaisler Research
104 AMBA Wrapper for OC I2C-master Gaisler Research
104 AMBA Wrapper for OC I2C-master Gaisler Research
105 General purpose I/O port Gaisler Research
105 General purpose I/O port Gaisler Research
106 AHB status register Gaisler Research
106 AHB status register Gaisler Research
107
107
108 Use command 'info sys' to print a detailed report of attached cores
108 Use command 'info sys' to print a detailed report of attached cores
109
109
110 grlib> inf sys
110 grlib> inf sys
111 00.01:003 Gaisler Research LEON3 SPARC V8 Processor (ver 0x0)
111 00.01:003 Gaisler Research LEON3 SPARC V8 Processor (ver 0x0)
112 ahb master 0
112 ahb master 0
113 01.01:01c Gaisler Research AHB Debug JTAG TAP (ver 0x1)
113 01.01:01c Gaisler Research AHB Debug JTAG TAP (ver 0x1)
114 ahb master 1
114 ahb master 1
115 02.01:01d Gaisler Research GR Ethernet MAC (ver 0x0)
115 02.01:01d Gaisler Research GR Ethernet MAC (ver 0x0)
116 ahb master 2, irq 12
116 ahb master 2, irq 12
117 apb: 80000e00 - 80000f00
117 apb: 80000e00 - 80000f00
118 Device index: dev0
118 Device index: dev0
119 edcl ip 192.168.1.51, buffer 2 kbyte
119 edcl ip 192.168.1.51, buffer 2 kbyte
120 00.04:00f European Space Agency LEON2 Memory Controller (ver 0x1)
120 00.04:00f European Space Agency LEON2 Memory Controller (ver 0x1)
121 ahb: 00000000 - 20000000
121 ahb: 00000000 - 20000000
122 apb: 80000000 - 80000100
122 apb: 80000000 - 80000100
123 16-bit prom @ 0x00000000
123 16-bit prom @ 0x00000000
124 01.01:006 Gaisler Research AHB/APB Bridge (ver 0x0)
124 01.01:006 Gaisler Research AHB/APB Bridge (ver 0x0)
125 ahb: 80000000 - 80100000
125 ahb: 80000000 - 80100000
126 02.01:004 Gaisler Research LEON3 Debug Support Unit (ver 0x1)
126 02.01:004 Gaisler Research LEON3 Debug Support Unit (ver 0x1)
127 ahb: 90000000 - a0000000
127 ahb: 90000000 - a0000000
128 AHB trace 256 lines, 32-bit bus, stack pointer 0x47fffff0
128 AHB trace 256 lines, 32-bit bus, stack pointer 0x47fffff0
129 CPU#0 win 8, hwbp 2, itrace 256, V8 mul/div, srmmu, lddel 1
129 CPU#0 win 8, hwbp 2, itrace 256, V8 mul/div, srmmu, lddel 1
130 icache 2 * 8 kbyte, 32 byte/line rnd
130 icache 2 * 8 kbyte, 32 byte/line rnd
131 dcache 2 * 4 kbyte, 16 byte/line rnd
131 dcache 2 * 4 kbyte, 16 byte/line rnd
132 04.01:06b Gaisler Research Xilinx MIG DDR2 controller (ver 0x0)
132 04.01:06b Gaisler Research Xilinx MIG DDR2 controller (ver 0x0)
133 ahb: 40000000 - 48000000
133 ahb: 40000000 - 48000000
134 apb: 80100000 - 80100100
134 apb: 80100000 - 80100100
135 DDR2: 128 Mbyte
135 DDR2: 128 Mbyte
136 0d.01:006 Gaisler Research AHB/APB Bridge (ver 0x0)
136 0d.01:006 Gaisler Research AHB/APB Bridge (ver 0x0)
137 ahb: 80100000 - 80200000
137 ahb: 80100000 - 80200000
138 01.01:00c Gaisler Research Generic APB UART (ver 0x1)
138 01.01:00c Gaisler Research Generic APB UART (ver 0x1)
139 irq 2
139 irq 2
140 apb: 80000100 - 80000200
140 apb: 80000100 - 80000200
141 baud rate 38343, DSU mode (FIFO debug)
141 baud rate 38343, DSU mode (FIFO debug)
142 02.01:00d Gaisler Research Multi-processor Interrupt Ctrl (ver 0x3)
142 02.01:00d Gaisler Research Multi-processor Interrupt Ctrl (ver 0x3)
143 apb: 80000200 - 80000300
143 apb: 80000200 - 80000300
144 03.01:011 Gaisler Research Modular Timer Unit (ver 0x0)
144 03.01:011 Gaisler Research Modular Timer Unit (ver 0x0)
145 irq 8
145 irq 8
146 apb: 80000300 - 80000400
146 apb: 80000300 - 80000400
147 8-bit scaler, 2 * 32-bit timers, divisor 50
147 8-bit scaler, 2 * 32-bit timers, divisor 50
148 06.01:063 Gaisler Research SVGA Controller (ver 0x0)
148 06.01:063 Gaisler Research SVGA Controller (ver 0x0)
149 apb: 80000600 - 80000700
149 apb: 80000600 - 80000700
150 clk0: 50.00 MHz
150 clk0: 50.00 MHz
151 09.01:028 Gaisler Research AMBA Wrapper for OC I2C-master (ver 0x3)
151 09.01:028 Gaisler Research AMBA Wrapper for OC I2C-master (ver 0x3)
152 irq 14
152 irq 14
153 apb: 80000900 - 80000a00
153 apb: 80000900 - 80000a00
154 0a.01:01a Gaisler Research General purpose I/O port (ver 0x1)
154 0a.01:01a Gaisler Research General purpose I/O port (ver 0x1)
155 apb: 80000a00 - 80000b00
155 apb: 80000a00 - 80000b00
156 0f.01:052 Gaisler Research AHB status register (ver 0x0)
156 0f.01:052 Gaisler Research AHB status register (ver 0x0)
157 irq 7
157 irq 7
158 apb: 80000f00 - 80001000
158 apb: 80000f00 - 80001000
159 grlib> fla
159 grlib> fla
160
160
161 Intel-style 16-bit flash on D[31:16]
161 Intel-style 16-bit flash on D[31:16]
162
162
163 Manuf. Intel
163 Manuf. Intel
164 Device Strataflash P30
164 Device Strataflash P30
165
165
166 Device ID 02e44603e127ffff
166 Device ID 02e44603e127ffff
167 User ID ffffffffffffffff
167 User ID ffffffffffffffff
168
168
169
169
170 1 x 32 Mbyte = 32 Mbyte total @ 0x00000000
170 1 x 32 Mbyte = 32 Mbyte total @ 0x00000000
171
171
172
172
173 CFI info
173 CFI info
174 flash family : 1
174 flash family : 1
175 flash size : 256 Mbit
175 flash size : 256 Mbit
176 erase regions : 2
176 erase regions : 2
177 erase blocks : 259
177 erase blocks : 259
178 write buffer : 1024 bytes
178 write buffer : 1024 bytes
179 lock-down : yes
179 lock-down : yes
180 region 0 : 255 blocks of 128 Kbytes
180 region 0 : 255 blocks of 128 Kbytes
181 region 1 : 4 blocks of 32 Kbytes
181 region 1 : 4 blocks of 32 Kbytes
182
182
183 grlib> lo ~/ibm/src/bench/leonbench/coremark.exe
183 grlib> lo ~/ibm/src/bench/leonbench/coremark.exe
184 section: .text at 0x40000000, size 102544 bytes
184 section: .text at 0x40000000, size 102544 bytes
185 section: .data at 0x40019090, size 2788 bytes
185 section: .data at 0x40019090, size 2788 bytes
186 total size: 105332 bytes (1.2 Mbit/s)
186 total size: 105332 bytes (1.2 Mbit/s)
187 read 272 symbols
187 read 272 symbols
188 entry point: 0x40000000
188 entry point: 0x40000000
189 grlib> run
189 grlib> run
190 2K performance run parameters for coremark.
190 2K performance run parameters for coremark.
191 CoreMark Size : 666
191 CoreMark Size : 666
192 Total ticks : 19945918
192 Total ticks : 19945918
193 Total time (secs): 19.945918
193 Total time (secs): 19.945918
194 Iterations/Sec : 100.271143
194 Iterations/Sec : 100.271143
195 Iterations : 2000
195 Iterations : 2000
196 Compiler version : GCC4.4.2
196 Compiler version : GCC4.4.2
197 Compiler flags : -O3 -mv8 -funroll-loops -fgcse-sm -combine -DPERFORMANCE_RUN=1 -mcpu=v8 -msoft-float
197 Compiler flags : -O3 -mv8 -funroll-loops -fgcse-sm -combine -DPERFORMANCE_RUN=1 -mcpu=v8 -msoft-float
198 Memory location : STACK
198 Memory location : STACK
199 seedcrc : 0xe9f5
199 seedcrc : 0xe9f5
200 [0]crclist : 0xe714
200 [0]crclist : 0xe714
201 [0]crcmatrix : 0x1fd7
201 [0]crcmatrix : 0x1fd7
202 [0]crcstate : 0x8e3a
202 [0]crcstate : 0x8e3a
203 [0]crcfinal : 0x4983
203 [0]crcfinal : 0x4983
204 Correct operation validated. See readme.txt for run and reporting rules.
204 Correct operation validated. See readme.txt for run and reporting rules.
205 CoreMark 1.0 : 100.271143 / GCC4.4.2 -O3 -mv8 -funroll-loops -fgcse-sm -combine -DPERFORMANCE_RUN=1 -mcpu=v8 -msoft-float / Stack
205 CoreMark 1.0 : 100.271143 / GCC4.4.2 -O3 -mv8 -funroll-loops -fgcse-sm -combine -DPERFORMANCE_RUN=1 -mcpu=v8 -msoft-float / Stack
206
206
207 Program exited normally.
207 Program exited normally.
208 grlib>
208 grlib>
209
209
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@@ -1,190 +1,190
1 -- Technology and synthesis options
1 -- Technology and synthesis options
2 constant CFG_FABTECH : integer := CONFIG_SYN_TECH;
2 constant CFG_FABTECH : integer := CONFIG_SYN_TECH;
3 constant CFG_MEMTECH : integer := CFG_RAM_TECH;
3 constant CFG_MEMTECH : integer := CFG_RAM_TECH;
4 constant CFG_PADTECH : integer := CFG_PAD_TECH;
4 constant CFG_PADTECH : integer := CFG_PAD_TECH;
5 constant CFG_NOASYNC : integer := CONFIG_SYN_NO_ASYNC;
5 constant CFG_NOASYNC : integer := CONFIG_SYN_NO_ASYNC;
6 constant CFG_SCAN : integer := CONFIG_SYN_SCAN;
6 constant CFG_SCAN : integer := CONFIG_SYN_SCAN;
7
7
8 -- Clock generator
8 -- Clock generator
9 constant CFG_CLKTECH : integer := CFG_CLK_TECH;
9 constant CFG_CLKTECH : integer := CFG_CLK_TECH;
10 constant CFG_CLKMUL : integer := CONFIG_CLK_MUL;
10 constant CFG_CLKMUL : integer := CONFIG_CLK_MUL;
11 constant CFG_CLKDIV : integer := CONFIG_CLK_DIV;
11 constant CFG_CLKDIV : integer := CONFIG_CLK_DIV;
12 constant CFG_OCLKDIV : integer := CONFIG_OCLK_DIV;
12 constant CFG_OCLKDIV : integer := CONFIG_OCLK_DIV;
13 constant CFG_OCLKBDIV : integer := CONFIG_OCLKB_DIV;
13 constant CFG_OCLKBDIV : integer := CONFIG_OCLKB_DIV;
14 constant CFG_OCLKCDIV : integer := CONFIG_OCLKC_DIV;
14 constant CFG_OCLKCDIV : integer := CONFIG_OCLKC_DIV;
15 constant CFG_PCIDLL : integer := CONFIG_PCI_CLKDLL;
15 constant CFG_PCIDLL : integer := CONFIG_PCI_CLKDLL;
16 constant CFG_PCISYSCLK: integer := CONFIG_PCI_SYSCLK;
16 constant CFG_PCISYSCLK: integer := CONFIG_PCI_SYSCLK;
17 constant CFG_CLK_NOFB : integer := CONFIG_CLK_NOFB;
17 constant CFG_CLK_NOFB : integer := CONFIG_CLK_NOFB;
18
18
19 -- LEON3 processor core
19 -- LEON3 processor core
20 constant CFG_LEON3 : integer := CONFIG_LEON3;
20 constant CFG_LEON3 : integer := CONFIG_LEON3;
21 constant CFG_NCPU : integer := CONFIG_PROC_NUM;
21 constant CFG_NCPU : integer := CONFIG_PROC_NUM;
22 constant CFG_NWIN : integer := CONFIG_IU_NWINDOWS;
22 constant CFG_NWIN : integer := CONFIG_IU_NWINDOWS;
23 constant CFG_V8 : integer := CFG_IU_V8 + 4*CFG_IU_MUL_STRUCT;
23 constant CFG_V8 : integer := CFG_IU_V8 + 4*CFG_IU_MUL_STRUCT;
24 constant CFG_MAC : integer := CONFIG_IU_MUL_MAC;
24 constant CFG_MAC : integer := CONFIG_IU_MUL_MAC;
25 constant CFG_BP : integer := CONFIG_IU_BP;
25 constant CFG_BP : integer := CONFIG_IU_BP;
26 constant CFG_SVT : integer := CONFIG_IU_SVT;
26 constant CFG_SVT : integer := CONFIG_IU_SVT;
27 constant CFG_RSTADDR : integer := 16#CONFIG_IU_RSTADDR#;
27 constant CFG_RSTADDR : integer := 16#CONFIG_IU_RSTADDR#;
28 constant CFG_LDDEL : integer := CONFIG_IU_LDELAY;
28 constant CFG_LDDEL : integer := CONFIG_IU_LDELAY;
29 constant CFG_NOTAG : integer := CONFIG_NOTAG;
29 constant CFG_NOTAG : integer := CONFIG_NOTAG;
30 constant CFG_NWP : integer := CONFIG_IU_WATCHPOINTS;
30 constant CFG_NWP : integer := CONFIG_IU_WATCHPOINTS;
31 constant CFG_PWD : integer := CONFIG_PWD*2;
31 constant CFG_PWD : integer := CONFIG_PWD*2;
32 constant CFG_FPU : integer := CONFIG_FPU + 16*CONFIG_FPU_NETLIST + 32*CONFIG_FPU_GRFPU_SHARED;
32 constant CFG_FPU : integer := CONFIG_FPU + 16*CONFIG_FPU_NETLIST + 32*CONFIG_FPU_GRFPU_SHARED;
33 constant CFG_GRFPUSH : integer := CONFIG_FPU_GRFPU_SHARED;
33 constant CFG_GRFPUSH : integer := CONFIG_FPU_GRFPU_SHARED;
34 constant CFG_ICEN : integer := CONFIG_ICACHE_ENABLE;
34 constant CFG_ICEN : integer := CONFIG_ICACHE_ENABLE;
35 constant CFG_ISETS : integer := CFG_IU_ISETS;
35 constant CFG_ISETS : integer := CFG_IU_ISETS;
36 constant CFG_ISETSZ : integer := CFG_ICACHE_SZ;
36 constant CFG_ISETSZ : integer := CFG_ICACHE_SZ;
37 constant CFG_ILINE : integer := CFG_ILINE_SZ;
37 constant CFG_ILINE : integer := CFG_ILINE_SZ;
38 constant CFG_IREPL : integer := CFG_ICACHE_ALGORND;
38 constant CFG_IREPL : integer := CFG_ICACHE_ALGORND;
39 constant CFG_ILOCK : integer := CONFIG_ICACHE_LOCK;
39 constant CFG_ILOCK : integer := CONFIG_ICACHE_LOCK;
40 constant CFG_ILRAMEN : integer := CONFIG_ICACHE_LRAM;
40 constant CFG_ILRAMEN : integer := CONFIG_ICACHE_LRAM;
41 constant CFG_ILRAMADDR: integer := 16#CONFIG_ICACHE_LRSTART#;
41 constant CFG_ILRAMADDR: integer := 16#CONFIG_ICACHE_LRSTART#;
42 constant CFG_ILRAMSZ : integer := CFG_ILRAM_SIZE;
42 constant CFG_ILRAMSZ : integer := CFG_ILRAM_SIZE;
43 constant CFG_DCEN : integer := CONFIG_DCACHE_ENABLE;
43 constant CFG_DCEN : integer := CONFIG_DCACHE_ENABLE;
44 constant CFG_DSETS : integer := CFG_IU_DSETS;
44 constant CFG_DSETS : integer := CFG_IU_DSETS;
45 constant CFG_DSETSZ : integer := CFG_DCACHE_SZ;
45 constant CFG_DSETSZ : integer := CFG_DCACHE_SZ;
46 constant CFG_DLINE : integer := CFG_DLINE_SZ;
46 constant CFG_DLINE : integer := CFG_DLINE_SZ;
47 constant CFG_DREPL : integer := CFG_DCACHE_ALGORND;
47 constant CFG_DREPL : integer := CFG_DCACHE_ALGORND;
48 constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK;
48 constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK;
49 constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG;
49 constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG;
50 constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#;
50 constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#;
51 constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM;
51 constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM;
52 constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#;
52 constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#;
53 constant CFG_DLRAMSZ : integer := CFG_DLRAM_SIZE;
53 constant CFG_DLRAMSZ : integer := CFG_DLRAM_SIZE;
54 constant CFG_MMUEN : integer := CONFIG_MMUEN;
54 constant CFG_MMUEN : integer := CONFIG_MMUEN;
55 constant CFG_ITLBNUM : integer := CONFIG_ITLBNUM;
55 constant CFG_ITLBNUM : integer := CONFIG_ITLBNUM;
56 constant CFG_DTLBNUM : integer := CONFIG_DTLBNUM;
56 constant CFG_DTLBNUM : integer := CONFIG_DTLBNUM;
57 constant CFG_TLB_TYPE : integer := CONFIG_TLB_TYPE + CFG_MMU_FASTWB*2;
57 constant CFG_TLB_TYPE : integer := CONFIG_TLB_TYPE + CFG_MMU_FASTWB*2;
58 constant CFG_TLB_REP : integer := CONFIG_TLB_REP;
58 constant CFG_TLB_REP : integer := CONFIG_TLB_REP;
59 constant CFG_MMU_PAGE : integer := CONFIG_MMU_PAGE;
59 constant CFG_MMU_PAGE : integer := CONFIG_MMU_PAGE;
60 constant CFG_DSU : integer := CONFIG_DSU_ENABLE;
60 constant CFG_DSU : integer := CONFIG_DSU_ENABLE;
61 constant CFG_ITBSZ : integer := CFG_DSU_ITB;
61 constant CFG_ITBSZ : integer := CFG_DSU_ITB;
62 constant CFG_ATBSZ : integer := CFG_DSU_ATB;
62 constant CFG_ATBSZ : integer := CFG_DSU_ATB;
63 constant CFG_LEON3FT_EN : integer := CONFIG_LEON3FT_EN;
63 constant CFG_LEON3FT_EN : integer := CONFIG_LEON3FT_EN;
64 constant CFG_IUFT_EN : integer := CONFIG_IUFT_EN;
64 constant CFG_IUFT_EN : integer := CONFIG_IUFT_EN;
65 constant CFG_FPUFT_EN : integer := CONFIG_FPUFT;
65 constant CFG_FPUFT_EN : integer := CONFIG_FPUFT;
66 constant CFG_RF_ERRINJ : integer := CONFIG_RF_ERRINJ;
66 constant CFG_RF_ERRINJ : integer := CONFIG_RF_ERRINJ;
67 constant CFG_CACHE_FT_EN : integer := CONFIG_CACHE_FT_EN;
67 constant CFG_CACHE_FT_EN : integer := CONFIG_CACHE_FT_EN;
68 constant CFG_CACHE_ERRINJ : integer := CONFIG_CACHE_ERRINJ;
68 constant CFG_CACHE_ERRINJ : integer := CONFIG_CACHE_ERRINJ;
69 constant CFG_LEON3_NETLIST: integer := CONFIG_LEON3_NETLIST;
69 constant CFG_LEON3_NETLIST: integer := CONFIG_LEON3_NETLIST;
70 constant CFG_DISAS : integer := CONFIG_IU_DISAS + CONFIG_IU_DISAS_NET;
70 constant CFG_DISAS : integer := CONFIG_IU_DISAS + CONFIG_IU_DISAS_NET;
71 constant CFG_PCLOW : integer := CFG_DEBUG_PC32;
71 constant CFG_PCLOW : integer := CFG_DEBUG_PC32;
72
72
73 -- AMBA settings
73 -- AMBA settings
74 constant CFG_DEFMST : integer := CONFIG_AHB_DEFMST;
74 constant CFG_DEFMST : integer := CONFIG_AHB_DEFMST;
75 constant CFG_RROBIN : integer := CONFIG_AHB_RROBIN;
75 constant CFG_RROBIN : integer := CONFIG_AHB_RROBIN;
76 constant CFG_SPLIT : integer := CONFIG_AHB_SPLIT;
76 constant CFG_SPLIT : integer := CONFIG_AHB_SPLIT;
77 constant CFG_AHBIO : integer := 16#CONFIG_AHB_IOADDR#;
77 constant CFG_AHBIO : integer := 16#CONFIG_AHB_IOADDR#;
78 constant CFG_APBADDR : integer := 16#CONFIG_APB_HADDR#;
78 constant CFG_APBADDR : integer := 16#CONFIG_APB_HADDR#;
79 constant CFG_AHB_MON : integer := CONFIG_AHB_MON;
79 constant CFG_AHB_MON : integer := CONFIG_AHB_MON;
80 constant CFG_AHB_MONERR : integer := CONFIG_AHB_MONERR;
80 constant CFG_AHB_MONERR : integer := CONFIG_AHB_MONERR;
81 constant CFG_AHB_MONWAR : integer := CONFIG_AHB_MONWAR;
81 constant CFG_AHB_MONWAR : integer := CONFIG_AHB_MONWAR;
82 constant CFG_AHB_DTRACE : integer := CONFIG_AHB_DTRACE;
82 constant CFG_AHB_DTRACE : integer := CONFIG_AHB_DTRACE;
83
83
84 -- JTAG based DSU interface
84 -- JTAG based DSU interface
85 constant CFG_AHB_JTAG : integer := CONFIG_DSU_JTAG;
85 constant CFG_AHB_JTAG : integer := CONFIG_DSU_JTAG;
86
86
87 -- Ethernet DSU
87 -- Ethernet DSU
88 constant CFG_DSU_ETH : integer := CONFIG_DSU_ETH + CONFIG_DSU_ETH_PROG + CONFIG_DSU_ETH_DIS;
88 constant CFG_DSU_ETH : integer := CONFIG_DSU_ETH + CONFIG_DSU_ETH_PROG + CONFIG_DSU_ETH_DIS;
89 constant CFG_ETH_BUF : integer := CFG_DSU_ETHB;
89 constant CFG_ETH_BUF : integer := CFG_DSU_ETHB;
90 constant CFG_ETH_IPM : integer := 16#CONFIG_DSU_IPMSB#;
90 constant CFG_ETH_IPM : integer := 16#CONFIG_DSU_IPMSB#;
91 constant CFG_ETH_IPL : integer := 16#CONFIG_DSU_IPLSB#;
91 constant CFG_ETH_IPL : integer := 16#CONFIG_DSU_IPLSB#;
92 constant CFG_ETH_ENM : integer := 16#CONFIG_DSU_ETHMSB#;
92 constant CFG_ETH_ENM : integer := 16#CONFIG_DSU_ETHMSB#;
93 constant CFG_ETH_ENL : integer := 16#CONFIG_DSU_ETHLSB#;
93 constant CFG_ETH_ENL : integer := 16#CONFIG_DSU_ETHLSB#;
94
94
95 -- LEON2 memory controller
95 -- LEON2 memory controller
96 constant CFG_MCTRL_LEON2 : integer := CONFIG_MCTRL_LEON2;
96 constant CFG_MCTRL_LEON2 : integer := CONFIG_MCTRL_LEON2;
97 constant CFG_MCTRL_RAM8BIT : integer := CONFIG_MCTRL_8BIT;
97 constant CFG_MCTRL_RAM8BIT : integer := CONFIG_MCTRL_8BIT;
98 constant CFG_MCTRL_RAM16BIT : integer := CONFIG_MCTRL_16BIT;
98 constant CFG_MCTRL_RAM16BIT : integer := CONFIG_MCTRL_16BIT;
99 constant CFG_MCTRL_5CS : integer := CONFIG_MCTRL_5CS;
99 constant CFG_MCTRL_5CS : integer := CONFIG_MCTRL_5CS;
100 constant CFG_MCTRL_SDEN : integer := CONFIG_MCTRL_SDRAM;
100 constant CFG_MCTRL_SDEN : integer := CONFIG_MCTRL_SDRAM;
101 constant CFG_MCTRL_SEPBUS : integer := CONFIG_MCTRL_SDRAM_SEPBUS;
101 constant CFG_MCTRL_SEPBUS : integer := CONFIG_MCTRL_SDRAM_SEPBUS;
102 constant CFG_MCTRL_INVCLK : integer := CONFIG_MCTRL_SDRAM_INVCLK;
102 constant CFG_MCTRL_INVCLK : integer := CONFIG_MCTRL_SDRAM_INVCLK;
103 constant CFG_MCTRL_SD64 : integer := CONFIG_MCTRL_SDRAM_BUS64;
103 constant CFG_MCTRL_SD64 : integer := CONFIG_MCTRL_SDRAM_BUS64;
104 constant CFG_MCTRL_PAGE : integer := CONFIG_MCTRL_PAGE + CONFIG_MCTRL_PROGPAGE;
104 constant CFG_MCTRL_PAGE : integer := CONFIG_MCTRL_PAGE + CONFIG_MCTRL_PROGPAGE;
105
105
106 -- Xilinx MIG
106 -- Xilinx MIG
107 constant CFG_MIG_DDR2 : integer := CONFIG_MIG_DDR2;
107 constant CFG_MIG_DDR2 : integer := CONFIG_MIG_DDR2;
108 constant CFG_MIG_RANKS : integer := CONFIG_MIG_RANKS;
108 constant CFG_MIG_RANKS : integer := CONFIG_MIG_RANKS;
109 constant CFG_MIG_COLBITS : integer := CONFIG_MIG_COLBITS;
109 constant CFG_MIG_COLBITS : integer := CONFIG_MIG_COLBITS;
110 constant CFG_MIG_ROWBITS : integer := CONFIG_MIG_ROWBITS;
110 constant CFG_MIG_ROWBITS : integer := CONFIG_MIG_ROWBITS;
111 constant CFG_MIG_BANKBITS: integer := CONFIG_MIG_BANKBITS;
111 constant CFG_MIG_BANKBITS: integer := CONFIG_MIG_BANKBITS;
112 constant CFG_MIG_HMASK : integer := 16#CONFIG_MIG_HMASK#;
112 constant CFG_MIG_HMASK : integer := 16#CONFIG_MIG_HMASK#;
113
113
114
114
115 -- AHB status register
115 -- AHB status register
116 constant CFG_AHBSTAT : integer := CONFIG_AHBSTAT_ENABLE;
116 constant CFG_AHBSTAT : integer := CONFIG_AHBSTAT_ENABLE;
117 constant CFG_AHBSTATN : integer := CONFIG_AHBSTAT_NFTSLV;
117 constant CFG_AHBSTATN : integer := CONFIG_AHBSTAT_NFTSLV;
118
118
119 -- AHB ROM
119 -- AHB ROM
120 constant CFG_AHBROMEN : integer := CONFIG_AHBROM_ENABLE;
120 constant CFG_AHBROMEN : integer := CONFIG_AHBROM_ENABLE;
121 constant CFG_AHBROPIP : integer := CONFIG_AHBROM_PIPE;
121 constant CFG_AHBROPIP : integer := CONFIG_AHBROM_PIPE;
122 constant CFG_AHBRODDR : integer := 16#CONFIG_AHBROM_START#;
122 constant CFG_AHBRODDR : integer := 16#CONFIG_AHBROM_START#;
123 constant CFG_ROMADDR : integer := 16#CONFIG_ROM_START#;
123 constant CFG_ROMADDR : integer := 16#CONFIG_ROM_START#;
124 constant CFG_ROMMASK : integer := 16#E00# + 16#CONFIG_ROM_START#;
124 constant CFG_ROMMASK : integer := 16#E00# + 16#CONFIG_ROM_START#;
125
125
126 -- AHB RAM
126 -- AHB RAM
127 constant CFG_AHBRAMEN : integer := CONFIG_AHBRAM_ENABLE;
127 constant CFG_AHBRAMEN : integer := CONFIG_AHBRAM_ENABLE;
128 constant CFG_AHBRSZ : integer := CFG_AHBRAMSZ;
128 constant CFG_AHBRSZ : integer := CFG_AHBRAMSZ;
129 constant CFG_AHBRADDR : integer := 16#CONFIG_AHBRAM_START#;
129 constant CFG_AHBRADDR : integer := 16#CONFIG_AHBRAM_START#;
130
130
131 -- Gaisler Ethernet core
131 -- Gaisler Ethernet core
132 constant CFG_GRETH : integer := CONFIG_GRETH_ENABLE;
132 constant CFG_GRETH : integer := CONFIG_GRETH_ENABLE;
133 constant CFG_GRETH1G : integer := CONFIG_GRETH_GIGA;
133 constant CFG_GRETH1G : integer := CONFIG_GRETH_GIGA;
134 constant CFG_ETH_FIFO : integer := CFG_GRETH_FIFO;
134 constant CFG_ETH_FIFO : integer := CFG_GRETH_FIFO;
135
135
136 -- UART 1
136 -- UART 1
137 constant CFG_UART1_ENABLE : integer := CONFIG_UART1_ENABLE;
137 constant CFG_UART1_ENABLE : integer := CONFIG_UART1_ENABLE;
138 constant CFG_UART1_FIFO : integer := CFG_UA1_FIFO;
138 constant CFG_UART1_FIFO : integer := CFG_UA1_FIFO;
139
139
140 -- LEON3 interrupt controller
140 -- LEON3 interrupt controller
141 constant CFG_IRQ3_ENABLE : integer := CONFIG_IRQ3_ENABLE;
141 constant CFG_IRQ3_ENABLE : integer := CONFIG_IRQ3_ENABLE;
142 constant CFG_IRQ3_NSEC : integer := CONFIG_IRQ3_NSEC;
142 constant CFG_IRQ3_NSEC : integer := CONFIG_IRQ3_NSEC;
143
143
144 -- Modular timer
144 -- Modular timer
145 constant CFG_GPT_ENABLE : integer := CONFIG_GPT_ENABLE;
145 constant CFG_GPT_ENABLE : integer := CONFIG_GPT_ENABLE;
146 constant CFG_GPT_NTIM : integer := CONFIG_GPT_NTIM;
146 constant CFG_GPT_NTIM : integer := CONFIG_GPT_NTIM;
147 constant CFG_GPT_SW : integer := CONFIG_GPT_SW;
147 constant CFG_GPT_SW : integer := CONFIG_GPT_SW;
148 constant CFG_GPT_TW : integer := CONFIG_GPT_TW;
148 constant CFG_GPT_TW : integer := CONFIG_GPT_TW;
149 constant CFG_GPT_IRQ : integer := CONFIG_GPT_IRQ;
149 constant CFG_GPT_IRQ : integer := CONFIG_GPT_IRQ;
150 constant CFG_GPT_SEPIRQ : integer := CONFIG_GPT_SEPIRQ;
150 constant CFG_GPT_SEPIRQ : integer := CONFIG_GPT_SEPIRQ;
151 constant CFG_GPT_WDOGEN : integer := CONFIG_GPT_WDOGEN;
151 constant CFG_GPT_WDOGEN : integer := CONFIG_GPT_WDOGEN;
152 constant CFG_GPT_WDOG : integer := 16#CONFIG_GPT_WDOG#;
152 constant CFG_GPT_WDOG : integer := 16#CONFIG_GPT_WDOG#;
153
153
154 -- GPIO port
154 -- GPIO port
155 constant CFG_GRGPIO_ENABLE : integer := CONFIG_GRGPIO_ENABLE;
155 constant CFG_GRGPIO_ENABLE : integer := CONFIG_GRGPIO_ENABLE;
156 constant CFG_GRGPIO_IMASK : integer := 16#CONFIG_GRGPIO_IMASK#;
156 constant CFG_GRGPIO_IMASK : integer := 16#CONFIG_GRGPIO_IMASK#;
157 constant CFG_GRGPIO_WIDTH : integer := CONFIG_GRGPIO_WIDTH;
157 constant CFG_GRGPIO_WIDTH : integer := CONFIG_GRGPIO_WIDTH;
158
158
159 -- VGA and PS2/ interface
159 -- VGA and PS2/ interface
160 constant CFG_KBD_ENABLE : integer := CONFIG_KBD_ENABLE;
160 constant CFG_KBD_ENABLE : integer := CONFIG_KBD_ENABLE;
161 constant CFG_VGA_ENABLE : integer := CONFIG_VGA_ENABLE;
161 constant CFG_VGA_ENABLE : integer := CONFIG_VGA_ENABLE;
162 constant CFG_SVGA_ENABLE : integer := CONFIG_SVGA_ENABLE;
162 constant CFG_SVGA_ENABLE : integer := CONFIG_SVGA_ENABLE;
163
163
164 -- SPI memory controller
164 -- SPI memory controller
165 constant CFG_SPIMCTRL : integer := CONFIG_SPIMCTRL;
165 constant CFG_SPIMCTRL : integer := CONFIG_SPIMCTRL;
166 constant CFG_SPIMCTRL_SDCARD : integer := CONFIG_SPIMCTRL_SDCARD;
166 constant CFG_SPIMCTRL_SDCARD : integer := CONFIG_SPIMCTRL_SDCARD;
167 constant CFG_SPIMCTRL_READCMD : integer := 16#CONFIG_SPIMCTRL_READCMD#;
167 constant CFG_SPIMCTRL_READCMD : integer := 16#CONFIG_SPIMCTRL_READCMD#;
168 constant CFG_SPIMCTRL_DUMMYBYTE : integer := CONFIG_SPIMCTRL_DUMMYBYTE;
168 constant CFG_SPIMCTRL_DUMMYBYTE : integer := CONFIG_SPIMCTRL_DUMMYBYTE;
169 constant CFG_SPIMCTRL_DUALOUTPUT : integer := CONFIG_SPIMCTRL_DUALOUTPUT;
169 constant CFG_SPIMCTRL_DUALOUTPUT : integer := CONFIG_SPIMCTRL_DUALOUTPUT;
170 constant CFG_SPIMCTRL_SCALER : integer := CONFIG_SPIMCTRL_SCALER;
170 constant CFG_SPIMCTRL_SCALER : integer := CONFIG_SPIMCTRL_SCALER;
171 constant CFG_SPIMCTRL_ASCALER : integer := CONFIG_SPIMCTRL_ASCALER;
171 constant CFG_SPIMCTRL_ASCALER : integer := CONFIG_SPIMCTRL_ASCALER;
172 constant CFG_SPIMCTRL_PWRUPCNT : integer := CONFIG_SPIMCTRL_PWRUPCNT;
172 constant CFG_SPIMCTRL_PWRUPCNT : integer := CONFIG_SPIMCTRL_PWRUPCNT;
173
173
174 -- SPI controller
174 -- SPI controller
175 constant CFG_SPICTRL_ENABLE : integer := CONFIG_SPICTRL_ENABLE;
175 constant CFG_SPICTRL_ENABLE : integer := CONFIG_SPICTRL_ENABLE;
176 constant CFG_SPICTRL_NUM : integer := CONFIG_SPICTRL_NUM;
176 constant CFG_SPICTRL_NUM : integer := CONFIG_SPICTRL_NUM;
177 constant CFG_SPICTRL_SLVS : integer := CONFIG_SPICTRL_SLVS;
177 constant CFG_SPICTRL_SLVS : integer := CONFIG_SPICTRL_SLVS;
178 constant CFG_SPICTRL_FIFO : integer := CONFIG_SPICTRL_FIFO;
178 constant CFG_SPICTRL_FIFO : integer := CONFIG_SPICTRL_FIFO;
179 constant CFG_SPICTRL_SLVREG : integer := CONFIG_SPICTRL_SLVREG;
179 constant CFG_SPICTRL_SLVREG : integer := CONFIG_SPICTRL_SLVREG;
180 constant CFG_SPICTRL_ODMODE : integer := CONFIG_SPICTRL_ODMODE;
180 constant CFG_SPICTRL_ODMODE : integer := CONFIG_SPICTRL_ODMODE;
181 constant CFG_SPICTRL_AM : integer := CONFIG_SPICTRL_AM;
181 constant CFG_SPICTRL_AM : integer := CONFIG_SPICTRL_AM;
182 constant CFG_SPICTRL_ASEL : integer := CONFIG_SPICTRL_ASEL;
182 constant CFG_SPICTRL_ASEL : integer := CONFIG_SPICTRL_ASEL;
183 constant CFG_SPICTRL_TWEN : integer := CONFIG_SPICTRL_TWEN;
183 constant CFG_SPICTRL_TWEN : integer := CONFIG_SPICTRL_TWEN;
184 constant CFG_SPICTRL_MAXWLEN : integer := CONFIG_SPICTRL_MAXWLEN;
184 constant CFG_SPICTRL_MAXWLEN : integer := CONFIG_SPICTRL_MAXWLEN;
185 constant CFG_SPICTRL_SYNCRAM : integer := CONFIG_SPICTRL_SYNCRAM;
185 constant CFG_SPICTRL_SYNCRAM : integer := CONFIG_SPICTRL_SYNCRAM;
186 constant CFG_SPICTRL_FT : integer := CONFIG_SPICTRL_FT;
186 constant CFG_SPICTRL_FT : integer := CONFIG_SPICTRL_FT;
187
187
188 -- GRLIB debugging
188 -- GRLIB debugging
189 constant CFG_DUART : integer := CONFIG_DEBUG_UART;
189 constant CFG_DUART : integer := CONFIG_DEBUG_UART;
190
190
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@@ -1,13 +1,13
1
1
2 SPARTAN6 50 MHz, MIG DDR2, 2x8 + 2x4 cache, GRFPU
2 SPARTAN6 50 MHz, MIG DDR2, 2x8 + 2x4 cache, GRFPU
3
3
4 LEON3 LEON3FTV2
4 LEON3 LEON3FTV2
5 Dhrystone 78.4 78.4
5 Dhrystone 78.4 78.4
6 Whetstone DP 27.7 27.7
6 Whetstone DP 27.7 27.7
7 gzip 43.98 s 41.38 s
7 gzip 43.98 s 41.38 s
8 bzip2 248.22 s 200.10 s
8 bzip2 248.22 s 200.10 s
9 176.gcc 208.62 s 180.48 s
9 176.gcc 208.62 s 180.48 s
10 coremark 100.12 i/s 100.12 i/s
10 coremark 100.12 i/s 100.12 i/s
11 aocs_v8 12388.7 i/s 12388.7 i/s
11 aocs_v8 12388.7 i/s 12388.7 i/s
12 basicmath_large 13245.0 i/s 13245.0 i/s
12 basicmath_large 13245.0 i/s 13245.0 i/s
13 linpack_unroll_dp_v8 3265 KFLOPS 3563 KFLOPS
13 linpack_unroll_dp_v8 3265 KFLOPS 3563 KFLOPS
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@@ -1,18 +1,18
1
1
2 main()
2 main()
3
3
4 {
4 {
5 report_start();
5 report_start();
6
6
7
7
8 // svgactrl_test(0x80000600, 1, 0, 0x40200000, -1, 0, 0);
8 // svgactrl_test(0x80000600, 1, 0, 0x40200000, -1, 0, 0);
9 base_test();
9 base_test();
10 /*
10 /*
11 greth_test(0x80000e00);
11 greth_test(0x80000e00);
12 spw_test(0x80100A00);
12 spw_test(0x80100A00);
13 spw_test(0x80100B00);
13 spw_test(0x80100B00);
14 spw_test(0x80100C00);
14 spw_test(0x80100C00);
15 svgactrl_test(0x80000600, 1, 0, 0x40200000, -1, 0, 0);
15 svgactrl_test(0x80000600, 1, 0, 0x40200000, -1, 0, 0);
16 */
16 */
17 report_end();
17 report_end();
18 }
18 }
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@@ -1,1051 +1,1051
1 #if defined CONFIG_SYN_INFERRED
1 #if defined CONFIG_SYN_INFERRED
2 #define CONFIG_SYN_TECH inferred
2 #define CONFIG_SYN_TECH inferred
3 #elif defined CONFIG_SYN_UMC
3 #elif defined CONFIG_SYN_UMC
4 #define CONFIG_SYN_TECH umc
4 #define CONFIG_SYN_TECH umc
5 #elif defined CONFIG_SYN_RHUMC
5 #elif defined CONFIG_SYN_RHUMC
6 #define CONFIG_SYN_TECH rhumc
6 #define CONFIG_SYN_TECH rhumc
7 #elif defined CONFIG_SYN_ATC18
7 #elif defined CONFIG_SYN_ATC18
8 #define CONFIG_SYN_TECH atc18s
8 #define CONFIG_SYN_TECH atc18s
9 #elif defined CONFIG_SYN_ATC18RHA
9 #elif defined CONFIG_SYN_ATC18RHA
10 #define CONFIG_SYN_TECH atc18rha
10 #define CONFIG_SYN_TECH atc18rha
11 #elif defined CONFIG_SYN_AXCEL
11 #elif defined CONFIG_SYN_AXCEL
12 #define CONFIG_SYN_TECH axcel
12 #define CONFIG_SYN_TECH axcel
13 #elif defined CONFIG_SYN_AXDSP
13 #elif defined CONFIG_SYN_AXDSP
14 #define CONFIG_SYN_TECH axdsp
14 #define CONFIG_SYN_TECH axdsp
15 #elif defined CONFIG_SYN_PROASICPLUS
15 #elif defined CONFIG_SYN_PROASICPLUS
16 #define CONFIG_SYN_TECH proasic
16 #define CONFIG_SYN_TECH proasic
17 #elif defined CONFIG_SYN_ALTERA
17 #elif defined CONFIG_SYN_ALTERA
18 #define CONFIG_SYN_TECH altera
18 #define CONFIG_SYN_TECH altera
19 #elif defined CONFIG_SYN_STRATIX
19 #elif defined CONFIG_SYN_STRATIX
20 #define CONFIG_SYN_TECH stratix1
20 #define CONFIG_SYN_TECH stratix1
21 #elif defined CONFIG_SYN_STRATIXII
21 #elif defined CONFIG_SYN_STRATIXII
22 #define CONFIG_SYN_TECH stratix2
22 #define CONFIG_SYN_TECH stratix2
23 #elif defined CONFIG_SYN_STRATIXIII
23 #elif defined CONFIG_SYN_STRATIXIII
24 #define CONFIG_SYN_TECH stratix3
24 #define CONFIG_SYN_TECH stratix3
25 #elif defined CONFIG_SYN_CYCLONEIII
25 #elif defined CONFIG_SYN_CYCLONEIII
26 #define CONFIG_SYN_TECH cyclone3
26 #define CONFIG_SYN_TECH cyclone3
27 #elif defined CONFIG_SYN_EASIC45
27 #elif defined CONFIG_SYN_EASIC45
28 #define CONFIG_SYN_TECH easic45
28 #define CONFIG_SYN_TECH easic45
29 #elif defined CONFIG_SYN_EASIC90
29 #elif defined CONFIG_SYN_EASIC90
30 #define CONFIG_SYN_TECH easic90
30 #define CONFIG_SYN_TECH easic90
31 #elif defined CONFIG_SYN_IHP25
31 #elif defined CONFIG_SYN_IHP25
32 #define CONFIG_SYN_TECH ihp25
32 #define CONFIG_SYN_TECH ihp25
33 #elif defined CONFIG_SYN_IHP25RH
33 #elif defined CONFIG_SYN_IHP25RH
34 #define CONFIG_SYN_TECH ihp25rh
34 #define CONFIG_SYN_TECH ihp25rh
35 #elif defined CONFIG_SYN_CMOS9SF
35 #elif defined CONFIG_SYN_CMOS9SF
36 #define CONFIG_SYN_TECH cmos9sf
36 #define CONFIG_SYN_TECH cmos9sf
37 #elif defined CONFIG_SYN_LATTICE
37 #elif defined CONFIG_SYN_LATTICE
38 #define CONFIG_SYN_TECH lattice
38 #define CONFIG_SYN_TECH lattice
39 #elif defined CONFIG_SYN_ECLIPSE
39 #elif defined CONFIG_SYN_ECLIPSE
40 #define CONFIG_SYN_TECH eclipse
40 #define CONFIG_SYN_TECH eclipse
41 #elif defined CONFIG_SYN_PEREGRINE
41 #elif defined CONFIG_SYN_PEREGRINE
42 #define CONFIG_SYN_TECH peregrine
42 #define CONFIG_SYN_TECH peregrine
43 #elif defined CONFIG_SYN_PROASIC
43 #elif defined CONFIG_SYN_PROASIC
44 #define CONFIG_SYN_TECH proasic
44 #define CONFIG_SYN_TECH proasic
45 #elif defined CONFIG_SYN_PROASIC3
45 #elif defined CONFIG_SYN_PROASIC3
46 #define CONFIG_SYN_TECH apa3
46 #define CONFIG_SYN_TECH apa3
47 #elif defined CONFIG_SYN_PROASIC3E
47 #elif defined CONFIG_SYN_PROASIC3E
48 #define CONFIG_SYN_TECH apa3e
48 #define CONFIG_SYN_TECH apa3e
49 #elif defined CONFIG_SYN_PROASIC3L
49 #elif defined CONFIG_SYN_PROASIC3L
50 #define CONFIG_SYN_TECH apa3l
50 #define CONFIG_SYN_TECH apa3l
51 #elif defined CONFIG_SYN_IGLOO
51 #elif defined CONFIG_SYN_IGLOO
52 #define CONFIG_SYN_TECH apa3
52 #define CONFIG_SYN_TECH apa3
53 #elif defined CONFIG_SYN_FUSION
53 #elif defined CONFIG_SYN_FUSION
54 #define CONFIG_SYN_TECH actfus
54 #define CONFIG_SYN_TECH actfus
55 #elif defined CONFIG_SYN_SPARTAN2
55 #elif defined CONFIG_SYN_SPARTAN2
56 #define CONFIG_SYN_TECH virtex
56 #define CONFIG_SYN_TECH virtex
57 #elif defined CONFIG_SYN_VIRTEX
57 #elif defined CONFIG_SYN_VIRTEX
58 #define CONFIG_SYN_TECH virtex
58 #define CONFIG_SYN_TECH virtex
59 #elif defined CONFIG_SYN_VIRTEXE
59 #elif defined CONFIG_SYN_VIRTEXE
60 #define CONFIG_SYN_TECH virtex
60 #define CONFIG_SYN_TECH virtex
61 #elif defined CONFIG_SYN_SPARTAN3
61 #elif defined CONFIG_SYN_SPARTAN3
62 #define CONFIG_SYN_TECH spartan3
62 #define CONFIG_SYN_TECH spartan3
63 #elif defined CONFIG_SYN_SPARTAN3E
63 #elif defined CONFIG_SYN_SPARTAN3E
64 #define CONFIG_SYN_TECH spartan3e
64 #define CONFIG_SYN_TECH spartan3e
65 #elif defined CONFIG_SYN_SPARTAN6
65 #elif defined CONFIG_SYN_SPARTAN6
66 #define CONFIG_SYN_TECH spartan6
66 #define CONFIG_SYN_TECH spartan6
67 #elif defined CONFIG_SYN_VIRTEX2
67 #elif defined CONFIG_SYN_VIRTEX2
68 #define CONFIG_SYN_TECH virtex2
68 #define CONFIG_SYN_TECH virtex2
69 #elif defined CONFIG_SYN_VIRTEX4
69 #elif defined CONFIG_SYN_VIRTEX4
70 #define CONFIG_SYN_TECH virtex4
70 #define CONFIG_SYN_TECH virtex4
71 #elif defined CONFIG_SYN_VIRTEX5
71 #elif defined CONFIG_SYN_VIRTEX5
72 #define CONFIG_SYN_TECH virtex5
72 #define CONFIG_SYN_TECH virtex5
73 #elif defined CONFIG_SYN_VIRTEX6
73 #elif defined CONFIG_SYN_VIRTEX6
74 #define CONFIG_SYN_TECH virtex6
74 #define CONFIG_SYN_TECH virtex6
75 #elif defined CONFIG_SYN_RH_LIB18T
75 #elif defined CONFIG_SYN_RH_LIB18T
76 #define CONFIG_SYN_TECH rhlib18t
76 #define CONFIG_SYN_TECH rhlib18t
77 #elif defined CONFIG_SYN_SMIC13
77 #elif defined CONFIG_SYN_SMIC13
78 #define CONFIG_SYN_TECH smic013
78 #define CONFIG_SYN_TECH smic013
79 #elif defined CONFIG_SYN_UT025CRH
79 #elif defined CONFIG_SYN_UT025CRH
80 #define CONFIG_SYN_TECH ut25
80 #define CONFIG_SYN_TECH ut25
81 #elif defined CONFIG_SYN_UT130HBD
81 #elif defined CONFIG_SYN_UT130HBD
82 #define CONFIG_SYN_TECH ut130
82 #define CONFIG_SYN_TECH ut130
83 #elif defined CONFIG_SYN_UT90NHBD
83 #elif defined CONFIG_SYN_UT90NHBD
84 #define CONFIG_SYN_TECH ut90
84 #define CONFIG_SYN_TECH ut90
85 #elif defined CONFIG_SYN_TSMC90
85 #elif defined CONFIG_SYN_TSMC90
86 #define CONFIG_SYN_TECH tsmc90
86 #define CONFIG_SYN_TECH tsmc90
87 #elif defined CONFIG_SYN_TM65GPLUS
87 #elif defined CONFIG_SYN_TM65GPLUS
88 #define CONFIG_SYN_TECH tm65gpl
88 #define CONFIG_SYN_TECH tm65gpl
89 #elif defined CONFIG_SYN_CUSTOM1
89 #elif defined CONFIG_SYN_CUSTOM1
90 #define CONFIG_SYN_TECH custom1
90 #define CONFIG_SYN_TECH custom1
91 #else
91 #else
92 #error "unknown target technology"
92 #error "unknown target technology"
93 #endif
93 #endif
94
94
95 #if defined CONFIG_SYN_INFER_RAM
95 #if defined CONFIG_SYN_INFER_RAM
96 #define CFG_RAM_TECH inferred
96 #define CFG_RAM_TECH inferred
97 #elif defined CONFIG_MEM_UMC
97 #elif defined CONFIG_MEM_UMC
98 #define CFG_RAM_TECH umc
98 #define CFG_RAM_TECH umc
99 #elif defined CONFIG_MEM_RHUMC
99 #elif defined CONFIG_MEM_RHUMC
100 #define CFG_RAM_TECH rhumc
100 #define CFG_RAM_TECH rhumc
101 #elif defined CONFIG_MEM_VIRAGE
101 #elif defined CONFIG_MEM_VIRAGE
102 #define CFG_RAM_TECH memvirage
102 #define CFG_RAM_TECH memvirage
103 #elif defined CONFIG_MEM_ARTISAN
103 #elif defined CONFIG_MEM_ARTISAN
104 #define CFG_RAM_TECH memartisan
104 #define CFG_RAM_TECH memartisan
105 #elif defined CONFIG_MEM_CUSTOM1
105 #elif defined CONFIG_MEM_CUSTOM1
106 #define CFG_RAM_TECH custom1
106 #define CFG_RAM_TECH custom1
107 #elif defined CONFIG_MEM_VIRAGE90
107 #elif defined CONFIG_MEM_VIRAGE90
108 #define CFG_RAM_TECH memvirage90
108 #define CFG_RAM_TECH memvirage90
109 #elif defined CONFIG_MEM_INFERRED
109 #elif defined CONFIG_MEM_INFERRED
110 #define CFG_RAM_TECH inferred
110 #define CFG_RAM_TECH inferred
111 #else
111 #else
112 #define CFG_RAM_TECH CONFIG_SYN_TECH
112 #define CFG_RAM_TECH CONFIG_SYN_TECH
113 #endif
113 #endif
114
114
115 #if defined CONFIG_SYN_INFER_PADS
115 #if defined CONFIG_SYN_INFER_PADS
116 #define CFG_PAD_TECH inferred
116 #define CFG_PAD_TECH inferred
117 #else
117 #else
118 #define CFG_PAD_TECH CONFIG_SYN_TECH
118 #define CFG_PAD_TECH CONFIG_SYN_TECH
119 #endif
119 #endif
120
120
121 #ifndef CONFIG_SYN_NO_ASYNC
121 #ifndef CONFIG_SYN_NO_ASYNC
122 #define CONFIG_SYN_NO_ASYNC 0
122 #define CONFIG_SYN_NO_ASYNC 0
123 #endif
123 #endif
124
124
125 #ifndef CONFIG_SYN_SCAN
125 #ifndef CONFIG_SYN_SCAN
126 #define CONFIG_SYN_SCAN 0
126 #define CONFIG_SYN_SCAN 0
127 #endif
127 #endif
128
128
129
129
130 #if defined CONFIG_CLK_ALTDLL
130 #if defined CONFIG_CLK_ALTDLL
131 #define CFG_CLK_TECH CONFIG_SYN_TECH
131 #define CFG_CLK_TECH CONFIG_SYN_TECH
132 #elif defined CONFIG_CLK_HCLKBUF
132 #elif defined CONFIG_CLK_HCLKBUF
133 #define CFG_CLK_TECH axcel
133 #define CFG_CLK_TECH axcel
134 #elif defined CONFIG_CLK_LATDLL
134 #elif defined CONFIG_CLK_LATDLL
135 #define CFG_CLK_TECH lattice
135 #define CFG_CLK_TECH lattice
136 #elif defined CONFIG_CLK_PRO3PLL
136 #elif defined CONFIG_CLK_PRO3PLL
137 #define CFG_CLK_TECH apa3
137 #define CFG_CLK_TECH apa3
138 #elif defined CONFIG_CLK_PRO3EPLL
138 #elif defined CONFIG_CLK_PRO3EPLL
139 #define CFG_CLK_TECH apa3e
139 #define CFG_CLK_TECH apa3e
140 #elif defined CONFIG_CLK_PRO3LPLL
140 #elif defined CONFIG_CLK_PRO3LPLL
141 #define CFG_CLK_TECH apa3l
141 #define CFG_CLK_TECH apa3l
142 #elif defined CONFIG_CLK_FUSPLL
142 #elif defined CONFIG_CLK_FUSPLL
143 #define CFG_CLK_TECH actfus
143 #define CFG_CLK_TECH actfus
144 #elif defined CONFIG_CLK_CLKDLL
144 #elif defined CONFIG_CLK_CLKDLL
145 #define CFG_CLK_TECH virtex
145 #define CFG_CLK_TECH virtex
146 #elif defined CONFIG_CLK_DCM
146 #elif defined CONFIG_CLK_DCM
147 #define CFG_CLK_TECH CONFIG_SYN_TECH
147 #define CFG_CLK_TECH CONFIG_SYN_TECH
148 #elif defined CONFIG_CLK_LIB18T
148 #elif defined CONFIG_CLK_LIB18T
149 #define CFG_CLK_TECH rhlib18t
149 #define CFG_CLK_TECH rhlib18t
150 #elif defined CONFIG_CLK_RHUMC
150 #elif defined CONFIG_CLK_RHUMC
151 #define CFG_CLK_TECH rhumc
151 #define CFG_CLK_TECH rhumc
152 #elif defined CONFIG_CLK_UT130HBD
152 #elif defined CONFIG_CLK_UT130HBD
153 #define CFG_CLK_TECH ut130
153 #define CFG_CLK_TECH ut130
154 #else
154 #else
155 #define CFG_CLK_TECH inferred
155 #define CFG_CLK_TECH inferred
156 #endif
156 #endif
157
157
158 #ifndef CONFIG_CLK_MUL
158 #ifndef CONFIG_CLK_MUL
159 #define CONFIG_CLK_MUL 2
159 #define CONFIG_CLK_MUL 2
160 #endif
160 #endif
161
161
162 #ifndef CONFIG_CLK_DIV
162 #ifndef CONFIG_CLK_DIV
163 #define CONFIG_CLK_DIV 2
163 #define CONFIG_CLK_DIV 2
164 #endif
164 #endif
165
165
166 #ifndef CONFIG_OCLK_DIV
166 #ifndef CONFIG_OCLK_DIV
167 #define CONFIG_OCLK_DIV 1
167 #define CONFIG_OCLK_DIV 1
168 #endif
168 #endif
169
169
170 #ifndef CONFIG_OCLKB_DIV
170 #ifndef CONFIG_OCLKB_DIV
171 #define CONFIG_OCLKB_DIV 0
171 #define CONFIG_OCLKB_DIV 0
172 #endif
172 #endif
173
173
174 #ifndef CONFIG_OCLKC_DIV
174 #ifndef CONFIG_OCLKC_DIV
175 #define CONFIG_OCLKC_DIV 0
175 #define CONFIG_OCLKC_DIV 0
176 #endif
176 #endif
177
177
178 #ifndef CONFIG_PCI_CLKDLL
178 #ifndef CONFIG_PCI_CLKDLL
179 #define CONFIG_PCI_CLKDLL 0
179 #define CONFIG_PCI_CLKDLL 0
180 #endif
180 #endif
181
181
182 #ifndef CONFIG_PCI_SYSCLK
182 #ifndef CONFIG_PCI_SYSCLK
183 #define CONFIG_PCI_SYSCLK 0
183 #define CONFIG_PCI_SYSCLK 0
184 #endif
184 #endif
185
185
186 #ifndef CONFIG_CLK_NOFB
186 #ifndef CONFIG_CLK_NOFB
187 #define CONFIG_CLK_NOFB 0
187 #define CONFIG_CLK_NOFB 0
188 #endif
188 #endif
189 #ifndef CONFIG_LEON3
189 #ifndef CONFIG_LEON3
190 #define CONFIG_LEON3 0
190 #define CONFIG_LEON3 0
191 #endif
191 #endif
192
192
193 #ifndef CONFIG_PROC_NUM
193 #ifndef CONFIG_PROC_NUM
194 #define CONFIG_PROC_NUM 1
194 #define CONFIG_PROC_NUM 1
195 #endif
195 #endif
196
196
197 #ifndef CONFIG_IU_NWINDOWS
197 #ifndef CONFIG_IU_NWINDOWS
198 #define CONFIG_IU_NWINDOWS 8
198 #define CONFIG_IU_NWINDOWS 8
199 #endif
199 #endif
200
200
201 #ifndef CONFIG_IU_RSTADDR
201 #ifndef CONFIG_IU_RSTADDR
202 #define CONFIG_IU_RSTADDR 8
202 #define CONFIG_IU_RSTADDR 8
203 #endif
203 #endif
204
204
205 #ifndef CONFIG_IU_LDELAY
205 #ifndef CONFIG_IU_LDELAY
206 #define CONFIG_IU_LDELAY 1
206 #define CONFIG_IU_LDELAY 1
207 #endif
207 #endif
208
208
209 #ifndef CONFIG_IU_WATCHPOINTS
209 #ifndef CONFIG_IU_WATCHPOINTS
210 #define CONFIG_IU_WATCHPOINTS 0
210 #define CONFIG_IU_WATCHPOINTS 0
211 #endif
211 #endif
212
212
213 #ifdef CONFIG_IU_V8MULDIV
213 #ifdef CONFIG_IU_V8MULDIV
214 #ifdef CONFIG_IU_MUL_LATENCY_4
214 #ifdef CONFIG_IU_MUL_LATENCY_4
215 #define CFG_IU_V8 1
215 #define CFG_IU_V8 1
216 #elif defined CONFIG_IU_MUL_LATENCY_5
216 #elif defined CONFIG_IU_MUL_LATENCY_5
217 #define CFG_IU_V8 2
217 #define CFG_IU_V8 2
218 #elif defined CONFIG_IU_MUL_LATENCY_2
218 #elif defined CONFIG_IU_MUL_LATENCY_2
219 #define CFG_IU_V8 16#32#
219 #define CFG_IU_V8 16#32#
220 #endif
220 #endif
221 #else
221 #else
222 #define CFG_IU_V8 0
222 #define CFG_IU_V8 0
223 #endif
223 #endif
224
224
225 #ifdef CONFIG_IU_MUL_MODGEN
225 #ifdef CONFIG_IU_MUL_MODGEN
226 #define CFG_IU_MUL_STRUCT 1
226 #define CFG_IU_MUL_STRUCT 1
227 #elif defined CONFIG_IU_MUL_TECHSPEC
227 #elif defined CONFIG_IU_MUL_TECHSPEC
228 #define CFG_IU_MUL_STRUCT 2
228 #define CFG_IU_MUL_STRUCT 2
229 #elif defined CONFIG_IU_MUL_DW
229 #elif defined CONFIG_IU_MUL_DW
230 #define CFG_IU_MUL_STRUCT 3
230 #define CFG_IU_MUL_STRUCT 3
231 #else
231 #else
232 #define CFG_IU_MUL_STRUCT 0
232 #define CFG_IU_MUL_STRUCT 0
233 #endif
233 #endif
234
234
235 #ifndef CONFIG_PWD
235 #ifndef CONFIG_PWD
236 #define CONFIG_PWD 0
236 #define CONFIG_PWD 0
237 #endif
237 #endif
238
238
239 #ifndef CONFIG_IU_MUL_MAC
239 #ifndef CONFIG_IU_MUL_MAC
240 #define CONFIG_IU_MUL_MAC 0
240 #define CONFIG_IU_MUL_MAC 0
241 #endif
241 #endif
242
242
243 #ifndef CONFIG_IU_BP
243 #ifndef CONFIG_IU_BP
244 #define CONFIG_IU_BP 0
244 #define CONFIG_IU_BP 0
245 #endif
245 #endif
246
246
247 #ifndef CONFIG_NOTAG
247 #ifndef CONFIG_NOTAG
248 #define CONFIG_NOTAG 0
248 #define CONFIG_NOTAG 0
249 #endif
249 #endif
250
250
251 #ifndef CONFIG_IU_SVT
251 #ifndef CONFIG_IU_SVT
252 #define CONFIG_IU_SVT 0
252 #define CONFIG_IU_SVT 0
253 #endif
253 #endif
254
254
255 #if defined CONFIG_FPU_GRFPC1
255 #if defined CONFIG_FPU_GRFPC1
256 #define CONFIG_FPU_GRFPC 1
256 #define CONFIG_FPU_GRFPC 1
257 #elif defined CONFIG_FPU_GRFPC2
257 #elif defined CONFIG_FPU_GRFPC2
258 #define CONFIG_FPU_GRFPC 2
258 #define CONFIG_FPU_GRFPC 2
259 #else
259 #else
260 #define CONFIG_FPU_GRFPC 0
260 #define CONFIG_FPU_GRFPC 0
261 #endif
261 #endif
262
262
263 #if defined CONFIG_FPU_GRFPU_INFMUL
263 #if defined CONFIG_FPU_GRFPU_INFMUL
264 #define CONFIG_FPU_GRFPU_MUL 0
264 #define CONFIG_FPU_GRFPU_MUL 0
265 #elif defined CONFIG_FPU_GRFPU_DWMUL
265 #elif defined CONFIG_FPU_GRFPU_DWMUL
266 #define CONFIG_FPU_GRFPU_MUL 1
266 #define CONFIG_FPU_GRFPU_MUL 1
267 #elif defined CONFIG_FPU_GRFPU_MODGEN
267 #elif defined CONFIG_FPU_GRFPU_MODGEN
268 #define CONFIG_FPU_GRFPU_MUL 2
268 #define CONFIG_FPU_GRFPU_MUL 2
269 #elif defined CONFIG_FPU_GRFPU_TECHSPEC
269 #elif defined CONFIG_FPU_GRFPU_TECHSPEC
270 #define CONFIG_FPU_GRFPU_MUL 3
270 #define CONFIG_FPU_GRFPU_MUL 3
271 #else
271 #else
272 #define CONFIG_FPU_GRFPU_MUL 0
272 #define CONFIG_FPU_GRFPU_MUL 0
273 #endif
273 #endif
274
274
275 #if defined CONFIG_FPU_GRFPU_SH
275 #if defined CONFIG_FPU_GRFPU_SH
276 #define CONFIG_FPU_GRFPU_SHARED 1
276 #define CONFIG_FPU_GRFPU_SHARED 1
277 #else
277 #else
278 #define CONFIG_FPU_GRFPU_SHARED 0
278 #define CONFIG_FPU_GRFPU_SHARED 0
279 #endif
279 #endif
280
280
281 #if defined CONFIG_FPU_GRFPU
281 #if defined CONFIG_FPU_GRFPU
282 #define CONFIG_FPU (1+CONFIG_FPU_GRFPU_MUL)
282 #define CONFIG_FPU (1+CONFIG_FPU_GRFPU_MUL)
283 #elif defined CONFIG_FPU_MEIKO
283 #elif defined CONFIG_FPU_MEIKO
284 #define CONFIG_FPU 15
284 #define CONFIG_FPU 15
285 #elif defined CONFIG_FPU_GRFPULITE
285 #elif defined CONFIG_FPU_GRFPULITE
286 #define CONFIG_FPU (8+CONFIG_FPU_GRFPC)
286 #define CONFIG_FPU (8+CONFIG_FPU_GRFPC)
287 #else
287 #else
288 #define CONFIG_FPU 0
288 #define CONFIG_FPU 0
289 #endif
289 #endif
290
290
291 #ifndef CONFIG_FPU_NETLIST
291 #ifndef CONFIG_FPU_NETLIST
292 #define CONFIG_FPU_NETLIST 0
292 #define CONFIG_FPU_NETLIST 0
293 #endif
293 #endif
294
294
295 #ifndef CONFIG_ICACHE_ENABLE
295 #ifndef CONFIG_ICACHE_ENABLE
296 #define CONFIG_ICACHE_ENABLE 0
296 #define CONFIG_ICACHE_ENABLE 0
297 #endif
297 #endif
298
298
299 #if defined CONFIG_ICACHE_ASSO1
299 #if defined CONFIG_ICACHE_ASSO1
300 #define CFG_IU_ISETS 1
300 #define CFG_IU_ISETS 1
301 #elif defined CONFIG_ICACHE_ASSO2
301 #elif defined CONFIG_ICACHE_ASSO2
302 #define CFG_IU_ISETS 2
302 #define CFG_IU_ISETS 2
303 #elif defined CONFIG_ICACHE_ASSO3
303 #elif defined CONFIG_ICACHE_ASSO3
304 #define CFG_IU_ISETS 3
304 #define CFG_IU_ISETS 3
305 #elif defined CONFIG_ICACHE_ASSO4
305 #elif defined CONFIG_ICACHE_ASSO4
306 #define CFG_IU_ISETS 4
306 #define CFG_IU_ISETS 4
307 #else
307 #else
308 #define CFG_IU_ISETS 1
308 #define CFG_IU_ISETS 1
309 #endif
309 #endif
310
310
311 #if defined CONFIG_ICACHE_SZ1
311 #if defined CONFIG_ICACHE_SZ1
312 #define CFG_ICACHE_SZ 1
312 #define CFG_ICACHE_SZ 1
313 #elif defined CONFIG_ICACHE_SZ2
313 #elif defined CONFIG_ICACHE_SZ2
314 #define CFG_ICACHE_SZ 2
314 #define CFG_ICACHE_SZ 2
315 #elif defined CONFIG_ICACHE_SZ4
315 #elif defined CONFIG_ICACHE_SZ4
316 #define CFG_ICACHE_SZ 4
316 #define CFG_ICACHE_SZ 4
317 #elif defined CONFIG_ICACHE_SZ8
317 #elif defined CONFIG_ICACHE_SZ8
318 #define CFG_ICACHE_SZ 8
318 #define CFG_ICACHE_SZ 8
319 #elif defined CONFIG_ICACHE_SZ16
319 #elif defined CONFIG_ICACHE_SZ16
320 #define CFG_ICACHE_SZ 16
320 #define CFG_ICACHE_SZ 16
321 #elif defined CONFIG_ICACHE_SZ32
321 #elif defined CONFIG_ICACHE_SZ32
322 #define CFG_ICACHE_SZ 32
322 #define CFG_ICACHE_SZ 32
323 #elif defined CONFIG_ICACHE_SZ64
323 #elif defined CONFIG_ICACHE_SZ64
324 #define CFG_ICACHE_SZ 64
324 #define CFG_ICACHE_SZ 64
325 #elif defined CONFIG_ICACHE_SZ128
325 #elif defined CONFIG_ICACHE_SZ128
326 #define CFG_ICACHE_SZ 128
326 #define CFG_ICACHE_SZ 128
327 #elif defined CONFIG_ICACHE_SZ256
327 #elif defined CONFIG_ICACHE_SZ256
328 #define CFG_ICACHE_SZ 256
328 #define CFG_ICACHE_SZ 256
329 #else
329 #else
330 #define CFG_ICACHE_SZ 1
330 #define CFG_ICACHE_SZ 1
331 #endif
331 #endif
332
332
333 #ifdef CONFIG_ICACHE_LZ16
333 #ifdef CONFIG_ICACHE_LZ16
334 #define CFG_ILINE_SZ 4
334 #define CFG_ILINE_SZ 4
335 #else
335 #else
336 #define CFG_ILINE_SZ 8
336 #define CFG_ILINE_SZ 8
337 #endif
337 #endif
338
338
339 #if defined CONFIG_ICACHE_ALGODIR
339 #if defined CONFIG_ICACHE_ALGODIR
340 #define CFG_ICACHE_ALGORND 3
340 #define CFG_ICACHE_ALGORND 3
341 #elif defined CONFIG_ICACHE_ALGORND
341 #elif defined CONFIG_ICACHE_ALGORND
342 #define CFG_ICACHE_ALGORND 2
342 #define CFG_ICACHE_ALGORND 2
343 #elif defined CONFIG_ICACHE_ALGOLRR
343 #elif defined CONFIG_ICACHE_ALGOLRR
344 #define CFG_ICACHE_ALGORND 1
344 #define CFG_ICACHE_ALGORND 1
345 #else
345 #else
346 #define CFG_ICACHE_ALGORND 0
346 #define CFG_ICACHE_ALGORND 0
347 #endif
347 #endif
348
348
349 #ifndef CONFIG_ICACHE_LOCK
349 #ifndef CONFIG_ICACHE_LOCK
350 #define CONFIG_ICACHE_LOCK 0
350 #define CONFIG_ICACHE_LOCK 0
351 #endif
351 #endif
352
352
353 #ifndef CONFIG_ICACHE_LRAM
353 #ifndef CONFIG_ICACHE_LRAM
354 #define CONFIG_ICACHE_LRAM 0
354 #define CONFIG_ICACHE_LRAM 0
355 #endif
355 #endif
356
356
357 #ifndef CONFIG_ICACHE_LRSTART
357 #ifndef CONFIG_ICACHE_LRSTART
358 #define CONFIG_ICACHE_LRSTART 8E
358 #define CONFIG_ICACHE_LRSTART 8E
359 #endif
359 #endif
360
360
361 #if defined CONFIG_ICACHE_LRAM_SZ2
361 #if defined CONFIG_ICACHE_LRAM_SZ2
362 #define CFG_ILRAM_SIZE 2
362 #define CFG_ILRAM_SIZE 2
363 #elif defined CONFIG_ICACHE_LRAM_SZ4
363 #elif defined CONFIG_ICACHE_LRAM_SZ4
364 #define CFG_ILRAM_SIZE 4
364 #define CFG_ILRAM_SIZE 4
365 #elif defined CONFIG_ICACHE_LRAM_SZ8
365 #elif defined CONFIG_ICACHE_LRAM_SZ8
366 #define CFG_ILRAM_SIZE 8
366 #define CFG_ILRAM_SIZE 8
367 #elif defined CONFIG_ICACHE_LRAM_SZ16
367 #elif defined CONFIG_ICACHE_LRAM_SZ16
368 #define CFG_ILRAM_SIZE 16
368 #define CFG_ILRAM_SIZE 16
369 #elif defined CONFIG_ICACHE_LRAM_SZ32
369 #elif defined CONFIG_ICACHE_LRAM_SZ32
370 #define CFG_ILRAM_SIZE 32
370 #define CFG_ILRAM_SIZE 32
371 #elif defined CONFIG_ICACHE_LRAM_SZ64
371 #elif defined CONFIG_ICACHE_LRAM_SZ64
372 #define CFG_ILRAM_SIZE 64
372 #define CFG_ILRAM_SIZE 64
373 #elif defined CONFIG_ICACHE_LRAM_SZ128
373 #elif defined CONFIG_ICACHE_LRAM_SZ128
374 #define CFG_ILRAM_SIZE 128
374 #define CFG_ILRAM_SIZE 128
375 #elif defined CONFIG_ICACHE_LRAM_SZ256
375 #elif defined CONFIG_ICACHE_LRAM_SZ256
376 #define CFG_ILRAM_SIZE 256
376 #define CFG_ILRAM_SIZE 256
377 #else
377 #else
378 #define CFG_ILRAM_SIZE 1
378 #define CFG_ILRAM_SIZE 1
379 #endif
379 #endif
380
380
381
381
382 #ifndef CONFIG_DCACHE_ENABLE
382 #ifndef CONFIG_DCACHE_ENABLE
383 #define CONFIG_DCACHE_ENABLE 0
383 #define CONFIG_DCACHE_ENABLE 0
384 #endif
384 #endif
385
385
386 #if defined CONFIG_DCACHE_ASSO1
386 #if defined CONFIG_DCACHE_ASSO1
387 #define CFG_IU_DSETS 1
387 #define CFG_IU_DSETS 1
388 #elif defined CONFIG_DCACHE_ASSO2
388 #elif defined CONFIG_DCACHE_ASSO2
389 #define CFG_IU_DSETS 2
389 #define CFG_IU_DSETS 2
390 #elif defined CONFIG_DCACHE_ASSO3
390 #elif defined CONFIG_DCACHE_ASSO3
391 #define CFG_IU_DSETS 3
391 #define CFG_IU_DSETS 3
392 #elif defined CONFIG_DCACHE_ASSO4
392 #elif defined CONFIG_DCACHE_ASSO4
393 #define CFG_IU_DSETS 4
393 #define CFG_IU_DSETS 4
394 #else
394 #else
395 #define CFG_IU_DSETS 1
395 #define CFG_IU_DSETS 1
396 #endif
396 #endif
397
397
398 #if defined CONFIG_DCACHE_SZ1
398 #if defined CONFIG_DCACHE_SZ1
399 #define CFG_DCACHE_SZ 1
399 #define CFG_DCACHE_SZ 1
400 #elif defined CONFIG_DCACHE_SZ2
400 #elif defined CONFIG_DCACHE_SZ2
401 #define CFG_DCACHE_SZ 2
401 #define CFG_DCACHE_SZ 2
402 #elif defined CONFIG_DCACHE_SZ4
402 #elif defined CONFIG_DCACHE_SZ4
403 #define CFG_DCACHE_SZ 4
403 #define CFG_DCACHE_SZ 4
404 #elif defined CONFIG_DCACHE_SZ8
404 #elif defined CONFIG_DCACHE_SZ8
405 #define CFG_DCACHE_SZ 8
405 #define CFG_DCACHE_SZ 8
406 #elif defined CONFIG_DCACHE_SZ16
406 #elif defined CONFIG_DCACHE_SZ16
407 #define CFG_DCACHE_SZ 16
407 #define CFG_DCACHE_SZ 16
408 #elif defined CONFIG_DCACHE_SZ32
408 #elif defined CONFIG_DCACHE_SZ32
409 #define CFG_DCACHE_SZ 32
409 #define CFG_DCACHE_SZ 32
410 #elif defined CONFIG_DCACHE_SZ64
410 #elif defined CONFIG_DCACHE_SZ64
411 #define CFG_DCACHE_SZ 64
411 #define CFG_DCACHE_SZ 64
412 #elif defined CONFIG_DCACHE_SZ128
412 #elif defined CONFIG_DCACHE_SZ128
413 #define CFG_DCACHE_SZ 128
413 #define CFG_DCACHE_SZ 128
414 #elif defined CONFIG_DCACHE_SZ256
414 #elif defined CONFIG_DCACHE_SZ256
415 #define CFG_DCACHE_SZ 256
415 #define CFG_DCACHE_SZ 256
416 #else
416 #else
417 #define CFG_DCACHE_SZ 1
417 #define CFG_DCACHE_SZ 1
418 #endif
418 #endif
419
419
420 #ifdef CONFIG_DCACHE_LZ16
420 #ifdef CONFIG_DCACHE_LZ16
421 #define CFG_DLINE_SZ 4
421 #define CFG_DLINE_SZ 4
422 #else
422 #else
423 #define CFG_DLINE_SZ 8
423 #define CFG_DLINE_SZ 8
424 #endif
424 #endif
425
425
426 #if defined CONFIG_DCACHE_ALGODIR
426 #if defined CONFIG_DCACHE_ALGODIR
427 #define CFG_DCACHE_ALGORND 3
427 #define CFG_DCACHE_ALGORND 3
428 #elif defined CONFIG_DCACHE_ALGORND
428 #elif defined CONFIG_DCACHE_ALGORND
429 #define CFG_DCACHE_ALGORND 2
429 #define CFG_DCACHE_ALGORND 2
430 #elif defined CONFIG_DCACHE_ALGOLRR
430 #elif defined CONFIG_DCACHE_ALGOLRR
431 #define CFG_DCACHE_ALGORND 1
431 #define CFG_DCACHE_ALGORND 1
432 #else
432 #else
433 #define CFG_DCACHE_ALGORND 0
433 #define CFG_DCACHE_ALGORND 0
434 #endif
434 #endif
435
435
436 #ifndef CONFIG_DCACHE_LOCK
436 #ifndef CONFIG_DCACHE_LOCK
437 #define CONFIG_DCACHE_LOCK 0
437 #define CONFIG_DCACHE_LOCK 0
438 #endif
438 #endif
439
439
440 #ifndef CONFIG_DCACHE_SNOOP
440 #ifndef CONFIG_DCACHE_SNOOP
441 #define CONFIG_DCACHE_SNOOP 0
441 #define CONFIG_DCACHE_SNOOP 0
442 #endif
442 #endif
443
443
444 #ifndef CONFIG_DCACHE_SNOOP_FAST
444 #ifndef CONFIG_DCACHE_SNOOP_FAST
445 #define CONFIG_DCACHE_SNOOP_FAST 0
445 #define CONFIG_DCACHE_SNOOP_FAST 0
446 #endif
446 #endif
447
447
448 #ifndef CONFIG_DCACHE_SNOOP_SEPTAG
448 #ifndef CONFIG_DCACHE_SNOOP_SEPTAG
449 #define CONFIG_DCACHE_SNOOP_SEPTAG 0
449 #define CONFIG_DCACHE_SNOOP_SEPTAG 0
450 #endif
450 #endif
451
451
452 #ifndef CONFIG_CACHE_FIXED
452 #ifndef CONFIG_CACHE_FIXED
453 #define CONFIG_CACHE_FIXED 0
453 #define CONFIG_CACHE_FIXED 0
454 #endif
454 #endif
455
455
456 #ifndef CONFIG_DCACHE_LRAM
456 #ifndef CONFIG_DCACHE_LRAM
457 #define CONFIG_DCACHE_LRAM 0
457 #define CONFIG_DCACHE_LRAM 0
458 #endif
458 #endif
459
459
460 #ifndef CONFIG_DCACHE_LRSTART
460 #ifndef CONFIG_DCACHE_LRSTART
461 #define CONFIG_DCACHE_LRSTART 8F
461 #define CONFIG_DCACHE_LRSTART 8F
462 #endif
462 #endif
463
463
464 #if defined CONFIG_DCACHE_LRAM_SZ2
464 #if defined CONFIG_DCACHE_LRAM_SZ2
465 #define CFG_DLRAM_SIZE 2
465 #define CFG_DLRAM_SIZE 2
466 #elif defined CONFIG_DCACHE_LRAM_SZ4
466 #elif defined CONFIG_DCACHE_LRAM_SZ4
467 #define CFG_DLRAM_SIZE 4
467 #define CFG_DLRAM_SIZE 4
468 #elif defined CONFIG_DCACHE_LRAM_SZ8
468 #elif defined CONFIG_DCACHE_LRAM_SZ8
469 #define CFG_DLRAM_SIZE 8
469 #define CFG_DLRAM_SIZE 8
470 #elif defined CONFIG_DCACHE_LRAM_SZ16
470 #elif defined CONFIG_DCACHE_LRAM_SZ16
471 #define CFG_DLRAM_SIZE 16
471 #define CFG_DLRAM_SIZE 16
472 #elif defined CONFIG_DCACHE_LRAM_SZ32
472 #elif defined CONFIG_DCACHE_LRAM_SZ32
473 #define CFG_DLRAM_SIZE 32
473 #define CFG_DLRAM_SIZE 32
474 #elif defined CONFIG_DCACHE_LRAM_SZ64
474 #elif defined CONFIG_DCACHE_LRAM_SZ64
475 #define CFG_DLRAM_SIZE 64
475 #define CFG_DLRAM_SIZE 64
476 #elif defined CONFIG_DCACHE_LRAM_SZ128
476 #elif defined CONFIG_DCACHE_LRAM_SZ128
477 #define CFG_DLRAM_SIZE 128
477 #define CFG_DLRAM_SIZE 128
478 #elif defined CONFIG_DCACHE_LRAM_SZ256
478 #elif defined CONFIG_DCACHE_LRAM_SZ256
479 #define CFG_DLRAM_SIZE 256
479 #define CFG_DLRAM_SIZE 256
480 #else
480 #else
481 #define CFG_DLRAM_SIZE 1
481 #define CFG_DLRAM_SIZE 1
482 #endif
482 #endif
483
483
484 #if defined CONFIG_MMU_PAGE_4K
484 #if defined CONFIG_MMU_PAGE_4K
485 #define CONFIG_MMU_PAGE 0
485 #define CONFIG_MMU_PAGE 0
486 #elif defined CONFIG_MMU_PAGE_8K
486 #elif defined CONFIG_MMU_PAGE_8K
487 #define CONFIG_MMU_PAGE 1
487 #define CONFIG_MMU_PAGE 1
488 #elif defined CONFIG_MMU_PAGE_16K
488 #elif defined CONFIG_MMU_PAGE_16K
489 #define CONFIG_MMU_PAGE 2
489 #define CONFIG_MMU_PAGE 2
490 #elif defined CONFIG_MMU_PAGE_32K
490 #elif defined CONFIG_MMU_PAGE_32K
491 #define CONFIG_MMU_PAGE 3
491 #define CONFIG_MMU_PAGE 3
492 #elif defined CONFIG_MMU_PAGE_PROG
492 #elif defined CONFIG_MMU_PAGE_PROG
493 #define CONFIG_MMU_PAGE 4
493 #define CONFIG_MMU_PAGE 4
494 #else
494 #else
495 #define CONFIG_MMU_PAGE 0
495 #define CONFIG_MMU_PAGE 0
496 #endif
496 #endif
497
497
498 #ifdef CONFIG_MMU_ENABLE
498 #ifdef CONFIG_MMU_ENABLE
499 #define CONFIG_MMUEN 1
499 #define CONFIG_MMUEN 1
500
500
501 #ifdef CONFIG_MMU_SPLIT
501 #ifdef CONFIG_MMU_SPLIT
502 #define CONFIG_TLB_TYPE 0
502 #define CONFIG_TLB_TYPE 0
503 #endif
503 #endif
504 #ifdef CONFIG_MMU_COMBINED
504 #ifdef CONFIG_MMU_COMBINED
505 #define CONFIG_TLB_TYPE 1
505 #define CONFIG_TLB_TYPE 1
506 #endif
506 #endif
507
507
508 #ifdef CONFIG_MMU_REPARRAY
508 #ifdef CONFIG_MMU_REPARRAY
509 #define CONFIG_TLB_REP 0
509 #define CONFIG_TLB_REP 0
510 #endif
510 #endif
511 #ifdef CONFIG_MMU_REPINCREMENT
511 #ifdef CONFIG_MMU_REPINCREMENT
512 #define CONFIG_TLB_REP 1
512 #define CONFIG_TLB_REP 1
513 #endif
513 #endif
514
514
515 #ifdef CONFIG_MMU_I2
515 #ifdef CONFIG_MMU_I2
516 #define CONFIG_ITLBNUM 2
516 #define CONFIG_ITLBNUM 2
517 #endif
517 #endif
518 #ifdef CONFIG_MMU_I4
518 #ifdef CONFIG_MMU_I4
519 #define CONFIG_ITLBNUM 4
519 #define CONFIG_ITLBNUM 4
520 #endif
520 #endif
521 #ifdef CONFIG_MMU_I8
521 #ifdef CONFIG_MMU_I8
522 #define CONFIG_ITLBNUM 8
522 #define CONFIG_ITLBNUM 8
523 #endif
523 #endif
524 #ifdef CONFIG_MMU_I16
524 #ifdef CONFIG_MMU_I16
525 #define CONFIG_ITLBNUM 16
525 #define CONFIG_ITLBNUM 16
526 #endif
526 #endif
527 #ifdef CONFIG_MMU_I32
527 #ifdef CONFIG_MMU_I32
528 #define CONFIG_ITLBNUM 32
528 #define CONFIG_ITLBNUM 32
529 #endif
529 #endif
530
530
531 #define CONFIG_DTLBNUM 2
531 #define CONFIG_DTLBNUM 2
532 #ifdef CONFIG_MMU_D2
532 #ifdef CONFIG_MMU_D2
533 #undef CONFIG_DTLBNUM
533 #undef CONFIG_DTLBNUM
534 #define CONFIG_DTLBNUM 2
534 #define CONFIG_DTLBNUM 2
535 #endif
535 #endif
536 #ifdef CONFIG_MMU_D4
536 #ifdef CONFIG_MMU_D4
537 #undef CONFIG_DTLBNUM
537 #undef CONFIG_DTLBNUM
538 #define CONFIG_DTLBNUM 4
538 #define CONFIG_DTLBNUM 4
539 #endif
539 #endif
540 #ifdef CONFIG_MMU_D8
540 #ifdef CONFIG_MMU_D8
541 #undef CONFIG_DTLBNUM
541 #undef CONFIG_DTLBNUM
542 #define CONFIG_DTLBNUM 8
542 #define CONFIG_DTLBNUM 8
543 #endif
543 #endif
544 #ifdef CONFIG_MMU_D16
544 #ifdef CONFIG_MMU_D16
545 #undef CONFIG_DTLBNUM
545 #undef CONFIG_DTLBNUM
546 #define CONFIG_DTLBNUM 16
546 #define CONFIG_DTLBNUM 16
547 #endif
547 #endif
548 #ifdef CONFIG_MMU_D32
548 #ifdef CONFIG_MMU_D32
549 #undef CONFIG_DTLBNUM
549 #undef CONFIG_DTLBNUM
550 #define CONFIG_DTLBNUM 32
550 #define CONFIG_DTLBNUM 32
551 #endif
551 #endif
552 #ifdef CONFIG_MMU_FASTWB
552 #ifdef CONFIG_MMU_FASTWB
553 #define CFG_MMU_FASTWB 1
553 #define CFG_MMU_FASTWB 1
554 #else
554 #else
555 #define CFG_MMU_FASTWB 0
555 #define CFG_MMU_FASTWB 0
556 #endif
556 #endif
557
557
558 #else
558 #else
559 #define CONFIG_MMUEN 0
559 #define CONFIG_MMUEN 0
560 #define CONFIG_ITLBNUM 2
560 #define CONFIG_ITLBNUM 2
561 #define CONFIG_DTLBNUM 2
561 #define CONFIG_DTLBNUM 2
562 #define CONFIG_TLB_TYPE 1
562 #define CONFIG_TLB_TYPE 1
563 #define CONFIG_TLB_REP 1
563 #define CONFIG_TLB_REP 1
564 #define CFG_MMU_FASTWB 0
564 #define CFG_MMU_FASTWB 0
565 #endif
565 #endif
566
566
567 #ifndef CONFIG_DSU_ENABLE
567 #ifndef CONFIG_DSU_ENABLE
568 #define CONFIG_DSU_ENABLE 0
568 #define CONFIG_DSU_ENABLE 0
569 #endif
569 #endif
570
570
571 #if defined CONFIG_DSU_ITRACESZ1
571 #if defined CONFIG_DSU_ITRACESZ1
572 #define CFG_DSU_ITB 1
572 #define CFG_DSU_ITB 1
573 #elif CONFIG_DSU_ITRACESZ2
573 #elif CONFIG_DSU_ITRACESZ2
574 #define CFG_DSU_ITB 2
574 #define CFG_DSU_ITB 2
575 #elif CONFIG_DSU_ITRACESZ4
575 #elif CONFIG_DSU_ITRACESZ4
576 #define CFG_DSU_ITB 4
576 #define CFG_DSU_ITB 4
577 #elif CONFIG_DSU_ITRACESZ8
577 #elif CONFIG_DSU_ITRACESZ8
578 #define CFG_DSU_ITB 8
578 #define CFG_DSU_ITB 8
579 #elif CONFIG_DSU_ITRACESZ16
579 #elif CONFIG_DSU_ITRACESZ16
580 #define CFG_DSU_ITB 16
580 #define CFG_DSU_ITB 16
581 #else
581 #else
582 #define CFG_DSU_ITB 0
582 #define CFG_DSU_ITB 0
583 #endif
583 #endif
584
584
585 #if defined CONFIG_DSU_ATRACESZ1
585 #if defined CONFIG_DSU_ATRACESZ1
586 #define CFG_DSU_ATB 1
586 #define CFG_DSU_ATB 1
587 #elif CONFIG_DSU_ATRACESZ2
587 #elif CONFIG_DSU_ATRACESZ2
588 #define CFG_DSU_ATB 2
588 #define CFG_DSU_ATB 2
589 #elif CONFIG_DSU_ATRACESZ4
589 #elif CONFIG_DSU_ATRACESZ4
590 #define CFG_DSU_ATB 4
590 #define CFG_DSU_ATB 4
591 #elif CONFIG_DSU_ATRACESZ8
591 #elif CONFIG_DSU_ATRACESZ8
592 #define CFG_DSU_ATB 8
592 #define CFG_DSU_ATB 8
593 #elif CONFIG_DSU_ATRACESZ16
593 #elif CONFIG_DSU_ATRACESZ16
594 #define CFG_DSU_ATB 16
594 #define CFG_DSU_ATB 16
595 #else
595 #else
596 #define CFG_DSU_ATB 0
596 #define CFG_DSU_ATB 0
597 #endif
597 #endif
598
598
599 #ifndef CONFIG_LEON3FT_EN
599 #ifndef CONFIG_LEON3FT_EN
600 #define CONFIG_LEON3FT_EN 0
600 #define CONFIG_LEON3FT_EN 0
601 #endif
601 #endif
602
602
603 #if defined CONFIG_IUFT_PAR
603 #if defined CONFIG_IUFT_PAR
604 #define CONFIG_IUFT_EN 1
604 #define CONFIG_IUFT_EN 1
605 #elif defined CONFIG_IUFT_DMR
605 #elif defined CONFIG_IUFT_DMR
606 #define CONFIG_IUFT_EN 2
606 #define CONFIG_IUFT_EN 2
607 #elif defined CONFIG_IUFT_BCH
607 #elif defined CONFIG_IUFT_BCH
608 #define CONFIG_IUFT_EN 3
608 #define CONFIG_IUFT_EN 3
609 #elif defined CONFIG_IUFT_TMR
609 #elif defined CONFIG_IUFT_TMR
610 #define CONFIG_IUFT_EN 4
610 #define CONFIG_IUFT_EN 4
611 #else
611 #else
612 #define CONFIG_IUFT_EN 0
612 #define CONFIG_IUFT_EN 0
613 #endif
613 #endif
614 #ifndef CONFIG_RF_ERRINJ
614 #ifndef CONFIG_RF_ERRINJ
615 #define CONFIG_RF_ERRINJ 0
615 #define CONFIG_RF_ERRINJ 0
616 #endif
616 #endif
617
617
618 #ifndef CONFIG_FPUFT_EN
618 #ifndef CONFIG_FPUFT_EN
619 #define CONFIG_FPUFT 0
619 #define CONFIG_FPUFT 0
620 #else
620 #else
621 #ifdef CONFIG_FPU_GRFPU
621 #ifdef CONFIG_FPU_GRFPU
622 #define CONFIG_FPUFT 2
622 #define CONFIG_FPUFT 2
623 #else
623 #else
624 #define CONFIG_FPUFT 1
624 #define CONFIG_FPUFT 1
625 #endif
625 #endif
626 #endif
626 #endif
627
627
628 #ifndef CONFIG_CACHE_FT_EN
628 #ifndef CONFIG_CACHE_FT_EN
629 #define CONFIG_CACHE_FT_EN 0
629 #define CONFIG_CACHE_FT_EN 0
630 #endif
630 #endif
631 #ifndef CONFIG_CACHE_ERRINJ
631 #ifndef CONFIG_CACHE_ERRINJ
632 #define CONFIG_CACHE_ERRINJ 0
632 #define CONFIG_CACHE_ERRINJ 0
633 #endif
633 #endif
634
634
635 #ifndef CONFIG_LEON3_NETLIST
635 #ifndef CONFIG_LEON3_NETLIST
636 #define CONFIG_LEON3_NETLIST 0
636 #define CONFIG_LEON3_NETLIST 0
637 #endif
637 #endif
638
638
639 #ifdef CONFIG_DEBUG_PC32
639 #ifdef CONFIG_DEBUG_PC32
640 #define CFG_DEBUG_PC32 0
640 #define CFG_DEBUG_PC32 0
641 #else
641 #else
642 #define CFG_DEBUG_PC32 2
642 #define CFG_DEBUG_PC32 2
643 #endif
643 #endif
644 #ifndef CONFIG_IU_DISAS
644 #ifndef CONFIG_IU_DISAS
645 #define CONFIG_IU_DISAS 0
645 #define CONFIG_IU_DISAS 0
646 #endif
646 #endif
647 #ifndef CONFIG_IU_DISAS_NET
647 #ifndef CONFIG_IU_DISAS_NET
648 #define CONFIG_IU_DISAS_NET 0
648 #define CONFIG_IU_DISAS_NET 0
649 #endif
649 #endif
650
650
651
651
652 #ifndef CONFIG_AHB_SPLIT
652 #ifndef CONFIG_AHB_SPLIT
653 #define CONFIG_AHB_SPLIT 0
653 #define CONFIG_AHB_SPLIT 0
654 #endif
654 #endif
655
655
656 #ifndef CONFIG_AHB_RROBIN
656 #ifndef CONFIG_AHB_RROBIN
657 #define CONFIG_AHB_RROBIN 0
657 #define CONFIG_AHB_RROBIN 0
658 #endif
658 #endif
659
659
660 #ifndef CONFIG_AHB_IOADDR
660 #ifndef CONFIG_AHB_IOADDR
661 #define CONFIG_AHB_IOADDR FFF
661 #define CONFIG_AHB_IOADDR FFF
662 #endif
662 #endif
663
663
664 #ifndef CONFIG_APB_HADDR
664 #ifndef CONFIG_APB_HADDR
665 #define CONFIG_APB_HADDR 800
665 #define CONFIG_APB_HADDR 800
666 #endif
666 #endif
667
667
668 #ifndef CONFIG_AHB_MON
668 #ifndef CONFIG_AHB_MON
669 #define CONFIG_AHB_MON 0
669 #define CONFIG_AHB_MON 0
670 #endif
670 #endif
671
671
672 #ifndef CONFIG_AHB_MONERR
672 #ifndef CONFIG_AHB_MONERR
673 #define CONFIG_AHB_MONERR 0
673 #define CONFIG_AHB_MONERR 0
674 #endif
674 #endif
675
675
676 #ifndef CONFIG_AHB_MONWAR
676 #ifndef CONFIG_AHB_MONWAR
677 #define CONFIG_AHB_MONWAR 0
677 #define CONFIG_AHB_MONWAR 0
678 #endif
678 #endif
679
679
680 #ifndef CONFIG_AHB_DTRACE
680 #ifndef CONFIG_AHB_DTRACE
681 #define CONFIG_AHB_DTRACE 0
681 #define CONFIG_AHB_DTRACE 0
682 #endif
682 #endif
683
683
684 #ifndef CONFIG_DSU_JTAG
684 #ifndef CONFIG_DSU_JTAG
685 #define CONFIG_DSU_JTAG 0
685 #define CONFIG_DSU_JTAG 0
686 #endif
686 #endif
687
687
688 #ifndef CONFIG_DSU_ETH
688 #ifndef CONFIG_DSU_ETH
689 #define CONFIG_DSU_ETH 0
689 #define CONFIG_DSU_ETH 0
690 #endif
690 #endif
691
691
692 #ifndef CONFIG_DSU_IPMSB
692 #ifndef CONFIG_DSU_IPMSB
693 #define CONFIG_DSU_IPMSB C0A8
693 #define CONFIG_DSU_IPMSB C0A8
694 #endif
694 #endif
695
695
696 #ifndef CONFIG_DSU_IPLSB
696 #ifndef CONFIG_DSU_IPLSB
697 #define CONFIG_DSU_IPLSB 0033
697 #define CONFIG_DSU_IPLSB 0033
698 #endif
698 #endif
699
699
700 #ifndef CONFIG_DSU_ETHMSB
700 #ifndef CONFIG_DSU_ETHMSB
701 #define CONFIG_DSU_ETHMSB 020000
701 #define CONFIG_DSU_ETHMSB 020000
702 #endif
702 #endif
703
703
704 #ifndef CONFIG_DSU_ETHLSB
704 #ifndef CONFIG_DSU_ETHLSB
705 #define CONFIG_DSU_ETHLSB 000009
705 #define CONFIG_DSU_ETHLSB 000009
706 #endif
706 #endif
707
707
708 #if defined CONFIG_DSU_ETHSZ1
708 #if defined CONFIG_DSU_ETHSZ1
709 #define CFG_DSU_ETHB 1
709 #define CFG_DSU_ETHB 1
710 #elif CONFIG_DSU_ETHSZ2
710 #elif CONFIG_DSU_ETHSZ2
711 #define CFG_DSU_ETHB 2
711 #define CFG_DSU_ETHB 2
712 #elif CONFIG_DSU_ETHSZ4
712 #elif CONFIG_DSU_ETHSZ4
713 #define CFG_DSU_ETHB 4
713 #define CFG_DSU_ETHB 4
714 #elif CONFIG_DSU_ETHSZ8
714 #elif CONFIG_DSU_ETHSZ8
715 #define CFG_DSU_ETHB 8
715 #define CFG_DSU_ETHB 8
716 #elif CONFIG_DSU_ETHSZ16
716 #elif CONFIG_DSU_ETHSZ16
717 #define CFG_DSU_ETHB 16
717 #define CFG_DSU_ETHB 16
718 #elif CONFIG_DSU_ETHSZ32
718 #elif CONFIG_DSU_ETHSZ32
719 #define CFG_DSU_ETHB 32
719 #define CFG_DSU_ETHB 32
720 #else
720 #else
721 #define CFG_DSU_ETHB 1
721 #define CFG_DSU_ETHB 1
722 #endif
722 #endif
723
723
724 #ifndef CONFIG_DSU_ETH_PROG
724 #ifndef CONFIG_DSU_ETH_PROG
725 #define CONFIG_DSU_ETH_PROG 0
725 #define CONFIG_DSU_ETH_PROG 0
726 #endif
726 #endif
727
727
728 #ifndef CONFIG_DSU_ETH_DIS
728 #ifndef CONFIG_DSU_ETH_DIS
729 #define CONFIG_DSU_ETH_DIS 0
729 #define CONFIG_DSU_ETH_DIS 0
730 #endif
730 #endif
731
731
732 #ifndef CONFIG_MCTRL_LEON2
732 #ifndef CONFIG_MCTRL_LEON2
733 #define CONFIG_MCTRL_LEON2 0
733 #define CONFIG_MCTRL_LEON2 0
734 #endif
734 #endif
735
735
736 #ifndef CONFIG_MCTRL_SDRAM
736 #ifndef CONFIG_MCTRL_SDRAM
737 #define CONFIG_MCTRL_SDRAM 0
737 #define CONFIG_MCTRL_SDRAM 0
738 #endif
738 #endif
739
739
740 #ifndef CONFIG_MCTRL_SDRAM_SEPBUS
740 #ifndef CONFIG_MCTRL_SDRAM_SEPBUS
741 #define CONFIG_MCTRL_SDRAM_SEPBUS 0
741 #define CONFIG_MCTRL_SDRAM_SEPBUS 0
742 #endif
742 #endif
743
743
744 #ifndef CONFIG_MCTRL_SDRAM_INVCLK
744 #ifndef CONFIG_MCTRL_SDRAM_INVCLK
745 #define CONFIG_MCTRL_SDRAM_INVCLK 0
745 #define CONFIG_MCTRL_SDRAM_INVCLK 0
746 #endif
746 #endif
747
747
748 #ifndef CONFIG_MCTRL_SDRAM_BUS64
748 #ifndef CONFIG_MCTRL_SDRAM_BUS64
749 #define CONFIG_MCTRL_SDRAM_BUS64 0
749 #define CONFIG_MCTRL_SDRAM_BUS64 0
750 #endif
750 #endif
751
751
752 #ifndef CONFIG_MCTRL_8BIT
752 #ifndef CONFIG_MCTRL_8BIT
753 #define CONFIG_MCTRL_8BIT 0
753 #define CONFIG_MCTRL_8BIT 0
754 #endif
754 #endif
755
755
756 #ifndef CONFIG_MCTRL_16BIT
756 #ifndef CONFIG_MCTRL_16BIT
757 #define CONFIG_MCTRL_16BIT 0
757 #define CONFIG_MCTRL_16BIT 0
758 #endif
758 #endif
759
759
760 #ifndef CONFIG_MCTRL_5CS
760 #ifndef CONFIG_MCTRL_5CS
761 #define CONFIG_MCTRL_5CS 0
761 #define CONFIG_MCTRL_5CS 0
762 #endif
762 #endif
763
763
764 #ifndef CONFIG_MCTRL_EDAC
764 #ifndef CONFIG_MCTRL_EDAC
765 #define CONFIG_MCTRL_EDAC 0
765 #define CONFIG_MCTRL_EDAC 0
766 #endif
766 #endif
767
767
768 #ifndef CONFIG_MCTRL_PAGE
768 #ifndef CONFIG_MCTRL_PAGE
769 #define CONFIG_MCTRL_PAGE 0
769 #define CONFIG_MCTRL_PAGE 0
770 #endif
770 #endif
771
771
772 #ifndef CONFIG_MCTRL_PROGPAGE
772 #ifndef CONFIG_MCTRL_PROGPAGE
773 #define CONFIG_MCTRL_PROGPAGE 0
773 #define CONFIG_MCTRL_PROGPAGE 0
774 #endif
774 #endif
775
775
776
776
777 #ifndef CONFIG_MIG_DDR2
777 #ifndef CONFIG_MIG_DDR2
778 #define CONFIG_MIG_DDR2 0
778 #define CONFIG_MIG_DDR2 0
779 #endif
779 #endif
780
780
781 #ifndef CONFIG_MIG_RANKS
781 #ifndef CONFIG_MIG_RANKS
782 #define CONFIG_MIG_RANKS 1
782 #define CONFIG_MIG_RANKS 1
783 #endif
783 #endif
784
784
785 #ifndef CONFIG_MIG_COLBITS
785 #ifndef CONFIG_MIG_COLBITS
786 #define CONFIG_MIG_COLBITS 10
786 #define CONFIG_MIG_COLBITS 10
787 #endif
787 #endif
788
788
789 #ifndef CONFIG_MIG_ROWBITS
789 #ifndef CONFIG_MIG_ROWBITS
790 #define CONFIG_MIG_ROWBITS 13
790 #define CONFIG_MIG_ROWBITS 13
791 #endif
791 #endif
792
792
793 #ifndef CONFIG_MIG_BANKBITS
793 #ifndef CONFIG_MIG_BANKBITS
794 #define CONFIG_MIG_BANKBITS 2
794 #define CONFIG_MIG_BANKBITS 2
795 #endif
795 #endif
796
796
797 #ifndef CONFIG_MIG_HMASK
797 #ifndef CONFIG_MIG_HMASK
798 #define CONFIG_MIG_HMASK F00
798 #define CONFIG_MIG_HMASK F00
799 #endif
799 #endif
800 #ifndef CONFIG_AHBSTAT_ENABLE
800 #ifndef CONFIG_AHBSTAT_ENABLE
801 #define CONFIG_AHBSTAT_ENABLE 0
801 #define CONFIG_AHBSTAT_ENABLE 0
802 #endif
802 #endif
803
803
804 #ifndef CONFIG_AHBSTAT_NFTSLV
804 #ifndef CONFIG_AHBSTAT_NFTSLV
805 #define CONFIG_AHBSTAT_NFTSLV 1
805 #define CONFIG_AHBSTAT_NFTSLV 1
806 #endif
806 #endif
807
807
808 #ifndef CONFIG_AHBROM_ENABLE
808 #ifndef CONFIG_AHBROM_ENABLE
809 #define CONFIG_AHBROM_ENABLE 0
809 #define CONFIG_AHBROM_ENABLE 0
810 #endif
810 #endif
811
811
812 #ifndef CONFIG_AHBROM_START
812 #ifndef CONFIG_AHBROM_START
813 #define CONFIG_AHBROM_START 000
813 #define CONFIG_AHBROM_START 000
814 #endif
814 #endif
815
815
816 #ifndef CONFIG_AHBROM_PIPE
816 #ifndef CONFIG_AHBROM_PIPE
817 #define CONFIG_AHBROM_PIPE 0
817 #define CONFIG_AHBROM_PIPE 0
818 #endif
818 #endif
819
819
820 #if (CONFIG_AHBROM_START == 0) && (CONFIG_AHBROM_ENABLE == 1)
820 #if (CONFIG_AHBROM_START == 0) && (CONFIG_AHBROM_ENABLE == 1)
821 #define CONFIG_ROM_START 100
821 #define CONFIG_ROM_START 100
822 #else
822 #else
823 #define CONFIG_ROM_START 000
823 #define CONFIG_ROM_START 000
824 #endif
824 #endif
825
825
826
826
827 #ifndef CONFIG_AHBRAM_ENABLE
827 #ifndef CONFIG_AHBRAM_ENABLE
828 #define CONFIG_AHBRAM_ENABLE 0
828 #define CONFIG_AHBRAM_ENABLE 0
829 #endif
829 #endif
830
830
831 #ifndef CONFIG_AHBRAM_START
831 #ifndef CONFIG_AHBRAM_START
832 #define CONFIG_AHBRAM_START A00
832 #define CONFIG_AHBRAM_START A00
833 #endif
833 #endif
834
834
835 #if defined CONFIG_AHBRAM_SZ1
835 #if defined CONFIG_AHBRAM_SZ1
836 #define CFG_AHBRAMSZ 1
836 #define CFG_AHBRAMSZ 1
837 #elif CONFIG_AHBRAM_SZ2
837 #elif CONFIG_AHBRAM_SZ2
838 #define CFG_AHBRAMSZ 2
838 #define CFG_AHBRAMSZ 2
839 #elif CONFIG_AHBRAM_SZ4
839 #elif CONFIG_AHBRAM_SZ4
840 #define CFG_AHBRAMSZ 4
840 #define CFG_AHBRAMSZ 4
841 #elif CONFIG_AHBRAM_SZ8
841 #elif CONFIG_AHBRAM_SZ8
842 #define CFG_AHBRAMSZ 8
842 #define CFG_AHBRAMSZ 8
843 #elif CONFIG_AHBRAM_SZ16
843 #elif CONFIG_AHBRAM_SZ16
844 #define CFG_AHBRAMSZ 16
844 #define CFG_AHBRAMSZ 16
845 #elif CONFIG_AHBRAM_SZ32
845 #elif CONFIG_AHBRAM_SZ32
846 #define CFG_AHBRAMSZ 32
846 #define CFG_AHBRAMSZ 32
847 #elif CONFIG_AHBRAM_SZ64
847 #elif CONFIG_AHBRAM_SZ64
848 #define CFG_AHBRAMSZ 64
848 #define CFG_AHBRAMSZ 64
849 #else
849 #else
850 #define CFG_AHBRAMSZ 1
850 #define CFG_AHBRAMSZ 1
851 #endif
851 #endif
852
852
853 #ifndef CONFIG_GRETH_ENABLE
853 #ifndef CONFIG_GRETH_ENABLE
854 #define CONFIG_GRETH_ENABLE 0
854 #define CONFIG_GRETH_ENABLE 0
855 #endif
855 #endif
856
856
857 #ifndef CONFIG_GRETH_GIGA
857 #ifndef CONFIG_GRETH_GIGA
858 #define CONFIG_GRETH_GIGA 0
858 #define CONFIG_GRETH_GIGA 0
859 #endif
859 #endif
860
860
861 #if defined CONFIG_GRETH_FIFO4
861 #if defined CONFIG_GRETH_FIFO4
862 #define CFG_GRETH_FIFO 4
862 #define CFG_GRETH_FIFO 4
863 #elif defined CONFIG_GRETH_FIFO8
863 #elif defined CONFIG_GRETH_FIFO8
864 #define CFG_GRETH_FIFO 8
864 #define CFG_GRETH_FIFO 8
865 #elif defined CONFIG_GRETH_FIFO16
865 #elif defined CONFIG_GRETH_FIFO16
866 #define CFG_GRETH_FIFO 16
866 #define CFG_GRETH_FIFO 16
867 #elif defined CONFIG_GRETH_FIFO32
867 #elif defined CONFIG_GRETH_FIFO32
868 #define CFG_GRETH_FIFO 32
868 #define CFG_GRETH_FIFO 32
869 #elif defined CONFIG_GRETH_FIFO64
869 #elif defined CONFIG_GRETH_FIFO64
870 #define CFG_GRETH_FIFO 64
870 #define CFG_GRETH_FIFO 64
871 #else
871 #else
872 #define CFG_GRETH_FIFO 8
872 #define CFG_GRETH_FIFO 8
873 #endif
873 #endif
874
874
875 #ifndef CONFIG_UART1_ENABLE
875 #ifndef CONFIG_UART1_ENABLE
876 #define CONFIG_UART1_ENABLE 0
876 #define CONFIG_UART1_ENABLE 0
877 #endif
877 #endif
878
878
879 #if defined CONFIG_UA1_FIFO1
879 #if defined CONFIG_UA1_FIFO1
880 #define CFG_UA1_FIFO 1
880 #define CFG_UA1_FIFO 1
881 #elif defined CONFIG_UA1_FIFO2
881 #elif defined CONFIG_UA1_FIFO2
882 #define CFG_UA1_FIFO 2
882 #define CFG_UA1_FIFO 2
883 #elif defined CONFIG_UA1_FIFO4
883 #elif defined CONFIG_UA1_FIFO4
884 #define CFG_UA1_FIFO 4
884 #define CFG_UA1_FIFO 4
885 #elif defined CONFIG_UA1_FIFO8
885 #elif defined CONFIG_UA1_FIFO8
886 #define CFG_UA1_FIFO 8
886 #define CFG_UA1_FIFO 8
887 #elif defined CONFIG_UA1_FIFO16
887 #elif defined CONFIG_UA1_FIFO16
888 #define CFG_UA1_FIFO 16
888 #define CFG_UA1_FIFO 16
889 #elif defined CONFIG_UA1_FIFO32
889 #elif defined CONFIG_UA1_FIFO32
890 #define CFG_UA1_FIFO 32
890 #define CFG_UA1_FIFO 32
891 #else
891 #else
892 #define CFG_UA1_FIFO 1
892 #define CFG_UA1_FIFO 1
893 #endif
893 #endif
894
894
895 #ifndef CONFIG_IRQ3_ENABLE
895 #ifndef CONFIG_IRQ3_ENABLE
896 #define CONFIG_IRQ3_ENABLE 0
896 #define CONFIG_IRQ3_ENABLE 0
897 #endif
897 #endif
898 #ifndef CONFIG_IRQ3_NSEC
898 #ifndef CONFIG_IRQ3_NSEC
899 #define CONFIG_IRQ3_NSEC 0
899 #define CONFIG_IRQ3_NSEC 0
900 #endif
900 #endif
901 #ifndef CONFIG_GPT_ENABLE
901 #ifndef CONFIG_GPT_ENABLE
902 #define CONFIG_GPT_ENABLE 0
902 #define CONFIG_GPT_ENABLE 0
903 #endif
903 #endif
904
904
905 #ifndef CONFIG_GPT_NTIM
905 #ifndef CONFIG_GPT_NTIM
906 #define CONFIG_GPT_NTIM 1
906 #define CONFIG_GPT_NTIM 1
907 #endif
907 #endif
908
908
909 #ifndef CONFIG_GPT_SW
909 #ifndef CONFIG_GPT_SW
910 #define CONFIG_GPT_SW 8
910 #define CONFIG_GPT_SW 8
911 #endif
911 #endif
912
912
913 #ifndef CONFIG_GPT_TW
913 #ifndef CONFIG_GPT_TW
914 #define CONFIG_GPT_TW 8
914 #define CONFIG_GPT_TW 8
915 #endif
915 #endif
916
916
917 #ifndef CONFIG_GPT_IRQ
917 #ifndef CONFIG_GPT_IRQ
918 #define CONFIG_GPT_IRQ 8
918 #define CONFIG_GPT_IRQ 8
919 #endif
919 #endif
920
920
921 #ifndef CONFIG_GPT_SEPIRQ
921 #ifndef CONFIG_GPT_SEPIRQ
922 #define CONFIG_GPT_SEPIRQ 0
922 #define CONFIG_GPT_SEPIRQ 0
923 #endif
923 #endif
924 #ifndef CONFIG_GPT_ENABLE
924 #ifndef CONFIG_GPT_ENABLE
925 #define CONFIG_GPT_ENABLE 0
925 #define CONFIG_GPT_ENABLE 0
926 #endif
926 #endif
927
927
928 #ifndef CONFIG_GPT_NTIM
928 #ifndef CONFIG_GPT_NTIM
929 #define CONFIG_GPT_NTIM 1
929 #define CONFIG_GPT_NTIM 1
930 #endif
930 #endif
931
931
932 #ifndef CONFIG_GPT_SW
932 #ifndef CONFIG_GPT_SW
933 #define CONFIG_GPT_SW 8
933 #define CONFIG_GPT_SW 8
934 #endif
934 #endif
935
935
936 #ifndef CONFIG_GPT_TW
936 #ifndef CONFIG_GPT_TW
937 #define CONFIG_GPT_TW 8
937 #define CONFIG_GPT_TW 8
938 #endif
938 #endif
939
939
940 #ifndef CONFIG_GPT_IRQ
940 #ifndef CONFIG_GPT_IRQ
941 #define CONFIG_GPT_IRQ 8
941 #define CONFIG_GPT_IRQ 8
942 #endif
942 #endif
943
943
944 #ifndef CONFIG_GPT_SEPIRQ
944 #ifndef CONFIG_GPT_SEPIRQ
945 #define CONFIG_GPT_SEPIRQ 0
945 #define CONFIG_GPT_SEPIRQ 0
946 #endif
946 #endif
947
947
948 #ifndef CONFIG_GPT_WDOGEN
948 #ifndef CONFIG_GPT_WDOGEN
949 #define CONFIG_GPT_WDOGEN 0
949 #define CONFIG_GPT_WDOGEN 0
950 #endif
950 #endif
951
951
952 #ifndef CONFIG_GPT_WDOG
952 #ifndef CONFIG_GPT_WDOG
953 #define CONFIG_GPT_WDOG 0
953 #define CONFIG_GPT_WDOG 0
954 #endif
954 #endif
955
955
956 #ifndef CONFIG_GRGPIO_ENABLE
956 #ifndef CONFIG_GRGPIO_ENABLE
957 #define CONFIG_GRGPIO_ENABLE 0
957 #define CONFIG_GRGPIO_ENABLE 0
958 #endif
958 #endif
959 #ifndef CONFIG_GRGPIO_IMASK
959 #ifndef CONFIG_GRGPIO_IMASK
960 #define CONFIG_GRGPIO_IMASK 0000
960 #define CONFIG_GRGPIO_IMASK 0000
961 #endif
961 #endif
962 #ifndef CONFIG_GRGPIO_WIDTH
962 #ifndef CONFIG_GRGPIO_WIDTH
963 #define CONFIG_GRGPIO_WIDTH 1
963 #define CONFIG_GRGPIO_WIDTH 1
964 #endif
964 #endif
965
965
966 #ifndef CONFIG_VGA_ENABLE
966 #ifndef CONFIG_VGA_ENABLE
967 #define CONFIG_VGA_ENABLE 0
967 #define CONFIG_VGA_ENABLE 0
968 #endif
968 #endif
969 #ifndef CONFIG_SVGA_ENABLE
969 #ifndef CONFIG_SVGA_ENABLE
970 #define CONFIG_SVGA_ENABLE 0
970 #define CONFIG_SVGA_ENABLE 0
971 #endif
971 #endif
972 #ifndef CONFIG_KBD_ENABLE
972 #ifndef CONFIG_KBD_ENABLE
973 #define CONFIG_KBD_ENABLE 0
973 #define CONFIG_KBD_ENABLE 0
974 #endif
974 #endif
975
975
976
976
977 #ifndef CONFIG_SPIMCTRL
977 #ifndef CONFIG_SPIMCTRL
978 #define CONFIG_SPIMCTRL 0
978 #define CONFIG_SPIMCTRL 0
979 #endif
979 #endif
980
980
981 #ifndef CONFIG_SPIMCTRL_SDCARD
981 #ifndef CONFIG_SPIMCTRL_SDCARD
982 #define CONFIG_SPIMCTRL_SDCARD 0
982 #define CONFIG_SPIMCTRL_SDCARD 0
983 #endif
983 #endif
984
984
985 #ifndef CONFIG_SPIMCTRL_READCMD
985 #ifndef CONFIG_SPIMCTRL_READCMD
986 #define CONFIG_SPIMCTRL_READCMD 0
986 #define CONFIG_SPIMCTRL_READCMD 0
987 #endif
987 #endif
988
988
989 #ifndef CONFIG_SPIMCTRL_DUMMYBYTE
989 #ifndef CONFIG_SPIMCTRL_DUMMYBYTE
990 #define CONFIG_SPIMCTRL_DUMMYBYTE 0
990 #define CONFIG_SPIMCTRL_DUMMYBYTE 0
991 #endif
991 #endif
992
992
993 #ifndef CONFIG_SPIMCTRL_DUALOUTPUT
993 #ifndef CONFIG_SPIMCTRL_DUALOUTPUT
994 #define CONFIG_SPIMCTRL_DUALOUTPUT 0
994 #define CONFIG_SPIMCTRL_DUALOUTPUT 0
995 #endif
995 #endif
996
996
997 #ifndef CONFIG_SPIMCTRL_SCALER
997 #ifndef CONFIG_SPIMCTRL_SCALER
998 #define CONFIG_SPIMCTRL_SCALER 1
998 #define CONFIG_SPIMCTRL_SCALER 1
999 #endif
999 #endif
1000
1000
1001 #ifndef CONFIG_SPIMCTRL_ASCALER
1001 #ifndef CONFIG_SPIMCTRL_ASCALER
1002 #define CONFIG_SPIMCTRL_ASCALER 1
1002 #define CONFIG_SPIMCTRL_ASCALER 1
1003 #endif
1003 #endif
1004
1004
1005 #ifndef CONFIG_SPIMCTRL_PWRUPCNT
1005 #ifndef CONFIG_SPIMCTRL_PWRUPCNT
1006 #define CONFIG_SPIMCTRL_PWRUPCNT 0
1006 #define CONFIG_SPIMCTRL_PWRUPCNT 0
1007 #endif
1007 #endif
1008 #ifndef CONFIG_SPICTRL_ENABLE
1008 #ifndef CONFIG_SPICTRL_ENABLE
1009 #define CONFIG_SPICTRL_ENABLE 0
1009 #define CONFIG_SPICTRL_ENABLE 0
1010 #endif
1010 #endif
1011 #ifndef CONFIG_SPICTRL_NUM
1011 #ifndef CONFIG_SPICTRL_NUM
1012 #define CONFIG_SPICTRL_NUM 1
1012 #define CONFIG_SPICTRL_NUM 1
1013 #endif
1013 #endif
1014 #ifndef CONFIG_SPICTRL_SLVS
1014 #ifndef CONFIG_SPICTRL_SLVS
1015 #define CONFIG_SPICTRL_SLVS 1
1015 #define CONFIG_SPICTRL_SLVS 1
1016 #endif
1016 #endif
1017 #ifndef CONFIG_SPICTRL_FIFO
1017 #ifndef CONFIG_SPICTRL_FIFO
1018 #define CONFIG_SPICTRL_FIFO 1
1018 #define CONFIG_SPICTRL_FIFO 1
1019 #endif
1019 #endif
1020 #ifndef CONFIG_SPICTRL_SLVREG
1020 #ifndef CONFIG_SPICTRL_SLVREG
1021 #define CONFIG_SPICTRL_SLVREG 0
1021 #define CONFIG_SPICTRL_SLVREG 0
1022 #endif
1022 #endif
1023 #ifndef CONFIG_SPICTRL_ODMODE
1023 #ifndef CONFIG_SPICTRL_ODMODE
1024 #define CONFIG_SPICTRL_ODMODE 0
1024 #define CONFIG_SPICTRL_ODMODE 0
1025 #endif
1025 #endif
1026 #ifndef CONFIG_SPICTRL_AM
1026 #ifndef CONFIG_SPICTRL_AM
1027 #define CONFIG_SPICTRL_AM 0
1027 #define CONFIG_SPICTRL_AM 0
1028 #endif
1028 #endif
1029 #ifndef CONFIG_SPICTRL_ASEL
1029 #ifndef CONFIG_SPICTRL_ASEL
1030 #define CONFIG_SPICTRL_ASEL 0
1030 #define CONFIG_SPICTRL_ASEL 0
1031 #endif
1031 #endif
1032 #ifndef CONFIG_SPICTRL_TWEN
1032 #ifndef CONFIG_SPICTRL_TWEN
1033 #define CONFIG_SPICTRL_TWEN 0
1033 #define CONFIG_SPICTRL_TWEN 0
1034 #endif
1034 #endif
1035 #ifndef CONFIG_SPICTRL_MAXWLEN
1035 #ifndef CONFIG_SPICTRL_MAXWLEN
1036 #define CONFIG_SPICTRL_MAXWLEN 0
1036 #define CONFIG_SPICTRL_MAXWLEN 0
1037 #endif
1037 #endif
1038 #ifndef CONFIG_SPICTRL_SYNCRAM
1038 #ifndef CONFIG_SPICTRL_SYNCRAM
1039 #define CONFIG_SPICTRL_SYNCRAM 0
1039 #define CONFIG_SPICTRL_SYNCRAM 0
1040 #endif
1040 #endif
1041 #if defined(CONFIG_SPICTRL_DMRFT)
1041 #if defined(CONFIG_SPICTRL_DMRFT)
1042 #define CONFIG_SPICTRL_FT 1
1042 #define CONFIG_SPICTRL_FT 1
1043 #elif defined(CONFIG_SPICTRL_TMRFT)
1043 #elif defined(CONFIG_SPICTRL_TMRFT)
1044 #define CONFIG_SPICTRL_FT 2
1044 #define CONFIG_SPICTRL_FT 2
1045 #else
1045 #else
1046 #define CONFIG_SPICTRL_FT 0
1046 #define CONFIG_SPICTRL_FT 0
1047 #endif
1047 #endif
1048
1048
1049 #ifndef CONFIG_DEBUG_UART
1049 #ifndef CONFIG_DEBUG_UART
1050 #define CONFIG_DEBUG_UART 0
1050 #define CONFIG_DEBUG_UART 0
1051 #endif
1051 #endif
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@@ -1,13 +1,13
1 leon3_soc :
1 leon3_soc :
2 ENABLE_AHB_UART = 0 (disabled)
2 ENABLE_AHB_UART = 0 (disabled)
3 ENABLE_APB_UART = 0 (disabled)
3 ENABLE_APB_UART = 0 (disabled)
4 FPU_NETLIST = 1 (enabled)
4 FPU_NETLIST = 1 (enabled)
5
5
6 apb_lfr_management :
6 apb_lfr_management :
7 lfr_cal_driver (enabled)
7 lfr_cal_driver (enabled)
8
8
9 top :
9 top :
10 LFR_rstn <= LFR_soft_rstn AND rstn_25;
10 LFR_rstn <= LFR_soft_rstn AND rstn_25;
11
11
12 GRSPW :
12 GRSPW :
13 ft = 1 (enabled)
13 ft = 1 (enabled)
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@@ -1,13 +1,13
1 leon3_soc :
1 leon3_soc :
2 ENABLE_AHB_UART = 0 (disabled)
2 ENABLE_AHB_UART = 0 (disabled)
3 ENABLE_APB_UART = 0 (disabled)
3 ENABLE_APB_UART = 0 (disabled)
4 FPU_NETLIST = 0 (enabled)
4 FPU_NETLIST = 0 (enabled)
5
5
6 apb_lfr_management :
6 apb_lfr_management :
7 lfr_cal_driver (enabled)
7 lfr_cal_driver (enabled)
8
8
9 top :
9 top :
10 LFR_rstn <= LFR_soft_rstn AND rstn_25;
10 LFR_rstn <= LFR_soft_rstn AND rstn_25;
11
11
12 GRSPW :
12 GRSPW :
13 ft = 1 (enabled)
13 ft = 1 (enabled)
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@@ -1,16 +1,16
1 leon3_soc :
1 leon3_soc :
2 ENABLE_AHB_UART = 0 (disabled)
2 ENABLE_AHB_UART = 0 (disabled)
3 ENABLE_APB_UART = 0 (disabled)
3 ENABLE_APB_UART = 0 (disabled)
4 FPU_NETLIST = 0 (enabled)
4 FPU_NETLIST = 0 (enabled)
5
5
6 apb_lfr_management :
6 apb_lfr_management :
7 lfr_cal_driver (enabled)
7 lfr_cal_driver (enabled)
8
8
9 top :
9 top :
10 LFR_rstn <= LFR_soft_rstn AND rstn_25;
10 LFR_rstn <= LFR_soft_rstn AND rstn_25;
11
11
12 GRSPW :
12 GRSPW :
13 ft = 1 (enabled)
13 ft = 1 (enabled)
14
14
15 Constraint file :
15 Constraint file :
16 LFR_EQM_altran_syn_fanout.sdc
16 LFR_EQM_altran_syn_fanout.sdc
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@@ -1,53 +1,56
1 #GRLIB=../..
1 #GRLIB=../..
2 VHDLIB=../..
2 VHDLIB=../..
3 SCRIPTSDIR=$(VHDLIB)/scripts/
3 SCRIPTSDIR=$(VHDLIB)/scripts/
4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
5 TOP=leon3mp
5 TOP=testbench
6 BOARD=em-LeonLPP-A3PE3kL-v3-core1
6 BOARD=LFR-EQM
7 include $(GRLIB)/boards/$(BOARD)/Makefile.inc
7 include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc
8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
9 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
9 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
10 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
10 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
11 EFFORT=high
11 EFFORT=high
12 XSTOPT=
12 XSTOPT=
13 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
13 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
15 VHDLSYNFILES=
15 VHDLSYNFILES= IIR_CEL_TEST.vhd tb.vhd IIR_CEL_TEST_v3.vhd generator.vhd
16 VHDLSIMFILES= tb.vhd
16 VHDLSIMFILES= tb.vhd
17 SIMTOP=testbench
17 SIMTOP=testbench
18 #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
18 #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
19 #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc
19 PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_RTAX.pdc
20 PDC=$(GRLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc
20 SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_altran_syn_fanout.sdc
21 BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
21 BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
22 CLEAN=soft-clean
22 CLEAN=soft-clean
23
23
24 TECHLIBS = proasic3e
24 TECHLIBS = axcelerator
25
25
26 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
26 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
27 tmtc openchip hynix ihp gleichmann micron usbhc
27 tmtc openchip hynix ihp gleichmann micron usbhc opencores
28
28
29 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
29 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
30 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
30 pci grusbhc haps slink ascs can pwm greth coremp7 spi ac97 \
31 ./amba_lcd_16x2_ctrlr \
31 ./amba_lcd_16x2_ctrlr \
32 ./general_purpose/lpp_AMR \
32 ./general_purpose/lpp_AMR \
33 ./general_purpose/lpp_balise \
33 ./general_purpose/lpp_balise \
34 ./general_purpose/lpp_delay \
34 ./general_purpose/lpp_delay \
35 ./lpp_bootloader \
35 ./lpp_bootloader \
36 ./lfr_management \
37 ./lpp_sim \
38 ./lpp_sim/CY7C1061DV33 \
36 ./lpp_cna \
39 ./lpp_cna \
37 ./lpp_uart \
40 ./lpp_uart \
38 ./lpp_usb \
41 ./lpp_usb \
39 ./dsp/lpp_fft_rtax \
42 ./dsp/lpp_fft \
40
43
41 FILESKIP = i2cmst.vhd \
44 FILESKIP = i2cmst.vhd \
42 APB_MULTI_DIODE.vhd \
45 APB_MULTI_DIODE.vhd \
43 APB_MULTI_DIODE.vhd \
46 APB_MULTI_DIODE.vhd \
44 Top_MatrixSpec.vhd \
47 Top_MatrixSpec.vhd \
45 APB_FFT.vhd \
48 APB_FFT.vhd \
46 lpp_lfr_apbreg.vhd \
49 lpp_lfr_apbreg.vhd \
47 CoreFFT.vhd
50 CoreFFT.vhd
48
51
49 include $(GRLIB)/bin/Makefile
52 include $(GRLIB)/bin/Makefile
50 include $(GRLIB)/software/leon3/Makefile
53 include $(GRLIB)/software/leon3/Makefile
51
54
52 ################## project specific targets ##########################
55 ################## project specific targets ##########################
53
56
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@@ -1,262 +1,276
1
1
2 LIBRARY ieee;
2 LIBRARY ieee;
3 USE ieee.std_logic_1164.ALL;
3 USE ieee.std_logic_1164.ALL;
4 USE IEEE.MATH_REAL.ALL;
4 use ieee.numeric_std.all;
5 USE ieee.numeric_std.ALL;
5 USE IEEE.std_logic_signed.ALL;
6 USE IEEE.MATH_real.ALL;
6
7
7 LIBRARY techmap;
8 LIBRARY techmap;
8 USE techmap.gencomp.ALL;
9 USE techmap.gencomp.ALL;
10
11 library std;
12 use std.textio.all;
9
13
10 LIBRARY lpp;
14 LIBRARY lpp;
11 USE lpp.iir_filter.ALL;
15 USE lpp.iir_filter.ALL;
12 USE lpp.lpp_ad_conv.ALL;
16 USE lpp.lpp_ad_conv.ALL;
13 USE lpp.FILTERcfg.ALL;
17 USE lpp.FILTERcfg.ALL;
14 USE lpp.lpp_lfr_filter_coeff.ALL;
18 USE lpp.lpp_lfr_filter_coeff.ALL;
15 USE lpp.general_purpose.ALL;
19 USE lpp.general_purpose.ALL;
16 USE lpp.data_type_pkg.ALL;
20 USE lpp.data_type_pkg.ALL;
17 USE lpp.chirp_pkg.ALL;
18 USE lpp.lpp_lfr_pkg.ALL;
21 USE lpp.lpp_lfr_pkg.ALL;
19 USE lpp.general_purpose.ALL;
22 USE lpp.general_purpose.ALL;
20
23
21 ENTITY testbench IS
24 ENTITY testbench IS
22 END;
25 END;
23
26
24 ARCHITECTURE behav OF testbench IS
27 ARCHITECTURE behav OF testbench IS
25
28
26 COMPONENT IIR_CEL_TEST
29 SIGNAL TSTAMP : INTEGER:=0;
27 PORT (
28 rstn : IN STD_LOGIC;
29 clk : IN STD_LOGIC;
30 sample_in_val : IN STD_LOGIC;
31 sample_in : IN samplT(7 DOWNTO 0, 17 DOWNTO 0);
32 sample_out_val : OUT STD_LOGIC;
33 sample_out : OUT samplT(7 DOWNTO 0, 17 DOWNTO 0));
34 END COMPONENT;
35
36 COMPONENT IIR_CEL_TEST_v3
37 PORT (
38 rstn : IN STD_LOGIC;
39 clk : IN STD_LOGIC;
40 sample_in1_val : IN STD_LOGIC;
41 sample_in1 : IN samplT(7 DOWNTO 0, 17 DOWNTO 0);
42 sample_in2_val : IN STD_LOGIC;
43 sample_in2 : IN samplT(7 DOWNTO 0, 17 DOWNTO 0);
44 sample_out1_val : OUT STD_LOGIC;
45 sample_out1 : OUT samplT(7 DOWNTO 0, 17 DOWNTO 0);
46 sample_out2_val : OUT STD_LOGIC;
47 sample_out2 : OUT samplT(7 DOWNTO 0, 17 DOWNTO 0));
48 END COMPONENT;
49
50 SIGNAL clk : STD_LOGIC := '0';
30 SIGNAL clk : STD_LOGIC := '0';
51 SIGNAL clk_24k : STD_LOGIC := '0';
31 SIGNAL clk_24k : STD_LOGIC := '0';
52 SIGNAL clk_24k_r : STD_LOGIC := '0';
32 SIGNAL clk_24k_r : STD_LOGIC := '0';
53 SIGNAL rstn : STD_LOGIC;
33 SIGNAL rstn : STD_LOGIC;
54
34
35 SIGNAL signal_gen : Samples(7 DOWNTO 0);
36 SIGNAL offset_gen : Samples(7 DOWNTO 0);
37
55 SIGNAL sample : Samples(7 DOWNTO 0);
38 SIGNAL sample : Samples(7 DOWNTO 0);
39
56 SIGNAL sample_val : STD_LOGIC;
40 SIGNAL sample_val : STD_LOGIC;
57 SIGNAL sample_val_2 : STD_LOGIC;
58
41
59 SIGNAL data_chirp : STD_LOGIC_VECTOR(15 DOWNTO 0);
42 SIGNAL sample_f0_val : STD_LOGIC;
60 SIGNAL data_chirp_2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
43 SIGNAL sample_f1_val : STD_LOGIC;
44 SIGNAL sample_f2_val : STD_LOGIC;
45 SIGNAL sample_f3_val : STD_LOGIC;
61
46
62 SIGNAL sample_s : samplT(7 DOWNTO 0, 17 DOWNTO 0);
47 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
63 SIGNAL sample_out_s : samplT(7 DOWNTO 0, 17 DOWNTO 0);
48 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
64 SIGNAL sample_out_s2 : samplT(7 DOWNTO 0, 17 DOWNTO 0);
49 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
65 SIGNAL sample_out_val : STD_LOGIC;
50 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
51
52 SIGNAL sample_f0 : Samples(5 DOWNTO 0);
53 SIGNAL sample_f1 : Samples(5 DOWNTO 0);
54 SIGNAL sample_f2 : Samples(5 DOWNTO 0);
55 SIGNAL sample_f3 : Samples(5 DOWNTO 0);
66
56
67
57
68 SIGNAL sample_out1_val : STD_LOGIC;
69 SIGNAL sample_out2_val : STD_LOGIC;
70 SIGNAL sample_out1 : samplT(7 DOWNTO 0, 17 DOWNTO 0);
71 SIGNAL sample_out2 : samplT(7 DOWNTO 0, 17 DOWNTO 0);
72 SIGNAL sample_out1_reg : samplT(7 DOWNTO 0, 17 DOWNTO 0);
73 SIGNAL sample_out2_reg : samplT(7 DOWNTO 0, 17 DOWNTO 0);
74
75 SIGNAL sample_s_v3 : samplT(7 DOWNTO 0, 17 DOWNTO 0);
76 SIGNAL sample_val_v3 : STD_LOGIC;
77 SIGNAL sample_val_v3_2 : STD_LOGIC;
78
58
79 SIGNAL temp : STD_LOGIC;
59 SIGNAL temp : STD_LOGIC;
60
61
62 COMPONENT generator IS
63 GENERIC (
64 AMPLITUDE : INTEGER := 100;
65 NB_BITS : INTEGER := 16);
66
67 PORT (
68 clk : IN STD_LOGIC;
69 rstn : IN STD_LOGIC;
70 run : IN STD_LOGIC;
71
72 data_ack : IN STD_LOGIC;
73 offset : IN STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0);
74 data : OUT STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0)
75 );
76 END COMPONENT;
77
78
79 file log_input : TEXT open write_mode is "log_input.txt";
80 file log_output_f0 : TEXT open write_mode is "log_output_f0.txt";
81 file log_output_f1 : TEXT open write_mode is "log_output_f1.txt";
82 file log_output_f2 : TEXT open write_mode is "log_output_f2.txt";
83 file log_output_f3 : TEXT open write_mode is "log_output_f3.txt";
84
85
80 BEGIN
86 BEGIN
81
87
82 -----------------------------------------------------------------------------
88 -----------------------------------------------------------------------------
83 -- CLOCK and RESET
89 -- CLOCK and RESET
84 -----------------------------------------------------------------------------
90 -----------------------------------------------------------------------------
85 clk <= NOT clk AFTER 5 ns;
91 clk <= NOT clk AFTER 5 ns;
86 PROCESS
92 PROCESS
87 BEGIN -- PROCESS
93 BEGIN -- PROCESS
88 WAIT UNTIL clk = '1';
94 WAIT UNTIL clk = '1';
89 rstn <= '0';
95 rstn <= '0';
90 WAIT UNTIL clk = '1';
96 WAIT UNTIL clk = '1';
91 WAIT UNTIL clk = '1';
97 WAIT UNTIL clk = '1';
92 WAIT UNTIL clk = '1';
98 WAIT UNTIL clk = '1';
93 rstn <= '1';
99 rstn <= '1';
94 WAIT FOR 30 ms;
100 WAIT FOR 2000 ms;
95 REPORT "*** END simulation ***" SEVERITY failure;
101 REPORT "*** END simulation ***" SEVERITY failure;
96 WAIT;
102 WAIT;
97 END PROCESS;
103 END PROCESS;
104 -----------------------------------------------------------------------------
105
106
98 -----------------------------------------------------------------------------
107 -----------------------------------------------------------------------------
99
108 -- COMMON TIMESTAMPS
109 -----------------------------------------------------------------------------
110
111 PROCESS(clk)
112 BEGIN
113 IF clk'event and clk ='1' THEN
114 TSTAMP <= TSTAMP+1;
115 END IF;
116 END PROCESS;
117 -----------------------------------------------------------------------------
118
100
119
101 -----------------------------------------------------------------------------
120 -----------------------------------------------------------------------------
102 -- LPP_LFR_FILTER
121 -- LPP_LFR_FILTER
103 -----------------------------------------------------------------------------
122 -----------------------------------------------------------------------------
104 lpp_lfr_filter_1: lpp_lfr_filter
123 lpp_lfr_filter_1: lpp_lfr_filter
105 GENERIC MAP (
124 GENERIC MAP (
106 Mem_use => use_CEL)
125 --tech => 0,
126 --Mem_use => use_CEL,
127 tech => axcel,
128 Mem_use => use_RAM,
129 RTL_DESIGN_LIGHT =>0
130 )
107 PORT MAP (
131 PORT MAP (
108 sample => sample,
132 sample => sample,
109 sample_val => sample_val,
133 sample_val => sample_val,
110
134 sample_time => (others=>'0'),
111 clk => clk,
135 clk => clk,
112 rstn => rstn,
136 rstn => rstn,
113
137
114 data_shaping_SP0 => '0',
138 data_shaping_SP0 => '0',
115 data_shaping_SP1 => '0',
139 data_shaping_SP1 => '0',
116 data_shaping_R0 => '0',
140 data_shaping_R0 => '0',
117 data_shaping_R1 => '0',
141 data_shaping_R1 => '0',
118 data_shaping_R2 => '0',
142 data_shaping_R2 => '0',
119
143
120 sample_f0_val => OPEN,
144 sample_f0_val => sample_f0_val,
121 sample_f1_val => OPEN,
145 sample_f1_val => sample_f1_val,
122 sample_f2_val => OPEN,
146 sample_f2_val => sample_f2_val,
123 sample_f3_val => OPEN,
147 sample_f3_val => sample_f3_val,
124 sample_f0_wdata => OPEN,
148
125 sample_f1_wdata => OPEN,
149 sample_f0_wdata => sample_f0_wdata,
126 sample_f2_wdata => OPEN,
150 sample_f1_wdata => sample_f1_wdata,
127 sample_f3_wdata => OPEN);
151 sample_f2_wdata => sample_f2_wdata,
152 sample_f3_wdata => sample_f3_wdata
153 );
128 -----------------------------------------------------------------------------
154 -----------------------------------------------------------------------------
129
155
130
156
131 -----------------------------------------------------------------------------
157 -----------------------------------------------------------------------------
132 -- SAMPLE GENERATION
158 -- SAMPLE GENERATION
133 -----------------------------------------------------------------------------
159 -----------------------------------------------------------------------------
134 clk_24k <= NOT clk_24k AFTER 20345 ns;
160 clk_24k <= NOT clk_24k AFTER 20345 ns;
135
161
136 PROCESS (clk, rstn)
162 PROCESS (clk, rstn)
137 BEGIN -- PROCESS
163 BEGIN -- PROCESS
138 IF rstn = '0' THEN -- asynchronous reset (active low)
164 IF rstn = '0' THEN -- asynchronous reset (active low)
139 sample_val <= '0';
165 sample_val <= '0';
140 sample_val_2 <= '0';
141 clk_24k_r <= '0';
166 clk_24k_r <= '0';
142 temp <= '0';
167 temp <= '0';
143 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
168 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
144 clk_24k_r <= clk_24k;
169 clk_24k_r <= clk_24k;
145 IF clk_24k = '1' AND clk_24k_r = '0' THEN
170 IF clk_24k = '1' AND clk_24k_r = '0' THEN
146 sample_val <= '1';
171 sample_val <= '1';
147 sample_val_2 <= temp;
148 temp <= NOT temp;
172 temp <= NOT temp;
149 ELSE
173 ELSE
150 sample_val <= '0';
174 sample_val <= '0';
151 sample_val_2 <= '0';
152 END IF;
175 END IF;
153 END IF;
176 END IF;
154 END PROCESS;
177 END PROCESS;
155 -----------------------------------------------------------------------------
178 -----------------------------------------------------------------------------
156 chirp_1: chirp
179 generators: FOR I IN 0 TO 7 GENERATE
180 gen1: generator
157 GENERIC MAP (
181 GENERIC MAP (
158 LOW_FREQUENCY_LIMIT => 0,
159 HIGH_FREQUENCY_LIMIT => 2000,
160 NB_POINT_TO_GEN => 10000,
161 AMPLITUDE => 100,
182 AMPLITUDE => 100,
162 NB_BITS => 16)
183 NB_BITS => 16)
163 PORT MAP (
184 PORT MAP (
164 clk => clk,
185 clk => clk,
165 rstn => rstn,
186 rstn => rstn,
166 run => '1',
187 run => '1',
167 data_ack => sample_val,
188 data_ack => sample_val,
168 data => data_chirp);
189 offset => offset_gen(I),
169
190 data => signal_gen(I)
170 chirp_2: chirp
191 );
171 GENERIC MAP (
192 offset_gen(I) <= std_logic_vector( to_signed((I*200),16) );
172 LOW_FREQUENCY_LIMIT => 0,
193 END GENERATE generators;
173 HIGH_FREQUENCY_LIMIT => 2000,
194
174 NB_POINT_TO_GEN => 100000,
195 output_splitter: FOR CHAN IN 0 TO 5 GENERATE
175 AMPLITUDE => 200,
196 bits_splitter: FOR BIT IN 0 TO 15 GENERATE
176 NB_BITS => 16)
197 sample_f0(CHAN)(BIT) <= sample_f0_wdata((CHAN*16) + BIT);
177 PORT MAP (
198 sample_f1(CHAN)(BIT) <= sample_f1_wdata((CHAN*16) + BIT);
178 clk => clk,
199 sample_f2(CHAN)(BIT) <= sample_f2_wdata((CHAN*16) + BIT);
179 rstn => rstn,
200 sample_f3(CHAN)(BIT) <= sample_f3_wdata((CHAN*16) + BIT);
180 run => '1',
201 END GENERATE bits_splitter;
181 data_ack => sample_val,
202 END GENERATE output_splitter;
182 data => data_chirp_2);
183
203
184 all_channel: FOR I IN 0 TO 3 GENERATE
185 sample(2*I) <= data_chirp;
186 sample(2*I+1) <= data_chirp_2;
187 END GENERATE all_channel;
188 -----------------------------------------------------------------------------
189
190 all_channel_test: FOR I IN 0 TO 3 GENERATE
191 all_bit_test: FOR J IN 0 TO 15 GENERATE
192 sample_s(2*I ,J) <= data_chirp(J);
193 sample_s(2*I+1,J) <= data_chirp_2(J);
194 END GENERATE all_bit_test;
195 sample_s(2*I,16) <= data_chirp(15);
196 sample_s(2*I,17) <= data_chirp(15);
197 sample_s(2*I+1,16) <= data_chirp_2(15);
198 sample_s(2*I+1,17) <= data_chirp_2(15);
199 END GENERATE all_channel_test;
200
204
201 IIR_CEL_TEST_1: IIR_CEL_TEST
205 sample <= signal_gen;
202 PORT MAP (
203 rstn => rstn,
204 clk => clk,
205 sample_in_val => sample_val,
206 sample_in => sample_s,
207 sample_out_val => sample_out_val,
208 sample_out => sample_out_s);
209
206
210 PROCESS (clk, rstn)
207 -----------------------------------------------------------------------------
211 BEGIN -- PROCESS
208 -- RECORD SIGNALS
212 IF rstn = '0' THEN -- asynchronous reset (active low)
213 all_channel: FOR I IN 0 TO 7 LOOP
214 all_bit: FOR J IN 0 TO 17 LOOP
215 sample_out_s2(I,J) <= '0';
216 END LOOP all_bit;
217 END LOOP all_channel;
218
219 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
220 IF sample_out_val = '1' THEN
221 sample_out_s2 <= sample_out_s;
222 END IF;
223 END IF;
224 END PROCESS;
225 -----------------------------------------------------------------------------
209 -----------------------------------------------------------------------------
226 IIR_CEL_TEST_v3_1: IIR_CEL_TEST_v3
210
227 PORT MAP (
211 process(sample_val)
228 rstn => rstn,
212 variable line_var : line;
229 clk => clk,
213 begin
230 sample_in1_val => sample_val_v3,
214 if sample_val'event and sample_val='1' then
231 sample_in1 => sample_s_v3,
215 write(line_var,integer'image(TSTAMP) );
232 sample_in2_val => sample_val_v3_2,
216 for I IN 0 TO 7 loop
233 sample_in2 => sample_s_v3,
217 write(line_var, " " & integer'image(to_integer(signed(signal_gen(I)))));
234 sample_out1_val => sample_out1_val,
218 end loop;
235 sample_out1 => sample_out1,
219 writeline(log_input,line_var);
236 sample_out2_val => sample_out2_val,
220 end if;
237 sample_out2 => sample_out2);
221 end process;
222
223 process(sample_f0_val)
224 variable line_var : line;
225 begin
226 if sample_f0_val'event and sample_f0_val='1' then
227 write(line_var,integer'image(TSTAMP) );
228 for I IN 0 TO 5 loop
229 write(line_var, " " & integer'image(to_integer(signed(sample_f0(I)))));
230 end loop;
231 writeline(log_output_f0,line_var);
232 end if;
233 end process;
234
235
236 process(sample_f1_val)
237 variable line_var : line;
238 begin
239 if sample_f1_val'event and sample_f1_val='1' then
240 write(line_var,integer'image(TSTAMP) );
241 for I IN 0 TO 5 loop
242 write(line_var, " " & integer'image(to_integer(signed(sample_f1(I)))));
243 end loop;
244 writeline(log_output_f1,line_var);
245 end if;
246 end process;
247
248
249 process(sample_f2_val)
250 variable line_var : line;
251 begin
252 if sample_f2_val'event and sample_f2_val='1' then
253 write(line_var,integer'image(TSTAMP) );
254 for I IN 0 TO 5 loop
255 write(line_var, " " & integer'image(to_integer(signed(sample_f2(I)))));
256 end loop;
257 writeline(log_output_f2,line_var);
258 end if;
259 end process;
260
261 process(sample_f3_val)
262 variable line_var : line;
263 begin
264 if sample_f3_val'event and sample_f3_val='1' then
265 write(line_var,integer'image(TSTAMP) );
266 for I IN 0 TO 5 loop
267 write(line_var, " " & integer'image(to_integer(signed(sample_f3(I)))));
268 end loop;
269 writeline(log_output_f3,line_var);
270 end if;
271 end process;
238
272
239 PROCESS (clk, rstn)
240 BEGIN -- PROCESS
241 IF rstn = '0' THEN -- asynchronous reset (active low)
242
243 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
244 IF sample_val = '1' THEN
245 sample_s_v3 <= sample_s;
246 END IF;
247 sample_val_v3 <= sample_val;
248 sample_val_v3_2 <= sample_val_2;
249
250 IF sample_out1_val = '1' THEN
251 sample_out1_reg <= sample_out1;
252 END IF;
253 IF sample_out2_val = '1' THEN
254 sample_out2_reg <= sample_out2;
255 END IF;
256 END IF;
257
258 END PROCESS;
259
273
260
274
261
275
262 END;
276 END;
Show file before | Show file after | Hide comments
@@ -1,209 +1,209
1 This leon3 design is tailored to the Xilinx SP605 Spartan6 board
1 This leon3 design is tailored to the Xilinx SP605 Spartan6 board
2
2
3 Simulation and synthesis
3 Simulation and synthesis
4 ------------------------
4 ------------------------
5
5
6 The design uses the Xilinx MIG memory interface with an AHB-2.0
6 The design uses the Xilinx MIG memory interface with an AHB-2.0
7 interface. The MIG source code cannot be distributed due to the
7 interface. The MIG source code cannot be distributed due to the
8 prohibitive Xilinx license, so the MIG must be re-generated with
8 prohibitive Xilinx license, so the MIG must be re-generated with
9 coregen before simulation and synthesis can be done.
9 coregen before simulation and synthesis can be done.
10
10
11 To generate the MIG and install tne Xilinx unisim simulation
11 To generate the MIG and install tne Xilinx unisim simulation
12 library, do as follows:
12 library, do as follows:
13
13
14 make mig
14 make mig
15 make install-secureip
15 make install-secureip
16
16
17 This will ONLY work with ISE-13.2 installed, and the XILINX variable
17 This will ONLY work with ISE-13.2 installed, and the XILINX variable
18 properly set in the shell. To synthesize the design, do
18 properly set in the shell. To synthesize the design, do
19
19
20 make ise
20 make ise
21
21
22 and then
22 and then
23
23
24 make ise-prog-fpga
24 make ise-prog-fpga
25
25
26 to program the FPGA.
26 to program the FPGA.
27
27
28 Design specifics
28 Design specifics
29 ----------------
29 ----------------
30
30
31 * System reset is mapped to the CPU RESET button
31 * System reset is mapped to the CPU RESET button
32
32
33 * The AHB and processor is clocked by a 60 MHz clock, generated
33 * The AHB and processor is clocked by a 60 MHz clock, generated
34 from the 33 MHz SYSACE clock using a DCM. You can change the frequency
34 from the 33 MHz SYSACE clock using a DCM. You can change the frequency
35 generation in the clocks menu of xconfig. The DDR3 (MIG) controller
35 generation in the clocks menu of xconfig. The DDR3 (MIG) controller
36 runs at 667 MHz.
36 runs at 667 MHz.
37
37
38 * The GRETH core is enabled and runs without problems at 100 Mbit.
38 * The GRETH core is enabled and runs without problems at 100 Mbit.
39 Ethernet debug link is enabled and has IP 192.168.0.51.
39 Ethernet debug link is enabled and has IP 192.168.0.51.
40 1 Gbit operation is also possible (requires grlib com release),
40 1 Gbit operation is also possible (requires grlib com release),
41 uncomment related timing constraints in the leon3mp.ucf first.
41 uncomment related timing constraints in the leon3mp.ucf first.
42
42
43 * 16-bit flash prom can be read at address 0. It can be programmed
43 * 16-bit flash prom can be read at address 0. It can be programmed
44 with GRMON version 1.1.16 or later.
44 with GRMON version 1.1.16 or later.
45
45
46 * DDR3 is working with the provided Xilinx MIG DDR3 controller.
46 * DDR3 is working with the provided Xilinx MIG DDR3 controller.
47 If you want to simulate this design, first install the secure
47 If you want to simulate this design, first install the secure
48 IP models with:
48 IP models with:
49
49
50 make install-secureip
50 make install-secureip
51
51
52 Then rebuild the scripts and simulation model:
52 Then rebuild the scripts and simulation model:
53
53
54 make distclean vsim
54 make distclean vsim
55
55
56 Modelsim v6.6e or newer is required to build the secure IP models.
56 Modelsim v6.6e or newer is required to build the secure IP models.
57 Note that the regular leon3 test bench cannot be run in simulation
57 Note that the regular leon3 test bench cannot be run in simulation
58 as the DDR3 model lacks data pre-load.
58 as the DDR3 model lacks data pre-load.
59
59
60 * The application UART1 is connected to the USB/UART connector
60 * The application UART1 is connected to the USB/UART connector
61
61
62 * The SVGA frame buffer uses a separate port on the DDR3 controller,
62 * The SVGA frame buffer uses a separate port on the DDR3 controller,
63 and therefore does not noticeably affect the performance of the processor.
63 and therefore does not noticeably affect the performance of the processor.
64 Default output is analog VGA, to switch to DVI mode execute this
64 Default output is analog VGA, to switch to DVI mode execute this
65 command in grmon:
65 command in grmon:
66
66
67 i2c dvi init_l4itx_vga
67 i2c dvi init_l4itx_vga
68
68
69 * The JTAG DSU interface is enabled and accesible via the USB/JTAG port.
69 * The JTAG DSU interface is enabled and accesible via the USB/JTAG port.
70 Start grmon with -xilusb to connect.
70 Start grmon with -xilusb to connect.
71
71
72 * Output from GRMON is:
72 * Output from GRMON is:
73
73
74 $ grmon -xilusb -u
74 $ grmon -xilusb -u
75
75
76 GRMON LEON debug monitor v1.1.51 professional version (debug)
76 GRMON LEON debug monitor v1.1.51 professional version (debug)
77
77
78 Copyright (C) 2004-2011 Aeroflex Gaisler - all rights reserved.
78 Copyright (C) 2004-2011 Aeroflex Gaisler - all rights reserved.
79 For latest updates, go to http://www.gaisler.com/
79 For latest updates, go to http://www.gaisler.com/
80 Comments or bug-reports to support@gaisler.com
80 Comments or bug-reports to support@gaisler.com
81
81
82 Xilinx cable: Cable type/rev : 0x3
82 Xilinx cable: Cable type/rev : 0x3
83 JTAG chain: xc6slx45t xccace
83 JTAG chain: xc6slx45t xccace
84
84
85 GRLIB build version: 4111
85 GRLIB build version: 4111
86
86
87 initialising ...............
87 initialising ...............
88 detected frequency: 50 MHz
88 detected frequency: 50 MHz
89 SRAM waitstates: 1
89 SRAM waitstates: 1
90
90
91 Component Vendor
91 Component Vendor
92 LEON3 SPARC V8 Processor Gaisler Research
92 LEON3 SPARC V8 Processor Gaisler Research
93 AHB Debug JTAG TAP Gaisler Research
93 AHB Debug JTAG TAP Gaisler Research
94 GR Ethernet MAC Gaisler Research
94 GR Ethernet MAC Gaisler Research
95 LEON2 Memory Controller European Space Agency
95 LEON2 Memory Controller European Space Agency
96 AHB/APB Bridge Gaisler Research
96 AHB/APB Bridge Gaisler Research
97 LEON3 Debug Support Unit Gaisler Research
97 LEON3 Debug Support Unit Gaisler Research
98 Xilinx MIG DDR2 controller Gaisler Research
98 Xilinx MIG DDR2 controller Gaisler Research
99 AHB/APB Bridge Gaisler Research
99 AHB/APB Bridge Gaisler Research
100 Generic APB UART Gaisler Research
100 Generic APB UART Gaisler Research
101 Multi-processor Interrupt Ctrl Gaisler Research
101 Multi-processor Interrupt Ctrl Gaisler Research
102 Modular Timer Unit Gaisler Research
102 Modular Timer Unit Gaisler Research
103 SVGA Controller Gaisler Research
103 SVGA Controller Gaisler Research
104 AMBA Wrapper for OC I2C-master Gaisler Research
104 AMBA Wrapper for OC I2C-master Gaisler Research
105 General purpose I/O port Gaisler Research
105 General purpose I/O port Gaisler Research
106 AHB status register Gaisler Research
106 AHB status register Gaisler Research
107
107
108 Use command 'info sys' to print a detailed report of attached cores
108 Use command 'info sys' to print a detailed report of attached cores
109
109
110 grlib> inf sys
110 grlib> inf sys
111 00.01:003 Gaisler Research LEON3 SPARC V8 Processor (ver 0x0)
111 00.01:003 Gaisler Research LEON3 SPARC V8 Processor (ver 0x0)
112 ahb master 0
112 ahb master 0
113 01.01:01c Gaisler Research AHB Debug JTAG TAP (ver 0x1)
113 01.01:01c Gaisler Research AHB Debug JTAG TAP (ver 0x1)
114 ahb master 1
114 ahb master 1
115 02.01:01d Gaisler Research GR Ethernet MAC (ver 0x0)
115 02.01:01d Gaisler Research GR Ethernet MAC (ver 0x0)
116 ahb master 2, irq 12
116 ahb master 2, irq 12
117 apb: 80000e00 - 80000f00
117 apb: 80000e00 - 80000f00
118 Device index: dev0
118 Device index: dev0
119 edcl ip 192.168.1.51, buffer 2 kbyte
119 edcl ip 192.168.1.51, buffer 2 kbyte
120 00.04:00f European Space Agency LEON2 Memory Controller (ver 0x1)
120 00.04:00f European Space Agency LEON2 Memory Controller (ver 0x1)
121 ahb: 00000000 - 20000000
121 ahb: 00000000 - 20000000
122 apb: 80000000 - 80000100
122 apb: 80000000 - 80000100
123 16-bit prom @ 0x00000000
123 16-bit prom @ 0x00000000
124 01.01:006 Gaisler Research AHB/APB Bridge (ver 0x0)
124 01.01:006 Gaisler Research AHB/APB Bridge (ver 0x0)
125 ahb: 80000000 - 80100000
125 ahb: 80000000 - 80100000
126 02.01:004 Gaisler Research LEON3 Debug Support Unit (ver 0x1)
126 02.01:004 Gaisler Research LEON3 Debug Support Unit (ver 0x1)
127 ahb: 90000000 - a0000000
127 ahb: 90000000 - a0000000
128 AHB trace 256 lines, 32-bit bus, stack pointer 0x47fffff0
128 AHB trace 256 lines, 32-bit bus, stack pointer 0x47fffff0
129 CPU#0 win 8, hwbp 2, itrace 256, V8 mul/div, srmmu, lddel 1
129 CPU#0 win 8, hwbp 2, itrace 256, V8 mul/div, srmmu, lddel 1
130 icache 2 * 8 kbyte, 32 byte/line rnd
130 icache 2 * 8 kbyte, 32 byte/line rnd
131 dcache 2 * 4 kbyte, 16 byte/line rnd
131 dcache 2 * 4 kbyte, 16 byte/line rnd
132 04.01:06b Gaisler Research Xilinx MIG DDR2 controller (ver 0x0)
132 04.01:06b Gaisler Research Xilinx MIG DDR2 controller (ver 0x0)
133 ahb: 40000000 - 48000000
133 ahb: 40000000 - 48000000
134 apb: 80100000 - 80100100
134 apb: 80100000 - 80100100
135 DDR2: 128 Mbyte
135 DDR2: 128 Mbyte
136 0d.01:006 Gaisler Research AHB/APB Bridge (ver 0x0)
136 0d.01:006 Gaisler Research AHB/APB Bridge (ver 0x0)
137 ahb: 80100000 - 80200000
137 ahb: 80100000 - 80200000
138 01.01:00c Gaisler Research Generic APB UART (ver 0x1)
138 01.01:00c Gaisler Research Generic APB UART (ver 0x1)
139 irq 2
139 irq 2
140 apb: 80000100 - 80000200
140 apb: 80000100 - 80000200
141 baud rate 38343, DSU mode (FIFO debug)
141 baud rate 38343, DSU mode (FIFO debug)
142 02.01:00d Gaisler Research Multi-processor Interrupt Ctrl (ver 0x3)
142 02.01:00d Gaisler Research Multi-processor Interrupt Ctrl (ver 0x3)
143 apb: 80000200 - 80000300
143 apb: 80000200 - 80000300
144 03.01:011 Gaisler Research Modular Timer Unit (ver 0x0)
144 03.01:011 Gaisler Research Modular Timer Unit (ver 0x0)
145 irq 8
145 irq 8
146 apb: 80000300 - 80000400
146 apb: 80000300 - 80000400
147 8-bit scaler, 2 * 32-bit timers, divisor 50
147 8-bit scaler, 2 * 32-bit timers, divisor 50
148 06.01:063 Gaisler Research SVGA Controller (ver 0x0)
148 06.01:063 Gaisler Research SVGA Controller (ver 0x0)
149 apb: 80000600 - 80000700
149 apb: 80000600 - 80000700
150 clk0: 50.00 MHz
150 clk0: 50.00 MHz
151 09.01:028 Gaisler Research AMBA Wrapper for OC I2C-master (ver 0x3)
151 09.01:028 Gaisler Research AMBA Wrapper for OC I2C-master (ver 0x3)
152 irq 14
152 irq 14
153 apb: 80000900 - 80000a00
153 apb: 80000900 - 80000a00
154 0a.01:01a Gaisler Research General purpose I/O port (ver 0x1)
154 0a.01:01a Gaisler Research General purpose I/O port (ver 0x1)
155 apb: 80000a00 - 80000b00
155 apb: 80000a00 - 80000b00
156 0f.01:052 Gaisler Research AHB status register (ver 0x0)
156 0f.01:052 Gaisler Research AHB status register (ver 0x0)
157 irq 7
157 irq 7
158 apb: 80000f00 - 80001000
158 apb: 80000f00 - 80001000
159 grlib> fla
159 grlib> fla
160
160
161 Intel-style 16-bit flash on D[31:16]
161 Intel-style 16-bit flash on D[31:16]
162
162
163 Manuf. Intel
163 Manuf. Intel
164 Device Strataflash P30
164 Device Strataflash P30
165
165
166 Device ID 02e44603e127ffff
166 Device ID 02e44603e127ffff
167 User ID ffffffffffffffff
167 User ID ffffffffffffffff
168
168
169
169
170 1 x 32 Mbyte = 32 Mbyte total @ 0x00000000
170 1 x 32 Mbyte = 32 Mbyte total @ 0x00000000
171
171
172
172
173 CFI info
173 CFI info
174 flash family : 1
174 flash family : 1
175 flash size : 256 Mbit
175 flash size : 256 Mbit
176 erase regions : 2
176 erase regions : 2
177 erase blocks : 259
177 erase blocks : 259
178 write buffer : 1024 bytes
178 write buffer : 1024 bytes
179 lock-down : yes
179 lock-down : yes
180 region 0 : 255 blocks of 128 Kbytes
180 region 0 : 255 blocks of 128 Kbytes
181 region 1 : 4 blocks of 32 Kbytes
181 region 1 : 4 blocks of 32 Kbytes
182
182
183 grlib> lo ~/ibm/src/bench/leonbench/coremark.exe
183 grlib> lo ~/ibm/src/bench/leonbench/coremark.exe
184 section: .text at 0x40000000, size 102544 bytes
184 section: .text at 0x40000000, size 102544 bytes
185 section: .data at 0x40019090, size 2788 bytes
185 section: .data at 0x40019090, size 2788 bytes
186 total size: 105332 bytes (1.2 Mbit/s)
186 total size: 105332 bytes (1.2 Mbit/s)
187 read 272 symbols
187 read 272 symbols
188 entry point: 0x40000000
188 entry point: 0x40000000
189 grlib> run
189 grlib> run
190 2K performance run parameters for coremark.
190 2K performance run parameters for coremark.
191 CoreMark Size : 666
191 CoreMark Size : 666
192 Total ticks : 19945918
192 Total ticks : 19945918
193 Total time (secs): 19.945918
193 Total time (secs): 19.945918
194 Iterations/Sec : 100.271143
194 Iterations/Sec : 100.271143
195 Iterations : 2000
195 Iterations : 2000
196 Compiler version : GCC4.4.2
196 Compiler version : GCC4.4.2
197 Compiler flags : -O3 -mv8 -funroll-loops -fgcse-sm -combine -DPERFORMANCE_RUN=1 -mcpu=v8 -msoft-float
197 Compiler flags : -O3 -mv8 -funroll-loops -fgcse-sm -combine -DPERFORMANCE_RUN=1 -mcpu=v8 -msoft-float
198 Memory location : STACK
198 Memory location : STACK
199 seedcrc : 0xe9f5
199 seedcrc : 0xe9f5
200 [0]crclist : 0xe714
200 [0]crclist : 0xe714
201 [0]crcmatrix : 0x1fd7
201 [0]crcmatrix : 0x1fd7
202 [0]crcstate : 0x8e3a
202 [0]crcstate : 0x8e3a
203 [0]crcfinal : 0x4983
203 [0]crcfinal : 0x4983
204 Correct operation validated. See readme.txt for run and reporting rules.
204 Correct operation validated. See readme.txt for run and reporting rules.
205 CoreMark 1.0 : 100.271143 / GCC4.4.2 -O3 -mv8 -funroll-loops -fgcse-sm -combine -DPERFORMANCE_RUN=1 -mcpu=v8 -msoft-float / Stack
205 CoreMark 1.0 : 100.271143 / GCC4.4.2 -O3 -mv8 -funroll-loops -fgcse-sm -combine -DPERFORMANCE_RUN=1 -mcpu=v8 -msoft-float / Stack
206
206
207 Program exited normally.
207 Program exited normally.
208 grlib>
208 grlib>
209
209
Show file before | Show file after | Hide comments
@@ -1,190 +1,190
1 -- Technology and synthesis options
1 -- Technology and synthesis options
2 constant CFG_FABTECH : integer := CONFIG_SYN_TECH;
2 constant CFG_FABTECH : integer := CONFIG_SYN_TECH;
3 constant CFG_MEMTECH : integer := CFG_RAM_TECH;
3 constant CFG_MEMTECH : integer := CFG_RAM_TECH;
4 constant CFG_PADTECH : integer := CFG_PAD_TECH;
4 constant CFG_PADTECH : integer := CFG_PAD_TECH;
5 constant CFG_NOASYNC : integer := CONFIG_SYN_NO_ASYNC;
5 constant CFG_NOASYNC : integer := CONFIG_SYN_NO_ASYNC;
6 constant CFG_SCAN : integer := CONFIG_SYN_SCAN;
6 constant CFG_SCAN : integer := CONFIG_SYN_SCAN;
7
7
8 -- Clock generator
8 -- Clock generator
9 constant CFG_CLKTECH : integer := CFG_CLK_TECH;
9 constant CFG_CLKTECH : integer := CFG_CLK_TECH;
10 constant CFG_CLKMUL : integer := CONFIG_CLK_MUL;
10 constant CFG_CLKMUL : integer := CONFIG_CLK_MUL;
11 constant CFG_CLKDIV : integer := CONFIG_CLK_DIV;
11 constant CFG_CLKDIV : integer := CONFIG_CLK_DIV;
12 constant CFG_OCLKDIV : integer := CONFIG_OCLK_DIV;
12 constant CFG_OCLKDIV : integer := CONFIG_OCLK_DIV;
13 constant CFG_OCLKBDIV : integer := CONFIG_OCLKB_DIV;
13 constant CFG_OCLKBDIV : integer := CONFIG_OCLKB_DIV;
14 constant CFG_OCLKCDIV : integer := CONFIG_OCLKC_DIV;
14 constant CFG_OCLKCDIV : integer := CONFIG_OCLKC_DIV;
15 constant CFG_PCIDLL : integer := CONFIG_PCI_CLKDLL;
15 constant CFG_PCIDLL : integer := CONFIG_PCI_CLKDLL;
16 constant CFG_PCISYSCLK: integer := CONFIG_PCI_SYSCLK;
16 constant CFG_PCISYSCLK: integer := CONFIG_PCI_SYSCLK;
17 constant CFG_CLK_NOFB : integer := CONFIG_CLK_NOFB;
17 constant CFG_CLK_NOFB : integer := CONFIG_CLK_NOFB;
18
18
19 -- LEON3 processor core
19 -- LEON3 processor core
20 constant CFG_LEON3 : integer := CONFIG_LEON3;
20 constant CFG_LEON3 : integer := CONFIG_LEON3;
21 constant CFG_NCPU : integer := CONFIG_PROC_NUM;
21 constant CFG_NCPU : integer := CONFIG_PROC_NUM;
22 constant CFG_NWIN : integer := CONFIG_IU_NWINDOWS;
22 constant CFG_NWIN : integer := CONFIG_IU_NWINDOWS;
23 constant CFG_V8 : integer := CFG_IU_V8 + 4*CFG_IU_MUL_STRUCT;
23 constant CFG_V8 : integer := CFG_IU_V8 + 4*CFG_IU_MUL_STRUCT;
24 constant CFG_MAC : integer := CONFIG_IU_MUL_MAC;
24 constant CFG_MAC : integer := CONFIG_IU_MUL_MAC;
25 constant CFG_BP : integer := CONFIG_IU_BP;
25 constant CFG_BP : integer := CONFIG_IU_BP;
26 constant CFG_SVT : integer := CONFIG_IU_SVT;
26 constant CFG_SVT : integer := CONFIG_IU_SVT;
27 constant CFG_RSTADDR : integer := 16#CONFIG_IU_RSTADDR#;
27 constant CFG_RSTADDR : integer := 16#CONFIG_IU_RSTADDR#;
28 constant CFG_LDDEL : integer := CONFIG_IU_LDELAY;
28 constant CFG_LDDEL : integer := CONFIG_IU_LDELAY;
29 constant CFG_NOTAG : integer := CONFIG_NOTAG;
29 constant CFG_NOTAG : integer := CONFIG_NOTAG;
30 constant CFG_NWP : integer := CONFIG_IU_WATCHPOINTS;
30 constant CFG_NWP : integer := CONFIG_IU_WATCHPOINTS;
31 constant CFG_PWD : integer := CONFIG_PWD*2;
31 constant CFG_PWD : integer := CONFIG_PWD*2;
32 constant CFG_FPU : integer := CONFIG_FPU + 16*CONFIG_FPU_NETLIST + 32*CONFIG_FPU_GRFPU_SHARED;
32 constant CFG_FPU : integer := CONFIG_FPU + 16*CONFIG_FPU_NETLIST + 32*CONFIG_FPU_GRFPU_SHARED;
33 constant CFG_GRFPUSH : integer := CONFIG_FPU_GRFPU_SHARED;
33 constant CFG_GRFPUSH : integer := CONFIG_FPU_GRFPU_SHARED;
34 constant CFG_ICEN : integer := CONFIG_ICACHE_ENABLE;
34 constant CFG_ICEN : integer := CONFIG_ICACHE_ENABLE;
35 constant CFG_ISETS : integer := CFG_IU_ISETS;
35 constant CFG_ISETS : integer := CFG_IU_ISETS;
36 constant CFG_ISETSZ : integer := CFG_ICACHE_SZ;
36 constant CFG_ISETSZ : integer := CFG_ICACHE_SZ;
37 constant CFG_ILINE : integer := CFG_ILINE_SZ;
37 constant CFG_ILINE : integer := CFG_ILINE_SZ;
38 constant CFG_IREPL : integer := CFG_ICACHE_ALGORND;
38 constant CFG_IREPL : integer := CFG_ICACHE_ALGORND;
39 constant CFG_ILOCK : integer := CONFIG_ICACHE_LOCK;
39 constant CFG_ILOCK : integer := CONFIG_ICACHE_LOCK;
40 constant CFG_ILRAMEN : integer := CONFIG_ICACHE_LRAM;
40 constant CFG_ILRAMEN : integer := CONFIG_ICACHE_LRAM;
41 constant CFG_ILRAMADDR: integer := 16#CONFIG_ICACHE_LRSTART#;
41 constant CFG_ILRAMADDR: integer := 16#CONFIG_ICACHE_LRSTART#;
42 constant CFG_ILRAMSZ : integer := CFG_ILRAM_SIZE;
42 constant CFG_ILRAMSZ : integer := CFG_ILRAM_SIZE;
43 constant CFG_DCEN : integer := CONFIG_DCACHE_ENABLE;
43 constant CFG_DCEN : integer := CONFIG_DCACHE_ENABLE;
44 constant CFG_DSETS : integer := CFG_IU_DSETS;
44 constant CFG_DSETS : integer := CFG_IU_DSETS;
45 constant CFG_DSETSZ : integer := CFG_DCACHE_SZ;
45 constant CFG_DSETSZ : integer := CFG_DCACHE_SZ;
46 constant CFG_DLINE : integer := CFG_DLINE_SZ;
46 constant CFG_DLINE : integer := CFG_DLINE_SZ;
47 constant CFG_DREPL : integer := CFG_DCACHE_ALGORND;
47 constant CFG_DREPL : integer := CFG_DCACHE_ALGORND;
48 constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK;
48 constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK;
49 constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG;
49 constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG;
50 constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#;
50 constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#;
51 constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM;
51 constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM;
52 constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#;
52 constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#;
53 constant CFG_DLRAMSZ : integer := CFG_DLRAM_SIZE;
53 constant CFG_DLRAMSZ : integer := CFG_DLRAM_SIZE;
54 constant CFG_MMUEN : integer := CONFIG_MMUEN;
54 constant CFG_MMUEN : integer := CONFIG_MMUEN;
55 constant CFG_ITLBNUM : integer := CONFIG_ITLBNUM;
55 constant CFG_ITLBNUM : integer := CONFIG_ITLBNUM;
56 constant CFG_DTLBNUM : integer := CONFIG_DTLBNUM;
56 constant CFG_DTLBNUM : integer := CONFIG_DTLBNUM;
57 constant CFG_TLB_TYPE : integer := CONFIG_TLB_TYPE + CFG_MMU_FASTWB*2;
57 constant CFG_TLB_TYPE : integer := CONFIG_TLB_TYPE + CFG_MMU_FASTWB*2;
58 constant CFG_TLB_REP : integer := CONFIG_TLB_REP;
58 constant CFG_TLB_REP : integer := CONFIG_TLB_REP;
59 constant CFG_MMU_PAGE : integer := CONFIG_MMU_PAGE;
59 constant CFG_MMU_PAGE : integer := CONFIG_MMU_PAGE;
60 constant CFG_DSU : integer := CONFIG_DSU_ENABLE;
60 constant CFG_DSU : integer := CONFIG_DSU_ENABLE;
61 constant CFG_ITBSZ : integer := CFG_DSU_ITB;
61 constant CFG_ITBSZ : integer := CFG_DSU_ITB;
62 constant CFG_ATBSZ : integer := CFG_DSU_ATB;
62 constant CFG_ATBSZ : integer := CFG_DSU_ATB;
63 constant CFG_LEON3FT_EN : integer := CONFIG_LEON3FT_EN;
63 constant CFG_LEON3FT_EN : integer := CONFIG_LEON3FT_EN;
64 constant CFG_IUFT_EN : integer := CONFIG_IUFT_EN;
64 constant CFG_IUFT_EN : integer := CONFIG_IUFT_EN;
65 constant CFG_FPUFT_EN : integer := CONFIG_FPUFT;
65 constant CFG_FPUFT_EN : integer := CONFIG_FPUFT;
66 constant CFG_RF_ERRINJ : integer := CONFIG_RF_ERRINJ;
66 constant CFG_RF_ERRINJ : integer := CONFIG_RF_ERRINJ;
67 constant CFG_CACHE_FT_EN : integer := CONFIG_CACHE_FT_EN;
67 constant CFG_CACHE_FT_EN : integer := CONFIG_CACHE_FT_EN;
68 constant CFG_CACHE_ERRINJ : integer := CONFIG_CACHE_ERRINJ;
68 constant CFG_CACHE_ERRINJ : integer := CONFIG_CACHE_ERRINJ;
69 constant CFG_LEON3_NETLIST: integer := CONFIG_LEON3_NETLIST;
69 constant CFG_LEON3_NETLIST: integer := CONFIG_LEON3_NETLIST;
70 constant CFG_DISAS : integer := CONFIG_IU_DISAS + CONFIG_IU_DISAS_NET;
70 constant CFG_DISAS : integer := CONFIG_IU_DISAS + CONFIG_IU_DISAS_NET;
71 constant CFG_PCLOW : integer := CFG_DEBUG_PC32;
71 constant CFG_PCLOW : integer := CFG_DEBUG_PC32;
72
72
73 -- AMBA settings
73 -- AMBA settings
74 constant CFG_DEFMST : integer := CONFIG_AHB_DEFMST;
74 constant CFG_DEFMST : integer := CONFIG_AHB_DEFMST;
75 constant CFG_RROBIN : integer := CONFIG_AHB_RROBIN;
75 constant CFG_RROBIN : integer := CONFIG_AHB_RROBIN;
76 constant CFG_SPLIT : integer := CONFIG_AHB_SPLIT;
76 constant CFG_SPLIT : integer := CONFIG_AHB_SPLIT;
77 constant CFG_AHBIO : integer := 16#CONFIG_AHB_IOADDR#;
77 constant CFG_AHBIO : integer := 16#CONFIG_AHB_IOADDR#;
78 constant CFG_APBADDR : integer := 16#CONFIG_APB_HADDR#;
78 constant CFG_APBADDR : integer := 16#CONFIG_APB_HADDR#;
79 constant CFG_AHB_MON : integer := CONFIG_AHB_MON;
79 constant CFG_AHB_MON : integer := CONFIG_AHB_MON;
80 constant CFG_AHB_MONERR : integer := CONFIG_AHB_MONERR;
80 constant CFG_AHB_MONERR : integer := CONFIG_AHB_MONERR;
81 constant CFG_AHB_MONWAR : integer := CONFIG_AHB_MONWAR;
81 constant CFG_AHB_MONWAR : integer := CONFIG_AHB_MONWAR;
82 constant CFG_AHB_DTRACE : integer := CONFIG_AHB_DTRACE;
82 constant CFG_AHB_DTRACE : integer := CONFIG_AHB_DTRACE;
83
83
84 -- JTAG based DSU interface
84 -- JTAG based DSU interface
85 constant CFG_AHB_JTAG : integer := CONFIG_DSU_JTAG;
85 constant CFG_AHB_JTAG : integer := CONFIG_DSU_JTAG;
86
86
87 -- Ethernet DSU
87 -- Ethernet DSU
88 constant CFG_DSU_ETH : integer := CONFIG_DSU_ETH + CONFIG_DSU_ETH_PROG + CONFIG_DSU_ETH_DIS;
88 constant CFG_DSU_ETH : integer := CONFIG_DSU_ETH + CONFIG_DSU_ETH_PROG + CONFIG_DSU_ETH_DIS;
89 constant CFG_ETH_BUF : integer := CFG_DSU_ETHB;
89 constant CFG_ETH_BUF : integer := CFG_DSU_ETHB;
90 constant CFG_ETH_IPM : integer := 16#CONFIG_DSU_IPMSB#;
90 constant CFG_ETH_IPM : integer := 16#CONFIG_DSU_IPMSB#;
91 constant CFG_ETH_IPL : integer := 16#CONFIG_DSU_IPLSB#;
91 constant CFG_ETH_IPL : integer := 16#CONFIG_DSU_IPLSB#;
92 constant CFG_ETH_ENM : integer := 16#CONFIG_DSU_ETHMSB#;
92 constant CFG_ETH_ENM : integer := 16#CONFIG_DSU_ETHMSB#;
93 constant CFG_ETH_ENL : integer := 16#CONFIG_DSU_ETHLSB#;
93 constant CFG_ETH_ENL : integer := 16#CONFIG_DSU_ETHLSB#;
94
94
95 -- LEON2 memory controller
95 -- LEON2 memory controller
96 constant CFG_MCTRL_LEON2 : integer := CONFIG_MCTRL_LEON2;
96 constant CFG_MCTRL_LEON2 : integer := CONFIG_MCTRL_LEON2;
97 constant CFG_MCTRL_RAM8BIT : integer := CONFIG_MCTRL_8BIT;
97 constant CFG_MCTRL_RAM8BIT : integer := CONFIG_MCTRL_8BIT;
98 constant CFG_MCTRL_RAM16BIT : integer := CONFIG_MCTRL_16BIT;
98 constant CFG_MCTRL_RAM16BIT : integer := CONFIG_MCTRL_16BIT;
99 constant CFG_MCTRL_5CS : integer := CONFIG_MCTRL_5CS;
99 constant CFG_MCTRL_5CS : integer := CONFIG_MCTRL_5CS;
100 constant CFG_MCTRL_SDEN : integer := CONFIG_MCTRL_SDRAM;
100 constant CFG_MCTRL_SDEN : integer := CONFIG_MCTRL_SDRAM;
101 constant CFG_MCTRL_SEPBUS : integer := CONFIG_MCTRL_SDRAM_SEPBUS;
101 constant CFG_MCTRL_SEPBUS : integer := CONFIG_MCTRL_SDRAM_SEPBUS;
102 constant CFG_MCTRL_INVCLK : integer := CONFIG_MCTRL_SDRAM_INVCLK;
102 constant CFG_MCTRL_INVCLK : integer := CONFIG_MCTRL_SDRAM_INVCLK;
103 constant CFG_MCTRL_SD64 : integer := CONFIG_MCTRL_SDRAM_BUS64;
103 constant CFG_MCTRL_SD64 : integer := CONFIG_MCTRL_SDRAM_BUS64;
104 constant CFG_MCTRL_PAGE : integer := CONFIG_MCTRL_PAGE + CONFIG_MCTRL_PROGPAGE;
104 constant CFG_MCTRL_PAGE : integer := CONFIG_MCTRL_PAGE + CONFIG_MCTRL_PROGPAGE;
105
105
106 -- Xilinx MIG
106 -- Xilinx MIG
107 constant CFG_MIG_DDR2 : integer := CONFIG_MIG_DDR2;
107 constant CFG_MIG_DDR2 : integer := CONFIG_MIG_DDR2;
108 constant CFG_MIG_RANKS : integer := CONFIG_MIG_RANKS;
108 constant CFG_MIG_RANKS : integer := CONFIG_MIG_RANKS;
109 constant CFG_MIG_COLBITS : integer := CONFIG_MIG_COLBITS;
109 constant CFG_MIG_COLBITS : integer := CONFIG_MIG_COLBITS;
110 constant CFG_MIG_ROWBITS : integer := CONFIG_MIG_ROWBITS;
110 constant CFG_MIG_ROWBITS : integer := CONFIG_MIG_ROWBITS;
111 constant CFG_MIG_BANKBITS: integer := CONFIG_MIG_BANKBITS;
111 constant CFG_MIG_BANKBITS: integer := CONFIG_MIG_BANKBITS;
112 constant CFG_MIG_HMASK : integer := 16#CONFIG_MIG_HMASK#;
112 constant CFG_MIG_HMASK : integer := 16#CONFIG_MIG_HMASK#;
113
113
114
114
115 -- AHB status register
115 -- AHB status register
116 constant CFG_AHBSTAT : integer := CONFIG_AHBSTAT_ENABLE;
116 constant CFG_AHBSTAT : integer := CONFIG_AHBSTAT_ENABLE;
117 constant CFG_AHBSTATN : integer := CONFIG_AHBSTAT_NFTSLV;
117 constant CFG_AHBSTATN : integer := CONFIG_AHBSTAT_NFTSLV;
118
118
119 -- AHB ROM
119 -- AHB ROM
120 constant CFG_AHBROMEN : integer := CONFIG_AHBROM_ENABLE;
120 constant CFG_AHBROMEN : integer := CONFIG_AHBROM_ENABLE;
121 constant CFG_AHBROPIP : integer := CONFIG_AHBROM_PIPE;
121 constant CFG_AHBROPIP : integer := CONFIG_AHBROM_PIPE;
122 constant CFG_AHBRODDR : integer := 16#CONFIG_AHBROM_START#;
122 constant CFG_AHBRODDR : integer := 16#CONFIG_AHBROM_START#;
123 constant CFG_ROMADDR : integer := 16#CONFIG_ROM_START#;
123 constant CFG_ROMADDR : integer := 16#CONFIG_ROM_START#;
124 constant CFG_ROMMASK : integer := 16#E00# + 16#CONFIG_ROM_START#;
124 constant CFG_ROMMASK : integer := 16#E00# + 16#CONFIG_ROM_START#;
125
125
126 -- AHB RAM
126 -- AHB RAM
127 constant CFG_AHBRAMEN : integer := CONFIG_AHBRAM_ENABLE;
127 constant CFG_AHBRAMEN : integer := CONFIG_AHBRAM_ENABLE;
128 constant CFG_AHBRSZ : integer := CFG_AHBRAMSZ;
128 constant CFG_AHBRSZ : integer := CFG_AHBRAMSZ;
129 constant CFG_AHBRADDR : integer := 16#CONFIG_AHBRAM_START#;
129 constant CFG_AHBRADDR : integer := 16#CONFIG_AHBRAM_START#;
130
130
131 -- Gaisler Ethernet core
131 -- Gaisler Ethernet core
132 constant CFG_GRETH : integer := CONFIG_GRETH_ENABLE;
132 constant CFG_GRETH : integer := CONFIG_GRETH_ENABLE;
133 constant CFG_GRETH1G : integer := CONFIG_GRETH_GIGA;
133 constant CFG_GRETH1G : integer := CONFIG_GRETH_GIGA;
134 constant CFG_ETH_FIFO : integer := CFG_GRETH_FIFO;
134 constant CFG_ETH_FIFO : integer := CFG_GRETH_FIFO;
135
135
136 -- UART 1
136 -- UART 1
137 constant CFG_UART1_ENABLE : integer := CONFIG_UART1_ENABLE;
137 constant CFG_UART1_ENABLE : integer := CONFIG_UART1_ENABLE;
138 constant CFG_UART1_FIFO : integer := CFG_UA1_FIFO;
138 constant CFG_UART1_FIFO : integer := CFG_UA1_FIFO;
139
139
140 -- LEON3 interrupt controller
140 -- LEON3 interrupt controller
141 constant CFG_IRQ3_ENABLE : integer := CONFIG_IRQ3_ENABLE;
141 constant CFG_IRQ3_ENABLE : integer := CONFIG_IRQ3_ENABLE;
142 constant CFG_IRQ3_NSEC : integer := CONFIG_IRQ3_NSEC;
142 constant CFG_IRQ3_NSEC : integer := CONFIG_IRQ3_NSEC;
143
143
144 -- Modular timer
144 -- Modular timer
145 constant CFG_GPT_ENABLE : integer := CONFIG_GPT_ENABLE;
145 constant CFG_GPT_ENABLE : integer := CONFIG_GPT_ENABLE;
146 constant CFG_GPT_NTIM : integer := CONFIG_GPT_NTIM;
146 constant CFG_GPT_NTIM : integer := CONFIG_GPT_NTIM;
147 constant CFG_GPT_SW : integer := CONFIG_GPT_SW;
147 constant CFG_GPT_SW : integer := CONFIG_GPT_SW;
148 constant CFG_GPT_TW : integer := CONFIG_GPT_TW;
148 constant CFG_GPT_TW : integer := CONFIG_GPT_TW;
149 constant CFG_GPT_IRQ : integer := CONFIG_GPT_IRQ;
149 constant CFG_GPT_IRQ : integer := CONFIG_GPT_IRQ;
150 constant CFG_GPT_SEPIRQ : integer := CONFIG_GPT_SEPIRQ;
150 constant CFG_GPT_SEPIRQ : integer := CONFIG_GPT_SEPIRQ;
151 constant CFG_GPT_WDOGEN : integer := CONFIG_GPT_WDOGEN;
151 constant CFG_GPT_WDOGEN : integer := CONFIG_GPT_WDOGEN;
152 constant CFG_GPT_WDOG : integer := 16#CONFIG_GPT_WDOG#;
152 constant CFG_GPT_WDOG : integer := 16#CONFIG_GPT_WDOG#;
153
153
154 -- GPIO port
154 -- GPIO port
155 constant CFG_GRGPIO_ENABLE : integer := CONFIG_GRGPIO_ENABLE;
155 constant CFG_GRGPIO_ENABLE : integer := CONFIG_GRGPIO_ENABLE;
156 constant CFG_GRGPIO_IMASK : integer := 16#CONFIG_GRGPIO_IMASK#;
156 constant CFG_GRGPIO_IMASK : integer := 16#CONFIG_GRGPIO_IMASK#;
157 constant CFG_GRGPIO_WIDTH : integer := CONFIG_GRGPIO_WIDTH;
157 constant CFG_GRGPIO_WIDTH : integer := CONFIG_GRGPIO_WIDTH;
158
158
159 -- VGA and PS2/ interface
159 -- VGA and PS2/ interface
160 constant CFG_KBD_ENABLE : integer := CONFIG_KBD_ENABLE;
160 constant CFG_KBD_ENABLE : integer := CONFIG_KBD_ENABLE;
161 constant CFG_VGA_ENABLE : integer := CONFIG_VGA_ENABLE;
161 constant CFG_VGA_ENABLE : integer := CONFIG_VGA_ENABLE;
162 constant CFG_SVGA_ENABLE : integer := CONFIG_SVGA_ENABLE;
162 constant CFG_SVGA_ENABLE : integer := CONFIG_SVGA_ENABLE;
163
163
164 -- SPI memory controller
164 -- SPI memory controller
165 constant CFG_SPIMCTRL : integer := CONFIG_SPIMCTRL;
165 constant CFG_SPIMCTRL : integer := CONFIG_SPIMCTRL;
166 constant CFG_SPIMCTRL_SDCARD : integer := CONFIG_SPIMCTRL_SDCARD;
166 constant CFG_SPIMCTRL_SDCARD : integer := CONFIG_SPIMCTRL_SDCARD;
167 constant CFG_SPIMCTRL_READCMD : integer := 16#CONFIG_SPIMCTRL_READCMD#;
167 constant CFG_SPIMCTRL_READCMD : integer := 16#CONFIG_SPIMCTRL_READCMD#;
168 constant CFG_SPIMCTRL_DUMMYBYTE : integer := CONFIG_SPIMCTRL_DUMMYBYTE;
168 constant CFG_SPIMCTRL_DUMMYBYTE : integer := CONFIG_SPIMCTRL_DUMMYBYTE;
169 constant CFG_SPIMCTRL_DUALOUTPUT : integer := CONFIG_SPIMCTRL_DUALOUTPUT;
169 constant CFG_SPIMCTRL_DUALOUTPUT : integer := CONFIG_SPIMCTRL_DUALOUTPUT;
170 constant CFG_SPIMCTRL_SCALER : integer := CONFIG_SPIMCTRL_SCALER;
170 constant CFG_SPIMCTRL_SCALER : integer := CONFIG_SPIMCTRL_SCALER;
171 constant CFG_SPIMCTRL_ASCALER : integer := CONFIG_SPIMCTRL_ASCALER;
171 constant CFG_SPIMCTRL_ASCALER : integer := CONFIG_SPIMCTRL_ASCALER;
172 constant CFG_SPIMCTRL_PWRUPCNT : integer := CONFIG_SPIMCTRL_PWRUPCNT;
172 constant CFG_SPIMCTRL_PWRUPCNT : integer := CONFIG_SPIMCTRL_PWRUPCNT;
173
173
174 -- SPI controller
174 -- SPI controller
175 constant CFG_SPICTRL_ENABLE : integer := CONFIG_SPICTRL_ENABLE;
175 constant CFG_SPICTRL_ENABLE : integer := CONFIG_SPICTRL_ENABLE;
176 constant CFG_SPICTRL_NUM : integer := CONFIG_SPICTRL_NUM;
176 constant CFG_SPICTRL_NUM : integer := CONFIG_SPICTRL_NUM;
177 constant CFG_SPICTRL_SLVS : integer := CONFIG_SPICTRL_SLVS;
177 constant CFG_SPICTRL_SLVS : integer := CONFIG_SPICTRL_SLVS;
178 constant CFG_SPICTRL_FIFO : integer := CONFIG_SPICTRL_FIFO;
178 constant CFG_SPICTRL_FIFO : integer := CONFIG_SPICTRL_FIFO;
179 constant CFG_SPICTRL_SLVREG : integer := CONFIG_SPICTRL_SLVREG;
179 constant CFG_SPICTRL_SLVREG : integer := CONFIG_SPICTRL_SLVREG;
180 constant CFG_SPICTRL_ODMODE : integer := CONFIG_SPICTRL_ODMODE;
180 constant CFG_SPICTRL_ODMODE : integer := CONFIG_SPICTRL_ODMODE;
181 constant CFG_SPICTRL_AM : integer := CONFIG_SPICTRL_AM;
181 constant CFG_SPICTRL_AM : integer := CONFIG_SPICTRL_AM;
182 constant CFG_SPICTRL_ASEL : integer := CONFIG_SPICTRL_ASEL;
182 constant CFG_SPICTRL_ASEL : integer := CONFIG_SPICTRL_ASEL;
183 constant CFG_SPICTRL_TWEN : integer := CONFIG_SPICTRL_TWEN;
183 constant CFG_SPICTRL_TWEN : integer := CONFIG_SPICTRL_TWEN;
184 constant CFG_SPICTRL_MAXWLEN : integer := CONFIG_SPICTRL_MAXWLEN;
184 constant CFG_SPICTRL_MAXWLEN : integer := CONFIG_SPICTRL_MAXWLEN;
185 constant CFG_SPICTRL_SYNCRAM : integer := CONFIG_SPICTRL_SYNCRAM;
185 constant CFG_SPICTRL_SYNCRAM : integer := CONFIG_SPICTRL_SYNCRAM;
186 constant CFG_SPICTRL_FT : integer := CONFIG_SPICTRL_FT;
186 constant CFG_SPICTRL_FT : integer := CONFIG_SPICTRL_FT;
187
187
188 -- GRLIB debugging
188 -- GRLIB debugging
189 constant CFG_DUART : integer := CONFIG_DEBUG_UART;
189 constant CFG_DUART : integer := CONFIG_DEBUG_UART;
190
190
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1 <HTML><HEAD><TITLE>Xilinx System Settings Report</TITLE></HEAD>
1 <HTML><HEAD><TITLE>Xilinx System Settings Report</TITLE></HEAD>
2 <BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
2 <BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
3 <center><big><big><b>System Settings</b></big></big></center><br>
3 <center><big><big><b>System Settings</b></big></big></center><br>
4 <A NAME="Environment Settings"></A>
4 <A NAME="Environment Settings"></A>
5 &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
5 &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
6 <TR ALIGN=CENTER BGCOLOR='#99CCFF'>
6 <TR ALIGN=CENTER BGCOLOR='#99CCFF'>
7 <TD ALIGN=CENTER COLSPAN='5'><B> Environment Settings </B></TD>
7 <TD ALIGN=CENTER COLSPAN='5'><B> Environment Settings </B></TD>
8 </tr>
8 </tr>
9 <tr bgcolor='#ffff99'>
9 <tr bgcolor='#ffff99'>
10 <td><b>Environment Variable</b></td>
10 <td><b>Environment Variable</b></td>
11 <td><b>xst</b></td>
11 <td><b>xst</b></td>
12 <td><b>ngdbuild</b></td>
12 <td><b>ngdbuild</b></td>
13 <td><b>map</b></td>
13 <td><b>map</b></td>
14 <td><b>par</b></td>
14 <td><b>par</b></td>
15 </tr>
15 </tr>
16 <tr>
16 <tr>
17 <td>LD_LIBRARY_PATH</td>
17 <td>LD_LIBRARY_PATH</td>
18 <td>/opt/Xilinx/14.2/ISE_DS/ISE//lib/lin64:<br>/usr/lib64/alliance/lib</td>
18 <td>/opt/Xilinx/14.2/ISE_DS/ISE//lib/lin64:<br>/usr/lib64/alliance/lib</td>
19 <td>/opt/Xilinx/14.2/ISE_DS/ISE//lib/lin64:<br>/usr/lib64/alliance/lib</td>
19 <td>/opt/Xilinx/14.2/ISE_DS/ISE//lib/lin64:<br>/usr/lib64/alliance/lib</td>
20 <td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
20 <td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
21 <td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
21 <td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
22 </tr>
22 </tr>
23 <tr>
23 <tr>
24 <td>PATH</td>
24 <td>PATH</td>
25 <td>/opt/Xilinx/14.2/ISE_DS/ISE//bin/lin64:<br>/usr/lib64/qt-3.3/bin:<br>/usr/kerberos/sbin:<br>/usr/kerberos/bin:<br>/usr/lib64/ccache:<br>/usr/libexec/lightdm:<br>/usr/local/bin:<br>/usr/bin:<br>/bin:<br>/usr/local/sbin:<br>/usr/sbin:<br>/usr/lib64/alliance/bin:<br>/usr/libexec/sdcc:<br>/opt/sparc-elf-4.4.2/bin:<br>/usr/local/MATLAB/R2012b/bin:<br>/opt/gcc-arm-none-eabi-4_7-2012q4/bin:<br>/home/jeandet/.local/bin:<br>/home/jeandet/bin</td>
25 <td>/opt/Xilinx/14.2/ISE_DS/ISE//bin/lin64:<br>/usr/lib64/qt-3.3/bin:<br>/usr/kerberos/sbin:<br>/usr/kerberos/bin:<br>/usr/lib64/ccache:<br>/usr/libexec/lightdm:<br>/usr/local/bin:<br>/usr/bin:<br>/bin:<br>/usr/local/sbin:<br>/usr/sbin:<br>/usr/lib64/alliance/bin:<br>/usr/libexec/sdcc:<br>/opt/sparc-elf-4.4.2/bin:<br>/usr/local/MATLAB/R2012b/bin:<br>/opt/gcc-arm-none-eabi-4_7-2012q4/bin:<br>/home/jeandet/.local/bin:<br>/home/jeandet/bin</td>
26 <td>/opt/Xilinx/14.2/ISE_DS/ISE//bin/lin64:<br>/usr/lib64/qt-3.3/bin:<br>/usr/kerberos/sbin:<br>/usr/kerberos/bin:<br>/usr/lib64/ccache:<br>/usr/libexec/lightdm:<br>/usr/local/bin:<br>/usr/bin:<br>/bin:<br>/usr/local/sbin:<br>/usr/sbin:<br>/usr/lib64/alliance/bin:<br>/usr/libexec/sdcc:<br>/opt/sparc-elf-4.4.2/bin:<br>/usr/local/MATLAB/R2012b/bin:<br>/opt/gcc-arm-none-eabi-4_7-2012q4/bin:<br>/home/jeandet/.local/bin:<br>/home/jeandet/bin</td>
26 <td>/opt/Xilinx/14.2/ISE_DS/ISE//bin/lin64:<br>/usr/lib64/qt-3.3/bin:<br>/usr/kerberos/sbin:<br>/usr/kerberos/bin:<br>/usr/lib64/ccache:<br>/usr/libexec/lightdm:<br>/usr/local/bin:<br>/usr/bin:<br>/bin:<br>/usr/local/sbin:<br>/usr/sbin:<br>/usr/lib64/alliance/bin:<br>/usr/libexec/sdcc:<br>/opt/sparc-elf-4.4.2/bin:<br>/usr/local/MATLAB/R2012b/bin:<br>/opt/gcc-arm-none-eabi-4_7-2012q4/bin:<br>/home/jeandet/.local/bin:<br>/home/jeandet/bin</td>
27 <td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
27 <td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
28 <td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
28 <td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
29 </tr>
29 </tr>
30 <tr>
30 <tr>
31 <td>XILINX</td>
31 <td>XILINX</td>
32 <td>/opt/Xilinx/14.2/ISE_DS/ISE/</td>
32 <td>/opt/Xilinx/14.2/ISE_DS/ISE/</td>
33 <td>/opt/Xilinx/14.2/ISE_DS/ISE/</td>
33 <td>/opt/Xilinx/14.2/ISE_DS/ISE/</td>
34 <td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
34 <td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
35 <td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
35 <td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
36 </tr>
36 </tr>
37 </TABLE>
37 </TABLE>
38 <A NAME="Synthesis Property Settings"></A>
38 <A NAME="Synthesis Property Settings"></A>
39 &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
39 &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
40 <TR ALIGN=CENTER BGCOLOR='#99CCFF'>
40 <TR ALIGN=CENTER BGCOLOR='#99CCFF'>
41 <TD ALIGN=CENTER COLSPAN='4'><B>Synthesis Property Settings </B></TD>
41 <TD ALIGN=CENTER COLSPAN='4'><B>Synthesis Property Settings </B></TD>
42 </tr>
42 </tr>
43 <tr bgcolor='#ffff99'>
43 <tr bgcolor='#ffff99'>
44 <td><b>Switch Name</b></td>
44 <td><b>Switch Name</b></td>
45 <td><b>Property Name</b></td>
45 <td><b>Property Name</b></td>
46 <td><b>Value</b></td>
46 <td><b>Value</b></td>
47 <td><b>Default Value</b></td>
47 <td><b>Default Value</b></td>
48 </tr>
48 </tr>
49 <tr>
49 <tr>
50 <td>-ifn</td>
50 <td>-ifn</td>
51 <td>&nbsp;</td>
51 <td>&nbsp;</td>
52 <td>leon3mp.prj</td>
52 <td>leon3mp.prj</td>
53 <td>&nbsp;</td>
53 <td>&nbsp;</td>
54 </tr>
54 </tr>
55 <tr>
55 <tr>
56 <td>-ofn</td>
56 <td>-ofn</td>
57 <td>&nbsp;</td>
57 <td>&nbsp;</td>
58 <td>leon3mp</td>
58 <td>leon3mp</td>
59 <td>&nbsp;</td>
59 <td>&nbsp;</td>
60 </tr>
60 </tr>
61 <tr>
61 <tr>
62 <td>-ofmt</td>
62 <td>-ofmt</td>
63 <td>&nbsp;</td>
63 <td>&nbsp;</td>
64 <td>NGC</td>
64 <td>NGC</td>
65 <td>NGC</td>
65 <td>NGC</td>
66 </tr>
66 </tr>
67 <tr>
67 <tr>
68 <td>-p</td>
68 <td>-p</td>
69 <td>&nbsp;</td>
69 <td>&nbsp;</td>
70 <td>xc6slx45-3-fgg484</td>
70 <td>xc6slx45-3-fgg484</td>
71 <td>&nbsp;</td>
71 <td>&nbsp;</td>
72 </tr>
72 </tr>
73 <tr>
73 <tr>
74 <td>-top</td>
74 <td>-top</td>
75 <td>&nbsp;</td>
75 <td>&nbsp;</td>
76 <td>leon3mp</td>
76 <td>leon3mp</td>
77 <td>&nbsp;</td>
77 <td>&nbsp;</td>
78 </tr>
78 </tr>
79 <tr>
79 <tr>
80 <td>-opt_mode</td>
80 <td>-opt_mode</td>
81 <td>Optimization Goal</td>
81 <td>Optimization Goal</td>
82 <td>Speed</td>
82 <td>Speed</td>
83 <td>Speed</td>
83 <td>Speed</td>
84 </tr>
84 </tr>
85 <tr>
85 <tr>
86 <td>-opt_level</td>
86 <td>-opt_level</td>
87 <td>Optimization Effort</td>
87 <td>Optimization Effort</td>
88 <td>1</td>
88 <td>1</td>
89 <td>1</td>
89 <td>1</td>
90 </tr>
90 </tr>
91 <tr>
91 <tr>
92 <td>-power</td>
92 <td>-power</td>
93 <td>Power Reduction</td>
93 <td>Power Reduction</td>
94 <td>NO</td>
94 <td>NO</td>
95 <td>No</td>
95 <td>No</td>
96 </tr>
96 </tr>
97 <tr>
97 <tr>
98 <td>-iuc</td>
98 <td>-iuc</td>
99 <td>Use synthesis Constraints File</td>
99 <td>Use synthesis Constraints File</td>
100 <td>NO</td>
100 <td>NO</td>
101 <td>No</td>
101 <td>No</td>
102 </tr>
102 </tr>
103 <tr>
103 <tr>
104 <td>-keep_hierarchy</td>
104 <td>-keep_hierarchy</td>
105 <td>Keep Hierarchy</td>
105 <td>Keep Hierarchy</td>
106 <td>No</td>
106 <td>No</td>
107 <td>No</td>
107 <td>No</td>
108 </tr>
108 </tr>
109 <tr>
109 <tr>
110 <td>-netlist_hierarchy</td>
110 <td>-netlist_hierarchy</td>
111 <td>Netlist Hierarchy</td>
111 <td>Netlist Hierarchy</td>
112 <td>As_Optimized</td>
112 <td>As_Optimized</td>
113 <td>As_Optimized</td>
113 <td>As_Optimized</td>
114 </tr>
114 </tr>
115 <tr>
115 <tr>
116 <td>-rtlview</td>
116 <td>-rtlview</td>
117 <td>Generate RTL Schematic</td>
117 <td>Generate RTL Schematic</td>
118 <td>Yes</td>
118 <td>Yes</td>
119 <td>No</td>
119 <td>No</td>
120 </tr>
120 </tr>
121 <tr>
121 <tr>
122 <td>-glob_opt</td>
122 <td>-glob_opt</td>
123 <td>Global Optimization Goal</td>
123 <td>Global Optimization Goal</td>
124 <td>AllClockNets</td>
124 <td>AllClockNets</td>
125 <td>AllClockNets</td>
125 <td>AllClockNets</td>
126 </tr>
126 </tr>
127 <tr>
127 <tr>
128 <td>-read_cores</td>
128 <td>-read_cores</td>
129 <td>Read Cores</td>
129 <td>Read Cores</td>
130 <td>YES</td>
130 <td>YES</td>
131 <td>Yes</td>
131 <td>Yes</td>
132 </tr>
132 </tr>
133 <tr>
133 <tr>
134 <td>-write_timing_constraints</td>
134 <td>-write_timing_constraints</td>
135 <td>Write Timing Constraints</td>
135 <td>Write Timing Constraints</td>
136 <td>NO</td>
136 <td>NO</td>
137 <td>No</td>
137 <td>No</td>
138 </tr>
138 </tr>
139 <tr>
139 <tr>
140 <td>-cross_clock_analysis</td>
140 <td>-cross_clock_analysis</td>
141 <td>Cross Clock Analysis</td>
141 <td>Cross Clock Analysis</td>
142 <td>NO</td>
142 <td>NO</td>
143 <td>No</td>
143 <td>No</td>
144 </tr>
144 </tr>
145 <tr>
145 <tr>
146 <td>-bus_delimiter</td>
146 <td>-bus_delimiter</td>
147 <td>Bus Delimiter</td>
147 <td>Bus Delimiter</td>
148 <td>()</td>
148 <td>()</td>
149 <td>&lt;&gt;</td>
149 <td>&lt;&gt;</td>
150 </tr>
150 </tr>
151 <tr>
151 <tr>
152 <td>-slice_utilization_ratio</td>
152 <td>-slice_utilization_ratio</td>
153 <td>Slice Utilization Ratio</td>
153 <td>Slice Utilization Ratio</td>
154 <td>100</td>
154 <td>100</td>
155 <td>100</td>
155 <td>100</td>
156 </tr>
156 </tr>
157 <tr>
157 <tr>
158 <td>-bram_utilization_ratio</td>
158 <td>-bram_utilization_ratio</td>
159 <td>BRAM Utilization Ratio</td>
159 <td>BRAM Utilization Ratio</td>
160 <td>100</td>
160 <td>100</td>
161 <td>100</td>
161 <td>100</td>
162 </tr>
162 </tr>
163 <tr>
163 <tr>
164 <td>-dsp_utilization_ratio</td>
164 <td>-dsp_utilization_ratio</td>
165 <td>DSP Utilization Ratio</td>
165 <td>DSP Utilization Ratio</td>
166 <td>100</td>
166 <td>100</td>
167 <td>100</td>
167 <td>100</td>
168 </tr>
168 </tr>
169 <tr>
169 <tr>
170 <td>-reduce_control_sets</td>
170 <td>-reduce_control_sets</td>
171 <td>&nbsp;</td>
171 <td>&nbsp;</td>
172 <td>Auto</td>
172 <td>Auto</td>
173 <td>Auto</td>
173 <td>Auto</td>
174 </tr>
174 </tr>
175 <tr>
175 <tr>
176 <td>-fsm_extract</td>
176 <td>-fsm_extract</td>
177 <td>&nbsp;</td>
177 <td>&nbsp;</td>
178 <td>NO</td>
178 <td>NO</td>
179 <td>Yes</td>
179 <td>Yes</td>
180 </tr>
180 </tr>
181 <tr>
181 <tr>
182 <td>-fsm_style</td>
182 <td>-fsm_style</td>
183 <td>&nbsp;</td>
183 <td>&nbsp;</td>
184 <td>LUT</td>
184 <td>LUT</td>
185 <td>LUT</td>
185 <td>LUT</td>
186 </tr>
186 </tr>
187 <tr>
187 <tr>
188 <td>-ram_extract</td>
188 <td>-ram_extract</td>
189 <td>&nbsp;</td>
189 <td>&nbsp;</td>
190 <td>Yes</td>
190 <td>Yes</td>
191 <td>Yes</td>
191 <td>Yes</td>
192 </tr>
192 </tr>
193 <tr>
193 <tr>
194 <td>-ram_style</td>
194 <td>-ram_style</td>
195 <td>&nbsp;</td>
195 <td>&nbsp;</td>
196 <td>Auto</td>
196 <td>Auto</td>
197 <td>Auto</td>
197 <td>Auto</td>
198 </tr>
198 </tr>
199 <tr>
199 <tr>
200 <td>-rom_extract</td>
200 <td>-rom_extract</td>
201 <td>&nbsp;</td>
201 <td>&nbsp;</td>
202 <td>Yes</td>
202 <td>Yes</td>
203 <td>Yes</td>
203 <td>Yes</td>
204 </tr>
204 </tr>
205 <tr>
205 <tr>
206 <td>-shreg_extract</td>
206 <td>-shreg_extract</td>
207 <td>&nbsp;</td>
207 <td>&nbsp;</td>
208 <td>YES</td>
208 <td>YES</td>
209 <td>Yes</td>
209 <td>Yes</td>
210 </tr>
210 </tr>
211 <tr>
211 <tr>
212 <td>-rom_style</td>
212 <td>-rom_style</td>
213 <td>&nbsp;</td>
213 <td>&nbsp;</td>
214 <td>Auto</td>
214 <td>Auto</td>
215 <td>Auto</td>
215 <td>Auto</td>
216 </tr>
216 </tr>
217 <tr>
217 <tr>
218 <td>-auto_bram_packing</td>
218 <td>-auto_bram_packing</td>
219 <td>&nbsp;</td>
219 <td>&nbsp;</td>
220 <td>NO</td>
220 <td>NO</td>
221 <td>No</td>
221 <td>No</td>
222 </tr>
222 </tr>
223 <tr>
223 <tr>
224 <td>-resource_sharing</td>
224 <td>-resource_sharing</td>
225 <td>&nbsp;</td>
225 <td>&nbsp;</td>
226 <td>YES</td>
226 <td>YES</td>
227 <td>Yes</td>
227 <td>Yes</td>
228 </tr>
228 </tr>
229 <tr>
229 <tr>
230 <td>-async_to_sync</td>
230 <td>-async_to_sync</td>
231 <td>&nbsp;</td>
231 <td>&nbsp;</td>
232 <td>NO</td>
232 <td>NO</td>
233 <td>No</td>
233 <td>No</td>
234 </tr>
234 </tr>
235 <tr>
235 <tr>
236 <td>-use_dsp48</td>
236 <td>-use_dsp48</td>
237 <td>&nbsp;</td>
237 <td>&nbsp;</td>
238 <td>Auto</td>
238 <td>Auto</td>
239 <td>Auto</td>
239 <td>Auto</td>
240 </tr>
240 </tr>
241 <tr>
241 <tr>
242 <td>-iobuf</td>
242 <td>-iobuf</td>
243 <td>&nbsp;</td>
243 <td>&nbsp;</td>
244 <td>YES</td>
244 <td>YES</td>
245 <td>Yes</td>
245 <td>Yes</td>
246 </tr>
246 </tr>
247 <tr>
247 <tr>
248 <td>-max_fanout</td>
248 <td>-max_fanout</td>
249 <td>&nbsp;</td>
249 <td>&nbsp;</td>
250 <td>100000</td>
250 <td>100000</td>
251 <td>100000</td>
251 <td>100000</td>
252 </tr>
252 </tr>
253 <tr>
253 <tr>
254 <td>-bufg</td>
254 <td>-bufg</td>
255 <td>&nbsp;</td>
255 <td>&nbsp;</td>
256 <td>16</td>
256 <td>16</td>
257 <td>16</td>
257 <td>16</td>
258 </tr>
258 </tr>
259 <tr>
259 <tr>
260 <td>-register_duplication</td>
260 <td>-register_duplication</td>
261 <td>&nbsp;</td>
261 <td>&nbsp;</td>
262 <td>YES</td>
262 <td>YES</td>
263 <td>Yes</td>
263 <td>Yes</td>
264 </tr>
264 </tr>
265 <tr>
265 <tr>
266 <td>-register_balancing</td>
266 <td>-register_balancing</td>
267 <td>&nbsp;</td>
267 <td>&nbsp;</td>
268 <td>No</td>
268 <td>No</td>
269 <td>No</td>
269 <td>No</td>
270 </tr>
270 </tr>
271 <tr>
271 <tr>
272 <td>-optimize_primitives</td>
272 <td>-optimize_primitives</td>
273 <td>&nbsp;</td>
273 <td>&nbsp;</td>
274 <td>NO</td>
274 <td>NO</td>
275 <td>No</td>
275 <td>No</td>
276 </tr>
276 </tr>
277 <tr>
277 <tr>
278 <td>-use_clock_enable</td>
278 <td>-use_clock_enable</td>
279 <td>&nbsp;</td>
279 <td>&nbsp;</td>
280 <td>Auto</td>
280 <td>Auto</td>
281 <td>Auto</td>
281 <td>Auto</td>
282 </tr>
282 </tr>
283 <tr>
283 <tr>
284 <td>-use_sync_set</td>
284 <td>-use_sync_set</td>
285 <td>&nbsp;</td>
285 <td>&nbsp;</td>
286 <td>Auto</td>
286 <td>Auto</td>
287 <td>Auto</td>
287 <td>Auto</td>
288 </tr>
288 </tr>
289 <tr>
289 <tr>
290 <td>-use_sync_reset</td>
290 <td>-use_sync_reset</td>
291 <td>&nbsp;</td>
291 <td>&nbsp;</td>
292 <td>Auto</td>
292 <td>Auto</td>
293 <td>Auto</td>
293 <td>Auto</td>
294 </tr>
294 </tr>
295 <tr>
295 <tr>
296 <td>-iob</td>
296 <td>-iob</td>
297 <td>&nbsp;</td>
297 <td>&nbsp;</td>
298 <td>True</td>
298 <td>True</td>
299 <td>Auto</td>
299 <td>Auto</td>
300 </tr>
300 </tr>
301 <tr>
301 <tr>
302 <td>-equivalent_register_removal</td>
302 <td>-equivalent_register_removal</td>
303 <td>&nbsp;</td>
303 <td>&nbsp;</td>
304 <td>YES</td>
304 <td>YES</td>
305 <td>Yes</td>
305 <td>Yes</td>
306 </tr>
306 </tr>
307 <tr>
307 <tr>
308 <td>-slice_utilization_ratio_maxmargin</td>
308 <td>-slice_utilization_ratio_maxmargin</td>
309 <td>&nbsp;</td>
309 <td>&nbsp;</td>
310 <td>5</td>
310 <td>5</td>
311 <td>0</td>
311 <td>0</td>
312 </tr>
312 </tr>
313 </TABLE>
313 </TABLE>
314 <A NAME="Translation Property Settings"></A>
314 <A NAME="Translation Property Settings"></A>
315 &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
315 &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
316 <TR ALIGN=CENTER BGCOLOR='#99CCFF'>
316 <TR ALIGN=CENTER BGCOLOR='#99CCFF'>
317 <TD ALIGN=CENTER COLSPAN='4'><B>Translation Property Settings </B></TD>
317 <TD ALIGN=CENTER COLSPAN='4'><B>Translation Property Settings </B></TD>
318 </tr>
318 </tr>
319 <tr bgcolor='#ffff99'>
319 <tr bgcolor='#ffff99'>
320 <td><b>Switch Name</b></td>
320 <td><b>Switch Name</b></td>
321 <td><b>Property Name</b></td>
321 <td><b>Property Name</b></td>
322 <td><b>Value</b></td>
322 <td><b>Value</b></td>
323 <td><b>Default Value</b></td>
323 <td><b>Default Value</b></td>
324 </tr>
324 </tr>
325 <tr>
325 <tr>
326 <td>-aul</td>
326 <td>-aul</td>
327 <td>Allow Unmatched LOC Constraints</td>
327 <td>Allow Unmatched LOC Constraints</td>
328 <td>true</td>
328 <td>true</td>
329 <td>false</td>
329 <td>false</td>
330 </tr>
330 </tr>
331 <tr>
331 <tr>
332 <td>-intstyle</td>
332 <td>-intstyle</td>
333 <td>&nbsp;</td>
333 <td>&nbsp;</td>
334 <td>ise</td>
334 <td>ise</td>
335 <td>None</td>
335 <td>None</td>
336 </tr>
336 </tr>
337 <tr>
337 <tr>
338 <td>-dd</td>
338 <td>-dd</td>
339 <td>&nbsp;</td>
339 <td>&nbsp;</td>
340 <td>_ngo</td>
340 <td>_ngo</td>
341 <td>None</td>
341 <td>None</td>
342 </tr>
342 </tr>
343 <tr>
343 <tr>
344 <td>-p</td>
344 <td>-p</td>
345 <td>&nbsp;</td>
345 <td>&nbsp;</td>
346 <td>xc6slx45-fgg484-3</td>
346 <td>xc6slx45-fgg484-3</td>
347 <td>None</td>
347 <td>None</td>
348 </tr>
348 </tr>
349 <tr>
349 <tr>
350 <td>-sd</td>
350 <td>-sd</td>
351 <td>Macro Search Path</td>
351 <td>Macro Search Path</td>
352 <td>../../netlists/xilinx/Spartan3</td>
352 <td>../../netlists/xilinx/Spartan3</td>
353 <td>None</td>
353 <td>None</td>
354 </tr>
354 </tr>
355 <tr>
355 <tr>
356 <td>-uc</td>
356 <td>-uc</td>
357 <td>&nbsp;</td>
357 <td>&nbsp;</td>
358 <td>leon3mp.ucf</td>
358 <td>leon3mp.ucf</td>
359 <td>None</td>
359 <td>None</td>
360 </tr>
360 </tr>
361 </TABLE>
361 </TABLE>
362 <A NAME="Operating System Information"></A>
362 <A NAME="Operating System Information"></A>
363 &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
363 &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
364 <TR ALIGN=CENTER BGCOLOR='#99CCFF'>
364 <TR ALIGN=CENTER BGCOLOR='#99CCFF'>
365 <TD ALIGN=CENTER COLSPAN='5'><B> Operating System Information </B></TD>
365 <TD ALIGN=CENTER COLSPAN='5'><B> Operating System Information </B></TD>
366 </tr>
366 </tr>
367 <tr bgcolor='#ffff99'>
367 <tr bgcolor='#ffff99'>
368 <td><b>Operating System Information</b></td>
368 <td><b>Operating System Information</b></td>
369 <td><b>xst</b></td>
369 <td><b>xst</b></td>
370 <td><b>ngdbuild</b></td>
370 <td><b>ngdbuild</b></td>
371 <td><b>map</b></td>
371 <td><b>map</b></td>
372 <td><b>par</b></td>
372 <td><b>par</b></td>
373 </tr>
373 </tr>
374 <tr>
374 <tr>
375 <td>CPU Architecture/Speed</td>
375 <td>CPU Architecture/Speed</td>
376 <td>Intel(R) Core(TM) i5-2557M CPU @ 1.70GHz/1701.000 MHz</td>
376 <td>Intel(R) Core(TM) i5-2557M CPU @ 1.70GHz/1701.000 MHz</td>
377 <td>Intel(R) Core(TM) i5-2557M CPU @ 1.70GHz/800.000 MHz</td>
377 <td>Intel(R) Core(TM) i5-2557M CPU @ 1.70GHz/800.000 MHz</td>
378 <td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
378 <td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
379 <td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
379 <td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
380 </tr>
380 </tr>
381 <tr>
381 <tr>
382 <td>Host</td>
382 <td>Host</td>
383 <td>pc-de-jeandet3.lab-lpp.local</td>
383 <td>pc-de-jeandet3.lab-lpp.local</td>
384 <td>pc-de-jeandet3.lab-lpp.local</td>
384 <td>pc-de-jeandet3.lab-lpp.local</td>
385 <td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
385 <td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
386 <td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
386 <td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
387 </tr>
387 </tr>
388 <tr>
388 <tr>
389 <td>OS Name</td>
389 <td>OS Name</td>
390 <td>Fedora</td>
390 <td>Fedora</td>
391 <td>Fedora</td>
391 <td>Fedora</td>
392 <td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
392 <td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
393 <td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
393 <td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
394 </tr>
394 </tr>
395 <tr>
395 <tr>
396 <td>OS Release</td>
396 <td>OS Release</td>
397 <td>Fedora release 18 (Spherical Cow)</td>
397 <td>Fedora release 18 (Spherical Cow)</td>
398 <td>Fedora release 18 (Spherical Cow)</td>
398 <td>Fedora release 18 (Spherical Cow)</td>
399 <td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
399 <td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
400 <td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
400 <td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
401 </tr>
401 </tr>
402 </TABLE>
402 </TABLE>
403 </BODY> </HTML> No newline at end of file
403 </BODY> </HTML>
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@@ -1,10 +1,10
1 #define MCFG1 0x10380033
1 #define MCFG1 0x10380033
2 #define MCFG2 0xe6B86e60
2 #define MCFG2 0xe6B86e60
3 #define MCFG3 0x000ff000
3 #define MCFG3 0x000ff000
4 #define ASDCFG 0x80000000
4 #define ASDCFG 0x80000000
5 #define DSDCFG 0xe6A06e60
5 #define DSDCFG 0xe6A06e60
6 #define L2MCTRLIO 0x80000000
6 #define L2MCTRLIO 0x80000000
7 #define IRQCTRL 0x80000200
7 #define IRQCTRL 0x80000200
8 #define RAMSTART 0x40000000
8 #define RAMSTART 0x40000000
9 #define RAMSIZE 0x00100000
9 #define RAMSIZE 0x00100000
10
10
Show file before | Show file after | Hide comments
@@ -1,13 +1,13
1
1
2 SPARTAN6 50 MHz, MIG DDR2, 2x8 + 2x4 cache, GRFPU
2 SPARTAN6 50 MHz, MIG DDR2, 2x8 + 2x4 cache, GRFPU
3
3
4 LEON3 LEON3FTV2
4 LEON3 LEON3FTV2
5 Dhrystone 78.4 78.4
5 Dhrystone 78.4 78.4
6 Whetstone DP 27.7 27.7
6 Whetstone DP 27.7 27.7
7 gzip 43.98 s 41.38 s
7 gzip 43.98 s 41.38 s
8 bzip2 248.22 s 200.10 s
8 bzip2 248.22 s 200.10 s
9 176.gcc 208.62 s 180.48 s
9 176.gcc 208.62 s 180.48 s
10 coremark 100.12 i/s 100.12 i/s
10 coremark 100.12 i/s 100.12 i/s
11 aocs_v8 12388.7 i/s 12388.7 i/s
11 aocs_v8 12388.7 i/s 12388.7 i/s
12 basicmath_large 13245.0 i/s 13245.0 i/s
12 basicmath_large 13245.0 i/s 13245.0 i/s
13 linpack_unroll_dp_v8 3265 KFLOPS 3563 KFLOPS
13 linpack_unroll_dp_v8 3265 KFLOPS 3563 KFLOPS
Show file before | Show file after | Hide comments
@@ -1,18 +1,18
1
1
2 main()
2 main()
3
3
4 {
4 {
5 report_start();
5 report_start();
6
6
7
7
8 // svgactrl_test(0x80000600, 1, 0, 0x40200000, -1, 0, 0);
8 // svgactrl_test(0x80000600, 1, 0, 0x40200000, -1, 0, 0);
9 base_test();
9 base_test();
10 /*
10 /*
11 greth_test(0x80000e00);
11 greth_test(0x80000e00);
12 spw_test(0x80100A00);
12 spw_test(0x80100A00);
13 spw_test(0x80100B00);
13 spw_test(0x80100B00);
14 spw_test(0x80100C00);
14 spw_test(0x80100C00);
15 svgactrl_test(0x80000600, 1, 0, 0x40200000, -1, 0, 0);
15 svgactrl_test(0x80000600, 1, 0, 0x40200000, -1, 0, 0);
16 */
16 */
17 report_end();
17 report_end();
18 }
18 }
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This diff has been collapsed as it changes many lines, (2102 lines changed) Show them Hide them
@@ -1,1051 +1,1051
1 #if defined CONFIG_SYN_INFERRED
1 #if defined CONFIG_SYN_INFERRED
2 #define CONFIG_SYN_TECH inferred
2 #define CONFIG_SYN_TECH inferred
3 #elif defined CONFIG_SYN_UMC
3 #elif defined CONFIG_SYN_UMC
4 #define CONFIG_SYN_TECH umc
4 #define CONFIG_SYN_TECH umc
5 #elif defined CONFIG_SYN_RHUMC
5 #elif defined CONFIG_SYN_RHUMC
6 #define CONFIG_SYN_TECH rhumc
6 #define CONFIG_SYN_TECH rhumc
7 #elif defined CONFIG_SYN_ATC18
7 #elif defined CONFIG_SYN_ATC18
8 #define CONFIG_SYN_TECH atc18s
8 #define CONFIG_SYN_TECH atc18s
9 #elif defined CONFIG_SYN_ATC18RHA
9 #elif defined CONFIG_SYN_ATC18RHA
10 #define CONFIG_SYN_TECH atc18rha
10 #define CONFIG_SYN_TECH atc18rha
11 #elif defined CONFIG_SYN_AXCEL
11 #elif defined CONFIG_SYN_AXCEL
12 #define CONFIG_SYN_TECH axcel
12 #define CONFIG_SYN_TECH axcel
13 #elif defined CONFIG_SYN_AXDSP
13 #elif defined CONFIG_SYN_AXDSP
14 #define CONFIG_SYN_TECH axdsp
14 #define CONFIG_SYN_TECH axdsp
15 #elif defined CONFIG_SYN_PROASICPLUS
15 #elif defined CONFIG_SYN_PROASICPLUS
16 #define CONFIG_SYN_TECH proasic
16 #define CONFIG_SYN_TECH proasic
17 #elif defined CONFIG_SYN_ALTERA
17 #elif defined CONFIG_SYN_ALTERA
18 #define CONFIG_SYN_TECH altera
18 #define CONFIG_SYN_TECH altera
19 #elif defined CONFIG_SYN_STRATIX
19 #elif defined CONFIG_SYN_STRATIX
20 #define CONFIG_SYN_TECH stratix1
20 #define CONFIG_SYN_TECH stratix1
21 #elif defined CONFIG_SYN_STRATIXII
21 #elif defined CONFIG_SYN_STRATIXII
22 #define CONFIG_SYN_TECH stratix2
22 #define CONFIG_SYN_TECH stratix2
23 #elif defined CONFIG_SYN_STRATIXIII
23 #elif defined CONFIG_SYN_STRATIXIII
24 #define CONFIG_SYN_TECH stratix3
24 #define CONFIG_SYN_TECH stratix3
25 #elif defined CONFIG_SYN_CYCLONEIII
25 #elif defined CONFIG_SYN_CYCLONEIII
26 #define CONFIG_SYN_TECH cyclone3
26 #define CONFIG_SYN_TECH cyclone3
27 #elif defined CONFIG_SYN_EASIC45
27 #elif defined CONFIG_SYN_EASIC45
28 #define CONFIG_SYN_TECH easic45
28 #define CONFIG_SYN_TECH easic45
29 #elif defined CONFIG_SYN_EASIC90
29 #elif defined CONFIG_SYN_EASIC90
30 #define CONFIG_SYN_TECH easic90
30 #define CONFIG_SYN_TECH easic90
31 #elif defined CONFIG_SYN_IHP25
31 #elif defined CONFIG_SYN_IHP25
32 #define CONFIG_SYN_TECH ihp25
32 #define CONFIG_SYN_TECH ihp25
33 #elif defined CONFIG_SYN_IHP25RH
33 #elif defined CONFIG_SYN_IHP25RH
34 #define CONFIG_SYN_TECH ihp25rh
34 #define CONFIG_SYN_TECH ihp25rh
35 #elif defined CONFIG_SYN_CMOS9SF
35 #elif defined CONFIG_SYN_CMOS9SF
36 #define CONFIG_SYN_TECH cmos9sf
36 #define CONFIG_SYN_TECH cmos9sf
37 #elif defined CONFIG_SYN_LATTICE
37 #elif defined CONFIG_SYN_LATTICE
38 #define CONFIG_SYN_TECH lattice
38 #define CONFIG_SYN_TECH lattice
39 #elif defined CONFIG_SYN_ECLIPSE
39 #elif defined CONFIG_SYN_ECLIPSE
40 #define CONFIG_SYN_TECH eclipse
40 #define CONFIG_SYN_TECH eclipse
41 #elif defined CONFIG_SYN_PEREGRINE
41 #elif defined CONFIG_SYN_PEREGRINE
42 #define CONFIG_SYN_TECH peregrine
42 #define CONFIG_SYN_TECH peregrine
43 #elif defined CONFIG_SYN_PROASIC
43 #elif defined CONFIG_SYN_PROASIC
44 #define CONFIG_SYN_TECH proasic
44 #define CONFIG_SYN_TECH proasic
45 #elif defined CONFIG_SYN_PROASIC3
45 #elif defined CONFIG_SYN_PROASIC3
46 #define CONFIG_SYN_TECH apa3
46 #define CONFIG_SYN_TECH apa3
47 #elif defined CONFIG_SYN_PROASIC3E
47 #elif defined CONFIG_SYN_PROASIC3E
48 #define CONFIG_SYN_TECH apa3e
48 #define CONFIG_SYN_TECH apa3e
49 #elif defined CONFIG_SYN_PROASIC3L
49 #elif defined CONFIG_SYN_PROASIC3L
50 #define CONFIG_SYN_TECH apa3l
50 #define CONFIG_SYN_TECH apa3l
51 #elif defined CONFIG_SYN_IGLOO
51 #elif defined CONFIG_SYN_IGLOO
52 #define CONFIG_SYN_TECH apa3
52 #define CONFIG_SYN_TECH apa3
53 #elif defined CONFIG_SYN_FUSION
53 #elif defined CONFIG_SYN_FUSION
54 #define CONFIG_SYN_TECH actfus
54 #define CONFIG_SYN_TECH actfus
55 #elif defined CONFIG_SYN_SPARTAN2
55 #elif defined CONFIG_SYN_SPARTAN2
56 #define CONFIG_SYN_TECH virtex
56 #define CONFIG_SYN_TECH virtex
57 #elif defined CONFIG_SYN_VIRTEX
57 #elif defined CONFIG_SYN_VIRTEX
58 #define CONFIG_SYN_TECH virtex
58 #define CONFIG_SYN_TECH virtex
59 #elif defined CONFIG_SYN_VIRTEXE
59 #elif defined CONFIG_SYN_VIRTEXE
60 #define CONFIG_SYN_TECH virtex
60 #define CONFIG_SYN_TECH virtex
61 #elif defined CONFIG_SYN_SPARTAN3
61 #elif defined CONFIG_SYN_SPARTAN3
62 #define CONFIG_SYN_TECH spartan3
62 #define CONFIG_SYN_TECH spartan3
63 #elif defined CONFIG_SYN_SPARTAN3E
63 #elif defined CONFIG_SYN_SPARTAN3E
64 #define CONFIG_SYN_TECH spartan3e
64 #define CONFIG_SYN_TECH spartan3e
65 #elif defined CONFIG_SYN_SPARTAN6
65 #elif defined CONFIG_SYN_SPARTAN6
66 #define CONFIG_SYN_TECH spartan6
66 #define CONFIG_SYN_TECH spartan6
67 #elif defined CONFIG_SYN_VIRTEX2
67 #elif defined CONFIG_SYN_VIRTEX2
68 #define CONFIG_SYN_TECH virtex2
68 #define CONFIG_SYN_TECH virtex2
69 #elif defined CONFIG_SYN_VIRTEX4
69 #elif defined CONFIG_SYN_VIRTEX4
70 #define CONFIG_SYN_TECH virtex4
70 #define CONFIG_SYN_TECH virtex4
71 #elif defined CONFIG_SYN_VIRTEX5
71 #elif defined CONFIG_SYN_VIRTEX5
72 #define CONFIG_SYN_TECH virtex5
72 #define CONFIG_SYN_TECH virtex5
73 #elif defined CONFIG_SYN_VIRTEX6
73 #elif defined CONFIG_SYN_VIRTEX6
74 #define CONFIG_SYN_TECH virtex6
74 #define CONFIG_SYN_TECH virtex6
75 #elif defined CONFIG_SYN_RH_LIB18T
75 #elif defined CONFIG_SYN_RH_LIB18T
76 #define CONFIG_SYN_TECH rhlib18t
76 #define CONFIG_SYN_TECH rhlib18t
77 #elif defined CONFIG_SYN_SMIC13
77 #elif defined CONFIG_SYN_SMIC13
78 #define CONFIG_SYN_TECH smic013
78 #define CONFIG_SYN_TECH smic013
79 #elif defined CONFIG_SYN_UT025CRH
79 #elif defined CONFIG_SYN_UT025CRH
80 #define CONFIG_SYN_TECH ut25
80 #define CONFIG_SYN_TECH ut25
81 #elif defined CONFIG_SYN_UT130HBD
81 #elif defined CONFIG_SYN_UT130HBD
82 #define CONFIG_SYN_TECH ut130
82 #define CONFIG_SYN_TECH ut130
83 #elif defined CONFIG_SYN_UT90NHBD
83 #elif defined CONFIG_SYN_UT90NHBD
84 #define CONFIG_SYN_TECH ut90
84 #define CONFIG_SYN_TECH ut90
85 #elif defined CONFIG_SYN_TSMC90
85 #elif defined CONFIG_SYN_TSMC90
86 #define CONFIG_SYN_TECH tsmc90
86 #define CONFIG_SYN_TECH tsmc90
87 #elif defined CONFIG_SYN_TM65GPLUS
87 #elif defined CONFIG_SYN_TM65GPLUS
88 #define CONFIG_SYN_TECH tm65gpl
88 #define CONFIG_SYN_TECH tm65gpl
89 #elif defined CONFIG_SYN_CUSTOM1
89 #elif defined CONFIG_SYN_CUSTOM1
90 #define CONFIG_SYN_TECH custom1
90 #define CONFIG_SYN_TECH custom1
91 #else
91 #else
92 #error "unknown target technology"
92 #error "unknown target technology"
93 #endif
93 #endif
94
94
95 #if defined CONFIG_SYN_INFER_RAM
95 #if defined CONFIG_SYN_INFER_RAM
96 #define CFG_RAM_TECH inferred
96 #define CFG_RAM_TECH inferred
97 #elif defined CONFIG_MEM_UMC
97 #elif defined CONFIG_MEM_UMC
98 #define CFG_RAM_TECH umc
98 #define CFG_RAM_TECH umc
99 #elif defined CONFIG_MEM_RHUMC
99 #elif defined CONFIG_MEM_RHUMC
100 #define CFG_RAM_TECH rhumc
100 #define CFG_RAM_TECH rhumc
101 #elif defined CONFIG_MEM_VIRAGE
101 #elif defined CONFIG_MEM_VIRAGE
102 #define CFG_RAM_TECH memvirage
102 #define CFG_RAM_TECH memvirage
103 #elif defined CONFIG_MEM_ARTISAN
103 #elif defined CONFIG_MEM_ARTISAN
104 #define CFG_RAM_TECH memartisan
104 #define CFG_RAM_TECH memartisan
105 #elif defined CONFIG_MEM_CUSTOM1
105 #elif defined CONFIG_MEM_CUSTOM1
106 #define CFG_RAM_TECH custom1
106 #define CFG_RAM_TECH custom1
107 #elif defined CONFIG_MEM_VIRAGE90
107 #elif defined CONFIG_MEM_VIRAGE90
108 #define CFG_RAM_TECH memvirage90
108 #define CFG_RAM_TECH memvirage90
109 #elif defined CONFIG_MEM_INFERRED
109 #elif defined CONFIG_MEM_INFERRED
110 #define CFG_RAM_TECH inferred
110 #define CFG_RAM_TECH inferred
111 #else
111 #else
112 #define CFG_RAM_TECH CONFIG_SYN_TECH
112 #define CFG_RAM_TECH CONFIG_SYN_TECH
113 #endif
113 #endif
114
114
115 #if defined CONFIG_SYN_INFER_PADS
115 #if defined CONFIG_SYN_INFER_PADS
116 #define CFG_PAD_TECH inferred
116 #define CFG_PAD_TECH inferred
117 #else
117 #else
118 #define CFG_PAD_TECH CONFIG_SYN_TECH
118 #define CFG_PAD_TECH CONFIG_SYN_TECH
119 #endif
119 #endif
120
120
121 #ifndef CONFIG_SYN_NO_ASYNC
121 #ifndef CONFIG_SYN_NO_ASYNC
122 #define CONFIG_SYN_NO_ASYNC 0
122 #define CONFIG_SYN_NO_ASYNC 0
123 #endif
123 #endif
124
124
125 #ifndef CONFIG_SYN_SCAN
125 #ifndef CONFIG_SYN_SCAN
126 #define CONFIG_SYN_SCAN 0
126 #define CONFIG_SYN_SCAN 0
127 #endif
127 #endif
128
128
129
129
130 #if defined CONFIG_CLK_ALTDLL
130 #if defined CONFIG_CLK_ALTDLL
131 #define CFG_CLK_TECH CONFIG_SYN_TECH
131 #define CFG_CLK_TECH CONFIG_SYN_TECH
132 #elif defined CONFIG_CLK_HCLKBUF
132 #elif defined CONFIG_CLK_HCLKBUF
133 #define CFG_CLK_TECH axcel
133 #define CFG_CLK_TECH axcel
134 #elif defined CONFIG_CLK_LATDLL
134 #elif defined CONFIG_CLK_LATDLL
135 #define CFG_CLK_TECH lattice
135 #define CFG_CLK_TECH lattice
136 #elif defined CONFIG_CLK_PRO3PLL
136 #elif defined CONFIG_CLK_PRO3PLL
137 #define CFG_CLK_TECH apa3
137 #define CFG_CLK_TECH apa3
138 #elif defined CONFIG_CLK_PRO3EPLL
138 #elif defined CONFIG_CLK_PRO3EPLL
139 #define CFG_CLK_TECH apa3e
139 #define CFG_CLK_TECH apa3e
140 #elif defined CONFIG_CLK_PRO3LPLL
140 #elif defined CONFIG_CLK_PRO3LPLL
141 #define CFG_CLK_TECH apa3l
141 #define CFG_CLK_TECH apa3l
142 #elif defined CONFIG_CLK_FUSPLL
142 #elif defined CONFIG_CLK_FUSPLL
143 #define CFG_CLK_TECH actfus
143 #define CFG_CLK_TECH actfus
144 #elif defined CONFIG_CLK_CLKDLL
144 #elif defined CONFIG_CLK_CLKDLL
145 #define CFG_CLK_TECH virtex
145 #define CFG_CLK_TECH virtex
146 #elif defined CONFIG_CLK_DCM
146 #elif defined CONFIG_CLK_DCM
147 #define CFG_CLK_TECH CONFIG_SYN_TECH
147 #define CFG_CLK_TECH CONFIG_SYN_TECH
148 #elif defined CONFIG_CLK_LIB18T
148 #elif defined CONFIG_CLK_LIB18T
149 #define CFG_CLK_TECH rhlib18t
149 #define CFG_CLK_TECH rhlib18t
150 #elif defined CONFIG_CLK_RHUMC
150 #elif defined CONFIG_CLK_RHUMC
151 #define CFG_CLK_TECH rhumc
151 #define CFG_CLK_TECH rhumc
152 #elif defined CONFIG_CLK_UT130HBD
152 #elif defined CONFIG_CLK_UT130HBD
153 #define CFG_CLK_TECH ut130
153 #define CFG_CLK_TECH ut130
154 #else
154 #else
155 #define CFG_CLK_TECH inferred
155 #define CFG_CLK_TECH inferred
156 #endif
156 #endif
157
157
158 #ifndef CONFIG_CLK_MUL
158 #ifndef CONFIG_CLK_MUL
159 #define CONFIG_CLK_MUL 2
159 #define CONFIG_CLK_MUL 2
160 #endif
160 #endif
161
161
162 #ifndef CONFIG_CLK_DIV
162 #ifndef CONFIG_CLK_DIV
163 #define CONFIG_CLK_DIV 2
163 #define CONFIG_CLK_DIV 2
164 #endif
164 #endif
165
165
166 #ifndef CONFIG_OCLK_DIV
166 #ifndef CONFIG_OCLK_DIV
167 #define CONFIG_OCLK_DIV 1
167 #define CONFIG_OCLK_DIV 1
168 #endif
168 #endif
169
169
170 #ifndef CONFIG_OCLKB_DIV
170 #ifndef CONFIG_OCLKB_DIV
171 #define CONFIG_OCLKB_DIV 0
171 #define CONFIG_OCLKB_DIV 0
172 #endif
172 #endif
173
173
174 #ifndef CONFIG_OCLKC_DIV
174 #ifndef CONFIG_OCLKC_DIV
175 #define CONFIG_OCLKC_DIV 0
175 #define CONFIG_OCLKC_DIV 0
176 #endif
176 #endif
177
177
178 #ifndef CONFIG_PCI_CLKDLL
178 #ifndef CONFIG_PCI_CLKDLL
179 #define CONFIG_PCI_CLKDLL 0
179 #define CONFIG_PCI_CLKDLL 0
180 #endif
180 #endif
181
181
182 #ifndef CONFIG_PCI_SYSCLK
182 #ifndef CONFIG_PCI_SYSCLK
183 #define CONFIG_PCI_SYSCLK 0
183 #define CONFIG_PCI_SYSCLK 0
184 #endif
184 #endif
185
185
186 #ifndef CONFIG_CLK_NOFB
186 #ifndef CONFIG_CLK_NOFB
187 #define CONFIG_CLK_NOFB 0
187 #define CONFIG_CLK_NOFB 0
188 #endif
188 #endif
189 #ifndef CONFIG_LEON3
189 #ifndef CONFIG_LEON3
190 #define CONFIG_LEON3 0
190 #define CONFIG_LEON3 0
191 #endif
191 #endif
192
192
193 #ifndef CONFIG_PROC_NUM
193 #ifndef CONFIG_PROC_NUM
194 #define CONFIG_PROC_NUM 1
194 #define CONFIG_PROC_NUM 1
195 #endif
195 #endif
196
196
197 #ifndef CONFIG_IU_NWINDOWS
197 #ifndef CONFIG_IU_NWINDOWS
198 #define CONFIG_IU_NWINDOWS 8
198 #define CONFIG_IU_NWINDOWS 8
199 #endif
199 #endif
200
200
201 #ifndef CONFIG_IU_RSTADDR
201 #ifndef CONFIG_IU_RSTADDR
202 #define CONFIG_IU_RSTADDR 8
202 #define CONFIG_IU_RSTADDR 8
203 #endif
203 #endif
204
204
205 #ifndef CONFIG_IU_LDELAY
205 #ifndef CONFIG_IU_LDELAY
206 #define CONFIG_IU_LDELAY 1
206 #define CONFIG_IU_LDELAY 1
207 #endif
207 #endif
208
208
209 #ifndef CONFIG_IU_WATCHPOINTS
209 #ifndef CONFIG_IU_WATCHPOINTS
210 #define CONFIG_IU_WATCHPOINTS 0
210 #define CONFIG_IU_WATCHPOINTS 0
211 #endif
211 #endif
212
212
213 #ifdef CONFIG_IU_V8MULDIV
213 #ifdef CONFIG_IU_V8MULDIV
214 #ifdef CONFIG_IU_MUL_LATENCY_4
214 #ifdef CONFIG_IU_MUL_LATENCY_4
215 #define CFG_IU_V8 1
215 #define CFG_IU_V8 1
216 #elif defined CONFIG_IU_MUL_LATENCY_5
216 #elif defined CONFIG_IU_MUL_LATENCY_5
217 #define CFG_IU_V8 2
217 #define CFG_IU_V8 2
218 #elif defined CONFIG_IU_MUL_LATENCY_2
218 #elif defined CONFIG_IU_MUL_LATENCY_2
219 #define CFG_IU_V8 16#32#
219 #define CFG_IU_V8 16#32#
220 #endif
220 #endif
221 #else
221 #else
222 #define CFG_IU_V8 0
222 #define CFG_IU_V8 0
223 #endif
223 #endif
224
224
225 #ifdef CONFIG_IU_MUL_MODGEN
225 #ifdef CONFIG_IU_MUL_MODGEN
226 #define CFG_IU_MUL_STRUCT 1
226 #define CFG_IU_MUL_STRUCT 1
227 #elif defined CONFIG_IU_MUL_TECHSPEC
227 #elif defined CONFIG_IU_MUL_TECHSPEC
228 #define CFG_IU_MUL_STRUCT 2
228 #define CFG_IU_MUL_STRUCT 2
229 #elif defined CONFIG_IU_MUL_DW
229 #elif defined CONFIG_IU_MUL_DW
230 #define CFG_IU_MUL_STRUCT 3
230 #define CFG_IU_MUL_STRUCT 3
231 #else
231 #else
232 #define CFG_IU_MUL_STRUCT 0
232 #define CFG_IU_MUL_STRUCT 0
233 #endif
233 #endif
234
234
235 #ifndef CONFIG_PWD
235 #ifndef CONFIG_PWD
236 #define CONFIG_PWD 0
236 #define CONFIG_PWD 0
237 #endif
237 #endif
238
238
239 #ifndef CONFIG_IU_MUL_MAC
239 #ifndef CONFIG_IU_MUL_MAC
240 #define CONFIG_IU_MUL_MAC 0
240 #define CONFIG_IU_MUL_MAC 0
241 #endif
241 #endif
242
242
243 #ifndef CONFIG_IU_BP
243 #ifndef CONFIG_IU_BP
244 #define CONFIG_IU_BP 0
244 #define CONFIG_IU_BP 0
245 #endif
245 #endif
246
246
247 #ifndef CONFIG_NOTAG
247 #ifndef CONFIG_NOTAG
248 #define CONFIG_NOTAG 0
248 #define CONFIG_NOTAG 0
249 #endif
249 #endif
250
250
251 #ifndef CONFIG_IU_SVT
251 #ifndef CONFIG_IU_SVT
252 #define CONFIG_IU_SVT 0
252 #define CONFIG_IU_SVT 0
253 #endif
253 #endif
254
254
255 #if defined CONFIG_FPU_GRFPC1
255 #if defined CONFIG_FPU_GRFPC1
256 #define CONFIG_FPU_GRFPC 1
256 #define CONFIG_FPU_GRFPC 1
257 #elif defined CONFIG_FPU_GRFPC2
257 #elif defined CONFIG_FPU_GRFPC2
258 #define CONFIG_FPU_GRFPC 2
258 #define CONFIG_FPU_GRFPC 2
259 #else
259 #else
260 #define CONFIG_FPU_GRFPC 0
260 #define CONFIG_FPU_GRFPC 0
261 #endif
261 #endif
262
262
263 #if defined CONFIG_FPU_GRFPU_INFMUL
263 #if defined CONFIG_FPU_GRFPU_INFMUL
264 #define CONFIG_FPU_GRFPU_MUL 0
264 #define CONFIG_FPU_GRFPU_MUL 0
265 #elif defined CONFIG_FPU_GRFPU_DWMUL
265 #elif defined CONFIG_FPU_GRFPU_DWMUL
266 #define CONFIG_FPU_GRFPU_MUL 1
266 #define CONFIG_FPU_GRFPU_MUL 1
267 #elif defined CONFIG_FPU_GRFPU_MODGEN
267 #elif defined CONFIG_FPU_GRFPU_MODGEN
268 #define CONFIG_FPU_GRFPU_MUL 2
268 #define CONFIG_FPU_GRFPU_MUL 2
269 #elif defined CONFIG_FPU_GRFPU_TECHSPEC
269 #elif defined CONFIG_FPU_GRFPU_TECHSPEC
270 #define CONFIG_FPU_GRFPU_MUL 3
270 #define CONFIG_FPU_GRFPU_MUL 3
271 #else
271 #else
272 #define CONFIG_FPU_GRFPU_MUL 0
272 #define CONFIG_FPU_GRFPU_MUL 0
273 #endif
273 #endif
274
274
275 #if defined CONFIG_FPU_GRFPU_SH
275 #if defined CONFIG_FPU_GRFPU_SH
276 #define CONFIG_FPU_GRFPU_SHARED 1
276 #define CONFIG_FPU_GRFPU_SHARED 1
277 #else
277 #else
278 #define CONFIG_FPU_GRFPU_SHARED 0
278 #define CONFIG_FPU_GRFPU_SHARED 0
279 #endif
279 #endif
280
280
281 #if defined CONFIG_FPU_GRFPU
281 #if defined CONFIG_FPU_GRFPU
282 #define CONFIG_FPU (1+CONFIG_FPU_GRFPU_MUL)
282 #define CONFIG_FPU (1+CONFIG_FPU_GRFPU_MUL)
283 #elif defined CONFIG_FPU_MEIKO
283 #elif defined CONFIG_FPU_MEIKO
284 #define CONFIG_FPU 15
284 #define CONFIG_FPU 15
285 #elif defined CONFIG_FPU_GRFPULITE
285 #elif defined CONFIG_FPU_GRFPULITE
286 #define CONFIG_FPU (8+CONFIG_FPU_GRFPC)
286 #define CONFIG_FPU (8+CONFIG_FPU_GRFPC)
287 #else
287 #else
288 #define CONFIG_FPU 0
288 #define CONFIG_FPU 0
289 #endif
289 #endif
290
290
291 #ifndef CONFIG_FPU_NETLIST
291 #ifndef CONFIG_FPU_NETLIST
292 #define CONFIG_FPU_NETLIST 0
292 #define CONFIG_FPU_NETLIST 0
293 #endif
293 #endif
294
294
295 #ifndef CONFIG_ICACHE_ENABLE
295 #ifndef CONFIG_ICACHE_ENABLE
296 #define CONFIG_ICACHE_ENABLE 0
296 #define CONFIG_ICACHE_ENABLE 0
297 #endif
297 #endif
298
298
299 #if defined CONFIG_ICACHE_ASSO1
299 #if defined CONFIG_ICACHE_ASSO1
300 #define CFG_IU_ISETS 1
300 #define CFG_IU_ISETS 1
301 #elif defined CONFIG_ICACHE_ASSO2
301 #elif defined CONFIG_ICACHE_ASSO2
302 #define CFG_IU_ISETS 2
302 #define CFG_IU_ISETS 2
303 #elif defined CONFIG_ICACHE_ASSO3
303 #elif defined CONFIG_ICACHE_ASSO3
304 #define CFG_IU_ISETS 3
304 #define CFG_IU_ISETS 3
305 #elif defined CONFIG_ICACHE_ASSO4
305 #elif defined CONFIG_ICACHE_ASSO4
306 #define CFG_IU_ISETS 4
306 #define CFG_IU_ISETS 4
307 #else
307 #else
308 #define CFG_IU_ISETS 1
308 #define CFG_IU_ISETS 1
309 #endif
309 #endif
310
310
311 #if defined CONFIG_ICACHE_SZ1
311 #if defined CONFIG_ICACHE_SZ1
312 #define CFG_ICACHE_SZ 1
312 #define CFG_ICACHE_SZ 1
313 #elif defined CONFIG_ICACHE_SZ2
313 #elif defined CONFIG_ICACHE_SZ2
314 #define CFG_ICACHE_SZ 2
314 #define CFG_ICACHE_SZ 2
315 #elif defined CONFIG_ICACHE_SZ4
315 #elif defined CONFIG_ICACHE_SZ4
316 #define CFG_ICACHE_SZ 4
316 #define CFG_ICACHE_SZ 4
317 #elif defined CONFIG_ICACHE_SZ8
317 #elif defined CONFIG_ICACHE_SZ8
318 #define CFG_ICACHE_SZ 8
318 #define CFG_ICACHE_SZ 8
319 #elif defined CONFIG_ICACHE_SZ16
319 #elif defined CONFIG_ICACHE_SZ16
320 #define CFG_ICACHE_SZ 16
320 #define CFG_ICACHE_SZ 16
321 #elif defined CONFIG_ICACHE_SZ32
321 #elif defined CONFIG_ICACHE_SZ32
322 #define CFG_ICACHE_SZ 32
322 #define CFG_ICACHE_SZ 32
323 #elif defined CONFIG_ICACHE_SZ64
323 #elif defined CONFIG_ICACHE_SZ64
324 #define CFG_ICACHE_SZ 64
324 #define CFG_ICACHE_SZ 64
325 #elif defined CONFIG_ICACHE_SZ128
325 #elif defined CONFIG_ICACHE_SZ128
326 #define CFG_ICACHE_SZ 128
326 #define CFG_ICACHE_SZ 128
327 #elif defined CONFIG_ICACHE_SZ256
327 #elif defined CONFIG_ICACHE_SZ256
328 #define CFG_ICACHE_SZ 256
328 #define CFG_ICACHE_SZ 256
329 #else
329 #else
330 #define CFG_ICACHE_SZ 1
330 #define CFG_ICACHE_SZ 1
331 #endif
331 #endif
332
332
333 #ifdef CONFIG_ICACHE_LZ16
333 #ifdef CONFIG_ICACHE_LZ16
334 #define CFG_ILINE_SZ 4
334 #define CFG_ILINE_SZ 4
335 #else
335 #else
336 #define CFG_ILINE_SZ 8
336 #define CFG_ILINE_SZ 8
337 #endif
337 #endif
338
338
339 #if defined CONFIG_ICACHE_ALGODIR
339 #if defined CONFIG_ICACHE_ALGODIR
340 #define CFG_ICACHE_ALGORND 3
340 #define CFG_ICACHE_ALGORND 3
341 #elif defined CONFIG_ICACHE_ALGORND
341 #elif defined CONFIG_ICACHE_ALGORND
342 #define CFG_ICACHE_ALGORND 2
342 #define CFG_ICACHE_ALGORND 2
343 #elif defined CONFIG_ICACHE_ALGOLRR
343 #elif defined CONFIG_ICACHE_ALGOLRR
344 #define CFG_ICACHE_ALGORND 1
344 #define CFG_ICACHE_ALGORND 1
345 #else
345 #else
346 #define CFG_ICACHE_ALGORND 0
346 #define CFG_ICACHE_ALGORND 0
347 #endif
347 #endif
348
348
349 #ifndef CONFIG_ICACHE_LOCK
349 #ifndef CONFIG_ICACHE_LOCK
350 #define CONFIG_ICACHE_LOCK 0
350 #define CONFIG_ICACHE_LOCK 0
351 #endif
351 #endif
352
352
353 #ifndef CONFIG_ICACHE_LRAM
353 #ifndef CONFIG_ICACHE_LRAM
354 #define CONFIG_ICACHE_LRAM 0
354 #define CONFIG_ICACHE_LRAM 0
355 #endif
355 #endif
356
356
357 #ifndef CONFIG_ICACHE_LRSTART
357 #ifndef CONFIG_ICACHE_LRSTART
358 #define CONFIG_ICACHE_LRSTART 8E
358 #define CONFIG_ICACHE_LRSTART 8E
359 #endif
359 #endif
360
360
361 #if defined CONFIG_ICACHE_LRAM_SZ2
361 #if defined CONFIG_ICACHE_LRAM_SZ2
362 #define CFG_ILRAM_SIZE 2
362 #define CFG_ILRAM_SIZE 2
363 #elif defined CONFIG_ICACHE_LRAM_SZ4
363 #elif defined CONFIG_ICACHE_LRAM_SZ4
364 #define CFG_ILRAM_SIZE 4
364 #define CFG_ILRAM_SIZE 4
365 #elif defined CONFIG_ICACHE_LRAM_SZ8
365 #elif defined CONFIG_ICACHE_LRAM_SZ8
366 #define CFG_ILRAM_SIZE 8
366 #define CFG_ILRAM_SIZE 8
367 #elif defined CONFIG_ICACHE_LRAM_SZ16
367 #elif defined CONFIG_ICACHE_LRAM_SZ16
368 #define CFG_ILRAM_SIZE 16
368 #define CFG_ILRAM_SIZE 16
369 #elif defined CONFIG_ICACHE_LRAM_SZ32
369 #elif defined CONFIG_ICACHE_LRAM_SZ32
370 #define CFG_ILRAM_SIZE 32
370 #define CFG_ILRAM_SIZE 32
371 #elif defined CONFIG_ICACHE_LRAM_SZ64
371 #elif defined CONFIG_ICACHE_LRAM_SZ64
372 #define CFG_ILRAM_SIZE 64
372 #define CFG_ILRAM_SIZE 64
373 #elif defined CONFIG_ICACHE_LRAM_SZ128
373 #elif defined CONFIG_ICACHE_LRAM_SZ128
374 #define CFG_ILRAM_SIZE 128
374 #define CFG_ILRAM_SIZE 128
375 #elif defined CONFIG_ICACHE_LRAM_SZ256
375 #elif defined CONFIG_ICACHE_LRAM_SZ256
376 #define CFG_ILRAM_SIZE 256
376 #define CFG_ILRAM_SIZE 256
377 #else
377 #else
378 #define CFG_ILRAM_SIZE 1
378 #define CFG_ILRAM_SIZE 1
379 #endif
379 #endif
380
380
381
381
382 #ifndef CONFIG_DCACHE_ENABLE
382 #ifndef CONFIG_DCACHE_ENABLE
383 #define CONFIG_DCACHE_ENABLE 0
383 #define CONFIG_DCACHE_ENABLE 0
384 #endif
384 #endif
385
385
386 #if defined CONFIG_DCACHE_ASSO1
386 #if defined CONFIG_DCACHE_ASSO1
387 #define CFG_IU_DSETS 1
387 #define CFG_IU_DSETS 1
388 #elif defined CONFIG_DCACHE_ASSO2
388 #elif defined CONFIG_DCACHE_ASSO2
389 #define CFG_IU_DSETS 2
389 #define CFG_IU_DSETS 2
390 #elif defined CONFIG_DCACHE_ASSO3
390 #elif defined CONFIG_DCACHE_ASSO3
391 #define CFG_IU_DSETS 3
391 #define CFG_IU_DSETS 3
392 #elif defined CONFIG_DCACHE_ASSO4
392 #elif defined CONFIG_DCACHE_ASSO4
393 #define CFG_IU_DSETS 4
393 #define CFG_IU_DSETS 4
394 #else
394 #else
395 #define CFG_IU_DSETS 1
395 #define CFG_IU_DSETS 1
396 #endif
396 #endif
397
397
398 #if defined CONFIG_DCACHE_SZ1
398 #if defined CONFIG_DCACHE_SZ1
399 #define CFG_DCACHE_SZ 1
399 #define CFG_DCACHE_SZ 1
400 #elif defined CONFIG_DCACHE_SZ2
400 #elif defined CONFIG_DCACHE_SZ2
401 #define CFG_DCACHE_SZ 2
401 #define CFG_DCACHE_SZ 2
402 #elif defined CONFIG_DCACHE_SZ4
402 #elif defined CONFIG_DCACHE_SZ4
403 #define CFG_DCACHE_SZ 4
403 #define CFG_DCACHE_SZ 4
404 #elif defined CONFIG_DCACHE_SZ8
404 #elif defined CONFIG_DCACHE_SZ8
405 #define CFG_DCACHE_SZ 8
405 #define CFG_DCACHE_SZ 8
406 #elif defined CONFIG_DCACHE_SZ16
406 #elif defined CONFIG_DCACHE_SZ16
407 #define CFG_DCACHE_SZ 16
407 #define CFG_DCACHE_SZ 16
408 #elif defined CONFIG_DCACHE_SZ32
408 #elif defined CONFIG_DCACHE_SZ32
409 #define CFG_DCACHE_SZ 32
409 #define CFG_DCACHE_SZ 32
410 #elif defined CONFIG_DCACHE_SZ64
410 #elif defined CONFIG_DCACHE_SZ64
411 #define CFG_DCACHE_SZ 64
411 #define CFG_DCACHE_SZ 64
412 #elif defined CONFIG_DCACHE_SZ128
412 #elif defined CONFIG_DCACHE_SZ128
413 #define CFG_DCACHE_SZ 128
413 #define CFG_DCACHE_SZ 128
414 #elif defined CONFIG_DCACHE_SZ256
414 #elif defined CONFIG_DCACHE_SZ256
415 #define CFG_DCACHE_SZ 256
415 #define CFG_DCACHE_SZ 256
416 #else
416 #else
417 #define CFG_DCACHE_SZ 1
417 #define CFG_DCACHE_SZ 1
418 #endif
418 #endif
419
419
420 #ifdef CONFIG_DCACHE_LZ16
420 #ifdef CONFIG_DCACHE_LZ16
421 #define CFG_DLINE_SZ 4
421 #define CFG_DLINE_SZ 4
422 #else
422 #else
423 #define CFG_DLINE_SZ 8
423 #define CFG_DLINE_SZ 8
424 #endif
424 #endif
425
425
426 #if defined CONFIG_DCACHE_ALGODIR
426 #if defined CONFIG_DCACHE_ALGODIR
427 #define CFG_DCACHE_ALGORND 3
427 #define CFG_DCACHE_ALGORND 3
428 #elif defined CONFIG_DCACHE_ALGORND
428 #elif defined CONFIG_DCACHE_ALGORND
429 #define CFG_DCACHE_ALGORND 2
429 #define CFG_DCACHE_ALGORND 2
430 #elif defined CONFIG_DCACHE_ALGOLRR
430 #elif defined CONFIG_DCACHE_ALGOLRR
431 #define CFG_DCACHE_ALGORND 1
431 #define CFG_DCACHE_ALGORND 1
432 #else
432 #else
433 #define CFG_DCACHE_ALGORND 0
433 #define CFG_DCACHE_ALGORND 0
434 #endif
434 #endif
435
435
436 #ifndef CONFIG_DCACHE_LOCK
436 #ifndef CONFIG_DCACHE_LOCK
437 #define CONFIG_DCACHE_LOCK 0
437 #define CONFIG_DCACHE_LOCK 0
438 #endif
438 #endif
439
439
440 #ifndef CONFIG_DCACHE_SNOOP
440 #ifndef CONFIG_DCACHE_SNOOP
441 #define CONFIG_DCACHE_SNOOP 0
441 #define CONFIG_DCACHE_SNOOP 0
442 #endif
442 #endif
443
443
444 #ifndef CONFIG_DCACHE_SNOOP_FAST
444 #ifndef CONFIG_DCACHE_SNOOP_FAST
445 #define CONFIG_DCACHE_SNOOP_FAST 0
445 #define CONFIG_DCACHE_SNOOP_FAST 0
446 #endif
446 #endif
447
447
448 #ifndef CONFIG_DCACHE_SNOOP_SEPTAG
448 #ifndef CONFIG_DCACHE_SNOOP_SEPTAG
449 #define CONFIG_DCACHE_SNOOP_SEPTAG 0
449 #define CONFIG_DCACHE_SNOOP_SEPTAG 0
450 #endif
450 #endif
451
451
452 #ifndef CONFIG_CACHE_FIXED
452 #ifndef CONFIG_CACHE_FIXED
453 #define CONFIG_CACHE_FIXED 0
453 #define CONFIG_CACHE_FIXED 0
454 #endif
454 #endif
455
455
456 #ifndef CONFIG_DCACHE_LRAM
456 #ifndef CONFIG_DCACHE_LRAM
457 #define CONFIG_DCACHE_LRAM 0
457 #define CONFIG_DCACHE_LRAM 0
458 #endif
458 #endif
459
459
460 #ifndef CONFIG_DCACHE_LRSTART
460 #ifndef CONFIG_DCACHE_LRSTART
461 #define CONFIG_DCACHE_LRSTART 8F
461 #define CONFIG_DCACHE_LRSTART 8F
462 #endif
462 #endif
463
463
464 #if defined CONFIG_DCACHE_LRAM_SZ2
464 #if defined CONFIG_DCACHE_LRAM_SZ2
465 #define CFG_DLRAM_SIZE 2
465 #define CFG_DLRAM_SIZE 2
466 #elif defined CONFIG_DCACHE_LRAM_SZ4
466 #elif defined CONFIG_DCACHE_LRAM_SZ4
467 #define CFG_DLRAM_SIZE 4
467 #define CFG_DLRAM_SIZE 4
468 #elif defined CONFIG_DCACHE_LRAM_SZ8
468 #elif defined CONFIG_DCACHE_LRAM_SZ8
469 #define CFG_DLRAM_SIZE 8
469 #define CFG_DLRAM_SIZE 8
470 #elif defined CONFIG_DCACHE_LRAM_SZ16
470 #elif defined CONFIG_DCACHE_LRAM_SZ16
471 #define CFG_DLRAM_SIZE 16
471 #define CFG_DLRAM_SIZE 16
472 #elif defined CONFIG_DCACHE_LRAM_SZ32
472 #elif defined CONFIG_DCACHE_LRAM_SZ32
473 #define CFG_DLRAM_SIZE 32
473 #define CFG_DLRAM_SIZE 32
474 #elif defined CONFIG_DCACHE_LRAM_SZ64
474 #elif defined CONFIG_DCACHE_LRAM_SZ64
475 #define CFG_DLRAM_SIZE 64
475 #define CFG_DLRAM_SIZE 64
476 #elif defined CONFIG_DCACHE_LRAM_SZ128
476 #elif defined CONFIG_DCACHE_LRAM_SZ128
477 #define CFG_DLRAM_SIZE 128
477 #define CFG_DLRAM_SIZE 128
478 #elif defined CONFIG_DCACHE_LRAM_SZ256
478 #elif defined CONFIG_DCACHE_LRAM_SZ256
479 #define CFG_DLRAM_SIZE 256
479 #define CFG_DLRAM_SIZE 256
480 #else
480 #else
481 #define CFG_DLRAM_SIZE 1
481 #define CFG_DLRAM_SIZE 1
482 #endif
482 #endif
483
483
484 #if defined CONFIG_MMU_PAGE_4K
484 #if defined CONFIG_MMU_PAGE_4K
485 #define CONFIG_MMU_PAGE 0
485 #define CONFIG_MMU_PAGE 0
486 #elif defined CONFIG_MMU_PAGE_8K
486 #elif defined CONFIG_MMU_PAGE_8K
487 #define CONFIG_MMU_PAGE 1
487 #define CONFIG_MMU_PAGE 1
488 #elif defined CONFIG_MMU_PAGE_16K
488 #elif defined CONFIG_MMU_PAGE_16K
489 #define CONFIG_MMU_PAGE 2
489 #define CONFIG_MMU_PAGE 2
490 #elif defined CONFIG_MMU_PAGE_32K
490 #elif defined CONFIG_MMU_PAGE_32K
491 #define CONFIG_MMU_PAGE 3
491 #define CONFIG_MMU_PAGE 3
492 #elif defined CONFIG_MMU_PAGE_PROG
492 #elif defined CONFIG_MMU_PAGE_PROG
493 #define CONFIG_MMU_PAGE 4
493 #define CONFIG_MMU_PAGE 4
494 #else
494 #else
495 #define CONFIG_MMU_PAGE 0
495 #define CONFIG_MMU_PAGE 0
496 #endif
496 #endif
497
497
498 #ifdef CONFIG_MMU_ENABLE
498 #ifdef CONFIG_MMU_ENABLE
499 #define CONFIG_MMUEN 1
499 #define CONFIG_MMUEN 1
500
500
501 #ifdef CONFIG_MMU_SPLIT
501 #ifdef CONFIG_MMU_SPLIT
502 #define CONFIG_TLB_TYPE 0
502 #define CONFIG_TLB_TYPE 0
503 #endif
503 #endif
504 #ifdef CONFIG_MMU_COMBINED
504 #ifdef CONFIG_MMU_COMBINED
505 #define CONFIG_TLB_TYPE 1
505 #define CONFIG_TLB_TYPE 1
506 #endif
506 #endif
507
507
508 #ifdef CONFIG_MMU_REPARRAY
508 #ifdef CONFIG_MMU_REPARRAY
509 #define CONFIG_TLB_REP 0
509 #define CONFIG_TLB_REP 0
510 #endif
510 #endif
511 #ifdef CONFIG_MMU_REPINCREMENT
511 #ifdef CONFIG_MMU_REPINCREMENT
512 #define CONFIG_TLB_REP 1
512 #define CONFIG_TLB_REP 1
513 #endif
513 #endif
514
514
515 #ifdef CONFIG_MMU_I2
515 #ifdef CONFIG_MMU_I2
516 #define CONFIG_ITLBNUM 2
516 #define CONFIG_ITLBNUM 2
517 #endif
517 #endif
518 #ifdef CONFIG_MMU_I4
518 #ifdef CONFIG_MMU_I4
519 #define CONFIG_ITLBNUM 4
519 #define CONFIG_ITLBNUM 4
520 #endif
520 #endif
521 #ifdef CONFIG_MMU_I8
521 #ifdef CONFIG_MMU_I8
522 #define CONFIG_ITLBNUM 8
522 #define CONFIG_ITLBNUM 8
523 #endif
523 #endif
524 #ifdef CONFIG_MMU_I16
524 #ifdef CONFIG_MMU_I16
525 #define CONFIG_ITLBNUM 16
525 #define CONFIG_ITLBNUM 16
526 #endif
526 #endif
527 #ifdef CONFIG_MMU_I32
527 #ifdef CONFIG_MMU_I32
528 #define CONFIG_ITLBNUM 32
528 #define CONFIG_ITLBNUM 32
529 #endif
529 #endif
530
530
531 #define CONFIG_DTLBNUM 2
531 #define CONFIG_DTLBNUM 2
532 #ifdef CONFIG_MMU_D2
532 #ifdef CONFIG_MMU_D2
533 #undef CONFIG_DTLBNUM
533 #undef CONFIG_DTLBNUM
534 #define CONFIG_DTLBNUM 2
534 #define CONFIG_DTLBNUM 2
535 #endif
535 #endif
536 #ifdef CONFIG_MMU_D4
536 #ifdef CONFIG_MMU_D4
537 #undef CONFIG_DTLBNUM
537 #undef CONFIG_DTLBNUM
538 #define CONFIG_DTLBNUM 4
538 #define CONFIG_DTLBNUM 4
539 #endif
539 #endif
540 #ifdef CONFIG_MMU_D8
540 #ifdef CONFIG_MMU_D8
541 #undef CONFIG_DTLBNUM
541 #undef CONFIG_DTLBNUM
542 #define CONFIG_DTLBNUM 8
542 #define CONFIG_DTLBNUM 8
543 #endif
543 #endif
544 #ifdef CONFIG_MMU_D16
544 #ifdef CONFIG_MMU_D16
545 #undef CONFIG_DTLBNUM
545 #undef CONFIG_DTLBNUM
546 #define CONFIG_DTLBNUM 16
546 #define CONFIG_DTLBNUM 16
547 #endif
547 #endif
548 #ifdef CONFIG_MMU_D32
548 #ifdef CONFIG_MMU_D32
549 #undef CONFIG_DTLBNUM
549 #undef CONFIG_DTLBNUM
550 #define CONFIG_DTLBNUM 32
550 #define CONFIG_DTLBNUM 32
551 #endif
551 #endif
552 #ifdef CONFIG_MMU_FASTWB
552 #ifdef CONFIG_MMU_FASTWB
553 #define CFG_MMU_FASTWB 1
553 #define CFG_MMU_FASTWB 1
554 #else
554 #else
555 #define CFG_MMU_FASTWB 0
555 #define CFG_MMU_FASTWB 0
556 #endif
556 #endif
557
557
558 #else
558 #else
559 #define CONFIG_MMUEN 0
559 #define CONFIG_MMUEN 0
560 #define CONFIG_ITLBNUM 2
560 #define CONFIG_ITLBNUM 2
561 #define CONFIG_DTLBNUM 2
561 #define CONFIG_DTLBNUM 2
562 #define CONFIG_TLB_TYPE 1
562 #define CONFIG_TLB_TYPE 1
563 #define CONFIG_TLB_REP 1
563 #define CONFIG_TLB_REP 1
564 #define CFG_MMU_FASTWB 0
564 #define CFG_MMU_FASTWB 0
565 #endif
565 #endif
566
566
567 #ifndef CONFIG_DSU_ENABLE
567 #ifndef CONFIG_DSU_ENABLE
568 #define CONFIG_DSU_ENABLE 0
568 #define CONFIG_DSU_ENABLE 0
569 #endif
569 #endif
570
570
571 #if defined CONFIG_DSU_ITRACESZ1
571 #if defined CONFIG_DSU_ITRACESZ1
572 #define CFG_DSU_ITB 1
572 #define CFG_DSU_ITB 1
573 #elif CONFIG_DSU_ITRACESZ2
573 #elif CONFIG_DSU_ITRACESZ2
574 #define CFG_DSU_ITB 2
574 #define CFG_DSU_ITB 2
575 #elif CONFIG_DSU_ITRACESZ4
575 #elif CONFIG_DSU_ITRACESZ4
576 #define CFG_DSU_ITB 4
576 #define CFG_DSU_ITB 4
577 #elif CONFIG_DSU_ITRACESZ8
577 #elif CONFIG_DSU_ITRACESZ8
578 #define CFG_DSU_ITB 8
578 #define CFG_DSU_ITB 8
579 #elif CONFIG_DSU_ITRACESZ16
579 #elif CONFIG_DSU_ITRACESZ16
580 #define CFG_DSU_ITB 16
580 #define CFG_DSU_ITB 16
581 #else
581 #else
582 #define CFG_DSU_ITB 0
582 #define CFG_DSU_ITB 0
583 #endif
583 #endif
584
584
585 #if defined CONFIG_DSU_ATRACESZ1
585 #if defined CONFIG_DSU_ATRACESZ1
586 #define CFG_DSU_ATB 1
586 #define CFG_DSU_ATB 1
587 #elif CONFIG_DSU_ATRACESZ2
587 #elif CONFIG_DSU_ATRACESZ2
588 #define CFG_DSU_ATB 2
588 #define CFG_DSU_ATB 2
589 #elif CONFIG_DSU_ATRACESZ4
589 #elif CONFIG_DSU_ATRACESZ4
590 #define CFG_DSU_ATB 4
590 #define CFG_DSU_ATB 4
591 #elif CONFIG_DSU_ATRACESZ8
591 #elif CONFIG_DSU_ATRACESZ8
592 #define CFG_DSU_ATB 8
592 #define CFG_DSU_ATB 8
593 #elif CONFIG_DSU_ATRACESZ16
593 #elif CONFIG_DSU_ATRACESZ16
594 #define CFG_DSU_ATB 16
594 #define CFG_DSU_ATB 16
595 #else
595 #else
596 #define CFG_DSU_ATB 0
596 #define CFG_DSU_ATB 0
597 #endif
597 #endif
598
598
599 #ifndef CONFIG_LEON3FT_EN
599 #ifndef CONFIG_LEON3FT_EN
600 #define CONFIG_LEON3FT_EN 0
600 #define CONFIG_LEON3FT_EN 0
601 #endif
601 #endif
602
602
603 #if defined CONFIG_IUFT_PAR
603 #if defined CONFIG_IUFT_PAR
604 #define CONFIG_IUFT_EN 1
604 #define CONFIG_IUFT_EN 1
605 #elif defined CONFIG_IUFT_DMR
605 #elif defined CONFIG_IUFT_DMR
606 #define CONFIG_IUFT_EN 2
606 #define CONFIG_IUFT_EN 2
607 #elif defined CONFIG_IUFT_BCH
607 #elif defined CONFIG_IUFT_BCH
608 #define CONFIG_IUFT_EN 3
608 #define CONFIG_IUFT_EN 3
609 #elif defined CONFIG_IUFT_TMR
609 #elif defined CONFIG_IUFT_TMR
610 #define CONFIG_IUFT_EN 4
610 #define CONFIG_IUFT_EN 4
611 #else
611 #else
612 #define CONFIG_IUFT_EN 0
612 #define CONFIG_IUFT_EN 0
613 #endif
613 #endif
614 #ifndef CONFIG_RF_ERRINJ
614 #ifndef CONFIG_RF_ERRINJ
615 #define CONFIG_RF_ERRINJ 0
615 #define CONFIG_RF_ERRINJ 0
616 #endif
616 #endif
617
617
618 #ifndef CONFIG_FPUFT_EN
618 #ifndef CONFIG_FPUFT_EN
619 #define CONFIG_FPUFT 0
619 #define CONFIG_FPUFT 0
620 #else
620 #else
621 #ifdef CONFIG_FPU_GRFPU
621 #ifdef CONFIG_FPU_GRFPU
622 #define CONFIG_FPUFT 2
622 #define CONFIG_FPUFT 2
623 #else
623 #else
624 #define CONFIG_FPUFT 1
624 #define CONFIG_FPUFT 1
625 #endif
625 #endif
626 #endif
626 #endif
627
627
628 #ifndef CONFIG_CACHE_FT_EN
628 #ifndef CONFIG_CACHE_FT_EN
629 #define CONFIG_CACHE_FT_EN 0
629 #define CONFIG_CACHE_FT_EN 0
630 #endif
630 #endif
631 #ifndef CONFIG_CACHE_ERRINJ
631 #ifndef CONFIG_CACHE_ERRINJ
632 #define CONFIG_CACHE_ERRINJ 0
632 #define CONFIG_CACHE_ERRINJ 0
633 #endif
633 #endif
634
634
635 #ifndef CONFIG_LEON3_NETLIST
635 #ifndef CONFIG_LEON3_NETLIST
636 #define CONFIG_LEON3_NETLIST 0
636 #define CONFIG_LEON3_NETLIST 0
637 #endif
637 #endif
638
638
639 #ifdef CONFIG_DEBUG_PC32
639 #ifdef CONFIG_DEBUG_PC32
640 #define CFG_DEBUG_PC32 0
640 #define CFG_DEBUG_PC32 0
641 #else
641 #else
642 #define CFG_DEBUG_PC32 2
642 #define CFG_DEBUG_PC32 2
643 #endif
643 #endif
644 #ifndef CONFIG_IU_DISAS
644 #ifndef CONFIG_IU_DISAS
645 #define CONFIG_IU_DISAS 0
645 #define CONFIG_IU_DISAS 0
646 #endif
646 #endif
647 #ifndef CONFIG_IU_DISAS_NET
647 #ifndef CONFIG_IU_DISAS_NET
648 #define CONFIG_IU_DISAS_NET 0
648 #define CONFIG_IU_DISAS_NET 0
649 #endif
649 #endif
650
650
651
651
652 #ifndef CONFIG_AHB_SPLIT
652 #ifndef CONFIG_AHB_SPLIT
653 #define CONFIG_AHB_SPLIT 0
653 #define CONFIG_AHB_SPLIT 0
654 #endif
654 #endif
655
655
656 #ifndef CONFIG_AHB_RROBIN
656 #ifndef CONFIG_AHB_RROBIN
657 #define CONFIG_AHB_RROBIN 0
657 #define CONFIG_AHB_RROBIN 0
658 #endif
658 #endif
659
659
660 #ifndef CONFIG_AHB_IOADDR
660 #ifndef CONFIG_AHB_IOADDR
661 #define CONFIG_AHB_IOADDR FFF
661 #define CONFIG_AHB_IOADDR FFF
662 #endif
662 #endif
663
663
664 #ifndef CONFIG_APB_HADDR
664 #ifndef CONFIG_APB_HADDR
665 #define CONFIG_APB_HADDR 800
665 #define CONFIG_APB_HADDR 800
666 #endif
666 #endif
667
667
668 #ifndef CONFIG_AHB_MON
668 #ifndef CONFIG_AHB_MON
669 #define CONFIG_AHB_MON 0
669 #define CONFIG_AHB_MON 0
670 #endif
670 #endif
671
671
672 #ifndef CONFIG_AHB_MONERR
672 #ifndef CONFIG_AHB_MONERR
673 #define CONFIG_AHB_MONERR 0
673 #define CONFIG_AHB_MONERR 0
674 #endif
674 #endif
675
675
676 #ifndef CONFIG_AHB_MONWAR
676 #ifndef CONFIG_AHB_MONWAR
677 #define CONFIG_AHB_MONWAR 0
677 #define CONFIG_AHB_MONWAR 0
678 #endif
678 #endif
679
679
680 #ifndef CONFIG_AHB_DTRACE
680 #ifndef CONFIG_AHB_DTRACE
681 #define CONFIG_AHB_DTRACE 0
681 #define CONFIG_AHB_DTRACE 0
682 #endif
682 #endif
683
683
684 #ifndef CONFIG_DSU_JTAG
684 #ifndef CONFIG_DSU_JTAG
685 #define CONFIG_DSU_JTAG 0
685 #define CONFIG_DSU_JTAG 0
686 #endif
686 #endif
687
687
688 #ifndef CONFIG_DSU_ETH
688 #ifndef CONFIG_DSU_ETH
689 #define CONFIG_DSU_ETH 0
689 #define CONFIG_DSU_ETH 0
690 #endif
690 #endif
691
691
692 #ifndef CONFIG_DSU_IPMSB
692 #ifndef CONFIG_DSU_IPMSB
693 #define CONFIG_DSU_IPMSB C0A8
693 #define CONFIG_DSU_IPMSB C0A8
694 #endif
694 #endif
695
695
696 #ifndef CONFIG_DSU_IPLSB
696 #ifndef CONFIG_DSU_IPLSB
697 #define CONFIG_DSU_IPLSB 0033
697 #define CONFIG_DSU_IPLSB 0033
698 #endif
698 #endif
699
699
700 #ifndef CONFIG_DSU_ETHMSB
700 #ifndef CONFIG_DSU_ETHMSB
701 #define CONFIG_DSU_ETHMSB 020000
701 #define CONFIG_DSU_ETHMSB 020000
702 #endif
702 #endif
703
703
704 #ifndef CONFIG_DSU_ETHLSB
704 #ifndef CONFIG_DSU_ETHLSB
705 #define CONFIG_DSU_ETHLSB 000009
705 #define CONFIG_DSU_ETHLSB 000009
706 #endif
706 #endif
707
707
708 #if defined CONFIG_DSU_ETHSZ1
708 #if defined CONFIG_DSU_ETHSZ1
709 #define CFG_DSU_ETHB 1
709 #define CFG_DSU_ETHB 1
710 #elif CONFIG_DSU_ETHSZ2
710 #elif CONFIG_DSU_ETHSZ2
711 #define CFG_DSU_ETHB 2
711 #define CFG_DSU_ETHB 2
712 #elif CONFIG_DSU_ETHSZ4
712 #elif CONFIG_DSU_ETHSZ4
713 #define CFG_DSU_ETHB 4
713 #define CFG_DSU_ETHB 4
714 #elif CONFIG_DSU_ETHSZ8
714 #elif CONFIG_DSU_ETHSZ8
715 #define CFG_DSU_ETHB 8
715 #define CFG_DSU_ETHB 8
716 #elif CONFIG_DSU_ETHSZ16
716 #elif CONFIG_DSU_ETHSZ16
717 #define CFG_DSU_ETHB 16
717 #define CFG_DSU_ETHB 16
718 #elif CONFIG_DSU_ETHSZ32
718 #elif CONFIG_DSU_ETHSZ32
719 #define CFG_DSU_ETHB 32
719 #define CFG_DSU_ETHB 32
720 #else
720 #else
721 #define CFG_DSU_ETHB 1
721 #define CFG_DSU_ETHB 1
722 #endif
722 #endif
723
723
724 #ifndef CONFIG_DSU_ETH_PROG
724 #ifndef CONFIG_DSU_ETH_PROG
725 #define CONFIG_DSU_ETH_PROG 0
725 #define CONFIG_DSU_ETH_PROG 0
726 #endif
726 #endif
727
727
728 #ifndef CONFIG_DSU_ETH_DIS
728 #ifndef CONFIG_DSU_ETH_DIS
729 #define CONFIG_DSU_ETH_DIS 0
729 #define CONFIG_DSU_ETH_DIS 0
730 #endif
730 #endif
731
731
732 #ifndef CONFIG_MCTRL_LEON2
732 #ifndef CONFIG_MCTRL_LEON2
733 #define CONFIG_MCTRL_LEON2 0
733 #define CONFIG_MCTRL_LEON2 0
734 #endif
734 #endif
735
735
736 #ifndef CONFIG_MCTRL_SDRAM
736 #ifndef CONFIG_MCTRL_SDRAM
737 #define CONFIG_MCTRL_SDRAM 0
737 #define CONFIG_MCTRL_SDRAM 0
738 #endif
738 #endif
739
739
740 #ifndef CONFIG_MCTRL_SDRAM_SEPBUS
740 #ifndef CONFIG_MCTRL_SDRAM_SEPBUS
741 #define CONFIG_MCTRL_SDRAM_SEPBUS 0
741 #define CONFIG_MCTRL_SDRAM_SEPBUS 0
742 #endif
742 #endif
743
743
744 #ifndef CONFIG_MCTRL_SDRAM_INVCLK
744 #ifndef CONFIG_MCTRL_SDRAM_INVCLK
745 #define CONFIG_MCTRL_SDRAM_INVCLK 0
745 #define CONFIG_MCTRL_SDRAM_INVCLK 0
746 #endif
746 #endif
747
747
748 #ifndef CONFIG_MCTRL_SDRAM_BUS64
748 #ifndef CONFIG_MCTRL_SDRAM_BUS64
749 #define CONFIG_MCTRL_SDRAM_BUS64 0
749 #define CONFIG_MCTRL_SDRAM_BUS64 0
750 #endif
750 #endif
751
751
752 #ifndef CONFIG_MCTRL_8BIT
752 #ifndef CONFIG_MCTRL_8BIT
753 #define CONFIG_MCTRL_8BIT 0
753 #define CONFIG_MCTRL_8BIT 0
754 #endif
754 #endif
755
755
756 #ifndef CONFIG_MCTRL_16BIT
756 #ifndef CONFIG_MCTRL_16BIT
757 #define CONFIG_MCTRL_16BIT 0
757 #define CONFIG_MCTRL_16BIT 0
758 #endif
758 #endif
759
759
760 #ifndef CONFIG_MCTRL_5CS
760 #ifndef CONFIG_MCTRL_5CS
761 #define CONFIG_MCTRL_5CS 0
761 #define CONFIG_MCTRL_5CS 0
762 #endif
762 #endif
763
763
764 #ifndef CONFIG_MCTRL_EDAC
764 #ifndef CONFIG_MCTRL_EDAC
765 #define CONFIG_MCTRL_EDAC 0
765 #define CONFIG_MCTRL_EDAC 0
766 #endif
766 #endif
767
767
768 #ifndef CONFIG_MCTRL_PAGE
768 #ifndef CONFIG_MCTRL_PAGE
769 #define CONFIG_MCTRL_PAGE 0
769 #define CONFIG_MCTRL_PAGE 0
770 #endif
770 #endif
771
771
772 #ifndef CONFIG_MCTRL_PROGPAGE
772 #ifndef CONFIG_MCTRL_PROGPAGE
773 #define CONFIG_MCTRL_PROGPAGE 0
773 #define CONFIG_MCTRL_PROGPAGE 0
774 #endif
774 #endif
775
775
776
776
777 #ifndef CONFIG_MIG_DDR2
777 #ifndef CONFIG_MIG_DDR2
778 #define CONFIG_MIG_DDR2 0
778 #define CONFIG_MIG_DDR2 0
779 #endif
779 #endif
780
780
781 #ifndef CONFIG_MIG_RANKS
781 #ifndef CONFIG_MIG_RANKS
782 #define CONFIG_MIG_RANKS 1
782 #define CONFIG_MIG_RANKS 1
783 #endif
783 #endif
784
784
785 #ifndef CONFIG_MIG_COLBITS
785 #ifndef CONFIG_MIG_COLBITS
786 #define CONFIG_MIG_COLBITS 10
786 #define CONFIG_MIG_COLBITS 10
787 #endif
787 #endif
788
788
789 #ifndef CONFIG_MIG_ROWBITS
789 #ifndef CONFIG_MIG_ROWBITS
790 #define CONFIG_MIG_ROWBITS 13
790 #define CONFIG_MIG_ROWBITS 13
791 #endif
791 #endif
792
792
793 #ifndef CONFIG_MIG_BANKBITS
793 #ifndef CONFIG_MIG_BANKBITS
794 #define CONFIG_MIG_BANKBITS 2
794 #define CONFIG_MIG_BANKBITS 2
795 #endif
795 #endif
796
796
797 #ifndef CONFIG_MIG_HMASK
797 #ifndef CONFIG_MIG_HMASK
798 #define CONFIG_MIG_HMASK F00
798 #define CONFIG_MIG_HMASK F00
799 #endif
799 #endif
800 #ifndef CONFIG_AHBSTAT_ENABLE
800 #ifndef CONFIG_AHBSTAT_ENABLE
801 #define CONFIG_AHBSTAT_ENABLE 0
801 #define CONFIG_AHBSTAT_ENABLE 0
802 #endif
802 #endif
803
803
804 #ifndef CONFIG_AHBSTAT_NFTSLV
804 #ifndef CONFIG_AHBSTAT_NFTSLV
805 #define CONFIG_AHBSTAT_NFTSLV 1
805 #define CONFIG_AHBSTAT_NFTSLV 1
806 #endif
806 #endif
807
807
808 #ifndef CONFIG_AHBROM_ENABLE
808 #ifndef CONFIG_AHBROM_ENABLE
809 #define CONFIG_AHBROM_ENABLE 0
809 #define CONFIG_AHBROM_ENABLE 0
810 #endif
810 #endif
811
811
812 #ifndef CONFIG_AHBROM_START
812 #ifndef CONFIG_AHBROM_START
813 #define CONFIG_AHBROM_START 000
813 #define CONFIG_AHBROM_START 000
814 #endif
814 #endif
815
815
816 #ifndef CONFIG_AHBROM_PIPE
816 #ifndef CONFIG_AHBROM_PIPE
817 #define CONFIG_AHBROM_PIPE 0
817 #define CONFIG_AHBROM_PIPE 0
818 #endif
818 #endif
819
819
820 #if (CONFIG_AHBROM_START == 0) && (CONFIG_AHBROM_ENABLE == 1)
820 #if (CONFIG_AHBROM_START == 0) && (CONFIG_AHBROM_ENABLE == 1)
821 #define CONFIG_ROM_START 100
821 #define CONFIG_ROM_START 100
822 #else
822 #else
823 #define CONFIG_ROM_START 000
823 #define CONFIG_ROM_START 000
824 #endif
824 #endif
825
825
826
826
827 #ifndef CONFIG_AHBRAM_ENABLE
827 #ifndef CONFIG_AHBRAM_ENABLE
828 #define CONFIG_AHBRAM_ENABLE 0
828 #define CONFIG_AHBRAM_ENABLE 0
829 #endif
829 #endif
830
830
831 #ifndef CONFIG_AHBRAM_START
831 #ifndef CONFIG_AHBRAM_START
832 #define CONFIG_AHBRAM_START A00
832 #define CONFIG_AHBRAM_START A00
833 #endif
833 #endif
834
834
835 #if defined CONFIG_AHBRAM_SZ1
835 #if defined CONFIG_AHBRAM_SZ1
836 #define CFG_AHBRAMSZ 1
836 #define CFG_AHBRAMSZ 1
837 #elif CONFIG_AHBRAM_SZ2
837 #elif CONFIG_AHBRAM_SZ2
838 #define CFG_AHBRAMSZ 2
838 #define CFG_AHBRAMSZ 2
839 #elif CONFIG_AHBRAM_SZ4
839 #elif CONFIG_AHBRAM_SZ4
840 #define CFG_AHBRAMSZ 4
840 #define CFG_AHBRAMSZ 4
841 #elif CONFIG_AHBRAM_SZ8
841 #elif CONFIG_AHBRAM_SZ8
842 #define CFG_AHBRAMSZ 8
842 #define CFG_AHBRAMSZ 8
843 #elif CONFIG_AHBRAM_SZ16
843 #elif CONFIG_AHBRAM_SZ16
844 #define CFG_AHBRAMSZ 16
844 #define CFG_AHBRAMSZ 16
845 #elif CONFIG_AHBRAM_SZ32
845 #elif CONFIG_AHBRAM_SZ32
846 #define CFG_AHBRAMSZ 32
846 #define CFG_AHBRAMSZ 32
847 #elif CONFIG_AHBRAM_SZ64
847 #elif CONFIG_AHBRAM_SZ64
848 #define CFG_AHBRAMSZ 64
848 #define CFG_AHBRAMSZ 64
849 #else
849 #else
850 #define CFG_AHBRAMSZ 1
850 #define CFG_AHBRAMSZ 1
851 #endif
851 #endif
852
852
853 #ifndef CONFIG_GRETH_ENABLE
853 #ifndef CONFIG_GRETH_ENABLE
854 #define CONFIG_GRETH_ENABLE 0
854 #define CONFIG_GRETH_ENABLE 0
855 #endif
855 #endif
856
856
857 #ifndef CONFIG_GRETH_GIGA
857 #ifndef CONFIG_GRETH_GIGA
858 #define CONFIG_GRETH_GIGA 0
858 #define CONFIG_GRETH_GIGA 0
859 #endif
859 #endif
860
860
861 #if defined CONFIG_GRETH_FIFO4
861 #if defined CONFIG_GRETH_FIFO4
862 #define CFG_GRETH_FIFO 4
862 #define CFG_GRETH_FIFO 4
863 #elif defined CONFIG_GRETH_FIFO8
863 #elif defined CONFIG_GRETH_FIFO8
864 #define CFG_GRETH_FIFO 8
864 #define CFG_GRETH_FIFO 8
865 #elif defined CONFIG_GRETH_FIFO16
865 #elif defined CONFIG_GRETH_FIFO16
866 #define CFG_GRETH_FIFO 16
866 #define CFG_GRETH_FIFO 16
867 #elif defined CONFIG_GRETH_FIFO32
867 #elif defined CONFIG_GRETH_FIFO32
868 #define CFG_GRETH_FIFO 32
868 #define CFG_GRETH_FIFO 32
869 #elif defined CONFIG_GRETH_FIFO64
869 #elif defined CONFIG_GRETH_FIFO64
870 #define CFG_GRETH_FIFO 64
870 #define CFG_GRETH_FIFO 64
871 #else
871 #else
872 #define CFG_GRETH_FIFO 8
872 #define CFG_GRETH_FIFO 8
873 #endif
873 #endif
874
874
875 #ifndef CONFIG_UART1_ENABLE
875 #ifndef CONFIG_UART1_ENABLE
876 #define CONFIG_UART1_ENABLE 0
876 #define CONFIG_UART1_ENABLE 0
877 #endif
877 #endif
878
878
879 #if defined CONFIG_UA1_FIFO1
879 #if defined CONFIG_UA1_FIFO1
880 #define CFG_UA1_FIFO 1
880 #define CFG_UA1_FIFO 1
881 #elif defined CONFIG_UA1_FIFO2
881 #elif defined CONFIG_UA1_FIFO2
882 #define CFG_UA1_FIFO 2
882 #define CFG_UA1_FIFO 2
883 #elif defined CONFIG_UA1_FIFO4
883 #elif defined CONFIG_UA1_FIFO4
884 #define CFG_UA1_FIFO 4
884 #define CFG_UA1_FIFO 4
885 #elif defined CONFIG_UA1_FIFO8
885 #elif defined CONFIG_UA1_FIFO8
886 #define CFG_UA1_FIFO 8
886 #define CFG_UA1_FIFO 8
887 #elif defined CONFIG_UA1_FIFO16
887 #elif defined CONFIG_UA1_FIFO16
888 #define CFG_UA1_FIFO 16
888 #define CFG_UA1_FIFO 16
889 #elif defined CONFIG_UA1_FIFO32
889 #elif defined CONFIG_UA1_FIFO32
890 #define CFG_UA1_FIFO 32
890 #define CFG_UA1_FIFO 32
891 #else
891 #else
892 #define CFG_UA1_FIFO 1
892 #define CFG_UA1_FIFO 1
893 #endif
893 #endif
894
894
895 #ifndef CONFIG_IRQ3_ENABLE
895 #ifndef CONFIG_IRQ3_ENABLE
896 #define CONFIG_IRQ3_ENABLE 0
896 #define CONFIG_IRQ3_ENABLE 0
897 #endif
897 #endif
898 #ifndef CONFIG_IRQ3_NSEC
898 #ifndef CONFIG_IRQ3_NSEC
899 #define CONFIG_IRQ3_NSEC 0
899 #define CONFIG_IRQ3_NSEC 0
900 #endif
900 #endif
901 #ifndef CONFIG_GPT_ENABLE
901 #ifndef CONFIG_GPT_ENABLE
902 #define CONFIG_GPT_ENABLE 0
902 #define CONFIG_GPT_ENABLE 0
903 #endif
903 #endif
904
904
905 #ifndef CONFIG_GPT_NTIM
905 #ifndef CONFIG_GPT_NTIM
906 #define CONFIG_GPT_NTIM 1
906 #define CONFIG_GPT_NTIM 1
907 #endif
907 #endif
908
908
909 #ifndef CONFIG_GPT_SW
909 #ifndef CONFIG_GPT_SW
910 #define CONFIG_GPT_SW 8
910 #define CONFIG_GPT_SW 8
911 #endif
911 #endif
912
912
913 #ifndef CONFIG_GPT_TW
913 #ifndef CONFIG_GPT_TW
914 #define CONFIG_GPT_TW 8
914 #define CONFIG_GPT_TW 8
915 #endif
915 #endif
916
916
917 #ifndef CONFIG_GPT_IRQ
917 #ifndef CONFIG_GPT_IRQ
918 #define CONFIG_GPT_IRQ 8
918 #define CONFIG_GPT_IRQ 8
919 #endif
919 #endif
920
920
921 #ifndef CONFIG_GPT_SEPIRQ
921 #ifndef CONFIG_GPT_SEPIRQ
922 #define CONFIG_GPT_SEPIRQ 0
922 #define CONFIG_GPT_SEPIRQ 0
923 #endif
923 #endif
924 #ifndef CONFIG_GPT_ENABLE
924 #ifndef CONFIG_GPT_ENABLE
925 #define CONFIG_GPT_ENABLE 0
925 #define CONFIG_GPT_ENABLE 0
926 #endif
926 #endif
927
927
928 #ifndef CONFIG_GPT_NTIM
928 #ifndef CONFIG_GPT_NTIM
929 #define CONFIG_GPT_NTIM 1
929 #define CONFIG_GPT_NTIM 1
930 #endif
930 #endif
931
931
932 #ifndef CONFIG_GPT_SW
932 #ifndef CONFIG_GPT_SW
933 #define CONFIG_GPT_SW 8
933 #define CONFIG_GPT_SW 8
934 #endif
934 #endif
935
935
936 #ifndef CONFIG_GPT_TW
936 #ifndef CONFIG_GPT_TW
937 #define CONFIG_GPT_TW 8
937 #define CONFIG_GPT_TW 8
938 #endif
938 #endif
939
939
940 #ifndef CONFIG_GPT_IRQ
940 #ifndef CONFIG_GPT_IRQ
941 #define CONFIG_GPT_IRQ 8
941 #define CONFIG_GPT_IRQ 8
942 #endif
942 #endif
943
943
944 #ifndef CONFIG_GPT_SEPIRQ
944 #ifndef CONFIG_GPT_SEPIRQ
945 #define CONFIG_GPT_SEPIRQ 0
945 #define CONFIG_GPT_SEPIRQ 0
946 #endif
946 #endif
947
947
948 #ifndef CONFIG_GPT_WDOGEN
948 #ifndef CONFIG_GPT_WDOGEN
949 #define CONFIG_GPT_WDOGEN 0
949 #define CONFIG_GPT_WDOGEN 0
950 #endif
950 #endif
951
951
952 #ifndef CONFIG_GPT_WDOG
952 #ifndef CONFIG_GPT_WDOG
953 #define CONFIG_GPT_WDOG 0
953 #define CONFIG_GPT_WDOG 0
954 #endif
954 #endif
955
955
956 #ifndef CONFIG_GRGPIO_ENABLE
956 #ifndef CONFIG_GRGPIO_ENABLE
957 #define CONFIG_GRGPIO_ENABLE 0
957 #define CONFIG_GRGPIO_ENABLE 0
958 #endif
958 #endif
959 #ifndef CONFIG_GRGPIO_IMASK
959 #ifndef CONFIG_GRGPIO_IMASK
960 #define CONFIG_GRGPIO_IMASK 0000
960 #define CONFIG_GRGPIO_IMASK 0000
961 #endif
961 #endif
962 #ifndef CONFIG_GRGPIO_WIDTH
962 #ifndef CONFIG_GRGPIO_WIDTH
963 #define CONFIG_GRGPIO_WIDTH 1
963 #define CONFIG_GRGPIO_WIDTH 1
964 #endif
964 #endif
965
965
966 #ifndef CONFIG_VGA_ENABLE
966 #ifndef CONFIG_VGA_ENABLE
967 #define CONFIG_VGA_ENABLE 0
967 #define CONFIG_VGA_ENABLE 0
968 #endif
968 #endif
969 #ifndef CONFIG_SVGA_ENABLE
969 #ifndef CONFIG_SVGA_ENABLE
970 #define CONFIG_SVGA_ENABLE 0
970 #define CONFIG_SVGA_ENABLE 0
971 #endif
971 #endif
972 #ifndef CONFIG_KBD_ENABLE
972 #ifndef CONFIG_KBD_ENABLE
973 #define CONFIG_KBD_ENABLE 0
973 #define CONFIG_KBD_ENABLE 0
974 #endif
974 #endif
975
975
976
976
977 #ifndef CONFIG_SPIMCTRL
977 #ifndef CONFIG_SPIMCTRL
978 #define CONFIG_SPIMCTRL 0
978 #define CONFIG_SPIMCTRL 0
979 #endif
979 #endif
980
980
981 #ifndef CONFIG_SPIMCTRL_SDCARD
981 #ifndef CONFIG_SPIMCTRL_SDCARD
982 #define CONFIG_SPIMCTRL_SDCARD 0
982 #define CONFIG_SPIMCTRL_SDCARD 0
983 #endif
983 #endif
984
984
985 #ifndef CONFIG_SPIMCTRL_READCMD
985 #ifndef CONFIG_SPIMCTRL_READCMD
986 #define CONFIG_SPIMCTRL_READCMD 0
986 #define CONFIG_SPIMCTRL_READCMD 0
987 #endif
987 #endif
988
988
989 #ifndef CONFIG_SPIMCTRL_DUMMYBYTE
989 #ifndef CONFIG_SPIMCTRL_DUMMYBYTE
990 #define CONFIG_SPIMCTRL_DUMMYBYTE 0
990 #define CONFIG_SPIMCTRL_DUMMYBYTE 0
991 #endif
991 #endif
992
992
993 #ifndef CONFIG_SPIMCTRL_DUALOUTPUT
993 #ifndef CONFIG_SPIMCTRL_DUALOUTPUT
994 #define CONFIG_SPIMCTRL_DUALOUTPUT 0
994 #define CONFIG_SPIMCTRL_DUALOUTPUT 0
995 #endif
995 #endif
996
996
997 #ifndef CONFIG_SPIMCTRL_SCALER
997 #ifndef CONFIG_SPIMCTRL_SCALER
998 #define CONFIG_SPIMCTRL_SCALER 1
998 #define CONFIG_SPIMCTRL_SCALER 1
999 #endif
999 #endif
1000
1000
1001 #ifndef CONFIG_SPIMCTRL_ASCALER
1001 #ifndef CONFIG_SPIMCTRL_ASCALER
1002 #define CONFIG_SPIMCTRL_ASCALER 1
1002 #define CONFIG_SPIMCTRL_ASCALER 1
1003 #endif
1003 #endif
1004
1004
1005 #ifndef CONFIG_SPIMCTRL_PWRUPCNT
1005 #ifndef CONFIG_SPIMCTRL_PWRUPCNT
1006 #define CONFIG_SPIMCTRL_PWRUPCNT 0
1006 #define CONFIG_SPIMCTRL_PWRUPCNT 0
1007 #endif
1007 #endif
1008 #ifndef CONFIG_SPICTRL_ENABLE
1008 #ifndef CONFIG_SPICTRL_ENABLE
1009 #define CONFIG_SPICTRL_ENABLE 0
1009 #define CONFIG_SPICTRL_ENABLE 0
1010 #endif
1010 #endif
1011 #ifndef CONFIG_SPICTRL_NUM
1011 #ifndef CONFIG_SPICTRL_NUM
1012 #define CONFIG_SPICTRL_NUM 1
1012 #define CONFIG_SPICTRL_NUM 1
1013 #endif
1013 #endif
1014 #ifndef CONFIG_SPICTRL_SLVS
1014 #ifndef CONFIG_SPICTRL_SLVS
1015 #define CONFIG_SPICTRL_SLVS 1
1015 #define CONFIG_SPICTRL_SLVS 1
1016 #endif
1016 #endif
1017 #ifndef CONFIG_SPICTRL_FIFO
1017 #ifndef CONFIG_SPICTRL_FIFO
1018 #define CONFIG_SPICTRL_FIFO 1
1018 #define CONFIG_SPICTRL_FIFO 1
1019 #endif
1019 #endif
1020 #ifndef CONFIG_SPICTRL_SLVREG
1020 #ifndef CONFIG_SPICTRL_SLVREG
1021 #define CONFIG_SPICTRL_SLVREG 0
1021 #define CONFIG_SPICTRL_SLVREG 0
1022 #endif
1022 #endif
1023 #ifndef CONFIG_SPICTRL_ODMODE
1023 #ifndef CONFIG_SPICTRL_ODMODE
1024 #define CONFIG_SPICTRL_ODMODE 0
1024 #define CONFIG_SPICTRL_ODMODE 0
1025 #endif
1025 #endif
1026 #ifndef CONFIG_SPICTRL_AM
1026 #ifndef CONFIG_SPICTRL_AM
1027 #define CONFIG_SPICTRL_AM 0
1027 #define CONFIG_SPICTRL_AM 0
1028 #endif
1028 #endif
1029 #ifndef CONFIG_SPICTRL_ASEL
1029 #ifndef CONFIG_SPICTRL_ASEL
1030 #define CONFIG_SPICTRL_ASEL 0
1030 #define CONFIG_SPICTRL_ASEL 0
1031 #endif
1031 #endif
1032 #ifndef CONFIG_SPICTRL_TWEN
1032 #ifndef CONFIG_SPICTRL_TWEN
1033 #define CONFIG_SPICTRL_TWEN 0
1033 #define CONFIG_SPICTRL_TWEN 0
1034 #endif
1034 #endif
1035 #ifndef CONFIG_SPICTRL_MAXWLEN
1035 #ifndef CONFIG_SPICTRL_MAXWLEN
1036 #define CONFIG_SPICTRL_MAXWLEN 0
1036 #define CONFIG_SPICTRL_MAXWLEN 0
1037 #endif
1037 #endif
1038 #ifndef CONFIG_SPICTRL_SYNCRAM
1038 #ifndef CONFIG_SPICTRL_SYNCRAM
1039 #define CONFIG_SPICTRL_SYNCRAM 0
1039 #define CONFIG_SPICTRL_SYNCRAM 0
1040 #endif
1040 #endif
1041 #if defined(CONFIG_SPICTRL_DMRFT)
1041 #if defined(CONFIG_SPICTRL_DMRFT)
1042 #define CONFIG_SPICTRL_FT 1
1042 #define CONFIG_SPICTRL_FT 1
1043 #elif defined(CONFIG_SPICTRL_TMRFT)
1043 #elif defined(CONFIG_SPICTRL_TMRFT)
1044 #define CONFIG_SPICTRL_FT 2
1044 #define CONFIG_SPICTRL_FT 2
1045 #else
1045 #else
1046 #define CONFIG_SPICTRL_FT 0
1046 #define CONFIG_SPICTRL_FT 0
1047 #endif
1047 #endif
1048
1048
1049 #ifndef CONFIG_DEBUG_UART
1049 #ifndef CONFIG_DEBUG_UART
1050 #define CONFIG_DEBUG_UART 0
1050 #define CONFIG_DEBUG_UART 0
1051 #endif
1051 #endif
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@@ -1,169 +1,169
1
1
2 This leon3 design is tailored to the Digilent Spartan3-1600E Evaluation board:
2 This leon3 design is tailored to the Digilent Spartan3-1600E Evaluation board:
3
3
4 http://www.digilentinc.com/Products/Detail.cfm?Prod=S3E1600&Nav1=Products&Nav2=Programmable
4 http://www.digilentinc.com/Products/Detail.cfm?Prod=S3E1600&Nav1=Products&Nav2=Programmable
5
5
6 Design specifics:
6 Design specifics:
7
7
8 * System reset is mapped to SW_SOUTH (reset)
8 * System reset is mapped to SW_SOUTH (reset)
9
9
10 * DSU break is mapped to SW_EAST
10 * DSU break is mapped to SW_EAST
11
11
12 * LED 0/1 indicates console UART RX and TX activity.
12 * LED 0/1 indicates console UART RX and TX activity.
13
13
14 * LED 2/3 indicates DSU UART RX and TX activity.
14 * LED 2/3 indicates DSU UART RX and TX activity.
15
15
16 * LED 4 indicates processor in debug mode
16 * LED 4 indicates processor in debug mode
17
17
18 * LED 7 indicates processor in error mode
18 * LED 7 indicates processor in error mode
19
19
20 * The GRETH core is enabled and runs without problems at 100 Mbit.
20 * The GRETH core is enabled and runs without problems at 100 Mbit.
21 Ethernet debug link is enabled, default IP is 192.168.0.51.
21 Ethernet debug link is enabled, default IP is 192.168.0.51.
22
22
23 * 16-bit flash prom can be read at address 0. It can be programmed
23 * 16-bit flash prom can be read at address 0. It can be programmed
24 with GRMON version 1.1.16 or later.
24 with GRMON version 1.1.16 or later.
25
25
26 * DDR is mapped at address 0x40000000 (64 Mbyte) and is clocked
26 * DDR is mapped at address 0x40000000 (64 Mbyte) and is clocked
27 at 100 MHz. The processor and AMBA system runs on a different
27 at 100 MHz. The processor and AMBA system runs on a different
28 clock, and can typically reach 40 MHz. The processor clock
28 clock, and can typically reach 40 MHz. The processor clock
29 is generated from the 50 MHz clock oscillator, scaled with the
29 is generated from the 50 MHz clock oscillator, scaled with the
30 DCM factors (4/5) in xconfig.
30 DCM factors (4/5) in xconfig.
31
31
32 * The APBPS2 PS/2 core is attached to the PS/2 connector
32 * The APBPS2 PS/2 core is attached to the PS/2 connector
33
33
34 * The SVGA frame buffer runs fine with 800x600 resolution. Due to the
34 * The SVGA frame buffer runs fine with 800x600 resolution. Due to the
35 limited number of clock buffers, no other resoltion is supported.
35 limited number of clock buffers, no other resoltion is supported.
36 Note that the board does not have a video DAC, so only the MSB bit (7)
36 Note that the board does not have a video DAC, so only the MSB bit (7)
37 of the three colour channels is connected to the VGA connector.
37 of the three colour channels is connected to the VGA connector.
38
38
39 A test patter can be generated using grmon-1.1.18 or later with:
39 A test patter can be generated using grmon-1.1.18 or later with:
40
40
41 draw test_screen 800 16
41 draw test_screen 800 16
42
42
43 * The DSU uart is connected to the female RS232 connected.
43 * The DSU uart is connected to the female RS232 connected.
44 The application UART1 is connected to the male RS232 connector.
44 The application UART1 is connected to the male RS232 connector.
45
45
46 * The JTAG DSU interface is enabled.
46 * The JTAG DSU interface is enabled.
47
47
48 * Output from GRMON info sys is:
48 * Output from GRMON info sys is:
49
49
50
50
51 ethernet startup.
51 ethernet startup.
52 GRLIB build version: 4090
52 GRLIB build version: 4090
53
53
54 initialising ..............
54 initialising ..............
55 detected frequency: 40 MHz
55 detected frequency: 40 MHz
56
56
57 Component Vendor
57 Component Vendor
58 LEON3 SPARC V8 Processor Gaisler Research
58 LEON3 SPARC V8 Processor Gaisler Research
59 AHB Debug UART Gaisler Research
59 AHB Debug UART Gaisler Research
60 AHB Debug JTAG TAP Gaisler Research
60 AHB Debug JTAG TAP Gaisler Research
61 SVGA Controller Gaisler Research
61 SVGA Controller Gaisler Research
62 GR Ethernet MAC Gaisler Research
62 GR Ethernet MAC Gaisler Research
63 AHB/APB Bridge Gaisler Research
63 AHB/APB Bridge Gaisler Research
64 LEON3 Debug Support Unit Gaisler Research
64 LEON3 Debug Support Unit Gaisler Research
65 DDR266 Controller Gaisler Research
65 DDR266 Controller Gaisler Research
66 LEON2 Memory Controller European Space Agency
66 LEON2 Memory Controller European Space Agency
67 Generic APB UART Gaisler Research
67 Generic APB UART Gaisler Research
68 Multi-processor Interrupt Ctrl Gaisler Research
68 Multi-processor Interrupt Ctrl Gaisler Research
69 Modular Timer Unit Gaisler Research
69 Modular Timer Unit Gaisler Research
70 PS/2 interface Gaisler Research
70 PS/2 interface Gaisler Research
71 General purpose I/O port Gaisler Research
71 General purpose I/O port Gaisler Research
72
72
73 Use command 'info sys' to print a detailed report of attached cores
73 Use command 'info sys' to print a detailed report of attached cores
74
74
75 grlib> inf sys
75 grlib> inf sys
76 00.01:003 Gaisler Research LEON3 SPARC V8 Processor (ver 0x0)
76 00.01:003 Gaisler Research LEON3 SPARC V8 Processor (ver 0x0)
77 ahb master 0
77 ahb master 0
78 01.01:007 Gaisler Research AHB Debug UART (ver 0x0)
78 01.01:007 Gaisler Research AHB Debug UART (ver 0x0)
79 ahb master 1
79 ahb master 1
80 apb: 80000700 - 80000800
80 apb: 80000700 - 80000800
81 baud rate 115200, ahb frequency 40.00
81 baud rate 115200, ahb frequency 40.00
82 02.01:01c Gaisler Research AHB Debug JTAG TAP (ver 0x0)
82 02.01:01c Gaisler Research AHB Debug JTAG TAP (ver 0x0)
83 ahb master 2
83 ahb master 2
84 03.01:063 Gaisler Research SVGA Controller (ver 0x0)
84 03.01:063 Gaisler Research SVGA Controller (ver 0x0)
85 ahb master 3
85 ahb master 3
86 apb: 80000600 - 80000700
86 apb: 80000600 - 80000700
87 clk0: 40.00 MHz
87 clk0: 40.00 MHz
88 04.01:01d Gaisler Research GR Ethernet MAC (ver 0x0)
88 04.01:01d Gaisler Research GR Ethernet MAC (ver 0x0)
89 ahb master 4, irq 12
89 ahb master 4, irq 12
90 apb: 80000f00 - 80001000
90 apb: 80000f00 - 80001000
91 edcl ip 192.168.0.51, buffer 2 kbyte
91 edcl ip 192.168.0.51, buffer 2 kbyte
92 01.01:006 Gaisler Research AHB/APB Bridge (ver 0x0)
92 01.01:006 Gaisler Research AHB/APB Bridge (ver 0x0)
93 ahb: 80000000 - 80100000
93 ahb: 80000000 - 80100000
94 02.01:004 Gaisler Research LEON3 Debug Support Unit (ver 0x1)
94 02.01:004 Gaisler Research LEON3 Debug Support Unit (ver 0x1)
95 ahb: 90000000 - a0000000
95 ahb: 90000000 - a0000000
96 AHB trace 256 lines, 32-bit bus, stack pointer 0x43fffff0
96 AHB trace 256 lines, 32-bit bus, stack pointer 0x43fffff0
97 CPU#0 win 8, hwbp 2, itrace 256, V8 mul/div, srmmu, lddel 1, GRFPU-lite
97 CPU#0 win 8, hwbp 2, itrace 256, V8 mul/div, srmmu, lddel 1, GRFPU-lite
98 icache 2 * 4 kbyte, 32 byte/line rnd
98 icache 2 * 4 kbyte, 32 byte/line rnd
99 dcache 2 * 4 kbyte, 16 byte/line rnd
99 dcache 2 * 4 kbyte, 16 byte/line rnd
100 04.01:025 Gaisler Research DDR266 Controller (ver 0x0)
100 04.01:025 Gaisler Research DDR266 Controller (ver 0x0)
101 ahb: 40000000 - 50000000
101 ahb: 40000000 - 50000000
102 ahb: fff00100 - fff00200
102 ahb: fff00100 - fff00200
103 16-bit DDR : 1 * 64 Mbyte @ 0x40000000
103 16-bit DDR : 1 * 64 Mbyte @ 0x40000000
104 100 MHz, col 10, ref 7.8 us, trfc 80 ns
104 100 MHz, col 10, ref 7.8 us, trfc 80 ns
105 05.04:00f European Space Agency LEON2 Memory Controller (ver 0x1)
105 05.04:00f European Space Agency LEON2 Memory Controller (ver 0x1)
106 ahb: 00000000 - 20000000
106 ahb: 00000000 - 20000000
107 ahb: 20000000 - 40000000
107 ahb: 20000000 - 40000000
108 ahb: 60000000 - 70000000
108 ahb: 60000000 - 70000000
109 apb: 80000000 - 80000100
109 apb: 80000000 - 80000100
110 16-bit prom @ 0x00000000
110 16-bit prom @ 0x00000000
111 01.01:00c Gaisler Research Generic APB UART (ver 0x1)
111 01.01:00c Gaisler Research Generic APB UART (ver 0x1)
112 irq 2
112 irq 2
113 apb: 80000100 - 80000200
113 apb: 80000100 - 80000200
114 baud rate 38461, DSU mode (FIFO debug)
114 baud rate 38461, DSU mode (FIFO debug)
115 02.01:00d Gaisler Research Multi-processor Interrupt Ctrl (ver 0x3)
115 02.01:00d Gaisler Research Multi-processor Interrupt Ctrl (ver 0x3)
116 apb: 80000200 - 80000300
116 apb: 80000200 - 80000300
117 03.01:011 Gaisler Research Modular Timer Unit (ver 0x0)
117 03.01:011 Gaisler Research Modular Timer Unit (ver 0x0)
118 irq 8
118 irq 8
119 apb: 80000300 - 80000400
119 apb: 80000300 - 80000400
120 8-bit scaler, 2 * 32-bit timers, divisor 40
120 8-bit scaler, 2 * 32-bit timers, divisor 40
121 05.01:060 Gaisler Research PS/2 interface (ver 0x2)
121 05.01:060 Gaisler Research PS/2 interface (ver 0x2)
122 irq 5
122 irq 5
123 apb: 80000500 - 80000600
123 apb: 80000500 - 80000600
124 0b.01:01a Gaisler Research General purpose I/O port (ver 0x0)
124 0b.01:01a Gaisler Research General purpose I/O port (ver 0x0)
125 apb: 80000b00 - 80000c00
125 apb: 80000b00 - 80000c00
126 grlib>
126 grlib>
127
127
128 grlib> flas
128 grlib> flas
129
129
130 Intel-style 16-bit flash on D[31:16]
130 Intel-style 16-bit flash on D[31:16]
131
131
132 Manuf. Intel
132 Manuf. Intel
133 Device MT28F128J3 )
133 Device MT28F128J3 )
134
134
135 Device ID 0418ffff008844d1
135 Device ID 0418ffff008844d1
136 User ID ffffffffffffffff
136 User ID ffffffffffffffff
137
137
138
138
139 1 x 16 Mbyte = 16 Mbyte total @ 0x00000000
139 1 x 16 Mbyte = 16 Mbyte total @ 0x00000000
140
140
141
141
142 CFI info
142 CFI info
143 flash family : 1
143 flash family : 1
144 flash size : 128 Mbit
144 flash size : 128 Mbit
145 erase regions : 1
145 erase regions : 1
146 erase blocks : 128
146 erase blocks : 128
147 write buffer : 32 bytes
147 write buffer : 32 bytes
148 region 0 : 128 blocks of 128 Kbytes
148 region 0 : 128 blocks of 128 Kbytes
149
149
150 grlib>
150 grlib>
151
151
152 grlib> lo ~/examples/dhry412
152 grlib> lo ~/examples/dhry412
153 section: .text at 0x40000000, size 53296 bytes
153 section: .text at 0x40000000, size 53296 bytes
154 section: .data at 0x4000d030, size 2764 bytes
154 section: .data at 0x4000d030, size 2764 bytes
155 total size: 56060 bytes (63.3 Mbit/s)
155 total size: 56060 bytes (63.3 Mbit/s)
156 read 262 symbols
156 read 262 symbols
157 entry point: 0x40000000
157 entry point: 0x40000000
158 grlib> run
158 grlib> run
159 Execution starts, 1000000 runs through Dhrystone
159 Execution starts, 1000000 runs through Dhrystone
160 Total execution time: 10.5 s
160 Total execution time: 10.5 s
161 Microseconds for one run through Dhrystone: 10.5
161 Microseconds for one run through Dhrystone: 10.5
162 Dhrystones per Second: 95073.0
162 Dhrystones per Second: 95073.0
163
163
164 Dhrystones MIPS : 54.1
164 Dhrystones MIPS : 54.1
165
165
166
166
167 Program exited normally.
167 Program exited normally.
168 grlib>
168 grlib>
169
169
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@@ -1,164 +1,164
1 -- Technology and synthesis options
1 -- Technology and synthesis options
2 constant CFG_FABTECH : integer := CONFIG_SYN_TECH;
2 constant CFG_FABTECH : integer := CONFIG_SYN_TECH;
3 constant CFG_MEMTECH : integer := CFG_RAM_TECH;
3 constant CFG_MEMTECH : integer := CFG_RAM_TECH;
4 constant CFG_PADTECH : integer := CFG_PAD_TECH;
4 constant CFG_PADTECH : integer := CFG_PAD_TECH;
5 constant CFG_NOASYNC : integer := CONFIG_SYN_NO_ASYNC;
5 constant CFG_NOASYNC : integer := CONFIG_SYN_NO_ASYNC;
6 constant CFG_SCAN : integer := CONFIG_SYN_SCAN;
6 constant CFG_SCAN : integer := CONFIG_SYN_SCAN;
7
7
8 -- Clock generator
8 -- Clock generator
9 constant CFG_CLKTECH : integer := CFG_CLK_TECH;
9 constant CFG_CLKTECH : integer := CFG_CLK_TECH;
10 constant CFG_CLKMUL : integer := CONFIG_CLK_MUL;
10 constant CFG_CLKMUL : integer := CONFIG_CLK_MUL;
11 constant CFG_CLKDIV : integer := CONFIG_CLK_DIV;
11 constant CFG_CLKDIV : integer := CONFIG_CLK_DIV;
12 constant CFG_OCLKDIV : integer := CONFIG_OCLK_DIV;
12 constant CFG_OCLKDIV : integer := CONFIG_OCLK_DIV;
13 constant CFG_OCLKBDIV : integer := CONFIG_OCLKB_DIV;
13 constant CFG_OCLKBDIV : integer := CONFIG_OCLKB_DIV;
14 constant CFG_OCLKCDIV : integer := CONFIG_OCLKC_DIV;
14 constant CFG_OCLKCDIV : integer := CONFIG_OCLKC_DIV;
15 constant CFG_PCIDLL : integer := CONFIG_PCI_CLKDLL;
15 constant CFG_PCIDLL : integer := CONFIG_PCI_CLKDLL;
16 constant CFG_PCISYSCLK: integer := CONFIG_PCI_SYSCLK;
16 constant CFG_PCISYSCLK: integer := CONFIG_PCI_SYSCLK;
17 constant CFG_CLK_NOFB : integer := CONFIG_CLK_NOFB;
17 constant CFG_CLK_NOFB : integer := CONFIG_CLK_NOFB;
18
18
19 -- LEON3 processor core
19 -- LEON3 processor core
20 constant CFG_LEON3 : integer := CONFIG_LEON3;
20 constant CFG_LEON3 : integer := CONFIG_LEON3;
21 constant CFG_NCPU : integer := CONFIG_PROC_NUM;
21 constant CFG_NCPU : integer := CONFIG_PROC_NUM;
22 constant CFG_NWIN : integer := CONFIG_IU_NWINDOWS;
22 constant CFG_NWIN : integer := CONFIG_IU_NWINDOWS;
23 constant CFG_V8 : integer := CFG_IU_V8;
23 constant CFG_V8 : integer := CFG_IU_V8;
24 constant CFG_MAC : integer := CONFIG_IU_MUL_MAC;
24 constant CFG_MAC : integer := CONFIG_IU_MUL_MAC;
25 constant CFG_BP : integer := CONFIG_IU_BP;
25 constant CFG_BP : integer := CONFIG_IU_BP;
26 constant CFG_SVT : integer := CONFIG_IU_SVT;
26 constant CFG_SVT : integer := CONFIG_IU_SVT;
27 constant CFG_RSTADDR : integer := 16#CONFIG_IU_RSTADDR#;
27 constant CFG_RSTADDR : integer := 16#CONFIG_IU_RSTADDR#;
28 constant CFG_LDDEL : integer := CONFIG_IU_LDELAY;
28 constant CFG_LDDEL : integer := CONFIG_IU_LDELAY;
29 constant CFG_NOTAG : integer := CONFIG_NOTAG;
29 constant CFG_NOTAG : integer := CONFIG_NOTAG;
30 constant CFG_NWP : integer := CONFIG_IU_WATCHPOINTS;
30 constant CFG_NWP : integer := CONFIG_IU_WATCHPOINTS;
31 constant CFG_PWD : integer := CONFIG_PWD*2;
31 constant CFG_PWD : integer := CONFIG_PWD*2;
32 constant CFG_FPU : integer := CONFIG_FPU + 16*CONFIG_FPU_NETLIST;
32 constant CFG_FPU : integer := CONFIG_FPU + 16*CONFIG_FPU_NETLIST;
33 constant CFG_GRFPUSH : integer := CONFIG_FPU_GRFPU_SHARED;
33 constant CFG_GRFPUSH : integer := CONFIG_FPU_GRFPU_SHARED;
34 constant CFG_ICEN : integer := CONFIG_ICACHE_ENABLE;
34 constant CFG_ICEN : integer := CONFIG_ICACHE_ENABLE;
35 constant CFG_ISETS : integer := CFG_IU_ISETS;
35 constant CFG_ISETS : integer := CFG_IU_ISETS;
36 constant CFG_ISETSZ : integer := CFG_ICACHE_SZ;
36 constant CFG_ISETSZ : integer := CFG_ICACHE_SZ;
37 constant CFG_ILINE : integer := CFG_ILINE_SZ;
37 constant CFG_ILINE : integer := CFG_ILINE_SZ;
38 constant CFG_IREPL : integer := CFG_ICACHE_ALGORND;
38 constant CFG_IREPL : integer := CFG_ICACHE_ALGORND;
39 constant CFG_ILOCK : integer := CONFIG_ICACHE_LOCK;
39 constant CFG_ILOCK : integer := CONFIG_ICACHE_LOCK;
40 constant CFG_ILRAMEN : integer := CONFIG_ICACHE_LRAM;
40 constant CFG_ILRAMEN : integer := CONFIG_ICACHE_LRAM;
41 constant CFG_ILRAMADDR: integer := 16#CONFIG_ICACHE_LRSTART#;
41 constant CFG_ILRAMADDR: integer := 16#CONFIG_ICACHE_LRSTART#;
42 constant CFG_ILRAMSZ : integer := CFG_ILRAM_SIZE;
42 constant CFG_ILRAMSZ : integer := CFG_ILRAM_SIZE;
43 constant CFG_DCEN : integer := CONFIG_DCACHE_ENABLE;
43 constant CFG_DCEN : integer := CONFIG_DCACHE_ENABLE;
44 constant CFG_DSETS : integer := CFG_IU_DSETS;
44 constant CFG_DSETS : integer := CFG_IU_DSETS;
45 constant CFG_DSETSZ : integer := CFG_DCACHE_SZ;
45 constant CFG_DSETSZ : integer := CFG_DCACHE_SZ;
46 constant CFG_DLINE : integer := CFG_DLINE_SZ;
46 constant CFG_DLINE : integer := CFG_DLINE_SZ;
47 constant CFG_DREPL : integer := CFG_DCACHE_ALGORND;
47 constant CFG_DREPL : integer := CFG_DCACHE_ALGORND;
48 constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK;
48 constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK;
49 constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG;
49 constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG;
50 constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#;
50 constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#;
51 constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM;
51 constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM;
52 constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#;
52 constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#;
53 constant CFG_DLRAMSZ : integer := CFG_DLRAM_SIZE;
53 constant CFG_DLRAMSZ : integer := CFG_DLRAM_SIZE;
54 constant CFG_MMUEN : integer := CONFIG_MMUEN;
54 constant CFG_MMUEN : integer := CONFIG_MMUEN;
55 constant CFG_ITLBNUM : integer := CONFIG_ITLBNUM;
55 constant CFG_ITLBNUM : integer := CONFIG_ITLBNUM;
56 constant CFG_DTLBNUM : integer := CONFIG_DTLBNUM;
56 constant CFG_DTLBNUM : integer := CONFIG_DTLBNUM;
57 constant CFG_TLB_TYPE : integer := CONFIG_TLB_TYPE + CFG_MMU_FASTWB*2;
57 constant CFG_TLB_TYPE : integer := CONFIG_TLB_TYPE + CFG_MMU_FASTWB*2;
58 constant CFG_TLB_REP : integer := CONFIG_TLB_REP;
58 constant CFG_TLB_REP : integer := CONFIG_TLB_REP;
59 constant CFG_MMU_PAGE : integer := CONFIG_MMU_PAGE;
59 constant CFG_MMU_PAGE : integer := CONFIG_MMU_PAGE;
60 constant CFG_DSU : integer := CONFIG_DSU_ENABLE;
60 constant CFG_DSU : integer := CONFIG_DSU_ENABLE;
61 constant CFG_ITBSZ : integer := CFG_DSU_ITB;
61 constant CFG_ITBSZ : integer := CFG_DSU_ITB;
62 constant CFG_ATBSZ : integer := CFG_DSU_ATB;
62 constant CFG_ATBSZ : integer := CFG_DSU_ATB;
63 constant CFG_LEON3FT_EN : integer := CONFIG_LEON3FT_EN;
63 constant CFG_LEON3FT_EN : integer := CONFIG_LEON3FT_EN;
64 constant CFG_IUFT_EN : integer := CONFIG_IUFT_EN;
64 constant CFG_IUFT_EN : integer := CONFIG_IUFT_EN;
65 constant CFG_FPUFT_EN : integer := CONFIG_FPUFT;
65 constant CFG_FPUFT_EN : integer := CONFIG_FPUFT;
66 constant CFG_RF_ERRINJ : integer := CONFIG_RF_ERRINJ;
66 constant CFG_RF_ERRINJ : integer := CONFIG_RF_ERRINJ;
67 constant CFG_CACHE_FT_EN : integer := CONFIG_CACHE_FT_EN;
67 constant CFG_CACHE_FT_EN : integer := CONFIG_CACHE_FT_EN;
68 constant CFG_CACHE_ERRINJ : integer := CONFIG_CACHE_ERRINJ;
68 constant CFG_CACHE_ERRINJ : integer := CONFIG_CACHE_ERRINJ;
69 constant CFG_LEON3_NETLIST: integer := CONFIG_LEON3_NETLIST;
69 constant CFG_LEON3_NETLIST: integer := CONFIG_LEON3_NETLIST;
70 constant CFG_DISAS : integer := CONFIG_IU_DISAS + CONFIG_IU_DISAS_NET;
70 constant CFG_DISAS : integer := CONFIG_IU_DISAS + CONFIG_IU_DISAS_NET;
71 constant CFG_PCLOW : integer := CFG_DEBUG_PC32;
71 constant CFG_PCLOW : integer := CFG_DEBUG_PC32;
72
72
73 -- AMBA settings
73 -- AMBA settings
74 constant CFG_DEFMST : integer := CONFIG_AHB_DEFMST;
74 constant CFG_DEFMST : integer := CONFIG_AHB_DEFMST;
75 constant CFG_RROBIN : integer := CONFIG_AHB_RROBIN;
75 constant CFG_RROBIN : integer := CONFIG_AHB_RROBIN;
76 constant CFG_SPLIT : integer := CONFIG_AHB_SPLIT;
76 constant CFG_SPLIT : integer := CONFIG_AHB_SPLIT;
77 constant CFG_AHBIO : integer := 16#CONFIG_AHB_IOADDR#;
77 constant CFG_AHBIO : integer := 16#CONFIG_AHB_IOADDR#;
78 constant CFG_APBADDR : integer := 16#CONFIG_APB_HADDR#;
78 constant CFG_APBADDR : integer := 16#CONFIG_APB_HADDR#;
79 constant CFG_AHB_MON : integer := CONFIG_AHB_MON;
79 constant CFG_AHB_MON : integer := CONFIG_AHB_MON;
80 constant CFG_AHB_MONERR : integer := CONFIG_AHB_MONERR;
80 constant CFG_AHB_MONERR : integer := CONFIG_AHB_MONERR;
81 constant CFG_AHB_MONWAR : integer := CONFIG_AHB_MONWAR;
81 constant CFG_AHB_MONWAR : integer := CONFIG_AHB_MONWAR;
82 constant CFG_AHB_DTRACE : integer := CONFIG_AHB_DTRACE;
82 constant CFG_AHB_DTRACE : integer := CONFIG_AHB_DTRACE;
83
83
84 -- DSU UART
84 -- DSU UART
85 constant CFG_AHB_UART : integer := CONFIG_DSU_UART;
85 constant CFG_AHB_UART : integer := CONFIG_DSU_UART;
86
86
87 -- JTAG based DSU interface
87 -- JTAG based DSU interface
88 constant CFG_AHB_JTAG : integer := CONFIG_DSU_JTAG;
88 constant CFG_AHB_JTAG : integer := CONFIG_DSU_JTAG;
89
89
90 -- Ethernet DSU
90 -- Ethernet DSU
91 constant CFG_DSU_ETH : integer := CONFIG_DSU_ETH + CONFIG_DSU_ETH_PROG;
91 constant CFG_DSU_ETH : integer := CONFIG_DSU_ETH + CONFIG_DSU_ETH_PROG;
92 constant CFG_ETH_BUF : integer := CFG_DSU_ETHB;
92 constant CFG_ETH_BUF : integer := CFG_DSU_ETHB;
93 constant CFG_ETH_IPM : integer := 16#CONFIG_DSU_IPMSB#;
93 constant CFG_ETH_IPM : integer := 16#CONFIG_DSU_IPMSB#;
94 constant CFG_ETH_IPL : integer := 16#CONFIG_DSU_IPLSB#;
94 constant CFG_ETH_IPL : integer := 16#CONFIG_DSU_IPLSB#;
95 constant CFG_ETH_ENM : integer := 16#CONFIG_DSU_ETHMSB#;
95 constant CFG_ETH_ENM : integer := 16#CONFIG_DSU_ETHMSB#;
96 constant CFG_ETH_ENL : integer := 16#CONFIG_DSU_ETHLSB#;
96 constant CFG_ETH_ENL : integer := 16#CONFIG_DSU_ETHLSB#;
97
97
98 -- LEON2 memory controller
98 -- LEON2 memory controller
99 constant CFG_MCTRL_LEON2 : integer := CONFIG_MCTRL_LEON2;
99 constant CFG_MCTRL_LEON2 : integer := CONFIG_MCTRL_LEON2;
100 constant CFG_MCTRL_RAM8BIT : integer := CONFIG_MCTRL_8BIT;
100 constant CFG_MCTRL_RAM8BIT : integer := CONFIG_MCTRL_8BIT;
101 constant CFG_MCTRL_RAM16BIT : integer := CONFIG_MCTRL_16BIT;
101 constant CFG_MCTRL_RAM16BIT : integer := CONFIG_MCTRL_16BIT;
102 constant CFG_MCTRL_5CS : integer := CONFIG_MCTRL_5CS;
102 constant CFG_MCTRL_5CS : integer := CONFIG_MCTRL_5CS;
103 constant CFG_MCTRL_SDEN : integer := CONFIG_MCTRL_SDRAM;
103 constant CFG_MCTRL_SDEN : integer := CONFIG_MCTRL_SDRAM;
104 constant CFG_MCTRL_SEPBUS : integer := CONFIG_MCTRL_SDRAM_SEPBUS;
104 constant CFG_MCTRL_SEPBUS : integer := CONFIG_MCTRL_SDRAM_SEPBUS;
105 constant CFG_MCTRL_INVCLK : integer := CONFIG_MCTRL_SDRAM_INVCLK;
105 constant CFG_MCTRL_INVCLK : integer := CONFIG_MCTRL_SDRAM_INVCLK;
106 constant CFG_MCTRL_SD64 : integer := CONFIG_MCTRL_SDRAM_BUS64;
106 constant CFG_MCTRL_SD64 : integer := CONFIG_MCTRL_SDRAM_BUS64;
107 constant CFG_MCTRL_PAGE : integer := CONFIG_MCTRL_PAGE + CONFIG_MCTRL_PROGPAGE;
107 constant CFG_MCTRL_PAGE : integer := CONFIG_MCTRL_PAGE + CONFIG_MCTRL_PROGPAGE;
108
108
109 -- DDR controller
109 -- DDR controller
110 constant CFG_DDRSP : integer := CONFIG_DDRSP;
110 constant CFG_DDRSP : integer := CONFIG_DDRSP;
111 constant CFG_DDRSP_INIT : integer := CONFIG_DDRSP_INIT;
111 constant CFG_DDRSP_INIT : integer := CONFIG_DDRSP_INIT;
112 constant CFG_DDRSP_FREQ : integer := CONFIG_DDRSP_FREQ;
112 constant CFG_DDRSP_FREQ : integer := CONFIG_DDRSP_FREQ;
113 constant CFG_DDRSP_COL : integer := CONFIG_DDRSP_COL;
113 constant CFG_DDRSP_COL : integer := CONFIG_DDRSP_COL;
114 constant CFG_DDRSP_SIZE : integer := CONFIG_DDRSP_MBYTE;
114 constant CFG_DDRSP_SIZE : integer := CONFIG_DDRSP_MBYTE;
115 constant CFG_DDRSP_RSKEW : integer := CONFIG_DDRSP_RSKEW;
115 constant CFG_DDRSP_RSKEW : integer := CONFIG_DDRSP_RSKEW;
116
116
117 -- AHB ROM
117 -- AHB ROM
118 constant CFG_AHBROMEN : integer := CONFIG_AHBROM_ENABLE;
118 constant CFG_AHBROMEN : integer := CONFIG_AHBROM_ENABLE;
119 constant CFG_AHBROPIP : integer := CONFIG_AHBROM_PIPE;
119 constant CFG_AHBROPIP : integer := CONFIG_AHBROM_PIPE;
120 constant CFG_AHBRODDR : integer := 16#CONFIG_AHBROM_START#;
120 constant CFG_AHBRODDR : integer := 16#CONFIG_AHBROM_START#;
121 constant CFG_ROMADDR : integer := 16#CONFIG_ROM_START#;
121 constant CFG_ROMADDR : integer := 16#CONFIG_ROM_START#;
122 constant CFG_ROMMASK : integer := 16#E00# + 16#CONFIG_ROM_START#;
122 constant CFG_ROMMASK : integer := 16#E00# + 16#CONFIG_ROM_START#;
123
123
124 -- AHB RAM
124 -- AHB RAM
125 constant CFG_AHBRAMEN : integer := CONFIG_AHBRAM_ENABLE;
125 constant CFG_AHBRAMEN : integer := CONFIG_AHBRAM_ENABLE;
126 constant CFG_AHBRSZ : integer := CFG_AHBRAMSZ;
126 constant CFG_AHBRSZ : integer := CFG_AHBRAMSZ;
127 constant CFG_AHBRADDR : integer := 16#CONFIG_AHBRAM_START#;
127 constant CFG_AHBRADDR : integer := 16#CONFIG_AHBRAM_START#;
128
128
129 -- Gaisler Ethernet core
129 -- Gaisler Ethernet core
130 constant CFG_GRETH : integer := CONFIG_GRETH_ENABLE;
130 constant CFG_GRETH : integer := CONFIG_GRETH_ENABLE;
131 constant CFG_GRETH1G : integer := CONFIG_GRETH_GIGA;
131 constant CFG_GRETH1G : integer := CONFIG_GRETH_GIGA;
132 constant CFG_ETH_FIFO : integer := CFG_GRETH_FIFO;
132 constant CFG_ETH_FIFO : integer := CFG_GRETH_FIFO;
133
133
134 -- UART 1
134 -- UART 1
135 constant CFG_UART1_ENABLE : integer := CONFIG_UART1_ENABLE;
135 constant CFG_UART1_ENABLE : integer := CONFIG_UART1_ENABLE;
136 constant CFG_UART1_FIFO : integer := CFG_UA1_FIFO;
136 constant CFG_UART1_FIFO : integer := CFG_UA1_FIFO;
137
137
138 -- LEON3 interrupt controller
138 -- LEON3 interrupt controller
139 constant CFG_IRQ3_ENABLE : integer := CONFIG_IRQ3_ENABLE;
139 constant CFG_IRQ3_ENABLE : integer := CONFIG_IRQ3_ENABLE;
140 constant CFG_IRQ3_NSEC : integer := CONFIG_IRQ3_NSEC;
140 constant CFG_IRQ3_NSEC : integer := CONFIG_IRQ3_NSEC;
141
141
142 -- Modular timer
142 -- Modular timer
143 constant CFG_GPT_ENABLE : integer := CONFIG_GPT_ENABLE;
143 constant CFG_GPT_ENABLE : integer := CONFIG_GPT_ENABLE;
144 constant CFG_GPT_NTIM : integer := CONFIG_GPT_NTIM;
144 constant CFG_GPT_NTIM : integer := CONFIG_GPT_NTIM;
145 constant CFG_GPT_SW : integer := CONFIG_GPT_SW;
145 constant CFG_GPT_SW : integer := CONFIG_GPT_SW;
146 constant CFG_GPT_TW : integer := CONFIG_GPT_TW;
146 constant CFG_GPT_TW : integer := CONFIG_GPT_TW;
147 constant CFG_GPT_IRQ : integer := CONFIG_GPT_IRQ;
147 constant CFG_GPT_IRQ : integer := CONFIG_GPT_IRQ;
148 constant CFG_GPT_SEPIRQ : integer := CONFIG_GPT_SEPIRQ;
148 constant CFG_GPT_SEPIRQ : integer := CONFIG_GPT_SEPIRQ;
149 constant CFG_GPT_WDOGEN : integer := CONFIG_GPT_WDOGEN;
149 constant CFG_GPT_WDOGEN : integer := CONFIG_GPT_WDOGEN;
150 constant CFG_GPT_WDOG : integer := 16#CONFIG_GPT_WDOG#;
150 constant CFG_GPT_WDOG : integer := 16#CONFIG_GPT_WDOG#;
151
151
152 -- GPIO port
152 -- GPIO port
153 constant CFG_GRGPIO_ENABLE : integer := CONFIG_GRGPIO_ENABLE;
153 constant CFG_GRGPIO_ENABLE : integer := CONFIG_GRGPIO_ENABLE;
154 constant CFG_GRGPIO_IMASK : integer := 16#CONFIG_GRGPIO_IMASK#;
154 constant CFG_GRGPIO_IMASK : integer := 16#CONFIG_GRGPIO_IMASK#;
155 constant CFG_GRGPIO_WIDTH : integer := CONFIG_GRGPIO_WIDTH;
155 constant CFG_GRGPIO_WIDTH : integer := CONFIG_GRGPIO_WIDTH;
156
156
157 -- VGA and PS2/ interface
157 -- VGA and PS2/ interface
158 constant CFG_KBD_ENABLE : integer := CONFIG_KBD_ENABLE;
158 constant CFG_KBD_ENABLE : integer := CONFIG_KBD_ENABLE;
159 constant CFG_VGA_ENABLE : integer := CONFIG_VGA_ENABLE;
159 constant CFG_VGA_ENABLE : integer := CONFIG_VGA_ENABLE;
160 constant CFG_SVGA_ENABLE : integer := CONFIG_SVGA_ENABLE;
160 constant CFG_SVGA_ENABLE : integer := CONFIG_SVGA_ENABLE;
161
161
162 -- GRLIB debugging
162 -- GRLIB debugging
163 constant CFG_DUART : integer := CONFIG_DEBUG_UART;
163 constant CFG_DUART : integer := CONFIG_DEBUG_UART;
164
164
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@@ -1,227 +1,227
1 [Library]
1 [Library]
2 grlib = modelsim/grlib
2 grlib = modelsim/grlib
3 unisim = modelsim/unisim
3 unisim = modelsim/unisim
4 dw02 = modelsim/dw02
4 dw02 = modelsim/dw02
5 synplify = modelsim/synplify
5 synplify = modelsim/synplify
6 techmap = modelsim/techmap
6 techmap = modelsim/techmap
7 eth = modelsim/eth
7 eth = modelsim/eth
8 gaisler = modelsim/gaisler
8 gaisler = modelsim/gaisler
9 esa = modelsim/esa
9 esa = modelsim/esa
10 fmf = modelsim/fmf
10 fmf = modelsim/fmf
11 spansion = modelsim/spansion
11 spansion = modelsim/spansion
12 gsi = modelsim/gsi
12 gsi = modelsim/gsi
13 lpp = modelsim/lpp
13 lpp = modelsim/lpp
14 cypress = modelsim/cypress
14 cypress = modelsim/cypress
15 hynix = modelsim/hynix
15 hynix = modelsim/hynix
16 micron = modelsim/micron
16 micron = modelsim/micron
17 work = modelsim/work
17 work = modelsim/work
18 std = $MODEL_TECH/../std
18 std = $MODEL_TECH/../std
19 ieee = $MODEL_TECH/../ieee
19 ieee = $MODEL_TECH/../ieee
20 vital2000 = $MODEL_TECH/../vital2000
20 vital2000 = $MODEL_TECH/../vital2000
21 verilog = $MODEL_TECH/../verilog
21 verilog = $MODEL_TECH/../verilog
22 arithmetic = $MODEL_TECH/../arithmetic
22 arithmetic = $MODEL_TECH/../arithmetic
23 mgc_portable = $MODEL_TECH/../mgc_portable
23 mgc_portable = $MODEL_TECH/../mgc_portable
24 std_developerskit = $MODEL_TECH/../std_developerskit
24 std_developerskit = $MODEL_TECH/../std_developerskit
25 synopsys = $MODEL_TECH/../synopsys
25 synopsys = $MODEL_TECH/../synopsys
26
26
27 [vcom]
27 [vcom]
28 ; Turn on VHDL-1993 as the default. Normally is off.
28 ; Turn on VHDL-1993 as the default. Normally is off.
29 VHDL93 = 1
29 VHDL93 = 1
30
30
31 ; Show source line containing error. Default is off.
31 ; Show source line containing error. Default is off.
32 Show_source = 1
32 Show_source = 1
33
33
34 ; Turn off unbound-component warnings. Default is on.
34 ; Turn off unbound-component warnings. Default is on.
35 Show_Warning1 = 0
35 Show_Warning1 = 0
36
36
37 ; Turn off process-without-a-wait-statement warnings. Default is on.
37 ; Turn off process-without-a-wait-statement warnings. Default is on.
38 ; Show_Warning2 = 0
38 ; Show_Warning2 = 0
39
39
40 ; Turn off null-range warnings. Default is on.
40 ; Turn off null-range warnings. Default is on.
41 ; Show_Warning3 = 0
41 ; Show_Warning3 = 0
42
42
43 ; Turn off no-space-in-time-literal warnings. Default is on.
43 ; Turn off no-space-in-time-literal warnings. Default is on.
44 ; Show_Warning4 = 0
44 ; Show_Warning4 = 0
45
45
46 ; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
46 ; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
47 Show_Warning5 = 0
47 Show_Warning5 = 0
48
48
49 ; Turn off optimization for IEEE std_logic_1164 package. Default is on.
49 ; Turn off optimization for IEEE std_logic_1164 package. Default is on.
50 ; Optimize_1164 = 0
50 ; Optimize_1164 = 0
51
51
52 ; Turn on resolving of ambiguous function overloading in favor of the
52 ; Turn on resolving of ambiguous function overloading in favor of the
53 ; "explicit" function declaration (not the one automatically created by
53 ; "explicit" function declaration (not the one automatically created by
54 ; the compiler for each type declaration). Default is off.
54 ; the compiler for each type declaration). Default is off.
55 Explicit = 1
55 Explicit = 1
56
56
57 ; Turn off VITAL compliance checking. Default is checking on.
57 ; Turn off VITAL compliance checking. Default is checking on.
58 ; NoVitalCheck = 1
58 ; NoVitalCheck = 1
59
59
60 ; Ignore VITAL compliance checking errors. Default is to not ignore.
60 ; Ignore VITAL compliance checking errors. Default is to not ignore.
61 ; IgnoreVitalErrors = 1
61 ; IgnoreVitalErrors = 1
62
62
63 ; Turn off VITAL compliance checking warnings. Default is to show warnings.
63 ; Turn off VITAL compliance checking warnings. Default is to show warnings.
64 ; Show_VitalChecksWarnings = false
64 ; Show_VitalChecksWarnings = false
65
65
66 ; Turn off acceleration of the VITAL packages. Default is to accelerate.
66 ; Turn off acceleration of the VITAL packages. Default is to accelerate.
67 ; NoVital = 1
67 ; NoVital = 1
68
68
69 ; Turn off inclusion of debugging info within design units. Default is to include.
69 ; Turn off inclusion of debugging info within design units. Default is to include.
70 ; NoDebug = 1
70 ; NoDebug = 1
71
71
72 ; Turn off "loading..." messages. Default is messages on.
72 ; Turn off "loading..." messages. Default is messages on.
73 Quiet = 1
73 Quiet = 1
74
74
75 ; Turn on some limited synthesis rule compliance checking. Checks only:
75 ; Turn on some limited synthesis rule compliance checking. Checks only:
76 ; -- signals used (read) by a process must be in the sensitivity list
76 ; -- signals used (read) by a process must be in the sensitivity list
77 ; CheckSynthesis = 1
77 ; CheckSynthesis = 1
78
78
79 [vlog]
79 [vlog]
80
80
81 ; Turn off inclusion of debugging info within design units. Default is to include.
81 ; Turn off inclusion of debugging info within design units. Default is to include.
82 ; NoDebug = 1
82 ; NoDebug = 1
83
83
84 ; Turn off "loading..." messages. Default is messages on.
84 ; Turn off "loading..." messages. Default is messages on.
85 Quiet = 1
85 Quiet = 1
86
86
87 ; Turn on Verilog hazard checking (order-dependent accessing of global vars).
87 ; Turn on Verilog hazard checking (order-dependent accessing of global vars).
88 ; Default is off.
88 ; Default is off.
89 ; Hazard = 1
89 ; Hazard = 1
90
90
91 ; Turn on converting regular Verilog identifiers to uppercase. Allows case
91 ; Turn on converting regular Verilog identifiers to uppercase. Allows case
92 ; insensitivity for module names. Default is no conversion.
92 ; insensitivity for module names. Default is no conversion.
93 ; UpCase = 1
93 ; UpCase = 1
94
94
95 [vsim]
95 [vsim]
96
96
97 ; vopt flow
97 ; vopt flow
98 ; Set to turn on automatic optimization of a design.
98 ; Set to turn on automatic optimization of a design.
99 ; Default is off (pre-6.0 flow without vopt).
99 ; Default is off (pre-6.0 flow without vopt).
100 VoptFlow = 0
100 VoptFlow = 0
101
101
102 ; Simulator resolution
102 ; Simulator resolution
103 ; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
103 ; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
104 Resolution = 1ps
104 Resolution = 1ps
105
105
106 ; User time unit for run commands
106 ; User time unit for run commands
107 ; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
107 ; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
108 ; unit specified for Resolution. For example, if Resolution is 100ps,
108 ; unit specified for Resolution. For example, if Resolution is 100ps,
109 ; then UserTimeUnit defaults to ps.
109 ; then UserTimeUnit defaults to ps.
110 UserTimeUnit = ns
110 UserTimeUnit = ns
111
111
112 ; Default run length
112 ; Default run length
113 RunLength = 100
113 RunLength = 100
114
114
115 ; Maximum iterations that can be run without advancing simulation time
115 ; Maximum iterations that can be run without advancing simulation time
116 IterationLimit = 5000
116 IterationLimit = 5000
117
117
118 ; Directive to license manager:
118 ; Directive to license manager:
119 ; vhdl Immediately reserve a VHDL license
119 ; vhdl Immediately reserve a VHDL license
120 ; vlog Immediately reserve a Verilog license
120 ; vlog Immediately reserve a Verilog license
121 ; plus Immediately reserve a VHDL and Verilog license
121 ; plus Immediately reserve a VHDL and Verilog license
122 ; nomgc Do not look for Mentor Graphics Licenses
122 ; nomgc Do not look for Mentor Graphics Licenses
123 ; nomti Do not look for Model Technology Licenses
123 ; nomti Do not look for Model Technology Licenses
124 ; noqueue Do not wait in the license queue when a license isn't available
124 ; noqueue Do not wait in the license queue when a license isn't available
125 ; License = plus
125 ; License = plus
126
126
127 ; Stop the simulator after an assertion message
127 ; Stop the simulator after an assertion message
128 ; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
128 ; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
129 BreakOnAssertion = 3
129 BreakOnAssertion = 3
130
130
131 ; Assertion Message Format
131 ; Assertion Message Format
132 ; %S - Severity Level
132 ; %S - Severity Level
133 ; %R - Report Message
133 ; %R - Report Message
134 ; %T - Time of assertion
134 ; %T - Time of assertion
135 ; %D - Delta
135 ; %D - Delta
136 ; %I - Instance or Region pathname (if available)
136 ; %I - Instance or Region pathname (if available)
137 ; %% - print '%' character
137 ; %% - print '%' character
138 ; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
138 ; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
139
139
140 ; Default radix for all windows and commands...
140 ; Default radix for all windows and commands...
141 ; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
141 ; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
142 DefaultRadix = symbolic
142 DefaultRadix = symbolic
143
143
144 ; VSIM Startup command
144 ; VSIM Startup command
145 ; Startup = do startup.do
145 ; Startup = do startup.do
146
146
147 ; File for saving command transcript
147 ; File for saving command transcript
148 TranscriptFile = transcript
148 TranscriptFile = transcript
149
149
150 ; Specify whether paths in simulator commands should be described
150 ; Specify whether paths in simulator commands should be described
151 ; in VHDL or Verilog format. For VHDL, PathSeparator = /
151 ; in VHDL or Verilog format. For VHDL, PathSeparator = /
152 ; for Verilog, PathSeparator = .
152 ; for Verilog, PathSeparator = .
153 PathSeparator = /
153 PathSeparator = /
154
154
155 ; Disable assertion messages
155 ; Disable assertion messages
156 ; IgnoreNote = 1
156 ; IgnoreNote = 1
157 ; IgnoreWarning = 1
157 ; IgnoreWarning = 1
158 ; IgnoreError = 1
158 ; IgnoreError = 1
159 ; IgnoreFailure = 1
159 ; IgnoreFailure = 1
160
160
161 ; Default force kind. May be freeze, drive, or deposit
161 ; Default force kind. May be freeze, drive, or deposit
162 ; or in other terms, fixed, wired or charged.
162 ; or in other terms, fixed, wired or charged.
163 ; DefaultForceKind = freeze
163 ; DefaultForceKind = freeze
164
164
165 ; If zero, open files when elaborated
165 ; If zero, open files when elaborated
166 ; else open files on first read or write
166 ; else open files on first read or write
167 ; DelayFileOpen = 0
167 ; DelayFileOpen = 0
168
168
169 ; Control VHDL files opened for write
169 ; Control VHDL files opened for write
170 ; 0 = Buffered, 1 = Unbuffered
170 ; 0 = Buffered, 1 = Unbuffered
171 UnbufferedOutput = 0
171 UnbufferedOutput = 0
172
172
173 ; This controls the number of characters of a signal name
173 ; This controls the number of characters of a signal name
174 ; shown in the waveform window and the postscript plot.
174 ; shown in the waveform window and the postscript plot.
175 ; The default value or a value of zero tells VSIM to display
175 ; The default value or a value of zero tells VSIM to display
176 ; the full name.
176 ; the full name.
177 ; WaveSignalNameWidth = 10
177 ; WaveSignalNameWidth = 10
178
178
179 ; Turn off warnings from the std_logic_arith, std_logic_unsigned
179 ; Turn off warnings from the std_logic_arith, std_logic_unsigned
180 ; and std_logic_signed packages.
180 ; and std_logic_signed packages.
181 ; StdArithNoWarnings = 1
181 ; StdArithNoWarnings = 1
182
182
183 ; Turn off warnings from the IEEE numeric_std and numeric_bit
183 ; Turn off warnings from the IEEE numeric_std and numeric_bit
184 ; packages.
184 ; packages.
185 ; NumericStdNoWarnings = 1
185 ; NumericStdNoWarnings = 1
186
186
187 ; Control the format of a generate statement label. Don't quote it.
187 ; Control the format of a generate statement label. Don't quote it.
188 ; GenerateFormat = %s__%d
188 ; GenerateFormat = %s__%d
189
189
190 ; Specify whether checkpoint files should be compressed.
190 ; Specify whether checkpoint files should be compressed.
191 ; The default is to be compressed.
191 ; The default is to be compressed.
192 ; CheckpointCompressMode = 0
192 ; CheckpointCompressMode = 0
193
193
194 ; List of dynamically loaded objects for Verilog PLI applications
194 ; List of dynamically loaded objects for Verilog PLI applications
195 ; Veriuser = veriuser.sl
195 ; Veriuser = veriuser.sl
196
196
197 [lmc]
197 [lmc]
198 ; ModelSim's interface to Logic Modeling's SmartModel SWIFT software
198 ; ModelSim's interface to Logic Modeling's SmartModel SWIFT software
199 libsm = $MODEL_TECH/libsm.sl
199 libsm = $MODEL_TECH/libsm.sl
200 ; ModelSim's interface to Logic Modeling's SmartModel SWIFT software (Windows NT)
200 ; ModelSim's interface to Logic Modeling's SmartModel SWIFT software (Windows NT)
201 ; libsm = $MODEL_TECH/libsm.dll
201 ; libsm = $MODEL_TECH/libsm.dll
202 ; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700)
202 ; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700)
203 ; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl
203 ; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl
204 ; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000)
204 ; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000)
205 ; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o
205 ; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o
206 ; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris)
206 ; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris)
207 ; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so
207 ; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so
208 ; Logic Modeling's SmartModel SWIFT software (Sun4 SunOS)
208 ; Logic Modeling's SmartModel SWIFT software (Sun4 SunOS)
209 ; do setenv LD_LIBRARY_PATH $LMC_HOME/lib/sun4SunOS.lib
209 ; do setenv LD_LIBRARY_PATH $LMC_HOME/lib/sun4SunOS.lib
210 ; and run "vsim.swift".
210 ; and run "vsim.swift".
211 ; Logic Modeling's SmartModel SWIFT software (Windows NT)
211 ; Logic Modeling's SmartModel SWIFT software (Windows NT)
212 ; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll
212 ; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll
213
213
214 ; ModelSim's interface to Logic Modeling's hardware modeler SFI software
214 ; ModelSim's interface to Logic Modeling's hardware modeler SFI software
215 libhm = $MODEL_TECH/libhm.sl
215 libhm = $MODEL_TECH/libhm.sl
216 ; ModelSim's interface to Logic Modeling's hardware modeler SFI software (Windows NT)
216 ; ModelSim's interface to Logic Modeling's hardware modeler SFI software (Windows NT)
217 ; libhm = $MODEL_TECH/libhm.dll
217 ; libhm = $MODEL_TECH/libhm.dll
218 ; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700)
218 ; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700)
219 ; libsfi = <sfi_dir>/lib/hp700/libsfi.sl
219 ; libsfi = <sfi_dir>/lib/hp700/libsfi.sl
220 ; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000)
220 ; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000)
221 ; libsfi = <sfi_dir>/lib/rs6000/libsfi.a
221 ; libsfi = <sfi_dir>/lib/rs6000/libsfi.a
222 ; Logic Modeling's hardware modeler SFI software (Sun4 Solaris)
222 ; Logic Modeling's hardware modeler SFI software (Sun4 Solaris)
223 ; libsfi = <sfi_dir>/lib/sun4.solaris/libsfi.so
223 ; libsfi = <sfi_dir>/lib/sun4.solaris/libsfi.so
224 ; Logic Modeling's hardware modeler SFI software (Sun4 SunOS)
224 ; Logic Modeling's hardware modeler SFI software (Sun4 SunOS)
225 ; libsfi = <sfi_dir>/lib/sun4.sunos/libsfi.so
225 ; libsfi = <sfi_dir>/lib/sun4.sunos/libsfi.so
226 ; Logic Modeling's hardware modeler SFI software (Window NT)
226 ; Logic Modeling's hardware modeler SFI software (Window NT)
227 ; libsfi = <sfi_dir>/lib/pcnt/lm_sfi.dll
227 ; libsfi = <sfi_dir>/lib/pcnt/lm_sfi.dll
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@@ -1,10 +1,10
1 #define MCFG1 0x10380133
1 #define MCFG1 0x10380133
2 #define MCFG2 0xe6B80e60
2 #define MCFG2 0xe6B80e60
3 #define MCFG3 0x000ff000
3 #define MCFG3 0x000ff000
4 #define ASDCFG 0xfff00100
4 #define ASDCFG 0xfff00100
5 #define DSDCFG 0xe6A06e60
5 #define DSDCFG 0xe6A06e60
6 #define L2MCTRLIO 0x80000000
6 #define L2MCTRLIO 0x80000000
7 #define IRQCTRL 0x80000200
7 #define IRQCTRL 0x80000200
8 #define RAMSTART 0x40000000
8 #define RAMSTART 0x40000000
9 #define RAMSIZE 0x00100000
9 #define RAMSIZE 0x00100000
10
10
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@@ -1,10 +1,10
1
1
2 main()
2 main()
3
3
4 {
4 {
5 report_start();
5 report_start();
6
6
7 base_test();
7 base_test();
8
8
9 report_end();
9 report_end();
10 }
10 }
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This diff has been collapsed as it changes many lines, (1898 lines changed) Show them Hide them
@@ -1,949 +1,949
1 #if defined CONFIG_SYN_INFERRED
1 #if defined CONFIG_SYN_INFERRED
2 #define CONFIG_SYN_TECH inferred
2 #define CONFIG_SYN_TECH inferred
3 #elif defined CONFIG_SYN_UMC
3 #elif defined CONFIG_SYN_UMC
4 #define CONFIG_SYN_TECH umc
4 #define CONFIG_SYN_TECH umc
5 #elif defined CONFIG_SYN_RHUMC
5 #elif defined CONFIG_SYN_RHUMC
6 #define CONFIG_SYN_TECH rhumc
6 #define CONFIG_SYN_TECH rhumc
7 #elif defined CONFIG_SYN_ATC18
7 #elif defined CONFIG_SYN_ATC18
8 #define CONFIG_SYN_TECH atc18s
8 #define CONFIG_SYN_TECH atc18s
9 #elif defined CONFIG_SYN_ATC18RHA
9 #elif defined CONFIG_SYN_ATC18RHA
10 #define CONFIG_SYN_TECH atc18rha
10 #define CONFIG_SYN_TECH atc18rha
11 #elif defined CONFIG_SYN_AXCEL
11 #elif defined CONFIG_SYN_AXCEL
12 #define CONFIG_SYN_TECH axcel
12 #define CONFIG_SYN_TECH axcel
13 #elif defined CONFIG_SYN_AXDSP
13 #elif defined CONFIG_SYN_AXDSP
14 #define CONFIG_SYN_TECH axdsp
14 #define CONFIG_SYN_TECH axdsp
15 #elif defined CONFIG_SYN_PROASICPLUS
15 #elif defined CONFIG_SYN_PROASICPLUS
16 #define CONFIG_SYN_TECH proasic
16 #define CONFIG_SYN_TECH proasic
17 #elif defined CONFIG_SYN_ALTERA
17 #elif defined CONFIG_SYN_ALTERA
18 #define CONFIG_SYN_TECH altera
18 #define CONFIG_SYN_TECH altera
19 #elif defined CONFIG_SYN_STRATIX
19 #elif defined CONFIG_SYN_STRATIX
20 #define CONFIG_SYN_TECH stratix1
20 #define CONFIG_SYN_TECH stratix1
21 #elif defined CONFIG_SYN_STRATIXII
21 #elif defined CONFIG_SYN_STRATIXII
22 #define CONFIG_SYN_TECH stratix2
22 #define CONFIG_SYN_TECH stratix2
23 #elif defined CONFIG_SYN_STRATIXIII
23 #elif defined CONFIG_SYN_STRATIXIII
24 #define CONFIG_SYN_TECH stratix3
24 #define CONFIG_SYN_TECH stratix3
25 #elif defined CONFIG_SYN_CYCLONEIII
25 #elif defined CONFIG_SYN_CYCLONEIII
26 #define CONFIG_SYN_TECH cyclone3
26 #define CONFIG_SYN_TECH cyclone3
27 #elif defined CONFIG_SYN_EASIC90
27 #elif defined CONFIG_SYN_EASIC90
28 #define CONFIG_SYN_TECH easic90
28 #define CONFIG_SYN_TECH easic90
29 #elif defined CONFIG_SYN_IHP25
29 #elif defined CONFIG_SYN_IHP25
30 #define CONFIG_SYN_TECH ihp25
30 #define CONFIG_SYN_TECH ihp25
31 #elif defined CONFIG_SYN_IHP25RH
31 #elif defined CONFIG_SYN_IHP25RH
32 #define CONFIG_SYN_TECH ihp25rh
32 #define CONFIG_SYN_TECH ihp25rh
33 #elif defined CONFIG_SYN_CMOS9SF
33 #elif defined CONFIG_SYN_CMOS9SF
34 #define CONFIG_SYN_TECH cmos9sf
34 #define CONFIG_SYN_TECH cmos9sf
35 #elif defined CONFIG_SYN_LATTICE
35 #elif defined CONFIG_SYN_LATTICE
36 #define CONFIG_SYN_TECH lattice
36 #define CONFIG_SYN_TECH lattice
37 #elif defined CONFIG_SYN_ECLIPSE
37 #elif defined CONFIG_SYN_ECLIPSE
38 #define CONFIG_SYN_TECH eclipse
38 #define CONFIG_SYN_TECH eclipse
39 #elif defined CONFIG_SYN_PEREGRINE
39 #elif defined CONFIG_SYN_PEREGRINE
40 #define CONFIG_SYN_TECH peregrine
40 #define CONFIG_SYN_TECH peregrine
41 #elif defined CONFIG_SYN_PROASIC
41 #elif defined CONFIG_SYN_PROASIC
42 #define CONFIG_SYN_TECH proasic
42 #define CONFIG_SYN_TECH proasic
43 #elif defined CONFIG_SYN_PROASIC3
43 #elif defined CONFIG_SYN_PROASIC3
44 #define CONFIG_SYN_TECH apa3
44 #define CONFIG_SYN_TECH apa3
45 #elif defined CONFIG_SYN_PROASIC3E
45 #elif defined CONFIG_SYN_PROASIC3E
46 #define CONFIG_SYN_TECH apa3e
46 #define CONFIG_SYN_TECH apa3e
47 #elif defined CONFIG_SYN_PROASIC3L
47 #elif defined CONFIG_SYN_PROASIC3L
48 #define CONFIG_SYN_TECH apa3l
48 #define CONFIG_SYN_TECH apa3l
49 #elif defined CONFIG_SYN_IGLOO
49 #elif defined CONFIG_SYN_IGLOO
50 #define CONFIG_SYN_TECH apa3
50 #define CONFIG_SYN_TECH apa3
51 #elif defined CONFIG_SYN_FUSION
51 #elif defined CONFIG_SYN_FUSION
52 #define CONFIG_SYN_TECH actfus
52 #define CONFIG_SYN_TECH actfus
53 #elif defined CONFIG_SYN_SPARTAN2
53 #elif defined CONFIG_SYN_SPARTAN2
54 #define CONFIG_SYN_TECH virtex
54 #define CONFIG_SYN_TECH virtex
55 #elif defined CONFIG_SYN_VIRTEX
55 #elif defined CONFIG_SYN_VIRTEX
56 #define CONFIG_SYN_TECH virtex
56 #define CONFIG_SYN_TECH virtex
57 #elif defined CONFIG_SYN_VIRTEXE
57 #elif defined CONFIG_SYN_VIRTEXE
58 #define CONFIG_SYN_TECH virtex
58 #define CONFIG_SYN_TECH virtex
59 #elif defined CONFIG_SYN_SPARTAN3
59 #elif defined CONFIG_SYN_SPARTAN3
60 #define CONFIG_SYN_TECH spartan3
60 #define CONFIG_SYN_TECH spartan3
61 #elif defined CONFIG_SYN_SPARTAN3E
61 #elif defined CONFIG_SYN_SPARTAN3E
62 #define CONFIG_SYN_TECH spartan3e
62 #define CONFIG_SYN_TECH spartan3e
63 #elif defined CONFIG_SYN_SPARTAN6
63 #elif defined CONFIG_SYN_SPARTAN6
64 #define CONFIG_SYN_TECH spartan6
64 #define CONFIG_SYN_TECH spartan6
65 #elif defined CONFIG_SYN_VIRTEX2
65 #elif defined CONFIG_SYN_VIRTEX2
66 #define CONFIG_SYN_TECH virtex2
66 #define CONFIG_SYN_TECH virtex2
67 #elif defined CONFIG_SYN_VIRTEX4
67 #elif defined CONFIG_SYN_VIRTEX4
68 #define CONFIG_SYN_TECH virtex4
68 #define CONFIG_SYN_TECH virtex4
69 #elif defined CONFIG_SYN_VIRTEX5
69 #elif defined CONFIG_SYN_VIRTEX5
70 #define CONFIG_SYN_TECH virtex5
70 #define CONFIG_SYN_TECH virtex5
71 #elif defined CONFIG_SYN_VIRTEX6
71 #elif defined CONFIG_SYN_VIRTEX6
72 #define CONFIG_SYN_TECH virtex6
72 #define CONFIG_SYN_TECH virtex6
73 #elif defined CONFIG_SYN_RH_LIB18T
73 #elif defined CONFIG_SYN_RH_LIB18T
74 #define CONFIG_SYN_TECH rhlib18t
74 #define CONFIG_SYN_TECH rhlib18t
75 #elif defined CONFIG_SYN_SMIC13
75 #elif defined CONFIG_SYN_SMIC13
76 #define CONFIG_SYN_TECH smic013
76 #define CONFIG_SYN_TECH smic013
77 #elif defined CONFIG_SYN_UT025CRH
77 #elif defined CONFIG_SYN_UT025CRH
78 #define CONFIG_SYN_TECH ut25
78 #define CONFIG_SYN_TECH ut25
79 #elif defined CONFIG_SYN_TSMC90
79 #elif defined CONFIG_SYN_TSMC90
80 #define CONFIG_SYN_TECH tsmc90
80 #define CONFIG_SYN_TECH tsmc90
81 #elif defined CONFIG_SYN_TM65GPLUS
81 #elif defined CONFIG_SYN_TM65GPLUS
82 #define CONFIG_SYN_TECH tm65gpl
82 #define CONFIG_SYN_TECH tm65gpl
83 #elif defined CONFIG_SYN_CUSTOM1
83 #elif defined CONFIG_SYN_CUSTOM1
84 #define CONFIG_SYN_TECH custom1
84 #define CONFIG_SYN_TECH custom1
85 #else
85 #else
86 #error "unknown target technology"
86 #error "unknown target technology"
87 #endif
87 #endif
88
88
89 #if defined CONFIG_SYN_INFER_RAM
89 #if defined CONFIG_SYN_INFER_RAM
90 #define CFG_RAM_TECH inferred
90 #define CFG_RAM_TECH inferred
91 #elif defined CONFIG_MEM_UMC
91 #elif defined CONFIG_MEM_UMC
92 #define CFG_RAM_TECH umc
92 #define CFG_RAM_TECH umc
93 #elif defined CONFIG_MEM_RHUMC
93 #elif defined CONFIG_MEM_RHUMC
94 #define CFG_RAM_TECH rhumc
94 #define CFG_RAM_TECH rhumc
95 #elif defined CONFIG_MEM_VIRAGE
95 #elif defined CONFIG_MEM_VIRAGE
96 #define CFG_RAM_TECH memvirage
96 #define CFG_RAM_TECH memvirage
97 #elif defined CONFIG_MEM_ARTISAN
97 #elif defined CONFIG_MEM_ARTISAN
98 #define CFG_RAM_TECH memartisan
98 #define CFG_RAM_TECH memartisan
99 #elif defined CONFIG_MEM_CUSTOM1
99 #elif defined CONFIG_MEM_CUSTOM1
100 #define CFG_RAM_TECH custom1
100 #define CFG_RAM_TECH custom1
101 #elif defined CONFIG_MEM_VIRAGE90
101 #elif defined CONFIG_MEM_VIRAGE90
102 #define CFG_RAM_TECH memvirage90
102 #define CFG_RAM_TECH memvirage90
103 #elif defined CONFIG_MEM_INFERRED
103 #elif defined CONFIG_MEM_INFERRED
104 #define CFG_RAM_TECH inferred
104 #define CFG_RAM_TECH inferred
105 #else
105 #else
106 #define CFG_RAM_TECH CONFIG_SYN_TECH
106 #define CFG_RAM_TECH CONFIG_SYN_TECH
107 #endif
107 #endif
108
108
109 #if defined CONFIG_SYN_INFER_PADS
109 #if defined CONFIG_SYN_INFER_PADS
110 #define CFG_PAD_TECH inferred
110 #define CFG_PAD_TECH inferred
111 #else
111 #else
112 #define CFG_PAD_TECH CONFIG_SYN_TECH
112 #define CFG_PAD_TECH CONFIG_SYN_TECH
113 #endif
113 #endif
114
114
115 #ifndef CONFIG_SYN_NO_ASYNC
115 #ifndef CONFIG_SYN_NO_ASYNC
116 #define CONFIG_SYN_NO_ASYNC 0
116 #define CONFIG_SYN_NO_ASYNC 0
117 #endif
117 #endif
118
118
119 #ifndef CONFIG_SYN_SCAN
119 #ifndef CONFIG_SYN_SCAN
120 #define CONFIG_SYN_SCAN 0
120 #define CONFIG_SYN_SCAN 0
121 #endif
121 #endif
122
122
123
123
124 #if defined CONFIG_CLK_ALTDLL
124 #if defined CONFIG_CLK_ALTDLL
125 #define CFG_CLK_TECH CONFIG_SYN_TECH
125 #define CFG_CLK_TECH CONFIG_SYN_TECH
126 #elif defined CONFIG_CLK_HCLKBUF
126 #elif defined CONFIG_CLK_HCLKBUF
127 #define CFG_CLK_TECH axcel
127 #define CFG_CLK_TECH axcel
128 #elif defined CONFIG_CLK_LATDLL
128 #elif defined CONFIG_CLK_LATDLL
129 #define CFG_CLK_TECH lattice
129 #define CFG_CLK_TECH lattice
130 #elif defined CONFIG_CLK_PRO3PLL
130 #elif defined CONFIG_CLK_PRO3PLL
131 #define CFG_CLK_TECH apa3
131 #define CFG_CLK_TECH apa3
132 #elif defined CONFIG_CLK_PRO3EPLL
132 #elif defined CONFIG_CLK_PRO3EPLL
133 #define CFG_CLK_TECH apa3e
133 #define CFG_CLK_TECH apa3e
134 #elif defined CONFIG_CLK_PRO3LPLL
134 #elif defined CONFIG_CLK_PRO3LPLL
135 #define CFG_CLK_TECH apa3l
135 #define CFG_CLK_TECH apa3l
136 #elif defined CONFIG_CLK_FUSPLL
136 #elif defined CONFIG_CLK_FUSPLL
137 #define CFG_CLK_TECH actfus
137 #define CFG_CLK_TECH actfus
138 #elif defined CONFIG_CLK_CLKDLL
138 #elif defined CONFIG_CLK_CLKDLL
139 #define CFG_CLK_TECH virtex
139 #define CFG_CLK_TECH virtex
140 #elif defined CONFIG_CLK_DCM
140 #elif defined CONFIG_CLK_DCM
141 #define CFG_CLK_TECH CONFIG_SYN_TECH
141 #define CFG_CLK_TECH CONFIG_SYN_TECH
142 #elif defined CONFIG_CLK_LIB18T
142 #elif defined CONFIG_CLK_LIB18T
143 #define CFG_CLK_TECH rhlib18t
143 #define CFG_CLK_TECH rhlib18t
144 #elif defined CONFIG_CLK_RHUMC
144 #elif defined CONFIG_CLK_RHUMC
145 #define CFG_CLK_TECH rhumc
145 #define CFG_CLK_TECH rhumc
146 #else
146 #else
147 #define CFG_CLK_TECH inferred
147 #define CFG_CLK_TECH inferred
148 #endif
148 #endif
149
149
150 #ifndef CONFIG_CLK_MUL
150 #ifndef CONFIG_CLK_MUL
151 #define CONFIG_CLK_MUL 2
151 #define CONFIG_CLK_MUL 2
152 #endif
152 #endif
153
153
154 #ifndef CONFIG_CLK_DIV
154 #ifndef CONFIG_CLK_DIV
155 #define CONFIG_CLK_DIV 2
155 #define CONFIG_CLK_DIV 2
156 #endif
156 #endif
157
157
158 #ifndef CONFIG_OCLK_DIV
158 #ifndef CONFIG_OCLK_DIV
159 #define CONFIG_OCLK_DIV 1
159 #define CONFIG_OCLK_DIV 1
160 #endif
160 #endif
161
161
162 #ifndef CONFIG_OCLKB_DIV
162 #ifndef CONFIG_OCLKB_DIV
163 #define CONFIG_OCLKB_DIV 0
163 #define CONFIG_OCLKB_DIV 0
164 #endif
164 #endif
165
165
166 #ifndef CONFIG_OCLKC_DIV
166 #ifndef CONFIG_OCLKC_DIV
167 #define CONFIG_OCLKC_DIV 0
167 #define CONFIG_OCLKC_DIV 0
168 #endif
168 #endif
169
169
170 #ifndef CONFIG_PCI_CLKDLL
170 #ifndef CONFIG_PCI_CLKDLL
171 #define CONFIG_PCI_CLKDLL 0
171 #define CONFIG_PCI_CLKDLL 0
172 #endif
172 #endif
173
173
174 #ifndef CONFIG_PCI_SYSCLK
174 #ifndef CONFIG_PCI_SYSCLK
175 #define CONFIG_PCI_SYSCLK 0
175 #define CONFIG_PCI_SYSCLK 0
176 #endif
176 #endif
177
177
178 #ifndef CONFIG_CLK_NOFB
178 #ifndef CONFIG_CLK_NOFB
179 #define CONFIG_CLK_NOFB 0
179 #define CONFIG_CLK_NOFB 0
180 #endif
180 #endif
181 #ifndef CONFIG_LEON3
181 #ifndef CONFIG_LEON3
182 #define CONFIG_LEON3 0
182 #define CONFIG_LEON3 0
183 #endif
183 #endif
184
184
185 #ifndef CONFIG_PROC_NUM
185 #ifndef CONFIG_PROC_NUM
186 #define CONFIG_PROC_NUM 1
186 #define CONFIG_PROC_NUM 1
187 #endif
187 #endif
188
188
189 #ifndef CONFIG_IU_NWINDOWS
189 #ifndef CONFIG_IU_NWINDOWS
190 #define CONFIG_IU_NWINDOWS 8
190 #define CONFIG_IU_NWINDOWS 8
191 #endif
191 #endif
192
192
193 #ifndef CONFIG_IU_RSTADDR
193 #ifndef CONFIG_IU_RSTADDR
194 #define CONFIG_IU_RSTADDR 8
194 #define CONFIG_IU_RSTADDR 8
195 #endif
195 #endif
196
196
197 #ifndef CONFIG_IU_LDELAY
197 #ifndef CONFIG_IU_LDELAY
198 #define CONFIG_IU_LDELAY 1
198 #define CONFIG_IU_LDELAY 1
199 #endif
199 #endif
200
200
201 #ifndef CONFIG_IU_WATCHPOINTS
201 #ifndef CONFIG_IU_WATCHPOINTS
202 #define CONFIG_IU_WATCHPOINTS 0
202 #define CONFIG_IU_WATCHPOINTS 0
203 #endif
203 #endif
204
204
205 #ifdef CONFIG_IU_V8MULDIV
205 #ifdef CONFIG_IU_V8MULDIV
206 #ifdef CONFIG_IU_MUL_LATENCY_4
206 #ifdef CONFIG_IU_MUL_LATENCY_4
207 #define CFG_IU_V8 1
207 #define CFG_IU_V8 1
208 #elif defined CONFIG_IU_MUL_LATENCY_5
208 #elif defined CONFIG_IU_MUL_LATENCY_5
209 #define CFG_IU_V8 2
209 #define CFG_IU_V8 2
210 #elif defined CONFIG_IU_MUL_LATENCY_2
210 #elif defined CONFIG_IU_MUL_LATENCY_2
211 #define CFG_IU_V8 16#32#
211 #define CFG_IU_V8 16#32#
212 #endif
212 #endif
213 #else
213 #else
214 #define CFG_IU_V8 0
214 #define CFG_IU_V8 0
215 #endif
215 #endif
216
216
217 #ifndef CONFIG_PWD
217 #ifndef CONFIG_PWD
218 #define CONFIG_PWD 0
218 #define CONFIG_PWD 0
219 #endif
219 #endif
220
220
221 #ifndef CONFIG_IU_MUL_MAC
221 #ifndef CONFIG_IU_MUL_MAC
222 #define CONFIG_IU_MUL_MAC 0
222 #define CONFIG_IU_MUL_MAC 0
223 #endif
223 #endif
224
224
225 #ifndef CONFIG_IU_BP
225 #ifndef CONFIG_IU_BP
226 #define CONFIG_IU_BP 0
226 #define CONFIG_IU_BP 0
227 #endif
227 #endif
228
228
229 #ifndef CONFIG_NOTAG
229 #ifndef CONFIG_NOTAG
230 #define CONFIG_NOTAG 0
230 #define CONFIG_NOTAG 0
231 #endif
231 #endif
232
232
233 #ifndef CONFIG_IU_SVT
233 #ifndef CONFIG_IU_SVT
234 #define CONFIG_IU_SVT 0
234 #define CONFIG_IU_SVT 0
235 #endif
235 #endif
236
236
237 #if defined CONFIG_FPU_GRFPC1
237 #if defined CONFIG_FPU_GRFPC1
238 #define CONFIG_FPU_GRFPC 1
238 #define CONFIG_FPU_GRFPC 1
239 #elif defined CONFIG_FPU_GRFPC2
239 #elif defined CONFIG_FPU_GRFPC2
240 #define CONFIG_FPU_GRFPC 2
240 #define CONFIG_FPU_GRFPC 2
241 #else
241 #else
242 #define CONFIG_FPU_GRFPC 0
242 #define CONFIG_FPU_GRFPC 0
243 #endif
243 #endif
244
244
245 #if defined CONFIG_FPU_GRFPU_INFMUL
245 #if defined CONFIG_FPU_GRFPU_INFMUL
246 #define CONFIG_FPU_GRFPU_MUL 0
246 #define CONFIG_FPU_GRFPU_MUL 0
247 #elif defined CONFIG_FPU_GRFPU_DWMUL
247 #elif defined CONFIG_FPU_GRFPU_DWMUL
248 #define CONFIG_FPU_GRFPU_MUL 1
248 #define CONFIG_FPU_GRFPU_MUL 1
249 #elif defined CONFIG_FPU_GRFPU_MODGEN
249 #elif defined CONFIG_FPU_GRFPU_MODGEN
250 #define CONFIG_FPU_GRFPU_MUL 2
250 #define CONFIG_FPU_GRFPU_MUL 2
251 #elif defined CONFIG_FPU_GRFPU_TECHSPEC
251 #elif defined CONFIG_FPU_GRFPU_TECHSPEC
252 #define CONFIG_FPU_GRFPU_MUL 3
252 #define CONFIG_FPU_GRFPU_MUL 3
253 #else
253 #else
254 #define CONFIG_FPU_GRFPU_MUL 0
254 #define CONFIG_FPU_GRFPU_MUL 0
255 #endif
255 #endif
256
256
257 #if defined CONFIG_FPU_GRFPU_SH
257 #if defined CONFIG_FPU_GRFPU_SH
258 #define CONFIG_FPU_GRFPU_SHARED 1
258 #define CONFIG_FPU_GRFPU_SHARED 1
259 #else
259 #else
260 #define CONFIG_FPU_GRFPU_SHARED 0
260 #define CONFIG_FPU_GRFPU_SHARED 0
261 #endif
261 #endif
262
262
263 #if defined CONFIG_FPU_GRFPU
263 #if defined CONFIG_FPU_GRFPU
264 #define CONFIG_FPU (1+CONFIG_FPU_GRFPU_MUL)
264 #define CONFIG_FPU (1+CONFIG_FPU_GRFPU_MUL)
265 #elif defined CONFIG_FPU_MEIKO
265 #elif defined CONFIG_FPU_MEIKO
266 #define CONFIG_FPU 15
266 #define CONFIG_FPU 15
267 #elif defined CONFIG_FPU_GRFPULITE
267 #elif defined CONFIG_FPU_GRFPULITE
268 #define CONFIG_FPU (8+CONFIG_FPU_GRFPC)
268 #define CONFIG_FPU (8+CONFIG_FPU_GRFPC)
269 #else
269 #else
270 #define CONFIG_FPU 0
270 #define CONFIG_FPU 0
271 #endif
271 #endif
272
272
273 #ifndef CONFIG_FPU_NETLIST
273 #ifndef CONFIG_FPU_NETLIST
274 #define CONFIG_FPU_NETLIST 0
274 #define CONFIG_FPU_NETLIST 0
275 #endif
275 #endif
276
276
277 #ifndef CONFIG_ICACHE_ENABLE
277 #ifndef CONFIG_ICACHE_ENABLE
278 #define CONFIG_ICACHE_ENABLE 0
278 #define CONFIG_ICACHE_ENABLE 0
279 #endif
279 #endif
280
280
281 #if defined CONFIG_ICACHE_ASSO1
281 #if defined CONFIG_ICACHE_ASSO1
282 #define CFG_IU_ISETS 1
282 #define CFG_IU_ISETS 1
283 #elif defined CONFIG_ICACHE_ASSO2
283 #elif defined CONFIG_ICACHE_ASSO2
284 #define CFG_IU_ISETS 2
284 #define CFG_IU_ISETS 2
285 #elif defined CONFIG_ICACHE_ASSO3
285 #elif defined CONFIG_ICACHE_ASSO3
286 #define CFG_IU_ISETS 3
286 #define CFG_IU_ISETS 3
287 #elif defined CONFIG_ICACHE_ASSO4
287 #elif defined CONFIG_ICACHE_ASSO4
288 #define CFG_IU_ISETS 4
288 #define CFG_IU_ISETS 4
289 #else
289 #else
290 #define CFG_IU_ISETS 1
290 #define CFG_IU_ISETS 1
291 #endif
291 #endif
292
292
293 #if defined CONFIG_ICACHE_SZ1
293 #if defined CONFIG_ICACHE_SZ1
294 #define CFG_ICACHE_SZ 1
294 #define CFG_ICACHE_SZ 1
295 #elif defined CONFIG_ICACHE_SZ2
295 #elif defined CONFIG_ICACHE_SZ2
296 #define CFG_ICACHE_SZ 2
296 #define CFG_ICACHE_SZ 2
297 #elif defined CONFIG_ICACHE_SZ4
297 #elif defined CONFIG_ICACHE_SZ4
298 #define CFG_ICACHE_SZ 4
298 #define CFG_ICACHE_SZ 4
299 #elif defined CONFIG_ICACHE_SZ8
299 #elif defined CONFIG_ICACHE_SZ8
300 #define CFG_ICACHE_SZ 8
300 #define CFG_ICACHE_SZ 8
301 #elif defined CONFIG_ICACHE_SZ16
301 #elif defined CONFIG_ICACHE_SZ16
302 #define CFG_ICACHE_SZ 16
302 #define CFG_ICACHE_SZ 16
303 #elif defined CONFIG_ICACHE_SZ32
303 #elif defined CONFIG_ICACHE_SZ32
304 #define CFG_ICACHE_SZ 32
304 #define CFG_ICACHE_SZ 32
305 #elif defined CONFIG_ICACHE_SZ64
305 #elif defined CONFIG_ICACHE_SZ64
306 #define CFG_ICACHE_SZ 64
306 #define CFG_ICACHE_SZ 64
307 #elif defined CONFIG_ICACHE_SZ128
307 #elif defined CONFIG_ICACHE_SZ128
308 #define CFG_ICACHE_SZ 128
308 #define CFG_ICACHE_SZ 128
309 #elif defined CONFIG_ICACHE_SZ256
309 #elif defined CONFIG_ICACHE_SZ256
310 #define CFG_ICACHE_SZ 256
310 #define CFG_ICACHE_SZ 256
311 #else
311 #else
312 #define CFG_ICACHE_SZ 1
312 #define CFG_ICACHE_SZ 1
313 #endif
313 #endif
314
314
315 #ifdef CONFIG_ICACHE_LZ16
315 #ifdef CONFIG_ICACHE_LZ16
316 #define CFG_ILINE_SZ 4
316 #define CFG_ILINE_SZ 4
317 #else
317 #else
318 #define CFG_ILINE_SZ 8
318 #define CFG_ILINE_SZ 8
319 #endif
319 #endif
320
320
321 #if defined CONFIG_ICACHE_ALGORND
321 #if defined CONFIG_ICACHE_ALGORND
322 #define CFG_ICACHE_ALGORND 2
322 #define CFG_ICACHE_ALGORND 2
323 #elif defined CONFIG_ICACHE_ALGOLRR
323 #elif defined CONFIG_ICACHE_ALGOLRR
324 #define CFG_ICACHE_ALGORND 1
324 #define CFG_ICACHE_ALGORND 1
325 #else
325 #else
326 #define CFG_ICACHE_ALGORND 0
326 #define CFG_ICACHE_ALGORND 0
327 #endif
327 #endif
328
328
329 #ifndef CONFIG_ICACHE_LOCK
329 #ifndef CONFIG_ICACHE_LOCK
330 #define CONFIG_ICACHE_LOCK 0
330 #define CONFIG_ICACHE_LOCK 0
331 #endif
331 #endif
332
332
333 #ifndef CONFIG_ICACHE_LRAM
333 #ifndef CONFIG_ICACHE_LRAM
334 #define CONFIG_ICACHE_LRAM 0
334 #define CONFIG_ICACHE_LRAM 0
335 #endif
335 #endif
336
336
337 #ifndef CONFIG_ICACHE_LRSTART
337 #ifndef CONFIG_ICACHE_LRSTART
338 #define CONFIG_ICACHE_LRSTART 8E
338 #define CONFIG_ICACHE_LRSTART 8E
339 #endif
339 #endif
340
340
341 #if defined CONFIG_ICACHE_LRAM_SZ2
341 #if defined CONFIG_ICACHE_LRAM_SZ2
342 #define CFG_ILRAM_SIZE 2
342 #define CFG_ILRAM_SIZE 2
343 #elif defined CONFIG_ICACHE_LRAM_SZ4
343 #elif defined CONFIG_ICACHE_LRAM_SZ4
344 #define CFG_ILRAM_SIZE 4
344 #define CFG_ILRAM_SIZE 4
345 #elif defined CONFIG_ICACHE_LRAM_SZ8
345 #elif defined CONFIG_ICACHE_LRAM_SZ8
346 #define CFG_ILRAM_SIZE 8
346 #define CFG_ILRAM_SIZE 8
347 #elif defined CONFIG_ICACHE_LRAM_SZ16
347 #elif defined CONFIG_ICACHE_LRAM_SZ16
348 #define CFG_ILRAM_SIZE 16
348 #define CFG_ILRAM_SIZE 16
349 #elif defined CONFIG_ICACHE_LRAM_SZ32
349 #elif defined CONFIG_ICACHE_LRAM_SZ32
350 #define CFG_ILRAM_SIZE 32
350 #define CFG_ILRAM_SIZE 32
351 #elif defined CONFIG_ICACHE_LRAM_SZ64
351 #elif defined CONFIG_ICACHE_LRAM_SZ64
352 #define CFG_ILRAM_SIZE 64
352 #define CFG_ILRAM_SIZE 64
353 #elif defined CONFIG_ICACHE_LRAM_SZ128
353 #elif defined CONFIG_ICACHE_LRAM_SZ128
354 #define CFG_ILRAM_SIZE 128
354 #define CFG_ILRAM_SIZE 128
355 #elif defined CONFIG_ICACHE_LRAM_SZ256
355 #elif defined CONFIG_ICACHE_LRAM_SZ256
356 #define CFG_ILRAM_SIZE 256
356 #define CFG_ILRAM_SIZE 256
357 #else
357 #else
358 #define CFG_ILRAM_SIZE 1
358 #define CFG_ILRAM_SIZE 1
359 #endif
359 #endif
360
360
361
361
362 #ifndef CONFIG_DCACHE_ENABLE
362 #ifndef CONFIG_DCACHE_ENABLE
363 #define CONFIG_DCACHE_ENABLE 0
363 #define CONFIG_DCACHE_ENABLE 0
364 #endif
364 #endif
365
365
366 #if defined CONFIG_DCACHE_ASSO1
366 #if defined CONFIG_DCACHE_ASSO1
367 #define CFG_IU_DSETS 1
367 #define CFG_IU_DSETS 1
368 #elif defined CONFIG_DCACHE_ASSO2
368 #elif defined CONFIG_DCACHE_ASSO2
369 #define CFG_IU_DSETS 2
369 #define CFG_IU_DSETS 2
370 #elif defined CONFIG_DCACHE_ASSO3
370 #elif defined CONFIG_DCACHE_ASSO3
371 #define CFG_IU_DSETS 3
371 #define CFG_IU_DSETS 3
372 #elif defined CONFIG_DCACHE_ASSO4
372 #elif defined CONFIG_DCACHE_ASSO4
373 #define CFG_IU_DSETS 4
373 #define CFG_IU_DSETS 4
374 #else
374 #else
375 #define CFG_IU_DSETS 1
375 #define CFG_IU_DSETS 1
376 #endif
376 #endif
377
377
378 #if defined CONFIG_DCACHE_SZ1
378 #if defined CONFIG_DCACHE_SZ1
379 #define CFG_DCACHE_SZ 1
379 #define CFG_DCACHE_SZ 1
380 #elif defined CONFIG_DCACHE_SZ2
380 #elif defined CONFIG_DCACHE_SZ2
381 #define CFG_DCACHE_SZ 2
381 #define CFG_DCACHE_SZ 2
382 #elif defined CONFIG_DCACHE_SZ4
382 #elif defined CONFIG_DCACHE_SZ4
383 #define CFG_DCACHE_SZ 4
383 #define CFG_DCACHE_SZ 4
384 #elif defined CONFIG_DCACHE_SZ8
384 #elif defined CONFIG_DCACHE_SZ8
385 #define CFG_DCACHE_SZ 8
385 #define CFG_DCACHE_SZ 8
386 #elif defined CONFIG_DCACHE_SZ16
386 #elif defined CONFIG_DCACHE_SZ16
387 #define CFG_DCACHE_SZ 16
387 #define CFG_DCACHE_SZ 16
388 #elif defined CONFIG_DCACHE_SZ32
388 #elif defined CONFIG_DCACHE_SZ32
389 #define CFG_DCACHE_SZ 32
389 #define CFG_DCACHE_SZ 32
390 #elif defined CONFIG_DCACHE_SZ64
390 #elif defined CONFIG_DCACHE_SZ64
391 #define CFG_DCACHE_SZ 64
391 #define CFG_DCACHE_SZ 64
392 #elif defined CONFIG_DCACHE_SZ128
392 #elif defined CONFIG_DCACHE_SZ128
393 #define CFG_DCACHE_SZ 128
393 #define CFG_DCACHE_SZ 128
394 #elif defined CONFIG_DCACHE_SZ256
394 #elif defined CONFIG_DCACHE_SZ256
395 #define CFG_DCACHE_SZ 256
395 #define CFG_DCACHE_SZ 256
396 #else
396 #else
397 #define CFG_DCACHE_SZ 1
397 #define CFG_DCACHE_SZ 1
398 #endif
398 #endif
399
399
400 #ifdef CONFIG_DCACHE_LZ16
400 #ifdef CONFIG_DCACHE_LZ16
401 #define CFG_DLINE_SZ 4
401 #define CFG_DLINE_SZ 4
402 #else
402 #else
403 #define CFG_DLINE_SZ 8
403 #define CFG_DLINE_SZ 8
404 #endif
404 #endif
405
405
406 #if defined CONFIG_DCACHE_ALGORND
406 #if defined CONFIG_DCACHE_ALGORND
407 #define CFG_DCACHE_ALGORND 2
407 #define CFG_DCACHE_ALGORND 2
408 #elif defined CONFIG_DCACHE_ALGOLRR
408 #elif defined CONFIG_DCACHE_ALGOLRR
409 #define CFG_DCACHE_ALGORND 1
409 #define CFG_DCACHE_ALGORND 1
410 #else
410 #else
411 #define CFG_DCACHE_ALGORND 0
411 #define CFG_DCACHE_ALGORND 0
412 #endif
412 #endif
413
413
414 #ifndef CONFIG_DCACHE_LOCK
414 #ifndef CONFIG_DCACHE_LOCK
415 #define CONFIG_DCACHE_LOCK 0
415 #define CONFIG_DCACHE_LOCK 0
416 #endif
416 #endif
417
417
418 #ifndef CONFIG_DCACHE_SNOOP
418 #ifndef CONFIG_DCACHE_SNOOP
419 #define CONFIG_DCACHE_SNOOP 0
419 #define CONFIG_DCACHE_SNOOP 0
420 #endif
420 #endif
421
421
422 #ifndef CONFIG_DCACHE_SNOOP_FAST
422 #ifndef CONFIG_DCACHE_SNOOP_FAST
423 #define CONFIG_DCACHE_SNOOP_FAST 0
423 #define CONFIG_DCACHE_SNOOP_FAST 0
424 #endif
424 #endif
425
425
426 #ifndef CONFIG_DCACHE_SNOOP_SEPTAG
426 #ifndef CONFIG_DCACHE_SNOOP_SEPTAG
427 #define CONFIG_DCACHE_SNOOP_SEPTAG 0
427 #define CONFIG_DCACHE_SNOOP_SEPTAG 0
428 #endif
428 #endif
429
429
430 #ifndef CONFIG_CACHE_FIXED
430 #ifndef CONFIG_CACHE_FIXED
431 #define CONFIG_CACHE_FIXED 0
431 #define CONFIG_CACHE_FIXED 0
432 #endif
432 #endif
433
433
434 #ifndef CONFIG_DCACHE_LRAM
434 #ifndef CONFIG_DCACHE_LRAM
435 #define CONFIG_DCACHE_LRAM 0
435 #define CONFIG_DCACHE_LRAM 0
436 #endif
436 #endif
437
437
438 #ifndef CONFIG_DCACHE_LRSTART
438 #ifndef CONFIG_DCACHE_LRSTART
439 #define CONFIG_DCACHE_LRSTART 8F
439 #define CONFIG_DCACHE_LRSTART 8F
440 #endif
440 #endif
441
441
442 #if defined CONFIG_DCACHE_LRAM_SZ2
442 #if defined CONFIG_DCACHE_LRAM_SZ2
443 #define CFG_DLRAM_SIZE 2
443 #define CFG_DLRAM_SIZE 2
444 #elif defined CONFIG_DCACHE_LRAM_SZ4
444 #elif defined CONFIG_DCACHE_LRAM_SZ4
445 #define CFG_DLRAM_SIZE 4
445 #define CFG_DLRAM_SIZE 4
446 #elif defined CONFIG_DCACHE_LRAM_SZ8
446 #elif defined CONFIG_DCACHE_LRAM_SZ8
447 #define CFG_DLRAM_SIZE 8
447 #define CFG_DLRAM_SIZE 8
448 #elif defined CONFIG_DCACHE_LRAM_SZ16
448 #elif defined CONFIG_DCACHE_LRAM_SZ16
449 #define CFG_DLRAM_SIZE 16
449 #define CFG_DLRAM_SIZE 16
450 #elif defined CONFIG_DCACHE_LRAM_SZ32
450 #elif defined CONFIG_DCACHE_LRAM_SZ32
451 #define CFG_DLRAM_SIZE 32
451 #define CFG_DLRAM_SIZE 32
452 #elif defined CONFIG_DCACHE_LRAM_SZ64
452 #elif defined CONFIG_DCACHE_LRAM_SZ64
453 #define CFG_DLRAM_SIZE 64
453 #define CFG_DLRAM_SIZE 64
454 #elif defined CONFIG_DCACHE_LRAM_SZ128
454 #elif defined CONFIG_DCACHE_LRAM_SZ128
455 #define CFG_DLRAM_SIZE 128
455 #define CFG_DLRAM_SIZE 128
456 #elif defined CONFIG_DCACHE_LRAM_SZ256
456 #elif defined CONFIG_DCACHE_LRAM_SZ256
457 #define CFG_DLRAM_SIZE 256
457 #define CFG_DLRAM_SIZE 256
458 #else
458 #else
459 #define CFG_DLRAM_SIZE 1
459 #define CFG_DLRAM_SIZE 1
460 #endif
460 #endif
461
461
462 #if defined CONFIG_MMU_PAGE_4K
462 #if defined CONFIG_MMU_PAGE_4K
463 #define CONFIG_MMU_PAGE 0
463 #define CONFIG_MMU_PAGE 0
464 #elif defined CONFIG_MMU_PAGE_8K
464 #elif defined CONFIG_MMU_PAGE_8K
465 #define CONFIG_MMU_PAGE 1
465 #define CONFIG_MMU_PAGE 1
466 #elif defined CONFIG_MMU_PAGE_16K
466 #elif defined CONFIG_MMU_PAGE_16K
467 #define CONFIG_MMU_PAGE 2
467 #define CONFIG_MMU_PAGE 2
468 #elif defined CONFIG_MMU_PAGE_32K
468 #elif defined CONFIG_MMU_PAGE_32K
469 #define CONFIG_MMU_PAGE 3
469 #define CONFIG_MMU_PAGE 3
470 #elif defined CONFIG_MMU_PAGE_PROG
470 #elif defined CONFIG_MMU_PAGE_PROG
471 #define CONFIG_MMU_PAGE 4
471 #define CONFIG_MMU_PAGE 4
472 #else
472 #else
473 #define CONFIG_MMU_PAGE 0
473 #define CONFIG_MMU_PAGE 0
474 #endif
474 #endif
475
475
476 #ifdef CONFIG_MMU_ENABLE
476 #ifdef CONFIG_MMU_ENABLE
477 #define CONFIG_MMUEN 1
477 #define CONFIG_MMUEN 1
478
478
479 #ifdef CONFIG_MMU_SPLIT
479 #ifdef CONFIG_MMU_SPLIT
480 #define CONFIG_TLB_TYPE 0
480 #define CONFIG_TLB_TYPE 0
481 #endif
481 #endif
482 #ifdef CONFIG_MMU_COMBINED
482 #ifdef CONFIG_MMU_COMBINED
483 #define CONFIG_TLB_TYPE 1
483 #define CONFIG_TLB_TYPE 1
484 #endif
484 #endif
485
485
486 #ifdef CONFIG_MMU_REPARRAY
486 #ifdef CONFIG_MMU_REPARRAY
487 #define CONFIG_TLB_REP 0
487 #define CONFIG_TLB_REP 0
488 #endif
488 #endif
489 #ifdef CONFIG_MMU_REPINCREMENT
489 #ifdef CONFIG_MMU_REPINCREMENT
490 #define CONFIG_TLB_REP 1
490 #define CONFIG_TLB_REP 1
491 #endif
491 #endif
492
492
493 #ifdef CONFIG_MMU_I2
493 #ifdef CONFIG_MMU_I2
494 #define CONFIG_ITLBNUM 2
494 #define CONFIG_ITLBNUM 2
495 #endif
495 #endif
496 #ifdef CONFIG_MMU_I4
496 #ifdef CONFIG_MMU_I4
497 #define CONFIG_ITLBNUM 4
497 #define CONFIG_ITLBNUM 4
498 #endif
498 #endif
499 #ifdef CONFIG_MMU_I8
499 #ifdef CONFIG_MMU_I8
500 #define CONFIG_ITLBNUM 8
500 #define CONFIG_ITLBNUM 8
501 #endif
501 #endif
502 #ifdef CONFIG_MMU_I16
502 #ifdef CONFIG_MMU_I16
503 #define CONFIG_ITLBNUM 16
503 #define CONFIG_ITLBNUM 16
504 #endif
504 #endif
505 #ifdef CONFIG_MMU_I32
505 #ifdef CONFIG_MMU_I32
506 #define CONFIG_ITLBNUM 32
506 #define CONFIG_ITLBNUM 32
507 #endif
507 #endif
508
508
509 #define CONFIG_DTLBNUM 2
509 #define CONFIG_DTLBNUM 2
510 #ifdef CONFIG_MMU_D2
510 #ifdef CONFIG_MMU_D2
511 #undef CONFIG_DTLBNUM
511 #undef CONFIG_DTLBNUM
512 #define CONFIG_DTLBNUM 2
512 #define CONFIG_DTLBNUM 2
513 #endif
513 #endif
514 #ifdef CONFIG_MMU_D4
514 #ifdef CONFIG_MMU_D4
515 #undef CONFIG_DTLBNUM
515 #undef CONFIG_DTLBNUM
516 #define CONFIG_DTLBNUM 4
516 #define CONFIG_DTLBNUM 4
517 #endif
517 #endif
518 #ifdef CONFIG_MMU_D8
518 #ifdef CONFIG_MMU_D8
519 #undef CONFIG_DTLBNUM
519 #undef CONFIG_DTLBNUM
520 #define CONFIG_DTLBNUM 8
520 #define CONFIG_DTLBNUM 8
521 #endif
521 #endif
522 #ifdef CONFIG_MMU_D16
522 #ifdef CONFIG_MMU_D16
523 #undef CONFIG_DTLBNUM
523 #undef CONFIG_DTLBNUM
524 #define CONFIG_DTLBNUM 16
524 #define CONFIG_DTLBNUM 16
525 #endif
525 #endif
526 #ifdef CONFIG_MMU_D32
526 #ifdef CONFIG_MMU_D32
527 #undef CONFIG_DTLBNUM
527 #undef CONFIG_DTLBNUM
528 #define CONFIG_DTLBNUM 32
528 #define CONFIG_DTLBNUM 32
529 #endif
529 #endif
530 #ifdef CONFIG_MMU_FASTWB
530 #ifdef CONFIG_MMU_FASTWB
531 #define CFG_MMU_FASTWB 1
531 #define CFG_MMU_FASTWB 1
532 #else
532 #else
533 #define CFG_MMU_FASTWB 0
533 #define CFG_MMU_FASTWB 0
534 #endif
534 #endif
535
535
536 #else
536 #else
537 #define CONFIG_MMUEN 0
537 #define CONFIG_MMUEN 0
538 #define CONFIG_ITLBNUM 2
538 #define CONFIG_ITLBNUM 2
539 #define CONFIG_DTLBNUM 2
539 #define CONFIG_DTLBNUM 2
540 #define CONFIG_TLB_TYPE 1
540 #define CONFIG_TLB_TYPE 1
541 #define CONFIG_TLB_REP 1
541 #define CONFIG_TLB_REP 1
542 #define CFG_MMU_FASTWB 0
542 #define CFG_MMU_FASTWB 0
543 #endif
543 #endif
544
544
545 #ifndef CONFIG_DSU_ENABLE
545 #ifndef CONFIG_DSU_ENABLE
546 #define CONFIG_DSU_ENABLE 0
546 #define CONFIG_DSU_ENABLE 0
547 #endif
547 #endif
548
548
549 #if defined CONFIG_DSU_ITRACESZ1
549 #if defined CONFIG_DSU_ITRACESZ1
550 #define CFG_DSU_ITB 1
550 #define CFG_DSU_ITB 1
551 #elif CONFIG_DSU_ITRACESZ2
551 #elif CONFIG_DSU_ITRACESZ2
552 #define CFG_DSU_ITB 2
552 #define CFG_DSU_ITB 2
553 #elif CONFIG_DSU_ITRACESZ4
553 #elif CONFIG_DSU_ITRACESZ4
554 #define CFG_DSU_ITB 4
554 #define CFG_DSU_ITB 4
555 #elif CONFIG_DSU_ITRACESZ8
555 #elif CONFIG_DSU_ITRACESZ8
556 #define CFG_DSU_ITB 8
556 #define CFG_DSU_ITB 8
557 #elif CONFIG_DSU_ITRACESZ16
557 #elif CONFIG_DSU_ITRACESZ16
558 #define CFG_DSU_ITB 16
558 #define CFG_DSU_ITB 16
559 #else
559 #else
560 #define CFG_DSU_ITB 0
560 #define CFG_DSU_ITB 0
561 #endif
561 #endif
562
562
563 #if defined CONFIG_DSU_ATRACESZ1
563 #if defined CONFIG_DSU_ATRACESZ1
564 #define CFG_DSU_ATB 1
564 #define CFG_DSU_ATB 1
565 #elif CONFIG_DSU_ATRACESZ2
565 #elif CONFIG_DSU_ATRACESZ2
566 #define CFG_DSU_ATB 2
566 #define CFG_DSU_ATB 2
567 #elif CONFIG_DSU_ATRACESZ4
567 #elif CONFIG_DSU_ATRACESZ4
568 #define CFG_DSU_ATB 4
568 #define CFG_DSU_ATB 4
569 #elif CONFIG_DSU_ATRACESZ8
569 #elif CONFIG_DSU_ATRACESZ8
570 #define CFG_DSU_ATB 8
570 #define CFG_DSU_ATB 8
571 #elif CONFIG_DSU_ATRACESZ16
571 #elif CONFIG_DSU_ATRACESZ16
572 #define CFG_DSU_ATB 16
572 #define CFG_DSU_ATB 16
573 #else
573 #else
574 #define CFG_DSU_ATB 0
574 #define CFG_DSU_ATB 0
575 #endif
575 #endif
576
576
577 #ifndef CONFIG_LEON3FT_EN
577 #ifndef CONFIG_LEON3FT_EN
578 #define CONFIG_LEON3FT_EN 0
578 #define CONFIG_LEON3FT_EN 0
579 #endif
579 #endif
580
580
581 #if defined CONFIG_IUFT_PAR
581 #if defined CONFIG_IUFT_PAR
582 #define CONFIG_IUFT_EN 1
582 #define CONFIG_IUFT_EN 1
583 #elif defined CONFIG_IUFT_DMR
583 #elif defined CONFIG_IUFT_DMR
584 #define CONFIG_IUFT_EN 2
584 #define CONFIG_IUFT_EN 2
585 #elif defined CONFIG_IUFT_BCH
585 #elif defined CONFIG_IUFT_BCH
586 #define CONFIG_IUFT_EN 3
586 #define CONFIG_IUFT_EN 3
587 #elif defined CONFIG_IUFT_TMR
587 #elif defined CONFIG_IUFT_TMR
588 #define CONFIG_IUFT_EN 4
588 #define CONFIG_IUFT_EN 4
589 #else
589 #else
590 #define CONFIG_IUFT_EN 0
590 #define CONFIG_IUFT_EN 0
591 #endif
591 #endif
592 #ifndef CONFIG_RF_ERRINJ
592 #ifndef CONFIG_RF_ERRINJ
593 #define CONFIG_RF_ERRINJ 0
593 #define CONFIG_RF_ERRINJ 0
594 #endif
594 #endif
595
595
596 #ifndef CONFIG_FPUFT_EN
596 #ifndef CONFIG_FPUFT_EN
597 #define CONFIG_FPUFT 0
597 #define CONFIG_FPUFT 0
598 #else
598 #else
599 #ifdef CONFIG_FPU_GRFPU
599 #ifdef CONFIG_FPU_GRFPU
600 #define CONFIG_FPUFT 2
600 #define CONFIG_FPUFT 2
601 #else
601 #else
602 #define CONFIG_FPUFT 1
602 #define CONFIG_FPUFT 1
603 #endif
603 #endif
604 #endif
604 #endif
605
605
606 #ifndef CONFIG_CACHE_FT_EN
606 #ifndef CONFIG_CACHE_FT_EN
607 #define CONFIG_CACHE_FT_EN 0
607 #define CONFIG_CACHE_FT_EN 0
608 #endif
608 #endif
609 #ifndef CONFIG_CACHE_ERRINJ
609 #ifndef CONFIG_CACHE_ERRINJ
610 #define CONFIG_CACHE_ERRINJ 0
610 #define CONFIG_CACHE_ERRINJ 0
611 #endif
611 #endif
612
612
613 #ifndef CONFIG_LEON3_NETLIST
613 #ifndef CONFIG_LEON3_NETLIST
614 #define CONFIG_LEON3_NETLIST 0
614 #define CONFIG_LEON3_NETLIST 0
615 #endif
615 #endif
616
616
617 #ifdef CONFIG_DEBUG_PC32
617 #ifdef CONFIG_DEBUG_PC32
618 #define CFG_DEBUG_PC32 0
618 #define CFG_DEBUG_PC32 0
619 #else
619 #else
620 #define CFG_DEBUG_PC32 2
620 #define CFG_DEBUG_PC32 2
621 #endif
621 #endif
622 #ifndef CONFIG_IU_DISAS
622 #ifndef CONFIG_IU_DISAS
623 #define CONFIG_IU_DISAS 0
623 #define CONFIG_IU_DISAS 0
624 #endif
624 #endif
625 #ifndef CONFIG_IU_DISAS_NET
625 #ifndef CONFIG_IU_DISAS_NET
626 #define CONFIG_IU_DISAS_NET 0
626 #define CONFIG_IU_DISAS_NET 0
627 #endif
627 #endif
628
628
629
629
630 #ifndef CONFIG_AHB_SPLIT
630 #ifndef CONFIG_AHB_SPLIT
631 #define CONFIG_AHB_SPLIT 0
631 #define CONFIG_AHB_SPLIT 0
632 #endif
632 #endif
633
633
634 #ifndef CONFIG_AHB_RROBIN
634 #ifndef CONFIG_AHB_RROBIN
635 #define CONFIG_AHB_RROBIN 0
635 #define CONFIG_AHB_RROBIN 0
636 #endif
636 #endif
637
637
638 #ifndef CONFIG_AHB_IOADDR
638 #ifndef CONFIG_AHB_IOADDR
639 #define CONFIG_AHB_IOADDR FFF
639 #define CONFIG_AHB_IOADDR FFF
640 #endif
640 #endif
641
641
642 #ifndef CONFIG_APB_HADDR
642 #ifndef CONFIG_APB_HADDR
643 #define CONFIG_APB_HADDR 800
643 #define CONFIG_APB_HADDR 800
644 #endif
644 #endif
645
645
646 #ifndef CONFIG_AHB_MON
646 #ifndef CONFIG_AHB_MON
647 #define CONFIG_AHB_MON 0
647 #define CONFIG_AHB_MON 0
648 #endif
648 #endif
649
649
650 #ifndef CONFIG_AHB_MONERR
650 #ifndef CONFIG_AHB_MONERR
651 #define CONFIG_AHB_MONERR 0
651 #define CONFIG_AHB_MONERR 0
652 #endif
652 #endif
653
653
654 #ifndef CONFIG_AHB_MONWAR
654 #ifndef CONFIG_AHB_MONWAR
655 #define CONFIG_AHB_MONWAR 0
655 #define CONFIG_AHB_MONWAR 0
656 #endif
656 #endif
657
657
658 #ifndef CONFIG_AHB_DTRACE
658 #ifndef CONFIG_AHB_DTRACE
659 #define CONFIG_AHB_DTRACE 0
659 #define CONFIG_AHB_DTRACE 0
660 #endif
660 #endif
661
661
662 #ifndef CONFIG_DSU_UART
662 #ifndef CONFIG_DSU_UART
663 #define CONFIG_DSU_UART 0
663 #define CONFIG_DSU_UART 0
664 #endif
664 #endif
665
665
666
666
667 #ifndef CONFIG_DSU_JTAG
667 #ifndef CONFIG_DSU_JTAG
668 #define CONFIG_DSU_JTAG 0
668 #define CONFIG_DSU_JTAG 0
669 #endif
669 #endif
670
670
671 #ifndef CONFIG_DSU_ETH
671 #ifndef CONFIG_DSU_ETH
672 #define CONFIG_DSU_ETH 0
672 #define CONFIG_DSU_ETH 0
673 #endif
673 #endif
674
674
675 #ifndef CONFIG_DSU_IPMSB
675 #ifndef CONFIG_DSU_IPMSB
676 #define CONFIG_DSU_IPMSB C0A8
676 #define CONFIG_DSU_IPMSB C0A8
677 #endif
677 #endif
678
678
679 #ifndef CONFIG_DSU_IPLSB
679 #ifndef CONFIG_DSU_IPLSB
680 #define CONFIG_DSU_IPLSB 0033
680 #define CONFIG_DSU_IPLSB 0033
681 #endif
681 #endif
682
682
683 #ifndef CONFIG_DSU_ETHMSB
683 #ifndef CONFIG_DSU_ETHMSB
684 #define CONFIG_DSU_ETHMSB 020000
684 #define CONFIG_DSU_ETHMSB 020000
685 #endif
685 #endif
686
686
687 #ifndef CONFIG_DSU_ETHLSB
687 #ifndef CONFIG_DSU_ETHLSB
688 #define CONFIG_DSU_ETHLSB 000009
688 #define CONFIG_DSU_ETHLSB 000009
689 #endif
689 #endif
690
690
691 #if defined CONFIG_DSU_ETHSZ1
691 #if defined CONFIG_DSU_ETHSZ1
692 #define CFG_DSU_ETHB 1
692 #define CFG_DSU_ETHB 1
693 #elif CONFIG_DSU_ETHSZ2
693 #elif CONFIG_DSU_ETHSZ2
694 #define CFG_DSU_ETHB 2
694 #define CFG_DSU_ETHB 2
695 #elif CONFIG_DSU_ETHSZ4
695 #elif CONFIG_DSU_ETHSZ4
696 #define CFG_DSU_ETHB 4
696 #define CFG_DSU_ETHB 4
697 #elif CONFIG_DSU_ETHSZ8
697 #elif CONFIG_DSU_ETHSZ8
698 #define CFG_DSU_ETHB 8
698 #define CFG_DSU_ETHB 8
699 #elif CONFIG_DSU_ETHSZ16
699 #elif CONFIG_DSU_ETHSZ16
700 #define CFG_DSU_ETHB 16
700 #define CFG_DSU_ETHB 16
701 #elif CONFIG_DSU_ETHSZ32
701 #elif CONFIG_DSU_ETHSZ32
702 #define CFG_DSU_ETHB 32
702 #define CFG_DSU_ETHB 32
703 #else
703 #else
704 #define CFG_DSU_ETHB 1
704 #define CFG_DSU_ETHB 1
705 #endif
705 #endif
706
706
707 #ifndef CONFIG_DSU_ETH_PROG
707 #ifndef CONFIG_DSU_ETH_PROG
708 #define CONFIG_DSU_ETH_PROG 0
708 #define CONFIG_DSU_ETH_PROG 0
709 #endif
709 #endif
710
710
711 #ifndef CONFIG_MCTRL_LEON2
711 #ifndef CONFIG_MCTRL_LEON2
712 #define CONFIG_MCTRL_LEON2 0
712 #define CONFIG_MCTRL_LEON2 0
713 #endif
713 #endif
714
714
715 #ifndef CONFIG_MCTRL_SDRAM
715 #ifndef CONFIG_MCTRL_SDRAM
716 #define CONFIG_MCTRL_SDRAM 0
716 #define CONFIG_MCTRL_SDRAM 0
717 #endif
717 #endif
718
718
719 #ifndef CONFIG_MCTRL_SDRAM_SEPBUS
719 #ifndef CONFIG_MCTRL_SDRAM_SEPBUS
720 #define CONFIG_MCTRL_SDRAM_SEPBUS 0
720 #define CONFIG_MCTRL_SDRAM_SEPBUS 0
721 #endif
721 #endif
722
722
723 #ifndef CONFIG_MCTRL_SDRAM_INVCLK
723 #ifndef CONFIG_MCTRL_SDRAM_INVCLK
724 #define CONFIG_MCTRL_SDRAM_INVCLK 0
724 #define CONFIG_MCTRL_SDRAM_INVCLK 0
725 #endif
725 #endif
726
726
727 #ifndef CONFIG_MCTRL_SDRAM_BUS64
727 #ifndef CONFIG_MCTRL_SDRAM_BUS64
728 #define CONFIG_MCTRL_SDRAM_BUS64 0
728 #define CONFIG_MCTRL_SDRAM_BUS64 0
729 #endif
729 #endif
730
730
731 #ifndef CONFIG_MCTRL_8BIT
731 #ifndef CONFIG_MCTRL_8BIT
732 #define CONFIG_MCTRL_8BIT 0
732 #define CONFIG_MCTRL_8BIT 0
733 #endif
733 #endif
734
734
735 #ifndef CONFIG_MCTRL_16BIT
735 #ifndef CONFIG_MCTRL_16BIT
736 #define CONFIG_MCTRL_16BIT 0
736 #define CONFIG_MCTRL_16BIT 0
737 #endif
737 #endif
738
738
739 #ifndef CONFIG_MCTRL_5CS
739 #ifndef CONFIG_MCTRL_5CS
740 #define CONFIG_MCTRL_5CS 0
740 #define CONFIG_MCTRL_5CS 0
741 #endif
741 #endif
742
742
743 #ifndef CONFIG_MCTRL_EDAC
743 #ifndef CONFIG_MCTRL_EDAC
744 #define CONFIG_MCTRL_EDAC 0
744 #define CONFIG_MCTRL_EDAC 0
745 #endif
745 #endif
746
746
747 #ifndef CONFIG_MCTRL_PAGE
747 #ifndef CONFIG_MCTRL_PAGE
748 #define CONFIG_MCTRL_PAGE 0
748 #define CONFIG_MCTRL_PAGE 0
749 #endif
749 #endif
750
750
751 #ifndef CONFIG_MCTRL_PROGPAGE
751 #ifndef CONFIG_MCTRL_PROGPAGE
752 #define CONFIG_MCTRL_PROGPAGE 0
752 #define CONFIG_MCTRL_PROGPAGE 0
753 #endif
753 #endif
754
754
755 #ifndef CONFIG_DDRSP
755 #ifndef CONFIG_DDRSP
756 #define CONFIG_DDRSP 0
756 #define CONFIG_DDRSP 0
757 #endif
757 #endif
758
758
759 #ifndef CONFIG_DDRSP_INIT
759 #ifndef CONFIG_DDRSP_INIT
760 #define CONFIG_DDRSP_INIT 0
760 #define CONFIG_DDRSP_INIT 0
761 #endif
761 #endif
762
762
763 #ifndef CONFIG_DDRSP_FREQ
763 #ifndef CONFIG_DDRSP_FREQ
764 #define CONFIG_DDRSP_FREQ 100
764 #define CONFIG_DDRSP_FREQ 100
765 #endif
765 #endif
766
766
767 #ifndef CONFIG_DDRSP_COL
767 #ifndef CONFIG_DDRSP_COL
768 #define CONFIG_DDRSP_COL 9
768 #define CONFIG_DDRSP_COL 9
769 #endif
769 #endif
770
770
771 #ifndef CONFIG_DDRSP_MBYTE
771 #ifndef CONFIG_DDRSP_MBYTE
772 #define CONFIG_DDRSP_MBYTE 8
772 #define CONFIG_DDRSP_MBYTE 8
773 #endif
773 #endif
774
774
775 #ifndef CONFIG_DDRSP_RSKEW
775 #ifndef CONFIG_DDRSP_RSKEW
776 #define CONFIG_DDRSP_RSKEW 0
776 #define CONFIG_DDRSP_RSKEW 0
777 #endif
777 #endif
778 #ifndef CONFIG_AHBROM_ENABLE
778 #ifndef CONFIG_AHBROM_ENABLE
779 #define CONFIG_AHBROM_ENABLE 0
779 #define CONFIG_AHBROM_ENABLE 0
780 #endif
780 #endif
781
781
782 #ifndef CONFIG_AHBROM_START
782 #ifndef CONFIG_AHBROM_START
783 #define CONFIG_AHBROM_START 000
783 #define CONFIG_AHBROM_START 000
784 #endif
784 #endif
785
785
786 #ifndef CONFIG_AHBROM_PIPE
786 #ifndef CONFIG_AHBROM_PIPE
787 #define CONFIG_AHBROM_PIPE 0
787 #define CONFIG_AHBROM_PIPE 0
788 #endif
788 #endif
789
789
790 #if (CONFIG_AHBROM_START == 0) && (CONFIG_AHBROM_ENABLE == 1)
790 #if (CONFIG_AHBROM_START == 0) && (CONFIG_AHBROM_ENABLE == 1)
791 #define CONFIG_ROM_START 100
791 #define CONFIG_ROM_START 100
792 #else
792 #else
793 #define CONFIG_ROM_START 000
793 #define CONFIG_ROM_START 000
794 #endif
794 #endif
795
795
796
796
797 #ifndef CONFIG_AHBRAM_ENABLE
797 #ifndef CONFIG_AHBRAM_ENABLE
798 #define CONFIG_AHBRAM_ENABLE 0
798 #define CONFIG_AHBRAM_ENABLE 0
799 #endif
799 #endif
800
800
801 #ifndef CONFIG_AHBRAM_START
801 #ifndef CONFIG_AHBRAM_START
802 #define CONFIG_AHBRAM_START A00
802 #define CONFIG_AHBRAM_START A00
803 #endif
803 #endif
804
804
805 #if defined CONFIG_AHBRAM_SZ1
805 #if defined CONFIG_AHBRAM_SZ1
806 #define CFG_AHBRAMSZ 1
806 #define CFG_AHBRAMSZ 1
807 #elif CONFIG_AHBRAM_SZ2
807 #elif CONFIG_AHBRAM_SZ2
808 #define CFG_AHBRAMSZ 2
808 #define CFG_AHBRAMSZ 2
809 #elif CONFIG_AHBRAM_SZ4
809 #elif CONFIG_AHBRAM_SZ4
810 #define CFG_AHBRAMSZ 4
810 #define CFG_AHBRAMSZ 4
811 #elif CONFIG_AHBRAM_SZ8
811 #elif CONFIG_AHBRAM_SZ8
812 #define CFG_AHBRAMSZ 8
812 #define CFG_AHBRAMSZ 8
813 #elif CONFIG_AHBRAM_SZ16
813 #elif CONFIG_AHBRAM_SZ16
814 #define CFG_AHBRAMSZ 16
814 #define CFG_AHBRAMSZ 16
815 #elif CONFIG_AHBRAM_SZ32
815 #elif CONFIG_AHBRAM_SZ32
816 #define CFG_AHBRAMSZ 32
816 #define CFG_AHBRAMSZ 32
817 #elif CONFIG_AHBRAM_SZ64
817 #elif CONFIG_AHBRAM_SZ64
818 #define CFG_AHBRAMSZ 64
818 #define CFG_AHBRAMSZ 64
819 #else
819 #else
820 #define CFG_AHBRAMSZ 1
820 #define CFG_AHBRAMSZ 1
821 #endif
821 #endif
822
822
823 #ifndef CONFIG_GRETH_ENABLE
823 #ifndef CONFIG_GRETH_ENABLE
824 #define CONFIG_GRETH_ENABLE 0
824 #define CONFIG_GRETH_ENABLE 0
825 #endif
825 #endif
826
826
827 #ifndef CONFIG_GRETH_GIGA
827 #ifndef CONFIG_GRETH_GIGA
828 #define CONFIG_GRETH_GIGA 0
828 #define CONFIG_GRETH_GIGA 0
829 #endif
829 #endif
830
830
831 #if defined CONFIG_GRETH_FIFO4
831 #if defined CONFIG_GRETH_FIFO4
832 #define CFG_GRETH_FIFO 4
832 #define CFG_GRETH_FIFO 4
833 #elif defined CONFIG_GRETH_FIFO8
833 #elif defined CONFIG_GRETH_FIFO8
834 #define CFG_GRETH_FIFO 8
834 #define CFG_GRETH_FIFO 8
835 #elif defined CONFIG_GRETH_FIFO16
835 #elif defined CONFIG_GRETH_FIFO16
836 #define CFG_GRETH_FIFO 16
836 #define CFG_GRETH_FIFO 16
837 #elif defined CONFIG_GRETH_FIFO32
837 #elif defined CONFIG_GRETH_FIFO32
838 #define CFG_GRETH_FIFO 32
838 #define CFG_GRETH_FIFO 32
839 #elif defined CONFIG_GRETH_FIFO64
839 #elif defined CONFIG_GRETH_FIFO64
840 #define CFG_GRETH_FIFO 64
840 #define CFG_GRETH_FIFO 64
841 #else
841 #else
842 #define CFG_GRETH_FIFO 8
842 #define CFG_GRETH_FIFO 8
843 #endif
843 #endif
844
844
845 #ifndef CONFIG_UART1_ENABLE
845 #ifndef CONFIG_UART1_ENABLE
846 #define CONFIG_UART1_ENABLE 0
846 #define CONFIG_UART1_ENABLE 0
847 #endif
847 #endif
848
848
849 #if defined CONFIG_UA1_FIFO1
849 #if defined CONFIG_UA1_FIFO1
850 #define CFG_UA1_FIFO 1
850 #define CFG_UA1_FIFO 1
851 #elif defined CONFIG_UA1_FIFO2
851 #elif defined CONFIG_UA1_FIFO2
852 #define CFG_UA1_FIFO 2
852 #define CFG_UA1_FIFO 2
853 #elif defined CONFIG_UA1_FIFO4
853 #elif defined CONFIG_UA1_FIFO4
854 #define CFG_UA1_FIFO 4
854 #define CFG_UA1_FIFO 4
855 #elif defined CONFIG_UA1_FIFO8
855 #elif defined CONFIG_UA1_FIFO8
856 #define CFG_UA1_FIFO 8
856 #define CFG_UA1_FIFO 8
857 #elif defined CONFIG_UA1_FIFO16
857 #elif defined CONFIG_UA1_FIFO16
858 #define CFG_UA1_FIFO 16
858 #define CFG_UA1_FIFO 16
859 #elif defined CONFIG_UA1_FIFO32
859 #elif defined CONFIG_UA1_FIFO32
860 #define CFG_UA1_FIFO 32
860 #define CFG_UA1_FIFO 32
861 #else
861 #else
862 #define CFG_UA1_FIFO 1
862 #define CFG_UA1_FIFO 1
863 #endif
863 #endif
864
864
865 #ifndef CONFIG_IRQ3_ENABLE
865 #ifndef CONFIG_IRQ3_ENABLE
866 #define CONFIG_IRQ3_ENABLE 0
866 #define CONFIG_IRQ3_ENABLE 0
867 #endif
867 #endif
868 #ifndef CONFIG_IRQ3_NSEC
868 #ifndef CONFIG_IRQ3_NSEC
869 #define CONFIG_IRQ3_NSEC 0
869 #define CONFIG_IRQ3_NSEC 0
870 #endif
870 #endif
871 #ifndef CONFIG_GPT_ENABLE
871 #ifndef CONFIG_GPT_ENABLE
872 #define CONFIG_GPT_ENABLE 0
872 #define CONFIG_GPT_ENABLE 0
873 #endif
873 #endif
874
874
875 #ifndef CONFIG_GPT_NTIM
875 #ifndef CONFIG_GPT_NTIM
876 #define CONFIG_GPT_NTIM 1
876 #define CONFIG_GPT_NTIM 1
877 #endif
877 #endif
878
878
879 #ifndef CONFIG_GPT_SW
879 #ifndef CONFIG_GPT_SW
880 #define CONFIG_GPT_SW 8
880 #define CONFIG_GPT_SW 8
881 #endif
881 #endif
882
882
883 #ifndef CONFIG_GPT_TW
883 #ifndef CONFIG_GPT_TW
884 #define CONFIG_GPT_TW 8
884 #define CONFIG_GPT_TW 8
885 #endif
885 #endif
886
886
887 #ifndef CONFIG_GPT_IRQ
887 #ifndef CONFIG_GPT_IRQ
888 #define CONFIG_GPT_IRQ 8
888 #define CONFIG_GPT_IRQ 8
889 #endif
889 #endif
890
890
891 #ifndef CONFIG_GPT_SEPIRQ
891 #ifndef CONFIG_GPT_SEPIRQ
892 #define CONFIG_GPT_SEPIRQ 0
892 #define CONFIG_GPT_SEPIRQ 0
893 #endif
893 #endif
894 #ifndef CONFIG_GPT_ENABLE
894 #ifndef CONFIG_GPT_ENABLE
895 #define CONFIG_GPT_ENABLE 0
895 #define CONFIG_GPT_ENABLE 0
896 #endif
896 #endif
897
897
898 #ifndef CONFIG_GPT_NTIM
898 #ifndef CONFIG_GPT_NTIM
899 #define CONFIG_GPT_NTIM 1
899 #define CONFIG_GPT_NTIM 1
900 #endif
900 #endif
901
901
902 #ifndef CONFIG_GPT_SW
902 #ifndef CONFIG_GPT_SW
903 #define CONFIG_GPT_SW 8
903 #define CONFIG_GPT_SW 8
904 #endif
904 #endif
905
905
906 #ifndef CONFIG_GPT_TW
906 #ifndef CONFIG_GPT_TW
907 #define CONFIG_GPT_TW 8
907 #define CONFIG_GPT_TW 8
908 #endif
908 #endif
909
909
910 #ifndef CONFIG_GPT_IRQ
910 #ifndef CONFIG_GPT_IRQ
911 #define CONFIG_GPT_IRQ 8
911 #define CONFIG_GPT_IRQ 8
912 #endif
912 #endif
913
913
914 #ifndef CONFIG_GPT_SEPIRQ
914 #ifndef CONFIG_GPT_SEPIRQ
915 #define CONFIG_GPT_SEPIRQ 0
915 #define CONFIG_GPT_SEPIRQ 0
916 #endif
916 #endif
917
917
918 #ifndef CONFIG_GPT_WDOGEN
918 #ifndef CONFIG_GPT_WDOGEN
919 #define CONFIG_GPT_WDOGEN 0
919 #define CONFIG_GPT_WDOGEN 0
920 #endif
920 #endif
921
921
922 #ifndef CONFIG_GPT_WDOG
922 #ifndef CONFIG_GPT_WDOG
923 #define CONFIG_GPT_WDOG 0
923 #define CONFIG_GPT_WDOG 0
924 #endif
924 #endif
925
925
926 #ifndef CONFIG_GRGPIO_ENABLE
926 #ifndef CONFIG_GRGPIO_ENABLE
927 #define CONFIG_GRGPIO_ENABLE 0
927 #define CONFIG_GRGPIO_ENABLE 0
928 #endif
928 #endif
929 #ifndef CONFIG_GRGPIO_IMASK
929 #ifndef CONFIG_GRGPIO_IMASK
930 #define CONFIG_GRGPIO_IMASK 0000
930 #define CONFIG_GRGPIO_IMASK 0000
931 #endif
931 #endif
932 #ifndef CONFIG_GRGPIO_WIDTH
932 #ifndef CONFIG_GRGPIO_WIDTH
933 #define CONFIG_GRGPIO_WIDTH 1
933 #define CONFIG_GRGPIO_WIDTH 1
934 #endif
934 #endif
935
935
936 #ifndef CONFIG_VGA_ENABLE
936 #ifndef CONFIG_VGA_ENABLE
937 #define CONFIG_VGA_ENABLE 0
937 #define CONFIG_VGA_ENABLE 0
938 #endif
938 #endif
939 #ifndef CONFIG_SVGA_ENABLE
939 #ifndef CONFIG_SVGA_ENABLE
940 #define CONFIG_SVGA_ENABLE 0
940 #define CONFIG_SVGA_ENABLE 0
941 #endif
941 #endif
942 #ifndef CONFIG_KBD_ENABLE
942 #ifndef CONFIG_KBD_ENABLE
943 #define CONFIG_KBD_ENABLE 0
943 #define CONFIG_KBD_ENABLE 0
944 #endif
944 #endif
945
945
946
946
947 #ifndef CONFIG_DEBUG_UART
947 #ifndef CONFIG_DEBUG_UART
948 #define CONFIG_DEBUG_UART 0
948 #define CONFIG_DEBUG_UART 0
949 #endif
949 #endif
Show file before | Show file after | Hide comments
@@ -1,56 +1,56
1 <?xml version="1.0" encoding="UTF-8" ?>
1 <?xml version="1.0" encoding="UTF-8" ?>
2 <document>
2 <document>
3 <!--The data in this file is primarily intended for consumption by Xilinx tools.
3 <!--The data in this file is primarily intended for consumption by Xilinx tools.
4 The structure and the elements are likely to change over the next few releases.
4 The structure and the elements are likely to change over the next few releases.
5 This means code written to parse this file will need to be revisited each subsequent release.-->
5 This means code written to parse this file will need to be revisited each subsequent release.-->
6 <application name="pn" timeStamp="Wed Dec 8 09:10:18 2010">
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13 <section name="Project Statistics" visible="true">
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14 <property name="PROP_Enable_Message_Filtering" value="false" type="design"/>
15 <property name="PROP_FitterReportFormat" value="HTML" type="process"/>
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16 <property name="PROP_LastAppliedGoal" value="Balanced" type="design"/>
16 <property name="PROP_LastAppliedGoal" value="Balanced" type="design"/>
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18 <property name="PROP_ManualCompileOrderImp" value="false" type="design"/>
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37 <property name="PROP_xilxMapPackRegInto" value="For Inputs and Outputs" type="process"/>
38 <property name="PROP_xilxNgdbldMacro" value="changed" type="process"/>
38 <property name="PROP_xilxNgdbldMacro" value="changed" type="process"/>
39 <property name="PROP_xilxNgdbld_AUL" value="true" type="process"/>
39 <property name="PROP_xilxNgdbld_AUL" value="true" type="process"/>
40 <property name="PROP_xstBusDelimiter" value="()" type="process"/>
40 <property name="PROP_xstBusDelimiter" value="()" type="process"/>
41 <property name="PROP_xstPackIORegister" value="Yes" type="process"/>
41 <property name="PROP_xstPackIORegister" value="Yes" type="process"/>
42 <property name="PROP_xst_otherCmdLineOptions" value="-uc leon3mp.xcf" type="process"/>
42 <property name="PROP_xst_otherCmdLineOptions" value="-uc leon3mp.xcf" type="process"/>
43 <property name="PROP_AutoTop" value="false" type="design"/>
43 <property name="PROP_AutoTop" value="false" type="design"/>
44 <property name="PROP_DevFamily" value="Spartan3E" type="design"/>
44 <property name="PROP_DevFamily" value="Spartan3E" type="design"/>
45 <property name="PROP_xilxBitgCfg_GenOpt_MaskFile" value="true" type="process"/>
45 <property name="PROP_xilxBitgCfg_GenOpt_MaskFile" value="true" type="process"/>
46 <property name="PROP_DevDevice" value="xc3s1600e" type="design"/>
46 <property name="PROP_DevDevice" value="xc3s1600e" type="design"/>
47 <property name="PROP_DevFamilyPMName" value="spartan3e" type="design"/>
47 <property name="PROP_DevFamilyPMName" value="spartan3e" type="design"/>
48 <property name="PROP_DevPackage" value="fg320" type="design"/>
48 <property name="PROP_DevPackage" value="fg320" type="design"/>
49 <property name="PROP_Synthesis_Tool" value="XST (VHDL/Verilog)" type="design"/>
49 <property name="PROP_Synthesis_Tool" value="XST (VHDL/Verilog)" type="design"/>
50 <property name="PROP_DevSpeed" value="-4" type="design"/>
50 <property name="PROP_DevSpeed" value="-4" type="design"/>
51 <property name="PROP_PreferredLanguage" value="VHDL" type="design"/>
51 <property name="PROP_PreferredLanguage" value="VHDL" type="design"/>
52 <property name="FILE_UCF" value="1" type="source"/>
52 <property name="FILE_UCF" value="1" type="source"/>
53 <property name="FILE_VHDL" value="302" type="source"/>
53 <property name="FILE_VHDL" value="302" type="source"/>
54 </section>
54 </section>
55 </application>
55 </application>
56 </document>
56 </document>
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@@ -1,258 +1,265
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22
22
23 LIBRARY IEEE;
23 LIBRARY IEEE;
24 USE IEEE.numeric_std.ALL;
24 USE IEEE.numeric_std.ALL;
25 USE IEEE.std_logic_1164.ALL;
25 USE IEEE.std_logic_1164.ALL;
26
26
27 LIBRARY techmap;
27 LIBRARY techmap;
28 USE techmap.gencomp.ALL;
28 USE techmap.gencomp.ALL;
29
29
30 LIBRARY lpp;
30 LIBRARY lpp;
31 USE lpp.iir_filter.ALL;
31 USE lpp.iir_filter.ALL;
32 USE lpp.general_purpose.ALL;
32 USE lpp.general_purpose.ALL;
33
33
34 ENTITY IIR_CEL_CTRLR_v2 IS
34 ENTITY IIR_CEL_CTRLR_v2 IS
35 GENERIC (
35 GENERIC (
36 tech : INTEGER := 0;
36 tech : INTEGER := 0;
37 Mem_use : INTEGER := use_RAM;
37 Mem_use : INTEGER := use_RAM;
38 Sample_SZ : INTEGER := 18;
38 Sample_SZ : INTEGER := 18;
39 Coef_SZ : INTEGER := 9;
39 Coef_SZ : INTEGER := 9;
40 Coef_Nb : INTEGER := 25;
40 Coef_Nb : INTEGER := 25;
41 Coef_sel_SZ : INTEGER := 5;
41 Coef_sel_SZ : INTEGER := 5;
42 Cels_count : INTEGER := 5;
42 Cels_count : INTEGER := 5;
43 ChanelsCount : INTEGER := 8);
43 ChanelsCount : INTEGER := 8);
44 PORT (
44 PORT (
45 rstn : IN STD_LOGIC;
45 rstn : IN STD_LOGIC;
46 clk : IN STD_LOGIC;
46 clk : IN STD_LOGIC;
47
47
48 virg_pos : IN INTEGER;
48 virg_pos : IN INTEGER;
49 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
49 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
50
50
51 sample_in_val : IN STD_LOGIC;
51 sample_in_val : IN STD_LOGIC;
52 sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
52 sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
53
53
54 sample_out_val : OUT STD_LOGIC;
54 sample_out_val : OUT STD_LOGIC;
55 sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0));
55 sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0));
56 END IIR_CEL_CTRLR_v2;
56 END IIR_CEL_CTRLR_v2;
57
57
58 ARCHITECTURE ar_IIR_CEL_CTRLR_v2 OF IIR_CEL_CTRLR_v2 IS
58 ARCHITECTURE ar_IIR_CEL_CTRLR_v2 OF IIR_CEL_CTRLR_v2 IS
59
59
60 COMPONENT IIR_CEL_CTRLR_v2_DATAFLOW
60 COMPONENT IIR_CEL_CTRLR_v2_DATAFLOW
61 GENERIC (
61 GENERIC (
62 tech : INTEGER;
62 tech : INTEGER;
63 Mem_use : INTEGER;
63 Mem_use : INTEGER;
64 Sample_SZ : INTEGER;
64 Sample_SZ : INTEGER;
65 Coef_SZ : INTEGER;
65 Coef_SZ : INTEGER;
66 Coef_Nb : INTEGER;
66 Coef_Nb : INTEGER;
67 Coef_sel_SZ : INTEGER);
67 Coef_sel_SZ : INTEGER);
68 PORT (
68 PORT (
69 rstn : IN STD_LOGIC;
69 rstn : IN STD_LOGIC;
70 clk : IN STD_LOGIC;
70 clk : IN STD_LOGIC;
71 virg_pos : IN INTEGER;
71 virg_pos : IN INTEGER;
72 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
72 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
73 in_sel_src : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
73 in_sel_src : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
74 init_mem_done : out STD_LOGIC;
74 ram_sel_Wdata : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
75 ram_sel_Wdata : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
75 ram_write : IN STD_LOGIC;
76 ram_write : IN STD_LOGIC;
76 ram_read : IN STD_LOGIC;
77 ram_read : IN STD_LOGIC;
77 raddr_rst : IN STD_LOGIC;
78 raddr_rst : IN STD_LOGIC;
78 raddr_add1 : IN STD_LOGIC;
79 raddr_add1 : IN STD_LOGIC;
79 waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
80 waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
80 alu_sel_input : IN STD_LOGIC;
81 alu_sel_input : IN STD_LOGIC;
81 alu_sel_coeff : IN STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
82 alu_sel_coeff : IN STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
82 alu_ctrl : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
83 alu_ctrl : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
83 alu_comp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
84 alu_comp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
84 sample_in : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
85 sample_in : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
85 sample_out : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0));
86 sample_out : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0));
86 END COMPONENT;
87 END COMPONENT;
87
88
88 COMPONENT IIR_CEL_CTRLR_v2_CONTROL
89 COMPONENT IIR_CEL_CTRLR_v2_CONTROL
89 GENERIC (
90 GENERIC (
90 Coef_sel_SZ : INTEGER;
91 Coef_sel_SZ : INTEGER;
91 Cels_count : INTEGER;
92 Cels_count : INTEGER;
92 ChanelsCount : INTEGER);
93 ChanelsCount : INTEGER);
93 PORT (
94 PORT (
94 rstn : IN STD_LOGIC;
95 rstn : IN STD_LOGIC;
95 clk : IN STD_LOGIC;
96 clk : IN STD_LOGIC;
96 sample_in_val : IN STD_LOGIC;
97 sample_in_val : IN STD_LOGIC;
97 sample_in_rot : OUT STD_LOGIC;
98 sample_in_rot : OUT STD_LOGIC;
98 sample_out_val : OUT STD_LOGIC;
99 sample_out_val : OUT STD_LOGIC;
99 sample_out_rot : OUT STD_LOGIC;
100 sample_out_rot : OUT STD_LOGIC;
101 init_mem_done : in STD_LOGIC; --TODO
100 in_sel_src : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
102 in_sel_src : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
101 ram_sel_Wdata : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
103 ram_sel_Wdata : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
102 ram_write : OUT STD_LOGIC;
104 ram_write : OUT STD_LOGIC;
103 ram_read : OUT STD_LOGIC;
105 ram_read : OUT STD_LOGIC;
104 raddr_rst : OUT STD_LOGIC;
106 raddr_rst : OUT STD_LOGIC;
105 raddr_add1 : OUT STD_LOGIC;
107 raddr_add1 : OUT STD_LOGIC;
106 waddr_previous : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
108 waddr_previous : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
107 alu_sel_input : OUT STD_LOGIC;
109 alu_sel_input : OUT STD_LOGIC;
108 alu_sel_coeff : OUT STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
110 alu_sel_coeff : OUT STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
109 alu_ctrl : OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
111 alu_ctrl : OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
110 END COMPONENT;
112 END COMPONENT;
111
113
112 SIGNAL in_sel_src : STD_LOGIC_VECTOR(1 DOWNTO 0);
114 SIGNAL in_sel_src : STD_LOGIC_VECTOR(1 DOWNTO 0);
113 SIGNAL ram_sel_Wdata : STD_LOGIC_VECTOR(1 DOWNTO 0);
115 SIGNAL ram_sel_Wdata : STD_LOGIC_VECTOR(1 DOWNTO 0);
114 SIGNAL ram_write : STD_LOGIC;
116 SIGNAL ram_write : STD_LOGIC;
115 SIGNAL ram_read : STD_LOGIC;
117 SIGNAL ram_read : STD_LOGIC;
116 SIGNAL raddr_rst : STD_LOGIC;
118 SIGNAL raddr_rst : STD_LOGIC;
117 SIGNAL raddr_add1 : STD_LOGIC;
119 SIGNAL raddr_add1 : STD_LOGIC;
118 SIGNAL waddr_previous : STD_LOGIC_VECTOR(1 DOWNTO 0);
120 SIGNAL waddr_previous : STD_LOGIC_VECTOR(1 DOWNTO 0);
119 SIGNAL alu_sel_input : STD_LOGIC;
121 SIGNAL alu_sel_input : STD_LOGIC;
120 SIGNAL alu_sel_coeff : STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
122 SIGNAL alu_sel_coeff : STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
121 SIGNAL alu_ctrl : STD_LOGIC_VECTOR(2 DOWNTO 0);
123 SIGNAL alu_ctrl : STD_LOGIC_VECTOR(2 DOWNTO 0);
122
124
123 SIGNAL sample_in_buf : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
125 SIGNAL sample_in_buf : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
124 SIGNAL sample_in_rotate : STD_LOGIC;
126 SIGNAL sample_in_rotate : STD_LOGIC;
125 SIGNAL sample_in_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
127 SIGNAL sample_in_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
126 SIGNAL sample_out_val_s : STD_LOGIC;
128 SIGNAL sample_out_val_s : STD_LOGIC;
127 SIGNAL sample_out_val_s2 : STD_LOGIC;
129 SIGNAL sample_out_val_s2 : STD_LOGIC;
128 SIGNAL sample_out_rot_s : STD_LOGIC;
130 SIGNAL sample_out_rot_s : STD_LOGIC;
129 SIGNAL sample_out_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
131 SIGNAL sample_out_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
130
132
131 SIGNAL sample_out_s2 : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
133 SIGNAL sample_out_s2 : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
132
134
135 signal init_mem_done : std_logic;
136
133 BEGIN
137 BEGIN
134
138
135 IIR_CEL_CTRLR_v2_DATAFLOW_1 : IIR_CEL_CTRLR_v2_DATAFLOW
139 IIR_CEL_CTRLR_v2_DATAFLOW_1 : IIR_CEL_CTRLR_v2_DATAFLOW
136 GENERIC MAP (
140 GENERIC MAP (
137 tech => tech,
141 tech => tech,
138 Mem_use => Mem_use,
142 Mem_use => Mem_use,
139 Sample_SZ => Sample_SZ,
143 Sample_SZ => Sample_SZ,
140 Coef_SZ => Coef_SZ,
144 Coef_SZ => Coef_SZ,
141 Coef_Nb => Coef_Nb,
145 Coef_Nb => Coef_Nb,
142 Coef_sel_SZ => Coef_sel_SZ)
146 Coef_sel_SZ => Coef_sel_SZ)
143 PORT MAP (
147 PORT MAP (
144 rstn => rstn,
148 rstn => rstn,
145 clk => clk,
149 clk => clk,
146 virg_pos => virg_pos,
150 virg_pos => virg_pos,
147 coefs => coefs,
151 coefs => coefs,
148 --CTRL
152 --CTRL
149 in_sel_src => in_sel_src,
153 in_sel_src => in_sel_src,
154 init_mem_done => init_mem_done, --TODO
150 ram_sel_Wdata => ram_sel_Wdata,
155 ram_sel_Wdata => ram_sel_Wdata,
151 ram_write => ram_write,
156 ram_write => ram_write,
152 ram_read => ram_read,
157 ram_read => ram_read,
153 raddr_rst => raddr_rst,
158 raddr_rst => raddr_rst,
154 raddr_add1 => raddr_add1,
159 raddr_add1 => raddr_add1,
155 waddr_previous => waddr_previous,
160 waddr_previous => waddr_previous,
156 alu_sel_input => alu_sel_input,
161 alu_sel_input => alu_sel_input,
157 alu_sel_coeff => alu_sel_coeff,
162 alu_sel_coeff => alu_sel_coeff,
158 alu_ctrl => alu_ctrl,
163 alu_ctrl => alu_ctrl,
159 alu_comp => "00",
164 alu_comp => "00",
160 --DATA
165 --DATA
161 sample_in => sample_in_s,
166 sample_in => sample_in_s,
162 sample_out => sample_out_s);
167 sample_out => sample_out_s);
163
168
164
169
165 IIR_CEL_CTRLR_v2_CONTROL_1 : IIR_CEL_CTRLR_v2_CONTROL
170 IIR_CEL_CTRLR_v2_CONTROL_1 : IIR_CEL_CTRLR_v2_CONTROL
166 GENERIC MAP (
171 GENERIC MAP (
167 Coef_sel_SZ => Coef_sel_SZ,
172 Coef_sel_SZ => Coef_sel_SZ,
168 Cels_count => Cels_count,
173 Cels_count => Cels_count,
169 ChanelsCount => ChanelsCount)
174 ChanelsCount => ChanelsCount)
170 PORT MAP (
175 PORT MAP (
171 rstn => rstn,
176 rstn => rstn,
172 clk => clk,
177 clk => clk,
173 sample_in_val => sample_in_val,
178 sample_in_val => sample_in_val,
174 sample_in_rot => sample_in_rotate,
179 sample_in_rot => sample_in_rotate,
175 sample_out_val => sample_out_val_s,
180 sample_out_val => sample_out_val_s,
176 sample_out_rot => sample_out_rot_s,
181 sample_out_rot => sample_out_rot_s,
182
183 init_mem_done => init_mem_done, --TODO
177
184
178 in_sel_src => in_sel_src,
185 in_sel_src => in_sel_src,
179 ram_sel_Wdata => ram_sel_Wdata,
186 ram_sel_Wdata => ram_sel_Wdata,
180 ram_write => ram_write,
187 ram_write => ram_write,
181 ram_read => ram_read,
188 ram_read => ram_read,
182 raddr_rst => raddr_rst,
189 raddr_rst => raddr_rst,
183 raddr_add1 => raddr_add1,
190 raddr_add1 => raddr_add1,
184 waddr_previous => waddr_previous,
191 waddr_previous => waddr_previous,
185 alu_sel_input => alu_sel_input,
192 alu_sel_input => alu_sel_input,
186 alu_sel_coeff => alu_sel_coeff,
193 alu_sel_coeff => alu_sel_coeff,
187 alu_ctrl => alu_ctrl);
194 alu_ctrl => alu_ctrl);
188
195
189 -----------------------------------------------------------------------------
196 -----------------------------------------------------------------------------
190 -- SAMPLE IN
197 -- SAMPLE IN
191 -----------------------------------------------------------------------------
198 -----------------------------------------------------------------------------
192 loop_all_sample : FOR J IN Sample_SZ-1 DOWNTO 0 GENERATE
199 loop_all_sample : FOR J IN Sample_SZ-1 DOWNTO 0 GENERATE
193
200
194 loop_all_chanel : FOR I IN ChanelsCount-1 DOWNTO 0 GENERATE
201 loop_all_chanel : FOR I IN ChanelsCount-1 DOWNTO 0 GENERATE
195 PROCESS (clk, rstn)
202 PROCESS (clk, rstn)
196 BEGIN -- PROCESS
203 BEGIN -- PROCESS
197 IF rstn = '0' THEN -- asynchronous reset (active low)
204 IF rstn = '0' THEN -- asynchronous reset (active low)
198 sample_in_buf(I, J) <= '0';
205 sample_in_buf(I, J) <= '0';
199 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
206 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
200 IF sample_in_val = '1' THEN
207 IF sample_in_val = '1' THEN
201 sample_in_buf(I, J) <= sample_in(I, J);
208 sample_in_buf(I, J) <= sample_in(I, J);
202 ELSIF sample_in_rotate = '1' THEN
209 ELSIF sample_in_rotate = '1' THEN
203 sample_in_buf(I, J) <= sample_in_buf((I+1) MOD ChanelsCount, J);
210 sample_in_buf(I, J) <= sample_in_buf((I+1) MOD ChanelsCount, J);
204 END IF;
211 END IF;
205 END IF;
212 END IF;
206 END PROCESS;
213 END PROCESS;
207 END GENERATE loop_all_chanel;
214 END GENERATE loop_all_chanel;
208
215
209 sample_in_s(J) <= sample_in(0, J) WHEN sample_in_val = '1' ELSE sample_in_buf(0, J);
216 sample_in_s(J) <= sample_in(0, J) WHEN sample_in_val = '1' ELSE sample_in_buf(0, J);
210
217
211 END GENERATE loop_all_sample;
218 END GENERATE loop_all_sample;
212
219
213 -----------------------------------------------------------------------------
220 -----------------------------------------------------------------------------
214 -- SAMPLE OUT
221 -- SAMPLE OUT
215 -----------------------------------------------------------------------------
222 -----------------------------------------------------------------------------
216 PROCESS (clk, rstn)
223 PROCESS (clk, rstn)
217 BEGIN -- PROCESS
224 BEGIN -- PROCESS
218 IF rstn = '0' THEN -- asynchronous reset (active low)
225 IF rstn = '0' THEN -- asynchronous reset (active low)
219 sample_out_val <= '0';
226 sample_out_val <= '0';
220 sample_out_val_s2 <= '0';
227 sample_out_val_s2 <= '0';
221 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
228 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
222 sample_out_val <= sample_out_val_s2;
229 sample_out_val <= sample_out_val_s2;
223 sample_out_val_s2 <= sample_out_val_s;
230 sample_out_val_s2 <= sample_out_val_s;
224 END IF;
231 END IF;
225 END PROCESS;
232 END PROCESS;
226
233
227 chanel_HIGH : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE
234 chanel_HIGH : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE
228 PROCESS (clk, rstn)
235 PROCESS (clk, rstn)
229 BEGIN -- PROCESS
236 BEGIN -- PROCESS
230 IF rstn = '0' THEN -- asynchronous reset (active low)
237 IF rstn = '0' THEN -- asynchronous reset (active low)
231 sample_out_s2(ChanelsCount-1, I) <= '0';
238 sample_out_s2(ChanelsCount-1, I) <= '0';
232 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
239 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
233 IF sample_out_rot_s = '1' THEN
240 IF sample_out_rot_s = '1' THEN
234 sample_out_s2(ChanelsCount-1, I) <= sample_out_s(I);
241 sample_out_s2(ChanelsCount-1, I) <= sample_out_s(I);
235 END IF;
242 END IF;
236 END IF;
243 END IF;
237 END PROCESS;
244 END PROCESS;
238 END GENERATE chanel_HIGH;
245 END GENERATE chanel_HIGH;
239
246
240 chanel_more : IF ChanelsCount > 1 GENERATE
247 chanel_more : IF ChanelsCount > 1 GENERATE
241 all_chanel : FOR J IN ChanelsCount-1 DOWNTO 1 GENERATE
248 all_chanel : FOR J IN ChanelsCount-1 DOWNTO 1 GENERATE
242 all_bit : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE
249 all_bit : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE
243 PROCESS (clk, rstn)
250 PROCESS (clk, rstn)
244 BEGIN -- PROCESS
251 BEGIN -- PROCESS
245 IF rstn = '0' THEN -- asynchronous reset (active low)
252 IF rstn = '0' THEN -- asynchronous reset (active low)
246 sample_out_s2(J-1, I) <= '0';
253 sample_out_s2(J-1, I) <= '0';
247 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
254 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
248 IF sample_out_rot_s = '1' THEN
255 IF sample_out_rot_s = '1' THEN
249 sample_out_s2(J-1, I) <= sample_out_s2(J, I);
256 sample_out_s2(J-1, I) <= sample_out_s2(J, I);
250 END IF;
257 END IF;
251 END IF;
258 END IF;
252 END PROCESS;
259 END PROCESS;
253 END GENERATE all_bit;
260 END GENERATE all_bit;
254 END GENERATE all_chanel;
261 END GENERATE all_chanel;
255 END GENERATE chanel_more;
262 END GENERATE chanel_more;
256
263
257 sample_out <= sample_out_s2;
264 sample_out <= sample_out_s2;
258 END ar_IIR_CEL_CTRLR_v2;
265 END ar_IIR_CEL_CTRLR_v2;
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@@ -1,315 +1,317
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more Cdetails.
13 -- GNU General Public License for more Cdetails.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22
22
23 LIBRARY IEEE;
23 LIBRARY IEEE;
24 USE IEEE.numeric_std.ALL;
24 USE IEEE.numeric_std.ALL;
25 USE IEEE.std_logic_1164.ALL;
25 USE IEEE.std_logic_1164.ALL;
26 LIBRARY lpp;
26 LIBRARY lpp;
27 USE lpp.iir_filter.ALL;
27 USE lpp.iir_filter.ALL;
28 USE lpp.general_purpose.ALL;
28 USE lpp.general_purpose.ALL;
29
29
30 ENTITY IIR_CEL_CTRLR_v2_CONTROL IS
30 ENTITY IIR_CEL_CTRLR_v2_CONTROL IS
31 GENERIC (
31 GENERIC (
32 Coef_sel_SZ : INTEGER;
32 Coef_sel_SZ : INTEGER;
33 Cels_count : INTEGER := 5;
33 Cels_count : INTEGER := 5;
34 ChanelsCount : INTEGER := 1);
34 ChanelsCount : INTEGER := 1);
35 PORT (
35 PORT (
36 rstn : IN STD_LOGIC;
36 rstn : IN STD_LOGIC;
37 clk : IN STD_LOGIC;
37 clk : IN STD_LOGIC;
38
38
39 sample_in_val : IN STD_LOGIC;
39 sample_in_val : IN STD_LOGIC;
40 sample_in_rot : OUT STD_LOGIC;
40 sample_in_rot : OUT STD_LOGIC;
41 sample_out_val : OUT STD_LOGIC;
41 sample_out_val : OUT STD_LOGIC;
42 sample_out_rot : OUT STD_LOGIC;
42 sample_out_rot : OUT STD_LOGIC;
43
43
44 init_mem_done : in STD_LOGIC; --TODO
45
44 in_sel_src : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
46 in_sel_src : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
45 ram_sel_Wdata : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
47 ram_sel_Wdata : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
46 ram_write : OUT STD_LOGIC;
48 ram_write : OUT STD_LOGIC;
47 ram_read : OUT STD_LOGIC;
49 ram_read : OUT STD_LOGIC;
48 raddr_rst : OUT STD_LOGIC;
50 raddr_rst : OUT STD_LOGIC;
49 raddr_add1 : OUT STD_LOGIC;
51 raddr_add1 : OUT STD_LOGIC;
50 waddr_previous : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
52 waddr_previous : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
51 alu_sel_input : OUT STD_LOGIC;
53 alu_sel_input : OUT STD_LOGIC;
52 alu_sel_coeff : OUT STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
54 alu_sel_coeff : OUT STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
53 alu_ctrl : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
55 alu_ctrl : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
54 );
56 );
55 END IIR_CEL_CTRLR_v2_CONTROL;
57 END IIR_CEL_CTRLR_v2_CONTROL;
56
58
57 ARCHITECTURE ar_IIR_CEL_CTRLR_v2_CONTROL OF IIR_CEL_CTRLR_v2_CONTROL IS
59 ARCHITECTURE ar_IIR_CEL_CTRLR_v2_CONTROL OF IIR_CEL_CTRLR_v2_CONTROL IS
58
60
59 TYPE fsmIIR_CEL_T IS (waiting,
61 TYPE fsmIIR_CEL_T IS (waiting,
60 first_read,
62 first_read,
61 compute_b0,
63 compute_b0,
62 compute_b1,
64 compute_b1,
63 compute_b2,
65 compute_b2,
64 compute_a1,
66 compute_a1,
65 compute_a2,
67 compute_a2,
66 LAST_CEL,
68 LAST_CEL,
67 wait_valid_last_output,
69 wait_valid_last_output,
68 wait_valid_last_output_2);
70 wait_valid_last_output_2);
69 SIGNAL IIR_CEL_STATE : fsmIIR_CEL_T;
71 SIGNAL IIR_CEL_STATE : fsmIIR_CEL_T;
70
72
71 SIGNAL alu_selected_coeff : INTEGER RANGE 0 TO 2**Coef_sel_SZ-1;
73 SIGNAL alu_selected_coeff : INTEGER RANGE 0 TO 2**Coef_sel_SZ-1;
72 SIGNAL Chanel_ongoing : INTEGER;
74 SIGNAL Chanel_ongoing : INTEGER;
73 SIGNAL Cel_ongoing : INTEGER;
75 SIGNAL Cel_ongoing : INTEGER;
74
76
75 BEGIN
77 BEGIN
76
78
77 alu_sel_coeff <= STD_LOGIC_VECTOR(to_unsigned(alu_selected_coeff, Coef_sel_SZ));
79 alu_sel_coeff <= STD_LOGIC_VECTOR(to_unsigned(alu_selected_coeff, Coef_sel_SZ));
78
80
79 PROCESS (clk, rstn)
81 PROCESS (clk, rstn)
80 BEGIN -- PROCESS
82 BEGIN -- PROCESS
81 IF rstn = '0' THEN -- asynchronous reset (active low)
83 IF rstn = '0' THEN -- asynchronous reset (active low)
82 --REG -------------------------------------------------------------------
84 --REG -------------------------------------------------------------------
83 in_sel_src <= (OTHERS => '0'); --
85 in_sel_src <= (OTHERS => '0'); --
84 --RAM_WRitE -------------------------------------------------------------
86 --RAM_WRitE -------------------------------------------------------------
85 ram_sel_Wdata <= "00"; --
87 ram_sel_Wdata <= "00"; --
86 ram_write <= '0'; --
88 ram_write <= '0'; --
87 waddr_previous <= "00"; --
89 waddr_previous <= "00"; --
88 --RAM_READ --------------------------------------------------------------
90 --RAM_READ --------------------------------------------------------------
89 ram_read <= '0'; --
91 ram_read <= '0'; --
90 raddr_rst <= '0'; --
92 raddr_rst <= '0'; --
91 raddr_add1 <= '0'; --
93 raddr_add1 <= '0'; --
92 --ALU -------------------------------------------------------------------
94 --ALU -------------------------------------------------------------------
93 alu_selected_coeff <= 0; --
95 alu_selected_coeff <= 0; --
94 alu_sel_input <= '0'; --
96 alu_sel_input <= '0'; --
95 alu_ctrl <= ctrl_IDLE; --
97 alu_ctrl <= ctrl_IDLE; --
96 --OUT
98 --OUT
97 sample_out_val <= '0'; --
99 sample_out_val <= '0'; --
98 sample_out_rot <= '0'; --
100 sample_out_rot <= '0'; --
99
101
100 Chanel_ongoing <= 0; --
102 Chanel_ongoing <= 0; --
101 Cel_ongoing <= 0; --
103 Cel_ongoing <= 0; --
102 sample_in_rot <= '0';
104 sample_in_rot <= '0';
103
105
104 IIR_CEL_STATE <= waiting;
106 IIR_CEL_STATE <= waiting;
105
107
106 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
108 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
107
109
108 CASE IIR_CEL_STATE IS
110 CASE IIR_CEL_STATE IS
109 WHEN waiting =>
111 WHEN waiting =>
110 sample_out_rot <= '0';
112 sample_out_rot <= '0';
111 sample_in_rot <= '0';
113 sample_in_rot <= '0';
112 sample_out_val <= '0';
114 sample_out_val <= '0';
113 alu_ctrl <= ctrl_CLRMAC;
115 alu_ctrl <= ctrl_CLRMAC;
114 alu_selected_coeff <= 0;
116 alu_selected_coeff <= 0;
115 in_sel_src <= "01";
117 in_sel_src <= "01";
116 ram_read <= '0';
118 ram_read <= '0';
117 ram_sel_Wdata <= "00";
119 ram_sel_Wdata <= "00";
118 ram_write <= '0';
120 ram_write <= '0';
119 waddr_previous <= "00";
121 waddr_previous <= "00";
120 IF sample_in_val = '1' THEN
122 IF sample_in_val = '1' and init_mem_done = '1' THEN
121 raddr_rst <= '0';
123 raddr_rst <= '0';
122 alu_sel_input <= '1';
124 alu_sel_input <= '1';
123 ram_read <= '1';
125 ram_read <= '1';
124 raddr_add1 <= '1';
126 raddr_add1 <= '1';
125 IIR_CEL_STATE <= first_read;
127 IIR_CEL_STATE <= first_read;
126 Chanel_ongoing <= Chanel_ongoing + 1;
128 Chanel_ongoing <= Chanel_ongoing + 1;
127 Cel_ongoing <= 1;
129 Cel_ongoing <= 1;
128 ELSE
130 ELSE
129 raddr_add1 <= '0';
131 raddr_add1 <= '0';
130 raddr_rst <= '1';
132 raddr_rst <= '1';
131 Chanel_ongoing <= 0;
133 Chanel_ongoing <= 0;
132 Cel_ongoing <= 0;
134 Cel_ongoing <= 0;
133 END IF;
135 END IF;
134
136
135 WHEN first_read =>
137 WHEN first_read =>
136 IIR_CEL_STATE <= compute_b2;
138 IIR_CEL_STATE <= compute_b2;
137 ram_read <= '1';
139 ram_read <= '1';
138 raddr_add1 <= '1';
140 raddr_add1 <= '1';
139 alu_ctrl <= ctrl_MULT;
141 alu_ctrl <= ctrl_MULT;
140 alu_sel_input <= '1';
142 alu_sel_input <= '1';
141 in_sel_src <= "01";
143 in_sel_src <= "01";
142
144
143
145
144 WHEN compute_b2 =>
146 WHEN compute_b2 =>
145 sample_out_rot <= '0';
147 sample_out_rot <= '0';
146
148
147 sample_in_rot <= '0';
149 sample_in_rot <= '0';
148 sample_out_val <= '0';
150 sample_out_val <= '0';
149
151
150 alu_sel_input <= '1';
152 alu_sel_input <= '1';
151 --
153 --
152 ram_sel_Wdata <= "10";
154 ram_sel_Wdata <= "10";
153 ram_write <= '1';
155 ram_write <= '1';
154 waddr_previous <= "10";
156 waddr_previous <= "10";
155 --
157 --
156 ram_read <= '1';
158 ram_read <= '1';
157 raddr_rst <= '0';
159 raddr_rst <= '0';
158 raddr_add1 <= '0';
160 raddr_add1 <= '0';
159 IF Cel_ongoing = 1 THEN
161 IF Cel_ongoing = 1 THEN
160 in_sel_src <= "00";
162 in_sel_src <= "00";
161 ELSE
163 ELSE
162 in_sel_src <= "11";
164 in_sel_src <= "11";
163 END IF;
165 END IF;
164 alu_selected_coeff <= alu_selected_coeff+1;
166 alu_selected_coeff <= alu_selected_coeff+1;
165 alu_ctrl <= ctrl_MAC;
167 alu_ctrl <= ctrl_MAC;
166 IIR_CEL_STATE <= compute_b1;
168 IIR_CEL_STATE <= compute_b1;
167
169
168 WHEN compute_b1 =>
170 WHEN compute_b1 =>
169 sample_in_rot <= '0';
171 sample_in_rot <= '0';
170 alu_sel_input <= '0';
172 alu_sel_input <= '0';
171 --
173 --
172 ram_sel_Wdata <= "00";
174 ram_sel_Wdata <= "00";
173 ram_write <= '1';
175 ram_write <= '1';
174 waddr_previous <= "01";
176 waddr_previous <= "01";
175 --
177 --
176 ram_read <= '1';
178 ram_read <= '1';
177 raddr_rst <= '0';
179 raddr_rst <= '0';
178 raddr_add1 <= '1';
180 raddr_add1 <= '1';
179 sample_out_rot <= '0';
181 sample_out_rot <= '0';
180 IF Cel_ongoing = 1 THEN
182 IF Cel_ongoing = 1 THEN
181 in_sel_src <= "10";
183 in_sel_src <= "10";
182 sample_out_val <= '0';
184 sample_out_val <= '0';
183 ELSE
185 ELSE
184 sample_out_val <= '0';
186 sample_out_val <= '0';
185 in_sel_src <= "00";
187 in_sel_src <= "00";
186 END IF;
188 END IF;
187 alu_selected_coeff <= alu_selected_coeff+1;
189 alu_selected_coeff <= alu_selected_coeff+1;
188 alu_ctrl <= ctrl_MAC;
190 alu_ctrl <= ctrl_MAC;
189 IIR_CEL_STATE <= compute_b0;
191 IIR_CEL_STATE <= compute_b0;
190
192
191 WHEN compute_b0 =>
193 WHEN compute_b0 =>
192 sample_out_rot <= '0';
194 sample_out_rot <= '0';
193 sample_out_val <= '0';
195 sample_out_val <= '0';
194 sample_in_rot <= '0';
196 sample_in_rot <= '0';
195 alu_sel_input <= '1';
197 alu_sel_input <= '1';
196 ram_sel_Wdata <= "00";
198 ram_sel_Wdata <= "00";
197 ram_write <= '0';
199 ram_write <= '0';
198 waddr_previous <= "01";
200 waddr_previous <= "01";
199 ram_read <= '1';
201 ram_read <= '1';
200 raddr_rst <= '0';
202 raddr_rst <= '0';
201 raddr_add1 <= '0';
203 raddr_add1 <= '0';
202 in_sel_src <= "10";
204 in_sel_src <= "10";
203 alu_selected_coeff <= alu_selected_coeff+1;
205 alu_selected_coeff <= alu_selected_coeff+1;
204 alu_ctrl <= ctrl_MAC;
206 alu_ctrl <= ctrl_MAC;
205 IIR_CEL_STATE <= compute_a2;
207 IIR_CEL_STATE <= compute_a2;
206 IF Cel_ongoing = Cels_count THEN
208 IF Cel_ongoing = Cels_count THEN
207 sample_in_rot <= '1';
209 sample_in_rot <= '1';
208 ELSE
210 ELSE
209 sample_in_rot <= '0';
211 sample_in_rot <= '0';
210 END IF;
212 END IF;
211
213
212 WHEN compute_a2 =>
214 WHEN compute_a2 =>
213 sample_out_val <= '0';
215 sample_out_val <= '0';
214 sample_out_rot <= '0';
216 sample_out_rot <= '0';
215 alu_sel_input <= '1';
217 alu_sel_input <= '1';
216 ram_sel_Wdata <= "00";
218 ram_sel_Wdata <= "00";
217 ram_write <= '0';
219 ram_write <= '0';
218 waddr_previous <= "01";
220 waddr_previous <= "01";
219 ram_read <= '1';
221 ram_read <= '1';
220 raddr_rst <= '0';
222 raddr_rst <= '0';
221 IF Cel_ongoing = Cels_count THEN
223 IF Cel_ongoing = Cels_count THEN
222 raddr_add1 <= '1';
224 raddr_add1 <= '1';
223 ELSE
225 ELSE
224 raddr_add1 <= '0';
226 raddr_add1 <= '0';
225 END IF;
227 END IF;
226 in_sel_src <= "00";
228 in_sel_src <= "00";
227 alu_selected_coeff <= alu_selected_coeff+1;
229 alu_selected_coeff <= alu_selected_coeff+1;
228 alu_ctrl <= ctrl_MAC;
230 alu_ctrl <= ctrl_MAC;
229 IIR_CEL_STATE <= compute_a1;
231 IIR_CEL_STATE <= compute_a1;
230 sample_in_rot <= '0';
232 sample_in_rot <= '0';
231
233
232 WHEN compute_a1 =>
234 WHEN compute_a1 =>
233 sample_out_val <= '0';
235 sample_out_val <= '0';
234 sample_out_rot <= '0';
236 sample_out_rot <= '0';
235 alu_sel_input <= '0';
237 alu_sel_input <= '0';
236 ram_sel_Wdata <= "00";
238 ram_sel_Wdata <= "00";
237 ram_write <= '0';
239 ram_write <= '0';
238 waddr_previous <= "01";
240 waddr_previous <= "01";
239 ram_read <= '1';
241 ram_read <= '1';
240 raddr_rst <= '0';
242 raddr_rst <= '0';
241 alu_ctrl <= ctrl_MULT;
243 alu_ctrl <= ctrl_MULT;
242 sample_in_rot <= '0';
244 sample_in_rot <= '0';
243 IF Cel_ongoing = Cels_count THEN
245 IF Cel_ongoing = Cels_count THEN
244 alu_selected_coeff <= 0;
246 alu_selected_coeff <= 0;
245
247
246 ram_sel_Wdata <= "10";
248 ram_sel_Wdata <= "10";
247 raddr_add1 <= '1';
249 raddr_add1 <= '1';
248 ram_write <= '1';
250 ram_write <= '1';
249 waddr_previous <= "10";
251 waddr_previous <= "10";
250
252
251 IF Chanel_ongoing = ChanelsCount THEN
253 IF Chanel_ongoing = ChanelsCount THEN
252 IIR_CEL_STATE <= wait_valid_last_output;
254 IIR_CEL_STATE <= wait_valid_last_output;
253 ELSE
255 ELSE
254 Chanel_ongoing <= Chanel_ongoing + 1;
256 Chanel_ongoing <= Chanel_ongoing + 1;
255 Cel_ongoing <= 1;
257 Cel_ongoing <= 1;
256 IIR_CEL_STATE <= LAST_CEL;
258 IIR_CEL_STATE <= LAST_CEL;
257 in_sel_src <= "01";
259 in_sel_src <= "01";
258 END IF;
260 END IF;
259 ELSE
261 ELSE
260 raddr_add1 <= '1';
262 raddr_add1 <= '1';
261 alu_selected_coeff <= alu_selected_coeff+1;
263 alu_selected_coeff <= alu_selected_coeff+1;
262 Cel_ongoing <= Cel_ongoing+1;
264 Cel_ongoing <= Cel_ongoing+1;
263 IIR_CEL_STATE <= compute_b2;
265 IIR_CEL_STATE <= compute_b2;
264 END IF;
266 END IF;
265
267
266 WHEN LAST_CEL =>
268 WHEN LAST_CEL =>
267 alu_sel_input <= '1';
269 alu_sel_input <= '1';
268 IIR_CEL_STATE <= compute_b2;
270 IIR_CEL_STATE <= compute_b2;
269 raddr_add1 <= '1';
271 raddr_add1 <= '1';
270 ram_sel_Wdata <= "01";
272 ram_sel_Wdata <= "01";
271 ram_write <= '1';
273 ram_write <= '1';
272 waddr_previous <= "10";
274 waddr_previous <= "10";
273 sample_out_rot <= '1';
275 sample_out_rot <= '1';
274
276
275
277
276 WHEN wait_valid_last_output =>
278 WHEN wait_valid_last_output =>
277 IIR_CEL_STATE <= wait_valid_last_output_2;
279 IIR_CEL_STATE <= wait_valid_last_output_2;
278 sample_in_rot <= '0';
280 sample_in_rot <= '0';
279 alu_ctrl <= ctrl_IDLE;
281 alu_ctrl <= ctrl_IDLE;
280 alu_selected_coeff <= 0;
282 alu_selected_coeff <= 0;
281 in_sel_src <= "01";
283 in_sel_src <= "01";
282 ram_read <= '0';
284 ram_read <= '0';
283 raddr_rst <= '1';
285 raddr_rst <= '1';
284 raddr_add1 <= '1';
286 raddr_add1 <= '1';
285 ram_sel_Wdata <= "01";
287 ram_sel_Wdata <= "01";
286 ram_write <= '1';
288 ram_write <= '1';
287 waddr_previous <= "10";
289 waddr_previous <= "10";
288 Chanel_ongoing <= 0;
290 Chanel_ongoing <= 0;
289 Cel_ongoing <= 0;
291 Cel_ongoing <= 0;
290 sample_out_val <= '0';
292 sample_out_val <= '0';
291 sample_out_rot <= '1';
293 sample_out_rot <= '1';
292
294
293 WHEN wait_valid_last_output_2 =>
295 WHEN wait_valid_last_output_2 =>
294 IIR_CEL_STATE <= waiting;
296 IIR_CEL_STATE <= waiting;
295 sample_in_rot <= '0';
297 sample_in_rot <= '0';
296 alu_ctrl <= ctrl_IDLE;
298 alu_ctrl <= ctrl_IDLE;
297 alu_selected_coeff <= 0;
299 alu_selected_coeff <= 0;
298 in_sel_src <= "01";
300 in_sel_src <= "01";
299 ram_read <= '0';
301 ram_read <= '0';
300 raddr_rst <= '1';
302 raddr_rst <= '1';
301 raddr_add1 <= '1';
303 raddr_add1 <= '1';
302 ram_sel_Wdata <= "10";
304 ram_sel_Wdata <= "10";
303 ram_write <= '1';
305 ram_write <= '1';
304 waddr_previous <= "10";
306 waddr_previous <= "10";
305 Chanel_ongoing <= 0;
307 Chanel_ongoing <= 0;
306 Cel_ongoing <= 0;
308 Cel_ongoing <= 0;
307 sample_out_val <= '1';
309 sample_out_val <= '1';
308 sample_out_rot <= '0';
310 sample_out_rot <= '0';
309 WHEN OTHERS => NULL;
311 WHEN OTHERS => NULL;
310 END CASE;
312 END CASE;
311
313
312 END IF;
314 END IF;
313 END PROCESS;
315 END PROCESS;
314
316
315 END ar_IIR_CEL_CTRLR_v2_CONTROL; No newline at end of file
317 END ar_IIR_CEL_CTRLR_v2_CONTROL;
Show file before | Show file after | Hide comments
@@ -1,251 +1,254
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY lpp;
25 LIBRARY lpp;
26 USE lpp.iir_filter.ALL;
26 USE lpp.iir_filter.ALL;
27 USE lpp.general_purpose.ALL;
27 USE lpp.general_purpose.ALL;
28
28
29
29
30
30
31 ENTITY IIR_CEL_CTRLR_v2_DATAFLOW IS
31 ENTITY IIR_CEL_CTRLR_v2_DATAFLOW IS
32 GENERIC(
32 GENERIC(
33 tech : INTEGER := 0;
33 tech : INTEGER := 0;
34 Mem_use : INTEGER := use_RAM;
34 Mem_use : INTEGER := use_RAM;
35 Sample_SZ : INTEGER := 16;
35 Sample_SZ : INTEGER := 16;
36 Coef_SZ : INTEGER := 9;
36 Coef_SZ : INTEGER := 9;
37 Coef_Nb : INTEGER := 30;
37 Coef_Nb : INTEGER := 30;
38 Coef_sel_SZ : INTEGER := 5
38 Coef_sel_SZ : INTEGER := 5
39 );
39 );
40 PORT(
40 PORT(
41 rstn : IN STD_LOGIC;
41 rstn : IN STD_LOGIC;
42 clk : IN STD_LOGIC;
42 clk : IN STD_LOGIC;
43 -- PARAMETER
43 -- PARAMETER
44 virg_pos : IN INTEGER;
44 virg_pos : IN INTEGER;
45 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
45 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
46 -- CONTROL
46 -- CONTROL
47 in_sel_src : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
47 in_sel_src : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
48 --
48 --
49 init_mem_done : out STD_LOGIC;
49 ram_sel_Wdata : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
50 ram_sel_Wdata : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
50 ram_write : IN STD_LOGIC;
51 ram_write : IN STD_LOGIC;
51 ram_read : IN STD_LOGIC;
52 ram_read : IN STD_LOGIC;
52 raddr_rst : IN STD_LOGIC;
53 raddr_rst : IN STD_LOGIC;
53 raddr_add1 : IN STD_LOGIC;
54 raddr_add1 : IN STD_LOGIC;
54 waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
55 waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
55 --
56 --
56 alu_sel_input : IN STD_LOGIC;
57 alu_sel_input : IN STD_LOGIC;
57 alu_sel_coeff : IN STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
58 alu_sel_coeff : IN STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
58 alu_ctrl : IN STD_LOGIC_VECTOR(2 DOWNTO 0);--(MAC_op, MULT_with_clear_ADD, IDLE)
59 alu_ctrl : IN STD_LOGIC_VECTOR(2 DOWNTO 0);--(MAC_op, MULT_with_clear_ADD, IDLE)
59 alu_comp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
60 alu_comp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
60 -- DATA
61 -- DATA
61 sample_in : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
62 sample_in : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
62 sample_out : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0)
63 sample_out : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0)
63 );
64 );
64 END IIR_CEL_CTRLR_v2_DATAFLOW;
65 END IIR_CEL_CTRLR_v2_DATAFLOW;
65
66
66 ARCHITECTURE ar_IIR_CEL_CTRLR_v2_DATAFLOW OF IIR_CEL_CTRLR_v2_DATAFLOW IS
67 ARCHITECTURE ar_IIR_CEL_CTRLR_v2_DATAFLOW OF IIR_CEL_CTRLR_v2_DATAFLOW IS
67
68
68 COMPONENT RAM_CTRLR_v2
69 COMPONENT RAM_CTRLR_v2
69 GENERIC (
70 GENERIC (
70 tech : INTEGER;
71 tech : INTEGER;
71 Input_SZ_1 : INTEGER;
72 Input_SZ_1 : INTEGER;
72 Mem_use : INTEGER);
73 Mem_use : INTEGER);
73 PORT (
74 PORT (
74 rstn : IN STD_LOGIC;
75 rstn : IN STD_LOGIC;
75 clk : IN STD_LOGIC;
76 clk : IN STD_LOGIC;
77 init_mem_done : out STD_LOGIC;
76 ram_write : IN STD_LOGIC;
78 ram_write : IN STD_LOGIC;
77 ram_read : IN STD_LOGIC;
79 ram_read : IN STD_LOGIC;
78 raddr_rst : IN STD_LOGIC;
80 raddr_rst : IN STD_LOGIC;
79 raddr_add1 : IN STD_LOGIC;
81 raddr_add1 : IN STD_LOGIC;
80 waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
82 waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
81 sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
83 sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
82 sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0));
84 sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0));
83 END COMPONENT;
85 END COMPONENT;
84
86
85 SIGNAL reg_sample_in : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
87 SIGNAL reg_sample_in : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
86 SIGNAL ram_output : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
88 SIGNAL ram_output : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
87 SIGNAL alu_output : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
89 SIGNAL alu_output : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
88 SIGNAL ram_input : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
90 SIGNAL ram_input : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
89 SIGNAL alu_sample : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
91 SIGNAL alu_sample : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
90 SIGNAL alu_output_s : STD_LOGIC_VECTOR(Sample_SZ+Coef_SZ-1 DOWNTO 0);
92 SIGNAL alu_output_s : STD_LOGIC_VECTOR(Sample_SZ+Coef_SZ-1 DOWNTO 0);
91
93
92 SIGNAL arrayCoeff : MUX_INPUT_TYPE(0 TO (2**Coef_sel_SZ)-1,Coef_SZ-1 DOWNTO 0);
94 SIGNAL arrayCoeff : MUX_INPUT_TYPE(0 TO (2**Coef_sel_SZ)-1,Coef_SZ-1 DOWNTO 0);
93 SIGNAL alu_coef_s : MUX_OUTPUT_TYPE(Coef_SZ-1 DOWNTO 0);
95 SIGNAL alu_coef_s : MUX_OUTPUT_TYPE(Coef_SZ-1 DOWNTO 0);
94
96
95 SIGNAL alu_coef : STD_LOGIC_VECTOR(Coef_SZ-1 DOWNTO 0);
97 SIGNAL alu_coef : STD_LOGIC_VECTOR(Coef_SZ-1 DOWNTO 0);
96
98
97 BEGIN
99 BEGIN
98
100
99 -----------------------------------------------------------------------------
101 -----------------------------------------------------------------------------
100 -- INPUT
102 -- INPUT
101 -----------------------------------------------------------------------------
103 -----------------------------------------------------------------------------
102 PROCESS (clk, rstn)
104 PROCESS (clk, rstn)
103 BEGIN -- PROCESS
105 BEGIN -- PROCESS
104 IF rstn = '0' THEN -- asynchronous reset (active low)
106 IF rstn = '0' THEN -- asynchronous reset (active low)
105 reg_sample_in <= (OTHERS => '0');
107 reg_sample_in <= (OTHERS => '0');
106 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
108 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
107 CASE in_sel_src IS
109 CASE in_sel_src IS
108 WHEN "00" => reg_sample_in <= reg_sample_in;
110 WHEN "00" => reg_sample_in <= reg_sample_in;
109 WHEN "01" => reg_sample_in <= sample_in;
111 WHEN "01" => reg_sample_in <= sample_in;
110 WHEN "10" => reg_sample_in <= ram_output;
112 WHEN "10" => reg_sample_in <= ram_output;
111 WHEN "11" => reg_sample_in <= alu_output;
113 WHEN "11" => reg_sample_in <= alu_output;
112 WHEN OTHERS => NULL;
114 WHEN OTHERS => NULL;
113 END CASE;
115 END CASE;
114 END IF;
116 END IF;
115 END PROCESS;
117 END PROCESS;
116
118
117
119
118 -----------------------------------------------------------------------------
120 -----------------------------------------------------------------------------
119 -- RAM + CTRL
121 -- RAM + CTRL
120 -----------------------------------------------------------------------------
122 -----------------------------------------------------------------------------
121
123
122 ram_input <= reg_sample_in WHEN ram_sel_Wdata = "00" ELSE
124 ram_input <= reg_sample_in WHEN ram_sel_Wdata = "00" ELSE
123 alu_output WHEN ram_sel_Wdata = "01" ELSE
125 alu_output WHEN ram_sel_Wdata = "01" ELSE
124 ram_output;
126 ram_output;
125
127
126 RAM_CTRLR_v2_1: RAM_CTRLR_v2
128 RAM_CTRLR_v2_1: RAM_CTRLR_v2
127 GENERIC MAP (
129 GENERIC MAP (
128 tech => tech,
130 tech => tech,
129 Input_SZ_1 => Sample_SZ,
131 Input_SZ_1 => Sample_SZ,
130 Mem_use => Mem_use)
132 Mem_use => Mem_use)
131 PORT MAP (
133 PORT MAP (
132 clk => clk,
134 clk => clk,
133 rstn => rstn,
135 rstn => rstn,
136 init_mem_done => init_mem_done,
134 ram_write => ram_write,
137 ram_write => ram_write,
135 ram_read => ram_read,
138 ram_read => ram_read,
136 raddr_rst => raddr_rst,
139 raddr_rst => raddr_rst,
137 raddr_add1 => raddr_add1,
140 raddr_add1 => raddr_add1,
138 waddr_previous => waddr_previous,
141 waddr_previous => waddr_previous,
139 sample_in => ram_input,
142 sample_in => ram_input,
140 sample_out => ram_output);
143 sample_out => ram_output);
141
144
142 -----------------------------------------------------------------------------
145 -----------------------------------------------------------------------------
143 -- MAC_ACC
146 -- MAC_ACC
144 -----------------------------------------------------------------------------
147 -----------------------------------------------------------------------------
145 -- Control : mac_ctrl (MAC_op, MULT_with_clear_ADD, IDLE)
148 -- Control : mac_ctrl (MAC_op, MULT_with_clear_ADD, IDLE)
146 -- Data In : mac_sample, mac_coef
149 -- Data In : mac_sample, mac_coef
147 -- Data Out: mac_output
150 -- Data Out: mac_output
148
151
149 alu_sample <= reg_sample_in WHEN alu_sel_input = '0' ELSE ram_output;
152 alu_sample <= reg_sample_in WHEN alu_sel_input = '0' ELSE ram_output;
150
153
151 coefftable: FOR I IN 0 TO (2**Coef_sel_SZ)-1 GENERATE
154 coefftable: FOR I IN 0 TO (2**Coef_sel_SZ)-1 GENERATE
152 coeff_in: IF I < Coef_Nb GENERATE
155 coeff_in: IF I < Coef_Nb GENERATE
153 all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE
156 all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE
154 arrayCoeff(I,J) <= coefs(Coef_SZ*I+J);
157 arrayCoeff(I,J) <= coefs(Coef_SZ*I+J);
155 END GENERATE all_bit;
158 END GENERATE all_bit;
156 END GENERATE coeff_in;
159 END GENERATE coeff_in;
157 coeff_null: IF I > (Coef_Nb -1) GENERATE
160 coeff_null: IF I > (Coef_Nb -1) GENERATE
158 all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE
161 all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE
159 arrayCoeff(I,J) <= '0';
162 arrayCoeff(I,J) <= '0';
160 END GENERATE all_bit;
163 END GENERATE all_bit;
161 END GENERATE coeff_null;
164 END GENERATE coeff_null;
162 END GENERATE coefftable;
165 END GENERATE coefftable;
163
166
164 Coeff_Mux : MUXN
167 Coeff_Mux : MUXN
165 GENERIC MAP (
168 GENERIC MAP (
166 Input_SZ => Coef_SZ,
169 Input_SZ => Coef_SZ,
167 NbStage => Coef_sel_SZ)
170 NbStage => Coef_sel_SZ)
168 PORT MAP (
171 PORT MAP (
169 sel => alu_sel_coeff,
172 sel => alu_sel_coeff,
170 INPUT => arrayCoeff,
173 INPUT => arrayCoeff,
171 RES => alu_coef_s);
174 RES => alu_coef_s);
172
175
173
176
174 all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE
177 all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE
175 alu_coef(J) <= alu_coef_s(J);
178 alu_coef(J) <= alu_coef_s(J);
176 END GENERATE all_bit;
179 END GENERATE all_bit;
177
180
178 -----------------------------------------------------------------------------
181 -----------------------------------------------------------------------------
179 -- TODO : just for Synthesis test
182 -- TODO : just for Synthesis test
180
183
181 --PROCESS (clk, rstn)
184 --PROCESS (clk, rstn)
182 --BEGIN
185 --BEGIN
183 -- IF rstn = '0' THEN
186 -- IF rstn = '0' THEN
184 -- alu_coef <= (OTHERS => '0');
187 -- alu_coef <= (OTHERS => '0');
185 -- ELSIF clk'event AND clk = '1' THEN
188 -- ELSIF clk'event AND clk = '1' THEN
186 -- all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 LOOP
189 -- all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 LOOP
187 -- alu_coef(J) <= alu_coef_s(J);
190 -- alu_coef(J) <= alu_coef_s(J);
188 -- END LOOP all_bit;
191 -- END LOOP all_bit;
189 -- END IF;
192 -- END IF;
190 --END PROCESS;
193 --END PROCESS;
191
194
192 -----------------------------------------------------------------------------
195 -----------------------------------------------------------------------------
193
196
194
197
195 ALU_1: ALU
198 ALU_1: ALU
196 GENERIC MAP (
199 GENERIC MAP (
197 Arith_en => 1,
200 Arith_en => 1,
198 Input_SZ_1 => Sample_SZ,
201 Input_SZ_1 => Sample_SZ,
199 Input_SZ_2 => Coef_SZ,
202 Input_SZ_2 => Coef_SZ,
200 COMP_EN => 1)
203 COMP_EN => 1)
201 PORT MAP (
204 PORT MAP (
202 clk => clk,
205 clk => clk,
203 reset => rstn,
206 reset => rstn,
204 ctrl => alu_ctrl,
207 ctrl => alu_ctrl,
205 comp => alu_comp,
208 comp => alu_comp,
206 OP1 => alu_sample,
209 OP1 => alu_sample,
207 OP2 => alu_coef,
210 OP2 => alu_coef,
208 RES => alu_output_s);
211 RES => alu_output_s);
209
212
210 alu_output <= alu_output_s(Sample_SZ+virg_pos-1 DOWNTO virg_pos);
213 alu_output <= alu_output_s(Sample_SZ+virg_pos-1 DOWNTO virg_pos);
211
214
212 sample_out <= alu_output;
215 sample_out <= alu_output;
213
216
214 END ar_IIR_CEL_CTRLR_v2_DATAFLOW;
217 END ar_IIR_CEL_CTRLR_v2_DATAFLOW;
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Show file before | Show file after | Hide comments
@@ -1,442 +1,454
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22
22
23 LIBRARY IEEE;
23 LIBRARY IEEE;
24 USE IEEE.numeric_std.ALL;
24 USE IEEE.numeric_std.ALL;
25 USE IEEE.std_logic_1164.ALL;
25 USE IEEE.std_logic_1164.ALL;
26
26
27 LIBRARY techmap;
27 LIBRARY techmap;
28 USE techmap.gencomp.ALL;
28 USE techmap.gencomp.ALL;
29
29
30 LIBRARY lpp;
30 LIBRARY lpp;
31 USE lpp.iir_filter.ALL;
31 USE lpp.iir_filter.ALL;
32 USE lpp.general_purpose.ALL;
32 USE lpp.general_purpose.ALL;
33
33
34 ENTITY IIR_CEL_CTRLR_v3 IS
34 ENTITY IIR_CEL_CTRLR_v3 IS
35 GENERIC (
35 GENERIC (
36 tech : INTEGER := 0;
36 tech : INTEGER := 0;
37 Mem_use : INTEGER := use_RAM;
37 Mem_use : INTEGER := use_RAM;
38 Sample_SZ : INTEGER := 18;
38 Sample_SZ : INTEGER := 18;
39 Coef_SZ : INTEGER := 9;
39 Coef_SZ : INTEGER := 9;
40 Coef_Nb : INTEGER := 25;
40 Coef_Nb : INTEGER := 25;
41 Coef_sel_SZ : INTEGER := 5;
41 Coef_sel_SZ : INTEGER := 5;
42 Cels_count : INTEGER := 5;
42 Cels_count : INTEGER := 5;
43 ChanelsCount : INTEGER := 8);
43 ChanelsCount : INTEGER := 8);
44 PORT (
44 PORT (
45 rstn : IN STD_LOGIC;
45 rstn : IN STD_LOGIC;
46 clk : IN STD_LOGIC;
46 clk : IN STD_LOGIC;
47
47
48 virg_pos : IN INTEGER;
48 virg_pos : IN INTEGER;
49 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
49 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
50
50
51 sample_in1_val : IN STD_LOGIC;
51 sample_in1_val : IN STD_LOGIC;
52 sample_in1 : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
52 sample_in1 : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
53 sample_in2_val : IN STD_LOGIC;
53 sample_in2_val : IN STD_LOGIC;
54 sample_in2 : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
54 sample_in2 : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
55
55
56 sample_out1_val : OUT STD_LOGIC;
56 sample_out1_val : OUT STD_LOGIC;
57 sample_out1 : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
57 sample_out1 : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
58 sample_out2_val : OUT STD_LOGIC;
58 sample_out2_val : OUT STD_LOGIC;
59 sample_out2 : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0));
59 sample_out2 : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0));
60 END IIR_CEL_CTRLR_v3;
60 END IIR_CEL_CTRLR_v3;
61
61
62 ARCHITECTURE ar_IIR_CEL_CTRLR_v3 OF IIR_CEL_CTRLR_v3 IS
62 ARCHITECTURE ar_IIR_CEL_CTRLR_v3 OF IIR_CEL_CTRLR_v3 IS
63
63
64 COMPONENT RAM_CTRLR_v2
64 COMPONENT RAM_CTRLR_v2
65 GENERIC (
65 GENERIC (
66 tech : INTEGER;
66 tech : INTEGER;
67 Input_SZ_1 : INTEGER;
67 Input_SZ_1 : INTEGER;
68 Mem_use : INTEGER);
68 Mem_use : INTEGER);
69 PORT (
69 PORT (
70 rstn : IN STD_LOGIC;
70 rstn : IN STD_LOGIC;
71 clk : IN STD_LOGIC;
71 clk : IN STD_LOGIC;
72 init_mem_done : out STD_LOGIC;
72 ram_write : IN STD_LOGIC;
73 ram_write : IN STD_LOGIC;
73 ram_read : IN STD_LOGIC;
74 ram_read : IN STD_LOGIC;
74 raddr_rst : IN STD_LOGIC;
75 raddr_rst : IN STD_LOGIC;
75 raddr_add1 : IN STD_LOGIC;
76 raddr_add1 : IN STD_LOGIC;
76 waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
77 waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
77 sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
78 sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
78 sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0));
79 sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0));
79 END COMPONENT;
80 END COMPONENT;
80
81
81 COMPONENT IIR_CEL_CTRLR_v3_DATAFLOW
82 COMPONENT IIR_CEL_CTRLR_v3_DATAFLOW
82 GENERIC (
83 GENERIC (
83 Sample_SZ : INTEGER;
84 Sample_SZ : INTEGER;
84 Coef_SZ : INTEGER;
85 Coef_SZ : INTEGER;
85 Coef_Nb : INTEGER;
86 Coef_Nb : INTEGER;
86 Coef_sel_SZ : INTEGER);
87 Coef_sel_SZ : INTEGER);
87 PORT (
88 PORT (
88 rstn : IN STD_LOGIC;
89 rstn : IN STD_LOGIC;
89 clk : IN STD_LOGIC;
90 clk : IN STD_LOGIC;
90 virg_pos : IN INTEGER;
91 virg_pos : IN INTEGER;
91 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
92 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
92 in_sel_src : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
93 in_sel_src : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
93 ram_sel_Wdata : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
94 ram_sel_Wdata : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
94 ram_input : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
95 ram_input : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
95 ram_output : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
96 ram_output : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
96 alu_sel_input : IN STD_LOGIC;
97 alu_sel_input : IN STD_LOGIC;
97 alu_sel_coeff : IN STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
98 alu_sel_coeff : IN STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
98 alu_ctrl : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
99 alu_ctrl : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
99 alu_comp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
100 alu_comp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
100 sample_in : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
101 sample_in : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
101 sample_out : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0));
102 sample_out : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0));
102 END COMPONENT;
103 END COMPONENT;
103
104
104 COMPONENT IIR_CEL_CTRLR_v2_CONTROL
105 COMPONENT IIR_CEL_CTRLR_v2_CONTROL
105 GENERIC (
106 GENERIC (
106 Coef_sel_SZ : INTEGER;
107 Coef_sel_SZ : INTEGER;
107 Cels_count : INTEGER;
108 Cels_count : INTEGER;
108 ChanelsCount : INTEGER);
109 ChanelsCount : INTEGER);
109 PORT (
110 PORT (
110 rstn : IN STD_LOGIC;
111 rstn : IN STD_LOGIC;
111 clk : IN STD_LOGIC;
112 clk : IN STD_LOGIC;
112 sample_in_val : IN STD_LOGIC;
113 sample_in_val : IN STD_LOGIC;
113 sample_in_rot : OUT STD_LOGIC;
114 sample_in_rot : OUT STD_LOGIC;
114 sample_out_val : OUT STD_LOGIC;
115 sample_out_val : OUT STD_LOGIC;
115 sample_out_rot : OUT STD_LOGIC;
116 sample_out_rot : OUT STD_LOGIC;
117
118 init_mem_done : in STD_LOGIC; --TODO
119
116 in_sel_src : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
120 in_sel_src : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
117 ram_sel_Wdata : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
121 ram_sel_Wdata : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
118 ram_write : OUT STD_LOGIC;
122 ram_write : OUT STD_LOGIC;
119 ram_read : OUT STD_LOGIC;
123 ram_read : OUT STD_LOGIC;
120 raddr_rst : OUT STD_LOGIC;
124 raddr_rst : OUT STD_LOGIC;
121 raddr_add1 : OUT STD_LOGIC;
125 raddr_add1 : OUT STD_LOGIC;
122 waddr_previous : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
126 waddr_previous : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
123 alu_sel_input : OUT STD_LOGIC;
127 alu_sel_input : OUT STD_LOGIC;
124 alu_sel_coeff : OUT STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
128 alu_sel_coeff : OUT STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
125 alu_ctrl : OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
129 alu_ctrl : OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
126 END COMPONENT;
130 END COMPONENT;
127
131
128 SIGNAL in_sel_src : STD_LOGIC_VECTOR(1 DOWNTO 0);
132 SIGNAL in_sel_src : STD_LOGIC_VECTOR(1 DOWNTO 0);
129 SIGNAL ram_sel_Wdata : STD_LOGIC_VECTOR(1 DOWNTO 0);
133 SIGNAL ram_sel_Wdata : STD_LOGIC_VECTOR(1 DOWNTO 0);
130 SIGNAL ram_write : STD_LOGIC;
134 SIGNAL ram_write : STD_LOGIC;
131 SIGNAL ram_read : STD_LOGIC;
135 SIGNAL ram_read : STD_LOGIC;
132 SIGNAL raddr_rst : STD_LOGIC;
136 SIGNAL raddr_rst : STD_LOGIC;
133 SIGNAL raddr_add1 : STD_LOGIC;
137 SIGNAL raddr_add1 : STD_LOGIC;
134 SIGNAL waddr_previous : STD_LOGIC_VECTOR(1 DOWNTO 0);
138 SIGNAL waddr_previous : STD_LOGIC_VECTOR(1 DOWNTO 0);
135 SIGNAL alu_sel_input : STD_LOGIC;
139 SIGNAL alu_sel_input : STD_LOGIC;
136 SIGNAL alu_sel_coeff : STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
140 SIGNAL alu_sel_coeff : STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
137 SIGNAL alu_ctrl : STD_LOGIC_VECTOR(2 DOWNTO 0);
141 SIGNAL alu_ctrl : STD_LOGIC_VECTOR(2 DOWNTO 0);
138
142
139 SIGNAL sample_in_buf : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
143 SIGNAL sample_in_buf : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
140 SIGNAL sample_in_rotate : STD_LOGIC;
144 SIGNAL sample_in_rotate : STD_LOGIC;
141 SIGNAL sample_in_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
145 SIGNAL sample_in_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
142 SIGNAL sample_out_val_s : STD_LOGIC;
146 SIGNAL sample_out_val_s : STD_LOGIC;
143 SIGNAL sample_out_val_s2 : STD_LOGIC;
147 SIGNAL sample_out_val_s2 : STD_LOGIC;
144 SIGNAL sample_out_rot_s : STD_LOGIC;
148 SIGNAL sample_out_rot_s : STD_LOGIC;
145 SIGNAL sample_out_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
149 SIGNAL sample_out_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
146
150
147 SIGNAL sample_out_s2 : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
151 SIGNAL sample_out_s2 : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
148
152
149 SIGNAL ram_input : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
153 SIGNAL ram_input : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
150 SIGNAL ram_output : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
154 SIGNAL ram_output : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
151 --
155 --
152 SIGNAL sample_in_val : STD_LOGIC;
156 SIGNAL sample_in_val : STD_LOGIC;
153 SIGNAL sample_in : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
157 SIGNAL sample_in : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
154 SIGNAL sample_out_val : STD_LOGIC;
158 SIGNAL sample_out_val : STD_LOGIC;
155 SIGNAL sample_out : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
159 SIGNAL sample_out : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
156
160
157 -----------------------------------------------------------------------------
161 -----------------------------------------------------------------------------
158 --
162 --
159 -----------------------------------------------------------------------------
163 -----------------------------------------------------------------------------
160 SIGNAL CHANNEL_SEL : STD_LOGIC;
164 SIGNAL CHANNEL_SEL : STD_LOGIC;
161
165
162 SIGNAL ram_output_1 : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
166 SIGNAL ram_output_1 : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
163 SIGNAL ram_output_2 : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
167 SIGNAL ram_output_2 : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
164
168
165 SIGNAL ram_write_1 : STD_LOGIC;
169 SIGNAL ram_write_1 : STD_LOGIC;
166 SIGNAL ram_read_1 : STD_LOGIC;
170 SIGNAL ram_read_1 : STD_LOGIC;
167 SIGNAL raddr_rst_1 : STD_LOGIC;
171 SIGNAL raddr_rst_1 : STD_LOGIC;
168 SIGNAL raddr_add1_1 : STD_LOGIC;
172 SIGNAL raddr_add1_1 : STD_LOGIC;
169 SIGNAL waddr_previous_1 : STD_LOGIC_VECTOR(1 DOWNTO 0);
173 SIGNAL waddr_previous_1 : STD_LOGIC_VECTOR(1 DOWNTO 0);
170
174
171 SIGNAL ram_write_2 : STD_LOGIC;
175 SIGNAL ram_write_2 : STD_LOGIC;
172 SIGNAL ram_read_2 : STD_LOGIC;
176 SIGNAL ram_read_2 : STD_LOGIC;
173 SIGNAL raddr_rst_2 : STD_LOGIC;
177 SIGNAL raddr_rst_2 : STD_LOGIC;
174 SIGNAL raddr_add1_2 : STD_LOGIC;
178 SIGNAL raddr_add1_2 : STD_LOGIC;
175 SIGNAL waddr_previous_2 : STD_LOGIC_VECTOR(1 DOWNTO 0);
179 SIGNAL waddr_previous_2 : STD_LOGIC_VECTOR(1 DOWNTO 0);
176 -----------------------------------------------------------------------------
180 -----------------------------------------------------------------------------
177 SIGNAL channel_ready : STD_LOGIC_VECTOR(1 DOWNTO 0);
181 SIGNAL channel_ready : STD_LOGIC_VECTOR(1 DOWNTO 0);
178 SIGNAL channel_val : STD_LOGIC_VECTOR(1 DOWNTO 0);
182 SIGNAL channel_val : STD_LOGIC_VECTOR(1 DOWNTO 0);
179 SIGNAL channel_done : STD_LOGIC_VECTOR(1 DOWNTO 0);
183 SIGNAL channel_done : STD_LOGIC_VECTOR(1 DOWNTO 0);
180 -----------------------------------------------------------------------------
184 -----------------------------------------------------------------------------
181 TYPE FSM_CHANNEL_SELECTION IS (IDLE, ONGOING_1, ONGOING_2, WAIT_STATE);
185 TYPE FSM_CHANNEL_SELECTION IS (IDLE, ONGOING_1, ONGOING_2, WAIT_STATE);
182 SIGNAL state_channel_selection : FSM_CHANNEL_SELECTION;
186 SIGNAL state_channel_selection : FSM_CHANNEL_SELECTION;
183
187
184 --SIGNAL sample_out_zero : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
188 --SIGNAL sample_out_zero : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
185
189 signal init_mem_done : std_logic;
190 signal init_mem_done_1 : std_logic;
191 signal init_mem_done_2 : std_logic;
186 BEGIN
192 BEGIN
187
193
188 -----------------------------------------------------------------------------
194 -----------------------------------------------------------------------------
189 channel_val(0) <= sample_in1_val;
195 channel_val(0) <= sample_in1_val when init_mem_done = '1' else '0';
190 channel_val(1) <= sample_in2_val;
196 channel_val(1) <= sample_in2_val when init_mem_done = '1' else '0';
191 all_channel_input_valid : FOR I IN 1 DOWNTO 0 GENERATE
197 all_channel_input_valid : FOR I IN 1 DOWNTO 0 GENERATE
192 PROCESS (clk, rstn)
198 PROCESS (clk, rstn)
193 BEGIN -- PROCESS
199 BEGIN -- PROCESS
194 IF rstn = '0' THEN -- asynchronous reset (active low)
200 IF rstn = '0' THEN -- asynchronous reset (active low)
195 channel_ready(I) <= '0';
201 channel_ready(I) <= '0';
196 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
202 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
197 IF channel_val(I) = '1' THEN
203 IF channel_val(I) = '1' THEN
198 channel_ready(I) <= '1';
204 channel_ready(I) <= '1';
199 ELSIF channel_done(I) = '1' THEN
205 ELSIF channel_done(I) = '1' THEN
200 channel_ready(I) <= '0';
206 channel_ready(I) <= '0';
201 END IF;
207 END IF;
202 END IF;
208 END IF;
203 END PROCESS;
209 END PROCESS;
204 END GENERATE all_channel_input_valid;
210 END GENERATE all_channel_input_valid;
205 -----------------------------------------------------------------------------
211 -----------------------------------------------------------------------------
206
212
207
213
208 PROCESS (clk, rstn)
214 PROCESS (clk, rstn)
209 BEGIN -- PROCESS
215 BEGIN -- PROCESS
210 IF rstn = '0' THEN -- asynchronous reset (active low)
216 IF rstn = '0' THEN -- asynchronous reset (active low)
211 state_channel_selection <= IDLE;
217 state_channel_selection <= IDLE;
212 CHANNEL_SEL <= '0';
218 CHANNEL_SEL <= '0';
213 sample_in_val <= '0';
219 sample_in_val <= '0';
214 sample_out1_val <= '0';
220 sample_out1_val <= '0';
215 sample_out2_val <= '0';
221 sample_out2_val <= '0';
216 all_channel_sample_out : FOR I IN ChanelsCount-1 DOWNTO 0 LOOP
222 all_channel_sample_out : FOR I IN ChanelsCount-1 DOWNTO 0 LOOP
217 all_bit : FOR J IN Sample_SZ-1 DOWNTO 0 LOOP
223 all_bit : FOR J IN Sample_SZ-1 DOWNTO 0 LOOP
218 sample_out1(I, J) <= '0';
224 sample_out1(I, J) <= '0';
219 sample_out2(I, J) <= '0';
225 sample_out2(I, J) <= '0';
220 END LOOP all_bit;
226 END LOOP all_bit;
221 END LOOP all_channel_sample_out;
227 END LOOP all_channel_sample_out;
222 channel_done <= "00";
228 channel_done <= "00";
223
229
224 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
230 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
225 CASE state_channel_selection IS
231 CASE state_channel_selection IS
226 WHEN IDLE =>
232 WHEN IDLE =>
227 CHANNEL_SEL <= '0';
233 CHANNEL_SEL <= '0';
228 sample_in_val <= '0';
234 sample_in_val <= '0';
229 sample_out1_val <= '0';
235 sample_out1_val <= '0';
230 sample_out2_val <= '0';
236 sample_out2_val <= '0';
231 channel_done <= "00";
237 channel_done <= "00";
232 IF channel_ready(0) = '1' THEN
238 IF channel_ready(0) = '1' THEN
233 state_channel_selection <= ONGOING_1;
239 state_channel_selection <= ONGOING_1;
234 CHANNEL_SEL <= '0';
240 CHANNEL_SEL <= '0';
235 sample_in_val <= '1';
241 sample_in_val <= '1';
236 ELSIF channel_ready(1) = '1' THEN
242 ELSIF channel_ready(1) = '1' THEN
237 state_channel_selection <= ONGOING_2;
243 state_channel_selection <= ONGOING_2;
238 CHANNEL_SEL <= '1';
244 CHANNEL_SEL <= '1';
239 sample_in_val <= '1';
245 sample_in_val <= '1';
240 END IF;
246 END IF;
241 WHEN ONGOING_1 =>
247 WHEN ONGOING_1 =>
242 sample_in_val <= '0';
248 sample_in_val <= '0';
243 IF sample_out_val = '1' THEN
249 IF sample_out_val = '1' THEN
244 state_channel_selection <= WAIT_STATE;
250 state_channel_selection <= WAIT_STATE;
245 sample_out1 <= sample_out;
251 sample_out1 <= sample_out;
246 sample_out1_val <= '1';
252 sample_out1_val <= '1';
247 channel_done(0) <= '1';
253 channel_done(0) <= '1';
248 END IF;
254 END IF;
249 WHEN ONGOING_2 =>
255 WHEN ONGOING_2 =>
250 sample_in_val <= '0';
256 sample_in_val <= '0';
251 IF sample_out_val = '1' THEN
257 IF sample_out_val = '1' THEN
252 state_channel_selection <= WAIT_STATE;
258 state_channel_selection <= WAIT_STATE;
253 sample_out2 <= sample_out;
259 sample_out2 <= sample_out;
254 sample_out2_val <= '1';
260 sample_out2_val <= '1';
255 channel_done(1) <= '1';
261 channel_done(1) <= '1';
256 END IF;
262 END IF;
257 WHEN WAIT_STATE =>
263 WHEN WAIT_STATE =>
258 state_channel_selection <= IDLE;
264 state_channel_selection <= IDLE;
259 CHANNEL_SEL <= '0';
265 CHANNEL_SEL <= '0';
260 sample_in_val <= '0';
266 sample_in_val <= '0';
261 sample_out1_val <= '0';
267 sample_out1_val <= '0';
262 sample_out2_val <= '0';
268 sample_out2_val <= '0';
263 channel_done <= "00";
269 channel_done <= "00";
264
270
265 WHEN OTHERS => NULL;
271 WHEN OTHERS => NULL;
266 END CASE;
272 END CASE;
267
273
268 END IF;
274 END IF;
269 END PROCESS;
275 END PROCESS;
270
276
271 sample_in <= sample_in1 WHEN CHANNEL_SEL = '0' ELSE sample_in2;
277 sample_in <= sample_in1 WHEN CHANNEL_SEL = '0' ELSE sample_in2;
272 -----------------------------------------------------------------------------
278 -----------------------------------------------------------------------------
273 ram_output <= ram_output_1 WHEN CHANNEL_SEL = '0' ELSE
279 ram_output <= ram_output_1 WHEN CHANNEL_SEL = '0' ELSE
274 ram_output_2;
280 ram_output_2;
275
281
276 ram_write_1 <= ram_write WHEN CHANNEL_SEL = '0' ELSE '0';
282 ram_write_1 <= ram_write WHEN CHANNEL_SEL = '0' ELSE '0';
277 ram_read_1 <= ram_read WHEN CHANNEL_SEL = '0' ELSE '0';
283 ram_read_1 <= ram_read WHEN CHANNEL_SEL = '0' ELSE '0';
278 raddr_rst_1 <= raddr_rst WHEN CHANNEL_SEL = '0' ELSE '1';
284 raddr_rst_1 <= raddr_rst WHEN CHANNEL_SEL = '0' ELSE '1';
279 raddr_add1_1 <= raddr_add1 WHEN CHANNEL_SEL = '0' ELSE '0';
285 raddr_add1_1 <= raddr_add1 WHEN CHANNEL_SEL = '0' ELSE '0';
280 waddr_previous_1 <= waddr_previous WHEN CHANNEL_SEL = '0' ELSE "00";
286 waddr_previous_1 <= waddr_previous WHEN CHANNEL_SEL = '0' ELSE "00";
281
287
282 ram_write_2 <= ram_write WHEN CHANNEL_SEL = '1' ELSE '0';
288 ram_write_2 <= ram_write WHEN CHANNEL_SEL = '1' ELSE '0';
283 ram_read_2 <= ram_read WHEN CHANNEL_SEL = '1' ELSE '0';
289 ram_read_2 <= ram_read WHEN CHANNEL_SEL = '1' ELSE '0';
284 raddr_rst_2 <= raddr_rst WHEN CHANNEL_SEL = '1' ELSE '1';
290 raddr_rst_2 <= raddr_rst WHEN CHANNEL_SEL = '1' ELSE '1';
285 raddr_add1_2 <= raddr_add1 WHEN CHANNEL_SEL = '1' ELSE '0';
291 raddr_add1_2 <= raddr_add1 WHEN CHANNEL_SEL = '1' ELSE '0';
286 waddr_previous_2 <= waddr_previous WHEN CHANNEL_SEL = '1' ELSE "00";
292 waddr_previous_2 <= waddr_previous WHEN CHANNEL_SEL = '1' ELSE "00";
287
293
294 init_mem_done <= init_mem_done_1 and init_mem_done_2;
295
288 RAM_CTRLR_v2_1 : RAM_CTRLR_v2
296 RAM_CTRLR_v2_1 : RAM_CTRLR_v2
289 GENERIC MAP (
297 GENERIC MAP (
290 tech => tech,
298 tech => tech,
291 Input_SZ_1 => Sample_SZ,
299 Input_SZ_1 => Sample_SZ,
292 Mem_use => Mem_use)
300 Mem_use => Mem_use)
293 PORT MAP (
301 PORT MAP (
294 clk => clk,
302 clk => clk,
295 rstn => rstn,
303 rstn => rstn,
304 init_mem_done => init_mem_done_1,
296 ram_write => ram_write_1,
305 ram_write => ram_write_1,
297 ram_read => ram_read_1,
306 ram_read => ram_read_1,
298 raddr_rst => raddr_rst_1,
307 raddr_rst => raddr_rst_1,
299 raddr_add1 => raddr_add1_1,
308 raddr_add1 => raddr_add1_1,
300 waddr_previous => waddr_previous_1,
309 waddr_previous => waddr_previous_1,
301 sample_in => ram_input,
310 sample_in => ram_input,
302 sample_out => ram_output_1);
311 sample_out => ram_output_1);
303
312
304 RAM_CTRLR_v2_2 : RAM_CTRLR_v2
313 RAM_CTRLR_v2_2 : RAM_CTRLR_v2
305 GENERIC MAP (
314 GENERIC MAP (
306 tech => tech,
315 tech => tech,
307 Input_SZ_1 => Sample_SZ,
316 Input_SZ_1 => Sample_SZ,
308 Mem_use => Mem_use)
317 Mem_use => Mem_use)
309 PORT MAP (
318 PORT MAP (
310 clk => clk,
319 clk => clk,
311 rstn => rstn,
320 rstn => rstn,
321 init_mem_done => init_mem_done_2,
312 ram_write => ram_write_2,
322 ram_write => ram_write_2,
313 ram_read => ram_read_2,
323 ram_read => ram_read_2,
314 raddr_rst => raddr_rst_2,
324 raddr_rst => raddr_rst_2,
315 raddr_add1 => raddr_add1_2,
325 raddr_add1 => raddr_add1_2,
316 waddr_previous => waddr_previous_2,
326 waddr_previous => waddr_previous_2,
317 sample_in => ram_input,
327 sample_in => ram_input,
318 sample_out => ram_output_2);
328 sample_out => ram_output_2);
319 -----------------------------------------------------------------------------
329 -----------------------------------------------------------------------------
320
330
321 IIR_CEL_CTRLR_v3_DATAFLOW_1 : IIR_CEL_CTRLR_v3_DATAFLOW
331 IIR_CEL_CTRLR_v3_DATAFLOW_1 : IIR_CEL_CTRLR_v3_DATAFLOW
322 GENERIC MAP (
332 GENERIC MAP (
323 Sample_SZ => Sample_SZ,
333 Sample_SZ => Sample_SZ,
324 Coef_SZ => Coef_SZ,
334 Coef_SZ => Coef_SZ,
325 Coef_Nb => Coef_Nb,
335 Coef_Nb => Coef_Nb,
326 Coef_sel_SZ => Coef_sel_SZ)
336 Coef_sel_SZ => Coef_sel_SZ)
327 PORT MAP (
337 PORT MAP (
328 rstn => rstn,
338 rstn => rstn,
329 clk => clk,
339 clk => clk,
330 virg_pos => virg_pos,
340 virg_pos => virg_pos,
331 coefs => coefs,
341 coefs => coefs,
332 --CTRL
342 --CTRL
333 in_sel_src => in_sel_src,
343 in_sel_src => in_sel_src,
334 ram_sel_Wdata => ram_sel_Wdata,
344 ram_sel_Wdata => ram_sel_Wdata,
335 --
345 --
336 ram_input => ram_input,
346 ram_input => ram_input,
337 ram_output => ram_output,
347 ram_output => ram_output,
338 --
348 --
339 alu_sel_input => alu_sel_input,
349 alu_sel_input => alu_sel_input,
340 alu_sel_coeff => alu_sel_coeff,
350 alu_sel_coeff => alu_sel_coeff,
341 alu_ctrl => alu_ctrl,
351 alu_ctrl => alu_ctrl,
342 alu_comp => "00",
352 alu_comp => "00",
343 --DATA
353 --DATA
344 sample_in => sample_in_s,
354 sample_in => sample_in_s,
345 sample_out => sample_out_s);
355 sample_out => sample_out_s);
346 -----------------------------------------------------------------------------
356 -----------------------------------------------------------------------------
347
357
348
358
349 IIR_CEL_CTRLR_v3_CONTROL_1 : IIR_CEL_CTRLR_v2_CONTROL
359 IIR_CEL_CTRLR_v3_CONTROL_1 : IIR_CEL_CTRLR_v2_CONTROL
350 GENERIC MAP (
360 GENERIC MAP (
351 Coef_sel_SZ => Coef_sel_SZ,
361 Coef_sel_SZ => Coef_sel_SZ,
352 Cels_count => Cels_count,
362 Cels_count => Cels_count,
353 ChanelsCount => ChanelsCount)
363 ChanelsCount => ChanelsCount)
354 PORT MAP (
364 PORT MAP (
355 rstn => rstn,
365 rstn => rstn,
356 clk => clk,
366 clk => clk,
357 sample_in_val => sample_in_val,
367 sample_in_val => sample_in_val,
358 sample_in_rot => sample_in_rotate,
368 sample_in_rot => sample_in_rotate,
359 sample_out_val => sample_out_val_s,
369 sample_out_val => sample_out_val_s,
360 sample_out_rot => sample_out_rot_s,
370 sample_out_rot => sample_out_rot_s,
361
371
372 init_mem_done => init_mem_done,
373
362 in_sel_src => in_sel_src,
374 in_sel_src => in_sel_src,
363 ram_sel_Wdata => ram_sel_Wdata,
375 ram_sel_Wdata => ram_sel_Wdata,
364 ram_write => ram_write,
376 ram_write => ram_write,
365 ram_read => ram_read,
377 ram_read => ram_read,
366 raddr_rst => raddr_rst,
378 raddr_rst => raddr_rst,
367 raddr_add1 => raddr_add1,
379 raddr_add1 => raddr_add1,
368 waddr_previous => waddr_previous,
380 waddr_previous => waddr_previous,
369 alu_sel_input => alu_sel_input,
381 alu_sel_input => alu_sel_input,
370 alu_sel_coeff => alu_sel_coeff,
382 alu_sel_coeff => alu_sel_coeff,
371 alu_ctrl => alu_ctrl);
383 alu_ctrl => alu_ctrl);
372
384
373 -----------------------------------------------------------------------------
385 -----------------------------------------------------------------------------
374 -- SAMPLE IN
386 -- SAMPLE IN
375 -----------------------------------------------------------------------------
387 -----------------------------------------------------------------------------
376 loop_all_sample : FOR J IN Sample_SZ-1 DOWNTO 0 GENERATE
388 loop_all_sample : FOR J IN Sample_SZ-1 DOWNTO 0 GENERATE
377
389
378 loop_all_chanel : FOR I IN ChanelsCount-1 DOWNTO 0 GENERATE
390 loop_all_chanel : FOR I IN ChanelsCount-1 DOWNTO 0 GENERATE
379 PROCESS (clk, rstn)
391 PROCESS (clk, rstn)
380 BEGIN -- PROCESS
392 BEGIN -- PROCESS
381 IF rstn = '0' THEN -- asynchronous reset (active low)
393 IF rstn = '0' THEN -- asynchronous reset (active low)
382 sample_in_buf(I, J) <= '0';
394 sample_in_buf(I, J) <= '0';
383 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
395 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
384 IF sample_in_val = '1' THEN
396 IF sample_in_val = '1' THEN
385 sample_in_buf(I, J) <= sample_in(I, J);
397 sample_in_buf(I, J) <= sample_in(I, J);
386 ELSIF sample_in_rotate = '1' THEN
398 ELSIF sample_in_rotate = '1' THEN
387 sample_in_buf(I, J) <= sample_in_buf((I+1) MOD ChanelsCount, J);
399 sample_in_buf(I, J) <= sample_in_buf((I+1) MOD ChanelsCount, J);
388 END IF;
400 END IF;
389 END IF;
401 END IF;
390 END PROCESS;
402 END PROCESS;
391 END GENERATE loop_all_chanel;
403 END GENERATE loop_all_chanel;
392
404
393 sample_in_s(J) <= sample_in(0, J) WHEN sample_in_val = '1' ELSE sample_in_buf(0, J);
405 sample_in_s(J) <= sample_in(0, J) WHEN sample_in_val = '1' ELSE sample_in_buf(0, J);
394
406
395 END GENERATE loop_all_sample;
407 END GENERATE loop_all_sample;
396
408
397 -----------------------------------------------------------------------------
409 -----------------------------------------------------------------------------
398 -- SAMPLE OUT
410 -- SAMPLE OUT
399 -----------------------------------------------------------------------------
411 -----------------------------------------------------------------------------
400 PROCESS (clk, rstn)
412 PROCESS (clk, rstn)
401 BEGIN -- PROCESS
413 BEGIN -- PROCESS
402 IF rstn = '0' THEN -- asynchronous reset (active low)
414 IF rstn = '0' THEN -- asynchronous reset (active low)
403 sample_out_val <= '0';
415 sample_out_val <= '0';
404 sample_out_val_s2 <= '0';
416 sample_out_val_s2 <= '0';
405 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
417 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
406 sample_out_val <= sample_out_val_s2;
418 sample_out_val <= sample_out_val_s2;
407 sample_out_val_s2 <= sample_out_val_s;
419 sample_out_val_s2 <= sample_out_val_s;
408 END IF;
420 END IF;
409 END PROCESS;
421 END PROCESS;
410
422
411 chanel_HIGH : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE
423 chanel_HIGH : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE
412 PROCESS (clk, rstn)
424 PROCESS (clk, rstn)
413 BEGIN -- PROCESS
425 BEGIN -- PROCESS
414 IF rstn = '0' THEN -- asynchronous reset (active low)
426 IF rstn = '0' THEN -- asynchronous reset (active low)
415 sample_out_s2(ChanelsCount-1, I) <= '0';
427 sample_out_s2(ChanelsCount-1, I) <= '0';
416 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
428 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
417 IF sample_out_rot_s = '1' THEN
429 IF sample_out_rot_s = '1' THEN
418 sample_out_s2(ChanelsCount-1, I) <= sample_out_s(I);
430 sample_out_s2(ChanelsCount-1, I) <= sample_out_s(I);
419 END IF;
431 END IF;
420 END IF;
432 END IF;
421 END PROCESS;
433 END PROCESS;
422 END GENERATE chanel_HIGH;
434 END GENERATE chanel_HIGH;
423
435
424 chanel_more : IF ChanelsCount > 1 GENERATE
436 chanel_more : IF ChanelsCount > 1 GENERATE
425 all_chanel : FOR J IN ChanelsCount-1 DOWNTO 1 GENERATE
437 all_chanel : FOR J IN ChanelsCount-1 DOWNTO 1 GENERATE
426 all_bit : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE
438 all_bit : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE
427 PROCESS (clk, rstn)
439 PROCESS (clk, rstn)
428 BEGIN -- PROCESS
440 BEGIN -- PROCESS
429 IF rstn = '0' THEN -- asynchronous reset (active low)
441 IF rstn = '0' THEN -- asynchronous reset (active low)
430 sample_out_s2(J-1, I) <= '0';
442 sample_out_s2(J-1, I) <= '0';
431 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
443 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
432 IF sample_out_rot_s = '1' THEN
444 IF sample_out_rot_s = '1' THEN
433 sample_out_s2(J-1, I) <= sample_out_s2(J, I);
445 sample_out_s2(J-1, I) <= sample_out_s2(J, I);
434 END IF;
446 END IF;
435 END IF;
447 END IF;
436 END PROCESS;
448 END PROCESS;
437 END GENERATE all_bit;
449 END GENERATE all_bit;
438 END GENERATE all_chanel;
450 END GENERATE all_chanel;
439 END GENERATE chanel_more;
451 END GENERATE chanel_more;
440
452
441 sample_out <= sample_out_s2;
453 sample_out <= sample_out_s2;
442 END ar_IIR_CEL_CTRLR_v3;
454 END ar_IIR_CEL_CTRLR_v3;
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@@ -1,122 +1,138
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
21 ----------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY lpp;
25 LIBRARY lpp;
26 USE lpp.iir_filter.ALL;
26 USE lpp.iir_filter.ALL;
27 USE lpp.FILTERcfg.ALL;
27 USE lpp.FILTERcfg.ALL;
28 USE lpp.general_purpose.ALL;
28 USE lpp.general_purpose.ALL;
29 LIBRARY techmap;
29 LIBRARY techmap;
30 USE techmap.gencomp.ALL;
30 USE techmap.gencomp.ALL;
31
31
32 ENTITY RAM_CTRLR_v2 IS
32 ENTITY RAM_CTRLR_v2 IS
33 GENERIC(
33 GENERIC(
34 tech : INTEGER := 0;
34 tech : INTEGER := 0;
35 Input_SZ_1 : INTEGER := 16;
35 Input_SZ_1 : INTEGER := 16;
36 Mem_use : INTEGER := use_RAM
36 Mem_use : INTEGER := use_RAM
37 );
37 );
38 PORT(
38 PORT(
39 rstn : IN STD_LOGIC;
39 rstn : IN STD_LOGIC;
40 clk : IN STD_LOGIC;
40 clk : IN STD_LOGIC;
41 -- ram init done
42 init_mem_done: out STD_LOGIC;
41 -- R/W Ctrl
43 -- R/W Ctrl
42 ram_write : IN STD_LOGIC;
44 ram_write : IN STD_LOGIC;
43 ram_read : IN STD_LOGIC;
45 ram_read : IN STD_LOGIC;
44 -- ADDR Ctrl
46 -- ADDR Ctrl
45 raddr_rst : IN STD_LOGIC;
47 raddr_rst : IN STD_LOGIC;
46 raddr_add1 : IN STD_LOGIC;
48 raddr_add1 : IN STD_LOGIC;
47 waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
49 waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
48 -- Data
50 -- Data
49 sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
51 sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
50 sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0)
52 sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0)
51 );
53 );
52 END RAM_CTRLR_v2;
54 END RAM_CTRLR_v2;
53
55
54
56
55 ARCHITECTURE ar_RAM_CTRLR_v2 OF RAM_CTRLR_v2 IS
57 ARCHITECTURE ar_RAM_CTRLR_v2 OF RAM_CTRLR_v2 IS
56
58
57 SIGNAL WD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
59 SIGNAL WD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
58 SIGNAL RD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
60 SIGNAL RD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
59 SIGNAL WEN, REN : STD_LOGIC;
61 SIGNAL WEN, REN : STD_LOGIC;
60 SIGNAL RADDR : STD_LOGIC_VECTOR(7 DOWNTO 0);
62 SIGNAL RADDR : STD_LOGIC_VECTOR(7 DOWNTO 0);
61 SIGNAL WADDR : STD_LOGIC_VECTOR(7 DOWNTO 0);
63 SIGNAL WADDR : STD_LOGIC_VECTOR(7 DOWNTO 0);
62 SIGNAL counter : STD_LOGIC_VECTOR(7 DOWNTO 0);
64 SIGNAL counter : STD_LOGIC_VECTOR(7 DOWNTO 0);
65
66 signal rst_mem_done_s : std_logic;
67 signal ram_write_s : std_logic;
63
68
64 BEGIN
69 BEGIN
65
70
66 sample_out <= RD(Input_SZ_1-1 DOWNTO 0);
71 init_mem_done <= rst_mem_done_s;
67 WD(Input_SZ_1-1 DOWNTO 0) <= sample_in;
72
73 sample_out <= RD(Input_SZ_1-1 DOWNTO 0) when rst_mem_done_s = '1' else (others => '0');
74 WD(Input_SZ_1-1 DOWNTO 0) <= sample_in when rst_mem_done_s = '1' else (others => '0');
75 ram_write_s <= ram_write when rst_mem_done_s = '1' else '1';
68 -----------------------------------------------------------------------------
76 -----------------------------------------------------------------------------
69 -- RAM
77 -- RAM
70 -----------------------------------------------------------------------------
78 -----------------------------------------------------------------------------
71
79
72 memCEL : IF Mem_use = use_CEL GENERATE
80 memCEL : IF Mem_use = use_CEL GENERATE
73 WEN <= NOT ram_write;
81 WEN <= NOT ram_write_s;
74 REN <= NOT ram_read;
82 REN <= NOT ram_read;
75 -- RAMblk : RAM_CEL_N
76 -- GENERIC MAP(Input_SZ_1)
77 RAMblk : RAM_CEL
83 RAMblk : RAM_CEL
78 GENERIC MAP(Input_SZ_1, 8)
84 GENERIC MAP(Input_SZ_1, 8)
79 PORT MAP(
85 PORT MAP(
80 WD => WD,
86 WD => WD,
81 RD => RD,
87 RD => RD,
82 WEN => WEN,
88 WEN => WEN,
83 REN => REN,
89 REN => REN,
84 WADDR => WADDR,
90 WADDR => WADDR,
85 RADDR => RADDR,
91 RADDR => RADDR,
86 RWCLK => clk,
92 RWCLK => clk,
87 RESET => rstn
93 RESET => rstn
88 ) ;
94 ) ;
89 END GENERATE;
95 END GENERATE;
90
96
91 memRAM : IF Mem_use = use_RAM GENERATE
97 memRAM : IF Mem_use = use_RAM GENERATE
92 SRAM : syncram_2p
98 SRAM : syncram_2p
93 GENERIC MAP(tech, 8, Input_SZ_1)
99 GENERIC MAP(tech, 8, Input_SZ_1)
94 PORT MAP(clk, ram_read, RADDR, RD, clk, ram_write, WADDR, WD);
100 PORT MAP(clk, ram_read, RADDR, RD, clk, ram_write_s, WADDR, WD);
95 END GENERATE;
101 END GENERATE;
96
102
97 -----------------------------------------------------------------------------
103 -----------------------------------------------------------------------------
98 -- RADDR
104 -- RADDR
99 -----------------------------------------------------------------------------
105 -----------------------------------------------------------------------------
100 PROCESS (clk, rstn)
106 PROCESS (clk, rstn)
101 BEGIN -- PROCESS
107 BEGIN -- PROCESS
102 IF rstn = '0' THEN -- asynchronous reset (active low)
108 IF rstn = '0' THEN -- asynchronous reset (active low)
103 counter <= (OTHERS => '0');
109 counter <= (OTHERS => '0');
110 rst_mem_done_s <= '0';
104 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
111 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
105 IF raddr_rst = '1' THEN
112 if rst_mem_done_s = '0' then
106 counter <= (OTHERS => '0');
107 ELSIF raddr_add1 = '1' THEN
108 counter <= STD_LOGIC_VECTOR(UNSIGNED(counter)+1);
113 counter <= STD_LOGIC_VECTOR(UNSIGNED(counter)+1);
109 END IF;
114 else
115 IF raddr_rst = '1' THEN
116 counter <= (OTHERS => '0');
117 ELSIF raddr_add1 = '1' THEN
118 counter <= STD_LOGIC_VECTOR(UNSIGNED(counter)+1);
119 END IF;
120 end if;
121 if counter = x"FF" then
122 rst_mem_done_s <= '1';
123 end if;
124
110 END IF;
125 END IF;
111 END PROCESS;
126 END PROCESS;
112 RADDR <= counter;
127 RADDR <= counter;
113
128
114 -----------------------------------------------------------------------------
129 -----------------------------------------------------------------------------
115 -- WADDR
130 -- WADDR
116 -----------------------------------------------------------------------------
131 -----------------------------------------------------------------------------
117 WADDR <= STD_LOGIC_VECTOR(UNSIGNED(counter)-2) WHEN waddr_previous = "10" ELSE
132 WADDR <= STD_LOGIC_VECTOR(UNSIGNED(counter)) when rst_mem_done_s = '0' else
133 STD_LOGIC_VECTOR(UNSIGNED(counter)-2) WHEN waddr_previous = "10" ELSE
118 STD_LOGIC_VECTOR(UNSIGNED(counter)-1) WHEN waddr_previous = "01" ELSE
134 STD_LOGIC_VECTOR(UNSIGNED(counter)-1) WHEN waddr_previous = "01" ELSE
119 STD_LOGIC_VECTOR(UNSIGNED(counter));
135 STD_LOGIC_VECTOR(UNSIGNED(counter));
120
136
121
137
122 END ar_RAM_CTRLR_v2;
138 END ar_RAM_CTRLR_v2;
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