HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r24:4029ae6c7747

optimisation code CNA

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lib/lpp/lpp_cna/Gene_SYNC.vhd created 644 +53 0

@@ -0,0 +1,53
	1	-- Gene_SYNC.vhd
	2	library IEEE;
	3	use IEEE.std_logic_1164.all;
	4	use IEEE.numeric_std.all;
	5
	6	entity Gene_SYNC is
	7
	8	port(
	9	SCLK,raz : in std_logic;
	10	enable : in std_logic;
	11	-- Sysclk : in std_logic;
	12	OKAI_send : out std_logic;
	13	SYNC : out std_logic
	14	);
	15
	16	end Gene_SYNC;
	17
	18
	19	architecture ar_Gene_SYNC of Gene_SYNC is
	20
	21	--signal Sysclk_reg : std_logic;
	22	signal count : integer;
	23
	24
	25	begin
	26	process (SCLK,raz)
	27	begin
	28	if(raz='0')then
	29	SYNC <= '0';
	30	-- Sysclk_reg <= '0';
	31	count <= 14;
	32	OKAI_send <= '0';
	33
	34	elsif(SCLK' event and SCLK='1')then
	35	if(enable='1')then
	36
	37	-- Sysclk_reg <= Sysclk;
	38	if(count=15)then
	39	SYNC <= '1';
	40	count <= count+1;
	41	elsif(count=16)then
	42	count <= 0;
	43	SYNC <= '0';
	44	OKAI_send <= '1';
	45	else
	46	count <= count+1;
	47	OKAI_send <= '0';
	48	end if;
	49	end if;
	50	end if;
	51	end process;
	52
	53	end ar_Gene_SYNC; No newline at end of file

lib/lpp/lpp_cna/APB_CNA.vhd +9 -14

             -- APB_CNA.vhd
             library ieee;
             use ieee.std_logic_1164.all;
             library grlib;
             use grlib.amba.all;
             use grlib.stdlib.all;
             use grlib.devices.all;
             library lpp;
             use lpp.lpp_amba.all;
             use lpp.lpp_cna.all;
             entity APB_CNA is
               generic (
                 pindex   : integer := 0;
                 paddr    : integer := 0;
                 pmask    : integer := 16#fff#;
                 pirq     : integer := 0;
                 abits    : integer := 8);
               port (
                 clk     : in  std_logic;
                 rst     : in  std_logic;
                 apbi    : in  apb_slv_in_type;
                 apbo    : out apb_slv_out_type;
                 SYNC    : out std_logic;
                 SCLK    : out std_logic;
                 DATA    : out std_logic
                 );
             end APB_CNA;
             architecture ar_APB_CNA of APB_CNA is
             constant REVISION : integer := 1;
             constant pconfig : apb_config_type := (
 => ahb_device_reg (VENDOR_LPP, LPP_CNA, 0, REVISION, 0),
 => apb_iobar(paddr, pmask));
-            signal flag_nw   : std_logic;
+            signal enable   : std_logic;
-            signal bp        : std_logic;
+            signal flag_sd : std_logic;
-            signal Rz        : std_logic;
-            signal flag_sd   : std_logic;
             type CNA_ctrlr_Reg is record
-                 CNA_Cfg  : std_logic_vector(3 downto 0);
+                 CNA_Cfg  : std_logic_vector(1 downto 0);
                  CNA_Data : std_logic_vector(15 downto 0);
             end record;
             signal Rec : CNA_ctrlr_Reg;
             signal Rdata     : std_logic_vector(31 downto 0);
             begin
-            bp <= Rec.CNA_Cfg(0);
+            enable <= Rec.CNA_Cfg(0);
-            flag_nw <= Rec.CNA_Cfg(1);
+            Rec.CNA_Cfg(1) <= flag_sd;
-            Rec.CNA_Cfg(2) <= flag_sd;
-            Rec.CNA_Cfg(3) <= Rz;
                 CONVERTER : entity Work.CNA_TabloC
-                    port map(clk,rst,flag_nw,bp,Rec.CNA_Data,SYNC,SCLK,Rz,flag_sd,Data);
+                    port map(clk,rst,enable,Rec.CNA_Data,SYNC,SCLK,flag_sd,Data);
                 process(rst,clk)
                 begin
                     if(rst='0')then
                         Rec.CNA_Data <=  (others => '0');
                     elsif(clk'event and clk='1')then
                 --APB Write OP
                         if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
                             case apbi.paddr(abits-1 downto 2) is
                                 when "000000" =>
-                                    Rec.CNA_Cfg(1 downto 0) <= apbi.pwdata(1 downto 0);
+                                    Rec.CNA_Cfg(0) <= apbi.pwdata(0);
                                 when "000001" =>
                                     Rec.CNA_Data <= apbi.pwdata(15 downto 0);
                                 when others =>
                                     null;
                             end case;
                         end if;
                 --APB READ OP
                         if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
                             case apbi.paddr(abits-1 downto 2) is
                                 when "000000" =>
-                                    Rdata(31 downto 4) <= X"ABCDEF5";
+                                    Rdata(31 downto 2) <= X"ABCDEF5" & "00";
-                                    Rdata(3 downto 0) <= Rec.CNA_Cfg;
+                                    Rdata(1 downto 0) <= Rec.CNA_Cfg;
                                 when "000001" =>
                                     Rdata(31 downto 16) <= X"FD18";
                                     Rdata(15 downto 0) <= Rec.CNA_Data;
                                 when others =>
                                     Rdata <= (others => '0');
                             end case;
                         end if;
                     end if;
                     apbo.pconfig <= pconfig;
                 end process;
             apbo.prdata     <=   Rdata when apbi.penable = '1';
             end ar_APB_CNA;

lib/lpp/lpp_cna/CNA_TabloC.vhd +14 -18

             -- CNA_TabloC.vhd
             library IEEE;
             use IEEE.std_logic_1164.all;
             use IEEE.numeric_std.all;
             use work.Convertisseur_config.all;
             entity CNA_TabloC is
                 port(
                     clock       : in std_logic;
                     rst         : in std_logic;
-                    flag_nw     : in std_logic;
+                    enable      : in std_logic;
-                    bp          : in std_logic;
+                    --bp          : in std_logic;
                     Data_C      : in std_logic_vector(15 downto 0);
                     SYNC        : out std_logic;
                     SCLK        : out std_logic;
-                    Rz          : out std_logic;
+                    --Rz          : out std_logic;
                     flag_sd     : out std_logic;
                     Data        : out std_logic
                     );
             end CNA_TabloC;
             architecture ar_CNA_TabloC of CNA_TabloC is
             component CLKINT
             port( A : in    std_logic := 'U';
                   Y : out   std_logic);
             end component;
             signal clk      : std_logic;
-            --signal reset    : std_logic;
             signal raz          : std_logic;
-            signal sys_clk      : std_logic;
+            signal s_SCLK      : std_logic;
-            signal Data_int     : std_logic_vector(15 downto 0);
             signal OKAI_send    : std_logic;
+            --signal Data_int     : std_logic_vector(15 downto 0);
             begin
             CLKINT_0 : CLKINT
                 port map(A => clock, Y => clk);
             CLKINT_1 : CLKINT
                 port map(A => rst, Y => raz);
             SystemCLK : entity work.Clock_Serie
                 generic map (nb_serial)
-                port map (clk,raz,sys_clk);
+                port map (clk,raz,s_SCLK);
-            Signal_sync : entity work.GeneSYNC_flag
+            Signal_sync : entity work.Gene_SYNC
-                port map (clk,raz,flag_nw,sys_clk,OKAI_send,SYNC);
+                port map (s_SCLK,raz,enable,OKAI_send,SYNC);
             Serial : entity work.serialize
-                port map (clk,raz,sys_clk,Data_int,OKAI_send,flag_sd,Data);
+                port map (clk,raz,s_SCLK,Data_C,OKAI_send,flag_sd,Data);
-            --raz         <= not reset;
+            --Rz          <= raz;
-            Rz          <= raz;
+            SCLK        <= s_SCLK;
-            SCLK        <= not sys_clk;
-            --Data_Cvec   <= std_logic_vector(to_unsigned(Data_C,12));
-            --Data_TOT    <= "0001" & Data_Cvec;
-            with bp select
+            --with bp select
-                Data_int <= X"9555" when '1',
+            --    Data_int <= X"9555" when '1',
-                            Data_C when others;
+            --                Data_C when others;
             end ar_CNA_TabloC;

lib/lpp/lpp_cna/Convertisseur_config.vhd +2 -2

             -- Convertisseur_config.vhd
             library IEEE;
             use IEEE.std_logic_1164.all;
             use IEEE.numeric_std.all;
             Package Convertisseur_config is
             --===========================================================|
             --================= Valeurs Sinus 1Khz ======================|
             --===========================================================|
             type Tbl is array(natural range <>) of std_logic_vector(11 downto 0);
             constant Tablo : Tbl (0 to 49):= (X"800",X"901",X"9FD",X"AF2",X"BDB",X"CB4",X"D7A",X"E2A",X"EC1",X"F3D",X"F9C",X"FDC",X"FFC",X"FFC",X"FDC",X"F9C",X"F3D",X"EC1",X"E2A",X"D7A",X"CB4",X"BDB",X"AF2",X"9FD",X"901",X"800",X"6FF",X"603",X"50E",X"425",X"34C",X"286",X"1D6",X"13F",X"0C3",X"064",X"024",X"004",X"004",X"024",X"064",X"0C3",X"13F",X"1D6",X"286",X"34C",X"425",X"50E",X"603",X"6FF");
             --constant Tablo : Tbl (0 to 49):= (X"C00",X"C80",X"CFF",X"D79",X"DED",X"E5A",X"EBD",X"F15",X"F61",X"F9F",X"FCE",X"FEE",X"FFE",X"FFE",X"FEE",X"FCE",X"F9F",X"F61",X"F15",X"EBD",X"E5A",X"DED",X"D79",X"CFF",X"C80",X"C00",X"B80",X"B01",X"A87",X"A13",X"9A6",X"943",X"8EB",X"89F",X"861",X"832",X"812",X"802",X"802",X"812",X"832",X"861",X"89F",X"8EB",X"943",X"9A6",X"A13",X"A87",X"B01",X"B80");
             --===========================================================|
             --============= Fr�quence de s�rialisation ==================|
             --===========================================================|
-            constant Freq_serial : integer := 1_000_000;
+            constant Freq_serial : integer := 5_000_000;
-            constant nb_serial : integer := 40_000_000 / Freq_serial;
+            constant nb_serial : integer := 30_000_000 / Freq_serial;
             end;

lib/lpp/lpp_cna/Serialize.vhd +1 -1

             -- Serialize.vhd
             library IEEE;
             use IEEE.numeric_std.all;
             use IEEE.std_logic_1164.all;
             entity Serialize is
             port(
                 clk,raz : in std_logic;
                 sclk    : in std_logic;
                 vectin  : in std_logic_vector(15 downto 0);
                 send    : in std_logic;
                 sended  : out std_logic;
                 Data    : out std_logic);
             end Serialize;
             architecture ar_Serialize of Serialize is
             type etat is (attente,serialize);
             signal ect      : etat;
             signal vector_int   : std_logic_vector(16 downto 0);
             signal vectin_reg   : std_logic_vector(15 downto 0);
             signal load         : std_logic;
             signal N            : integer range 0 to 16;
             signal CPT_ended    : std_logic:='0';
             begin
                 process(clk,raz)
                     begin
                     if(raz='0')then
                         ect         <= attente;
                         vectin_reg  <= (others=> '0');
                         load        <= '0';
                         sended      <= '1';
                     elsif(clk'event and clk='1')then
                         vectin_reg <= vectin;
                         case ect is
                             when attente =>
                                 if (send='1') then
                                     sended  <= '0';
                                     load    <= '1';
                                     ect     <= serialize;
                                 else
                                     ect <= attente;
                                 end if;
                             when serialize =>
                                 load <= '0';
                                 if(CPT_ended='1')then
                                     ect     <= attente;
                                     sended  <= '1';
                                 end if;
                         end case;
                     end if;
                 end process;
                 process(sclk,load,raz)
                     begin
                     if (raz='0')then
                         vector_int <= (others=> '0');
                         N <= 16;
                     elsif(load='1')then
                         vector_int <= vectin & '0';
                         N <= 0;
-                    elsif(sclk'event and sclk='0')then
+                    elsif(sclk'event and sclk='1')then
                         if (CPT_ended='0') then
                             vector_int <= vector_int(15 downto 0) & '0';
                             N <= N+1;
                         end if;
                     end if;
                 end process;
             CPT_ended   <=  '1' when N = 16 else '0';
             with ect select
                 Data <=  vector_int(16) when serialize,
                         '0' when others;
             end ar_Serialize;

lib/lpp/lpp_cna/lpp_cna.vhd +2 -2

             library ieee;
             use ieee.std_logic_1164.all;
             library grlib;
             use grlib.amba.all;
             -- pragma translate_off
             use std.textio.all;
             -- pragma translate_on
             library lpp;
             use lpp.lpp_amba.all;
             package lpp_cna is
             component APB_CNA is
               generic (
                 pindex   : integer := 0;
                 paddr    : integer := 0;
                 pmask    : integer := 16#fff#;
                 pirq     : integer := 0;
                 abits    : integer := 8);
               port (
                 clk     : in  std_logic;
                 rst     : in  std_logic;
                 apbi    : in  apb_slv_in_type;
                 apbo    : out apb_slv_out_type;
                 SYNC    : out std_logic;
                 SCLK    : out std_logic;
                 DATA    : out std_logic
                 );
             end component;
             component CNA_TabloC is
                 port(
                     clock       : in std_logic;
                     rst         : in std_logic;
                     flag_nw     : in std_logic;
                     bp          : in std_logic;
                     Data_C      : in std_logic_vector(15 downto 0);
                     SYNC        : out std_logic;
                     SCLK        : out std_logic;
                     Rz          : out std_logic;
                     flag_sd     : out std_logic;
                     Data        : out std_logic
                     );
             end component;
             component Clock_Serie is
                 generic(N :integer := 695);
                 port(
                     clk, raz   : in std_logic ;
                     clock      : out std_logic);
             end component;
-            component GeneSYNC_flag is
+            component Gene_SYNC is
                 port(
                     clk,raz     : in std_logic;
-                    flag_nw     : in std_logic;
+                    send     : in std_logic;
                     Sysclk      : in std_logic;
                     OKAI_send   : out std_logic;
                     SYNC        : out std_logic);
             end component;
             component Serialize is
             port(
                 clk,raz : in std_logic;
                 sclk    : in std_logic;
                 vectin  : in std_logic_vector(15 downto 0);
                 send    : in std_logic;
                 sended  : out std_logic;
                 Data    : out std_logic);
             end component;
             end;

lib/lpp/lpp_cna/GeneSYNC_flag.vhd removed 0 -94

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