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optimisation code CNA
martin -
r24:4029ae6c7747 default
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@@ -0,0 +1,53
1 -- Gene_SYNC.vhd
2 library IEEE;
3 use IEEE.std_logic_1164.all;
4 use IEEE.numeric_std.all;
5
6 entity Gene_SYNC is
7
8 port(
9 SCLK,raz : in std_logic;
10 enable : in std_logic;
11 -- Sysclk : in std_logic;
12 OKAI_send : out std_logic;
13 SYNC : out std_logic
14 );
15
16 end Gene_SYNC;
17
18
19 architecture ar_Gene_SYNC of Gene_SYNC is
20
21 --signal Sysclk_reg : std_logic;
22 signal count : integer;
23
24
25 begin
26 process (SCLK,raz)
27 begin
28 if(raz='0')then
29 SYNC <= '0';
30 -- Sysclk_reg <= '0';
31 count <= 14;
32 OKAI_send <= '0';
33
34 elsif(SCLK' event and SCLK='1')then
35 if(enable='1')then
36
37 -- Sysclk_reg <= Sysclk;
38 if(count=15)then
39 SYNC <= '1';
40 count <= count+1;
41 elsif(count=16)then
42 count <= 0;
43 SYNC <= '0';
44 OKAI_send <= '1';
45 else
46 count <= count+1;
47 OKAI_send <= '0';
48 end if;
49 end if;
50 end if;
51 end process;
52
53 end ar_Gene_SYNC; No newline at end of file
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@@ -38,13 +38,11 constant pconfig : apb_config_type := (
38 0 => ahb_device_reg (VENDOR_LPP, LPP_CNA, 0, REVISION, 0),
38 0 => ahb_device_reg (VENDOR_LPP, LPP_CNA, 0, REVISION, 0),
39 1 => apb_iobar(paddr, pmask));
39 1 => apb_iobar(paddr, pmask));
40
40
41 signal flag_nw : std_logic;
41 signal enable : std_logic;
42 signal bp : std_logic;
42 signal flag_sd : std_logic;
43 signal Rz : std_logic;
44 signal flag_sd : std_logic;
45
43
46 type CNA_ctrlr_Reg is record
44 type CNA_ctrlr_Reg is record
47 CNA_Cfg : std_logic_vector(3 downto 0);
45 CNA_Cfg : std_logic_vector(1 downto 0);
48 CNA_Data : std_logic_vector(15 downto 0);
46 CNA_Data : std_logic_vector(15 downto 0);
49 end record;
47 end record;
50
48
@@ -53,14 +51,11 signal Rdata : std_logic_vector(31 d
53
51
54 begin
52 begin
55
53
56 bp <= Rec.CNA_Cfg(0);
54 enable <= Rec.CNA_Cfg(0);
57 flag_nw <= Rec.CNA_Cfg(1);
55 Rec.CNA_Cfg(1) <= flag_sd;
58 Rec.CNA_Cfg(2) <= flag_sd;
59 Rec.CNA_Cfg(3) <= Rz;
60
56
61
62 CONVERTER : entity Work.CNA_TabloC
57 CONVERTER : entity Work.CNA_TabloC
63 port map(clk,rst,flag_nw,bp,Rec.CNA_Data,SYNC,SCLK,Rz,flag_sd,Data);
58 port map(clk,rst,enable,Rec.CNA_Data,SYNC,SCLK,flag_sd,Data);
64
59
65
60
66 process(rst,clk)
61 process(rst,clk)
@@ -75,7 +70,7 Rec.CNA_Cfg(3) <= Rz;
75 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
70 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
76 case apbi.paddr(abits-1 downto 2) is
71 case apbi.paddr(abits-1 downto 2) is
77 when "000000" =>
72 when "000000" =>
78 Rec.CNA_Cfg(1 downto 0) <= apbi.pwdata(1 downto 0);
73 Rec.CNA_Cfg(0) <= apbi.pwdata(0);
79 when "000001" =>
74 when "000001" =>
80 Rec.CNA_Data <= apbi.pwdata(15 downto 0);
75 Rec.CNA_Data <= apbi.pwdata(15 downto 0);
81 when others =>
76 when others =>
@@ -87,8 +82,8 Rec.CNA_Cfg(3) <= Rz;
87 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
82 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
88 case apbi.paddr(abits-1 downto 2) is
83 case apbi.paddr(abits-1 downto 2) is
89 when "000000" =>
84 when "000000" =>
90 Rdata(31 downto 4) <= X"ABCDEF5";
85 Rdata(31 downto 2) <= X"ABCDEF5" & "00";
91 Rdata(3 downto 0) <= Rec.CNA_Cfg;
86 Rdata(1 downto 0) <= Rec.CNA_Cfg;
92 when "000001" =>
87 when "000001" =>
93 Rdata(31 downto 16) <= X"FD18";
88 Rdata(31 downto 16) <= X"FD18";
94 Rdata(15 downto 0) <= Rec.CNA_Data;
89 Rdata(15 downto 0) <= Rec.CNA_Data;
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@@ -8,12 +8,12 entity CNA_TabloC is
8 port(
8 port(
9 clock : in std_logic;
9 clock : in std_logic;
10 rst : in std_logic;
10 rst : in std_logic;
11 flag_nw : in std_logic;
11 enable : in std_logic;
12 bp : in std_logic;
12 --bp : in std_logic;
13 Data_C : in std_logic_vector(15 downto 0);
13 Data_C : in std_logic_vector(15 downto 0);
14 SYNC : out std_logic;
14 SYNC : out std_logic;
15 SCLK : out std_logic;
15 SCLK : out std_logic;
16 Rz : out std_logic;
16 --Rz : out std_logic;
17 flag_sd : out std_logic;
17 flag_sd : out std_logic;
18 Data : out std_logic
18 Data : out std_logic
19 );
19 );
@@ -28,12 +28,11 port( A : in std_logic := 'U';
28 end component;
28 end component;
29
29
30 signal clk : std_logic;
30 signal clk : std_logic;
31 --signal reset : std_logic;
32
31
33 signal raz : std_logic;
32 signal raz : std_logic;
34 signal sys_clk : std_logic;
33 signal s_SCLK : std_logic;
35 signal Data_int : std_logic_vector(15 downto 0);
36 signal OKAI_send : std_logic;
34 signal OKAI_send : std_logic;
35 --signal Data_int : std_logic_vector(15 downto 0);
37
36
38 begin
37 begin
39
38
@@ -47,25 +46,22 CLKINT_1 : CLKINT
47
46
48 SystemCLK : entity work.Clock_Serie
47 SystemCLK : entity work.Clock_Serie
49 generic map (nb_serial)
48 generic map (nb_serial)
50 port map (clk,raz,sys_clk);
49 port map (clk,raz,s_SCLK);
51
50
52
51
53 Signal_sync : entity work.GeneSYNC_flag
52 Signal_sync : entity work.Gene_SYNC
54 port map (clk,raz,flag_nw,sys_clk,OKAI_send,SYNC);
53 port map (s_SCLK,raz,enable,OKAI_send,SYNC);
55
54
56
55
57 Serial : entity work.serialize
56 Serial : entity work.serialize
58 port map (clk,raz,sys_clk,Data_int,OKAI_send,flag_sd,Data);
57 port map (clk,raz,s_SCLK,Data_C,OKAI_send,flag_sd,Data);
59
58
60
59
61 --raz <= not reset;
60 --Rz <= raz;
62 Rz <= raz;
61 SCLK <= s_SCLK;
63 SCLK <= not sys_clk;
64 --Data_Cvec <= std_logic_vector(to_unsigned(Data_C,12));
65 --Data_TOT <= "0001" & Data_Cvec;
66
62
67 with bp select
63 --with bp select
68 Data_int <= X"9555" when '1',
64 -- Data_int <= X"9555" when '1',
69 Data_C when others;
65 -- Data_C when others;
70
66
71 end ar_CNA_TabloC; No newline at end of file
67 end ar_CNA_TabloC;
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@@ -18,7 +18,7 constant Tablo : Tbl (0 to 49):= (X"800"
18 --===========================================================|
18 --===========================================================|
19 --============= Fr�quence de s�rialisation ==================|
19 --============= Fr�quence de s�rialisation ==================|
20 --===========================================================|
20 --===========================================================|
21 constant Freq_serial : integer := 1_000_000;
21 constant Freq_serial : integer := 5_000_000;
22 constant nb_serial : integer := 40_000_000 / Freq_serial;
22 constant nb_serial : integer := 30_000_000 / Freq_serial;
23
23
24 end; No newline at end of file
24 end;
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@@ -68,7 +68,7 begin
68 elsif(load='1')then
68 elsif(load='1')then
69 vector_int <= vectin & '0';
69 vector_int <= vectin & '0';
70 N <= 0;
70 N <= 0;
71 elsif(sclk'event and sclk='0')then
71 elsif(sclk'event and sclk='1')then
72 if (CPT_ended='0') then
72 if (CPT_ended='0') then
73 vector_int <= vector_int(15 downto 0) & '0';
73 vector_int <= vector_int(15 downto 0) & '0';
74 N <= N+1;
74 N <= N+1;
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@@ -54,10 +54,10 component Clock_Serie is
54 end component;
54 end component;
55
55
56
56
57 component GeneSYNC_flag is
57 component Gene_SYNC is
58 port(
58 port(
59 clk,raz : in std_logic;
59 clk,raz : in std_logic;
60 flag_nw : in std_logic;
60 send : in std_logic;
61 Sysclk : in std_logic;
61 Sysclk : in std_logic;
62 OKAI_send : out std_logic;
62 OKAI_send : out std_logic;
63 SYNC : out std_logic);
63 SYNC : out std_logic);
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