diff --git a/lib/lpp/lpp_cna/APB_CNA.vhd b/lib/lpp/lpp_cna/APB_CNA.vhd --- a/lib/lpp/lpp_cna/APB_CNA.vhd +++ b/lib/lpp/lpp_cna/APB_CNA.vhd @@ -38,13 +38,11 @@ constant pconfig : apb_config_type := ( 0 => ahb_device_reg (VENDOR_LPP, LPP_CNA, 0, REVISION, 0), 1 => apb_iobar(paddr, pmask)); -signal flag_nw : std_logic; -signal bp : std_logic; -signal Rz : std_logic; -signal flag_sd : std_logic; +signal enable : std_logic; +signal flag_sd : std_logic; type CNA_ctrlr_Reg is record - CNA_Cfg : std_logic_vector(3 downto 0); + CNA_Cfg : std_logic_vector(1 downto 0); CNA_Data : std_logic_vector(15 downto 0); end record; @@ -53,14 +51,11 @@ signal Rdata : std_logic_vector(31 d begin -bp <= Rec.CNA_Cfg(0); -flag_nw <= Rec.CNA_Cfg(1); -Rec.CNA_Cfg(2) <= flag_sd; -Rec.CNA_Cfg(3) <= Rz; +enable <= Rec.CNA_Cfg(0); +Rec.CNA_Cfg(1) <= flag_sd; - CONVERTER : entity Work.CNA_TabloC - port map(clk,rst,flag_nw,bp,Rec.CNA_Data,SYNC,SCLK,Rz,flag_sd,Data); + port map(clk,rst,enable,Rec.CNA_Data,SYNC,SCLK,flag_sd,Data); process(rst,clk) @@ -75,7 +70,7 @@ Rec.CNA_Cfg(3) <= Rz; if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then case apbi.paddr(abits-1 downto 2) is when "000000" => - Rec.CNA_Cfg(1 downto 0) <= apbi.pwdata(1 downto 0); + Rec.CNA_Cfg(0) <= apbi.pwdata(0); when "000001" => Rec.CNA_Data <= apbi.pwdata(15 downto 0); when others => @@ -87,8 +82,8 @@ Rec.CNA_Cfg(3) <= Rz; if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then case apbi.paddr(abits-1 downto 2) is when "000000" => - Rdata(31 downto 4) <= X"ABCDEF5"; - Rdata(3 downto 0) <= Rec.CNA_Cfg; + Rdata(31 downto 2) <= X"ABCDEF5" & "00"; + Rdata(1 downto 0) <= Rec.CNA_Cfg; when "000001" => Rdata(31 downto 16) <= X"FD18"; Rdata(15 downto 0) <= Rec.CNA_Data; diff --git a/lib/lpp/lpp_cna/CNA_TabloC.vhd b/lib/lpp/lpp_cna/CNA_TabloC.vhd --- a/lib/lpp/lpp_cna/CNA_TabloC.vhd +++ b/lib/lpp/lpp_cna/CNA_TabloC.vhd @@ -8,12 +8,12 @@ entity CNA_TabloC is port( clock : in std_logic; rst : in std_logic; - flag_nw : in std_logic; - bp : in std_logic; + enable : in std_logic; + --bp : in std_logic; Data_C : in std_logic_vector(15 downto 0); SYNC : out std_logic; SCLK : out std_logic; - Rz : out std_logic; + --Rz : out std_logic; flag_sd : out std_logic; Data : out std_logic ); @@ -28,12 +28,11 @@ port( A : in std_logic := 'U'; end component; signal clk : std_logic; ---signal reset : std_logic; signal raz : std_logic; -signal sys_clk : std_logic; -signal Data_int : std_logic_vector(15 downto 0); +signal s_SCLK : std_logic; signal OKAI_send : std_logic; +--signal Data_int : std_logic_vector(15 downto 0); begin @@ -47,25 +46,22 @@ CLKINT_1 : CLKINT SystemCLK : entity work.Clock_Serie generic map (nb_serial) - port map (clk,raz,sys_clk); + port map (clk,raz,s_SCLK); -Signal_sync : entity work.GeneSYNC_flag - port map (clk,raz,flag_nw,sys_clk,OKAI_send,SYNC); +Signal_sync : entity work.Gene_SYNC + port map (s_SCLK,raz,enable,OKAI_send,SYNC); Serial : entity work.serialize - port map (clk,raz,sys_clk,Data_int,OKAI_send,flag_sd,Data); + port map (clk,raz,s_SCLK,Data_C,OKAI_send,flag_sd,Data); ---raz <= not reset; -Rz <= raz; -SCLK <= not sys_clk; ---Data_Cvec <= std_logic_vector(to_unsigned(Data_C,12)); ---Data_TOT <= "0001" & Data_Cvec; +--Rz <= raz; +SCLK <= s_SCLK; -with bp select - Data_int <= X"9555" when '1', - Data_C when others; +--with bp select +-- Data_int <= X"9555" when '1', +-- Data_C when others; end ar_CNA_TabloC; \ No newline at end of file diff --git a/lib/lpp/lpp_cna/Convertisseur_config.vhd b/lib/lpp/lpp_cna/Convertisseur_config.vhd --- a/lib/lpp/lpp_cna/Convertisseur_config.vhd +++ b/lib/lpp/lpp_cna/Convertisseur_config.vhd @@ -18,7 +18,7 @@ constant Tablo : Tbl (0 to 49):= (X"800" --===========================================================| --============= Fréquence de sérialisation ==================| --===========================================================| -constant Freq_serial : integer := 1_000_000; -constant nb_serial : integer := 40_000_000 / Freq_serial; +constant Freq_serial : integer := 5_000_000; +constant nb_serial : integer := 30_000_000 / Freq_serial; end; \ No newline at end of file diff --git a/lib/lpp/lpp_cna/GeneSYNC_flag.vhd b/lib/lpp/lpp_cna/GeneSYNC_flag.vhd deleted file mode 100644 --- a/lib/lpp/lpp_cna/GeneSYNC_flag.vhd +++ /dev/null @@ -1,94 +0,0 @@ --- GeneSYNC_flag.vhd -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity GeneSYNC_flag is - -port( - clk,raz : in std_logic; - flag_nw : in std_logic; - Sysclk : in std_logic; - OKAI_send : out std_logic; - SYNC : out std_logic -); - -end GeneSYNC_flag; - - -architecture ar_GeneSYNC_flag of GeneSYNC_flag is - -signal Sysclk_reg : std_logic; -signal flag_nw_reg : std_logic; -signal count : integer; - -type etat is (e0,e1,e2,eX); -signal ect : etat; - -begin - process (clk,raz) - begin - if(raz='0')then - SYNC <= '0'; - Sysclk_reg <= '0'; - flag_nw_reg <= '0'; - count <= 14; - OKAI_send <= '0'; - ect <= e0; - - elsif(clk' event and clk='1')then - Sysclk_reg <= Sysclk; - flag_nw_reg <= flag_nw; - - case ect is - when e0 => - if(flag_nw_reg='0' and flag_nw='1')then - ect <= e1; - else - count <= 14; - ect <= e0; - end if; - - - when e1 => - if(Sysclk_reg='1' and Sysclk='0')then - if(count=15)then - SYNC <= '1'; - count <= count+1; - ect <= e2; - elsif(count=16)then - count <= 0; - OKAI_send <= '1'; - ect <= eX; - else - count <= count+1; - OKAI_send <= '0'; - ect <= e1; - end if; - end if; - - - when e2 => - if(Sysclk_reg='0' and Sysclk='1')then - if(count=16)then - SYNC <= '0'; - ect <= e1; - end if; - end if; - - when eX => - if(Sysclk_reg='0' and Sysclk='1')then - if(count=15)then - OKAI_send <= '0'; - ect <= e0; - else - count <= count+1; - ect <= eX; - end if; - end if; - - end case; - end if; - - end process; -end ar_GeneSYNC_flag; \ No newline at end of file diff --git a/lib/lpp/lpp_cna/Gene_SYNC.vhd b/lib/lpp/lpp_cna/Gene_SYNC.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_cna/Gene_SYNC.vhd @@ -0,0 +1,53 @@ +-- Gene_SYNC.vhd +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity Gene_SYNC is + +port( + SCLK,raz : in std_logic; + enable : in std_logic; +-- Sysclk : in std_logic; + OKAI_send : out std_logic; + SYNC : out std_logic +); + +end Gene_SYNC; + + +architecture ar_Gene_SYNC of Gene_SYNC is + +--signal Sysclk_reg : std_logic; +signal count : integer; + + +begin + process (SCLK,raz) + begin + if(raz='0')then + SYNC <= '0'; +-- Sysclk_reg <= '0'; + count <= 14; + OKAI_send <= '0'; + + elsif(SCLK' event and SCLK='1')then + if(enable='1')then + +-- Sysclk_reg <= Sysclk; + if(count=15)then + SYNC <= '1'; + count <= count+1; + elsif(count=16)then + count <= 0; + SYNC <= '0'; + OKAI_send <= '1'; + else + count <= count+1; + OKAI_send <= '0'; + end if; + end if; + end if; + end process; + +end ar_Gene_SYNC; \ No newline at end of file diff --git a/lib/lpp/lpp_cna/Serialize.vhd b/lib/lpp/lpp_cna/Serialize.vhd --- a/lib/lpp/lpp_cna/Serialize.vhd +++ b/lib/lpp/lpp_cna/Serialize.vhd @@ -68,7 +68,7 @@ begin elsif(load='1')then vector_int <= vectin & '0'; N <= 0; - elsif(sclk'event and sclk='0')then + elsif(sclk'event and sclk='1')then if (CPT_ended='0') then vector_int <= vector_int(15 downto 0) & '0'; N <= N+1; diff --git a/lib/lpp/lpp_cna/lpp_cna.vhd b/lib/lpp/lpp_cna/lpp_cna.vhd --- a/lib/lpp/lpp_cna/lpp_cna.vhd +++ b/lib/lpp/lpp_cna/lpp_cna.vhd @@ -54,10 +54,10 @@ component Clock_Serie is end component; -component GeneSYNC_flag is +component Gene_SYNC is port( clk,raz : in std_logic; - flag_nw : in std_logic; + send : in std_logic; Sysclk : in std_logic; OKAI_send : out std_logic; SYNC : out std_logic);