@@ -0,0 +1,53 | |||
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1 | -- Gene_SYNC.vhd | |
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2 | library IEEE; | |
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3 | use IEEE.std_logic_1164.all; | |
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4 | use IEEE.numeric_std.all; | |
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5 | ||
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6 | entity Gene_SYNC is | |
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7 | ||
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8 | port( | |
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9 | SCLK,raz : in std_logic; | |
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10 | enable : in std_logic; | |
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11 | -- Sysclk : in std_logic; | |
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12 | OKAI_send : out std_logic; | |
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13 | SYNC : out std_logic | |
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14 | ); | |
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15 | ||
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16 | end Gene_SYNC; | |
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17 | ||
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18 | ||
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19 | architecture ar_Gene_SYNC of Gene_SYNC is | |
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20 | ||
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21 | --signal Sysclk_reg : std_logic; | |
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22 | signal count : integer; | |
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23 | ||
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24 | ||
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25 | begin | |
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26 | process (SCLK,raz) | |
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27 | begin | |
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28 | if(raz='0')then | |
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29 | SYNC <= '0'; | |
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30 | -- Sysclk_reg <= '0'; | |
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31 | count <= 14; | |
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32 | OKAI_send <= '0'; | |
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33 | ||
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34 | elsif(SCLK' event and SCLK='1')then | |
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35 | if(enable='1')then | |
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36 | ||
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37 | -- Sysclk_reg <= Sysclk; | |
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38 | if(count=15)then | |
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39 | SYNC <= '1'; | |
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40 | count <= count+1; | |
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41 | elsif(count=16)then | |
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42 | count <= 0; | |
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43 | SYNC <= '0'; | |
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44 | OKAI_send <= '1'; | |
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45 | else | |
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46 | count <= count+1; | |
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47 | OKAI_send <= '0'; | |
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48 | end if; | |
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49 | end if; | |
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50 | end if; | |
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51 | end process; | |
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52 | ||
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53 | end ar_Gene_SYNC; No newline at end of file |
@@ -38,13 +38,11 constant pconfig : apb_config_type := ( | |||
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38 | 38 | 0 => ahb_device_reg (VENDOR_LPP, LPP_CNA, 0, REVISION, 0), |
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39 | 39 | 1 => apb_iobar(paddr, pmask)); |
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40 | 40 | |
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41 |
signal |
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42 |
signal |
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43 | signal Rz : std_logic; | |
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44 | signal flag_sd : std_logic; | |
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41 | signal enable : std_logic; | |
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42 | signal flag_sd : std_logic; | |
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45 | 43 | |
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46 | 44 | type CNA_ctrlr_Reg is record |
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47 |
CNA_Cfg : std_logic_vector( |
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45 | CNA_Cfg : std_logic_vector(1 downto 0); | |
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48 | 46 | CNA_Data : std_logic_vector(15 downto 0); |
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49 | 47 | end record; |
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50 | 48 | |
@@ -53,14 +51,11 signal Rdata : std_logic_vector(31 d | |||
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53 | 51 | |
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54 | 52 | begin |
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55 | 53 | |
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56 |
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57 | flag_nw <= Rec.CNA_Cfg(1); | |
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58 | Rec.CNA_Cfg(2) <= flag_sd; | |
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59 | Rec.CNA_Cfg(3) <= Rz; | |
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54 | enable <= Rec.CNA_Cfg(0); | |
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55 | Rec.CNA_Cfg(1) <= flag_sd; | |
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60 | 56 | |
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61 | ||
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62 | 57 | CONVERTER : entity Work.CNA_TabloC |
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63 |
port map(clk,rst, |
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58 | port map(clk,rst,enable,Rec.CNA_Data,SYNC,SCLK,flag_sd,Data); | |
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64 | 59 | |
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65 | 60 | |
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66 | 61 | process(rst,clk) |
@@ -75,7 +70,7 Rec.CNA_Cfg(3) <= Rz; | |||
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75 | 70 | if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then |
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76 | 71 | case apbi.paddr(abits-1 downto 2) is |
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77 | 72 | when "000000" => |
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78 |
Rec.CNA_Cfg( |
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73 | Rec.CNA_Cfg(0) <= apbi.pwdata(0); | |
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79 | 74 | when "000001" => |
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80 | 75 | Rec.CNA_Data <= apbi.pwdata(15 downto 0); |
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81 | 76 | when others => |
@@ -87,8 +82,8 Rec.CNA_Cfg(3) <= Rz; | |||
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87 | 82 | if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then |
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88 | 83 | case apbi.paddr(abits-1 downto 2) is |
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89 | 84 | when "000000" => |
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90 |
Rdata(31 downto |
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91 |
Rdata( |
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85 | Rdata(31 downto 2) <= X"ABCDEF5" & "00"; | |
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86 | Rdata(1 downto 0) <= Rec.CNA_Cfg; | |
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92 | 87 | when "000001" => |
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93 | 88 | Rdata(31 downto 16) <= X"FD18"; |
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94 | 89 | Rdata(15 downto 0) <= Rec.CNA_Data; |
@@ -8,12 +8,12 entity CNA_TabloC is | |||
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8 | 8 | port( |
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9 | 9 | clock : in std_logic; |
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10 | 10 | rst : in std_logic; |
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11 |
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12 | bp : in std_logic; | |
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11 | enable : in std_logic; | |
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12 | --bp : in std_logic; | |
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13 | 13 | Data_C : in std_logic_vector(15 downto 0); |
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14 | 14 | SYNC : out std_logic; |
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15 | 15 | SCLK : out std_logic; |
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16 | Rz : out std_logic; | |
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16 | --Rz : out std_logic; | |
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17 | 17 | flag_sd : out std_logic; |
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18 | 18 | Data : out std_logic |
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19 | 19 | ); |
@@ -28,12 +28,11 port( A : in std_logic := 'U'; | |||
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28 | 28 | end component; |
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29 | 29 | |
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30 | 30 | signal clk : std_logic; |
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31 | --signal reset : std_logic; | |
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32 | 31 | |
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33 | 32 | signal raz : std_logic; |
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34 |
signal s |
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35 | signal Data_int : std_logic_vector(15 downto 0); | |
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33 | signal s_SCLK : std_logic; | |
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36 | 34 | signal OKAI_send : std_logic; |
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35 | --signal Data_int : std_logic_vector(15 downto 0); | |
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37 | 36 | |
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38 | 37 | begin |
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39 | 38 | |
@@ -47,25 +46,22 CLKINT_1 : CLKINT | |||
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47 | 46 | |
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48 | 47 | SystemCLK : entity work.Clock_Serie |
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49 | 48 | generic map (nb_serial) |
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50 |
port map (clk,raz,s |
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49 | port map (clk,raz,s_SCLK); | |
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51 | 50 | |
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52 | 51 | |
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53 |
Signal_sync : entity work.GeneSYNC |
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54 |
port map ( |
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52 | Signal_sync : entity work.Gene_SYNC | |
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53 | port map (s_SCLK,raz,enable,OKAI_send,SYNC); | |
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55 | 54 | |
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56 | 55 | |
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57 | 56 | Serial : entity work.serialize |
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58 |
port map (clk,raz,s |
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57 | port map (clk,raz,s_SCLK,Data_C,OKAI_send,flag_sd,Data); | |
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59 | 58 | |
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60 | 59 | |
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61 |
-- |
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62 | Rz <= raz; | |
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63 | SCLK <= not sys_clk; | |
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64 | --Data_Cvec <= std_logic_vector(to_unsigned(Data_C,12)); | |
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65 | --Data_TOT <= "0001" & Data_Cvec; | |
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60 | --Rz <= raz; | |
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61 | SCLK <= s_SCLK; | |
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66 | 62 | |
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67 | with bp select | |
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68 | Data_int <= X"9555" when '1', | |
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69 | Data_C when others; | |
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63 | --with bp select | |
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64 | -- Data_int <= X"9555" when '1', | |
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65 | -- Data_C when others; | |
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70 | 66 | |
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71 | 67 | end ar_CNA_TabloC; No newline at end of file |
@@ -18,7 +18,7 constant Tablo : Tbl (0 to 49):= (X"800" | |||
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18 | 18 | --===========================================================| |
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19 | 19 | --============= Fr�quence de s�rialisation ==================| |
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20 | 20 | --===========================================================| |
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21 |
constant Freq_serial : integer := |
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22 |
constant nb_serial : integer := |
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21 | constant Freq_serial : integer := 5_000_000; | |
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22 | constant nb_serial : integer := 30_000_000 / Freq_serial; | |
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23 | 23 | |
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24 | 24 | end; No newline at end of file |
@@ -68,7 +68,7 begin | |||
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68 | 68 | elsif(load='1')then |
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69 | 69 | vector_int <= vectin & '0'; |
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70 | 70 | N <= 0; |
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71 |
elsif(sclk'event and sclk=' |
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71 | elsif(sclk'event and sclk='1')then | |
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72 | 72 | if (CPT_ended='0') then |
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73 | 73 | vector_int <= vector_int(15 downto 0) & '0'; |
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74 | 74 | N <= N+1; |
@@ -54,10 +54,10 component Clock_Serie is | |||
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54 | 54 | end component; |
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55 | 55 | |
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56 | 56 | |
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57 |
component GeneSYNC |
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57 | component Gene_SYNC is | |
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58 | 58 | port( |
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59 | 59 | clk,raz : in std_logic; |
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60 |
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60 | send : in std_logic; | |
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61 | 61 | Sysclk : in std_logic; |
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62 | 62 | OKAI_send : out std_logic; |
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63 | 63 | SYNC : out std_logic); |
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1 | NO CONTENT: file was removed |
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