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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25 library lpp;
26 use lpp.lpp_fft.all;
27 use work.fft_components.all;
28
29 entity FFT is
30 generic(
31 Data_sz : integer := 16;
32 NbData : integer := 256);
33 port(
34 clkm : in std_logic;
35 rstn : in std_logic;
36 FifoIN_Empty : in std_logic_vector(4 downto 0);
37 FifoIN_Data : in std_logic_vector(79 downto 0);
38 FifoOUT_Full : in std_logic_vector(4 downto 0);
39 Read : out std_logic_vector(4 downto 0);
40 Write : out std_logic_vector(4 downto 0);
41 ReUse : out std_logic_vector(4 downto 0);
42 Data : out std_logic_vector(79 downto 0)
43 );
44 end entity;
45
46
47 architecture ar_FFT of FFT is
48
49 signal Drive_Write : std_logic;
50 signal Drive_DataRE : std_logic_vector(15 downto 0);
51 signal Drive_DataIM : std_logic_vector(15 downto 0);
52
53 signal Start : std_logic;
54 signal FFT_Load : std_logic;
55 signal FFT_Ready : std_logic;
56 signal FFT_Valid : std_logic;
57 signal FFT_DataRE : std_logic_vector(15 downto 0);
58 signal FFT_DataIM : std_logic_vector(15 downto 0);
59
60 signal Link_Read : std_logic;
61
62 begin
63
64 Start <= '0';
65
66 DRIVE : Driver_FFT
67 generic map(Data_sz,NbData)
68 port map(clkm,rstn,FFT_Load,FifoIN_Empty,FifoIN_Data,Drive_Write,Read,Drive_DataRE,Drive_DataIM);
69
70 FFT0 : CoreFFT
71 generic map(
72 LOGPTS => gLOGPTS,
73 LOGLOGPTS => gLOGLOGPTS,
74 WSIZE => gWSIZE,
75 TWIDTH => gTWIDTH,
76 DWIDTH => gDWIDTH,
77 TDWIDTH => gTDWIDTH,
78 RND_MODE => gRND_MODE,
79 SCALE_MODE => gSCALE_MODE,
80 PTS => gPTS,
81 HALFPTS => gHALFPTS,
82 inBuf_RWDLY => gInBuf_RWDLY)
83 port map(clkm,start,rstn,Drive_Write,Link_Read,Drive_DataIM,Drive_DataRE,FFT_Load,open,FFT_DataIM,FFT_DataRE,FFT_Valid,FFT_Ready);
84
85
86 LINK : Linker_FFT
87 generic map(Data_sz,NbData)
88 port map(clkm,rstn,FFT_Ready,FFT_Valid,FifoOUT_Full,FFT_DataRE,FFT_DataIM,Link_Read,Write,ReUse,Data);
89
90
91 end architecture; No newline at end of file
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25
26 --! Programme permetant de compl�menter ou non les entr�es de l'ALU, et ainsi de travailler avec des nombres n�gatifs
27
28 entity TwoComplementer is
29 generic(
30 Input_SZ : integer := 16);
31 port(
32 clk : in std_logic; --! Horloge du composant
33 reset : in std_logic; --! Reset general du composant
34 clr : in std_logic; --! Un reset sp�cifique au programme
35 TwoComp : in std_logic; --! Autorise l'utilisation du compl�ment
36 OP : in std_logic_vector(Input_SZ-1 downto 0); --! Op�rande d'entr�e
37 RES : out std_logic_vector(Input_SZ-1 downto 0) --! R�sultat, op�rande compl�ment� ou non
38 );
39 end TwoComplementer;
40
41
42 architecture ar_TwoComplementer of TwoComplementer is
43
44 signal REG : std_logic_vector(Input_SZ-1 downto 0);
45 signal OPinteger : integer;
46 signal RESCOMP : std_logic_vector(Input_SZ-1 downto 0);
47
48 begin
49
50 RES <= REG;
51 OPinteger <= to_integer(signed(OP));
52 RESCOMP <= std_logic_vector(to_signed(-OPinteger,Input_SZ));
53
54 process(clk,reset)
55 begin
56
57 if(reset='0')then
58 REG <= (others => '0');
59 elsif(clk'event and clk='1')then
60
61 if(clr='1')then
62 REG <= (others => '0');
63 elsif(TwoComp='1')then
64 REG <= RESCOMP;
65 else
66 REG <= OP;
67 end if;
68
69 end if;
70
71 end process;
72 end ar_TwoComplementer; No newline at end of file
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25 library lpp;
26 use lpp.lpp_demux.all;
27
28 entity Demultiplex is
29 generic(
30 Data_sz : integer range 1 to 32 := 16);
31 port(
32 clk : in std_logic;
33 rstn : in std_logic;
34
35 Read : in std_logic_vector(4 downto 0);
36
37 EmptyF0a : in std_logic_vector(4 downto 0);
38 EmptyF0b : in std_logic_vector(4 downto 0);
39 EmptyF1 : in std_logic_vector(4 downto 0);
40 EmptyF2 : in std_logic_vector(4 downto 0);
41
42 DataF0a : in std_logic_vector((5*Data_sz)-1 downto 0);
43 DataF0b : in std_logic_vector((5*Data_sz)-1 downto 0);
44 DataF1 : in std_logic_vector((5*Data_sz)-1 downto 0);
45 DataF2 : in std_logic_vector((5*Data_sz)-1 downto 0);
46
47 Read_DEMUX : out std_logic_vector(19 downto 0);
48 Empty : out std_logic_vector(4 downto 0);
49 Data : out std_logic_vector((5*Data_sz)-1 downto 0)
50 );
51 end entity;
52
53
54 architecture ar_Demultiplex of Demultiplex is
55
56 signal DataCpt : std_logic_vector(3 downto 0);
57
58 begin
59
60 FLG0 : WatchFlag
61 port map(clk,rstn,EmptyF0a,EmptyF0b,EmptyF1,EmptyF2,DataCpt);
62
63 DEM : DEMUX
64 generic map(Data_sz)
65 port map(clk,rstn,Read,DataCpt,EmptyF0a,EmptyF0b,EmptyF1,EmptyF2,DataF0a,DataF0b,DataF1,DataF2,Read_DEMUX,Empty,Data);
66
67 end architecture;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25 library lpp;
26 use lpp.lpp_matrix.all;
27
28 entity MatriceSpectrale is
29 generic(
30 Input_SZ : integer := 16;
31 Result_SZ : integer := 32);
32 port(
33 clkm : in std_logic;
34 rstn : in std_logic;
35
36 FifoIN_Full : in std_logic_vector(4 downto 0);
37 FifoOUT_Full : in std_logic_vector(1 downto 0);
38 Data_IN : in std_logic_vector(79 downto 0);
39 ACQ : in std_logic;
40 FlagError : out std_logic;
41 Pong : out std_logic;
42 Write : out std_logic_vector(1 downto 0);
43 Read : out std_logic_vector(4 downto 0);
44 Data_OUT : out std_logic_vector(63 downto 0)
45 );
46 end entity;
47
48
49 architecture ar_MatriceSpectrale of MatriceSpectrale is
50
51 signal Matrix_Write : std_logic;
52 signal Matrix_Read : std_logic_vector(1 downto 0);
53 signal Matrix_Result : std_logic_vector(31 downto 0);
54
55 signal TopSM_Start : std_logic;
56 signal TopSM_Statu : std_logic_vector(3 downto 0);
57 signal TopSM_Data1 : std_logic_vector(15 downto 0);
58 signal TopSM_Data2 : std_logic_vector(15 downto 0);
59
60 begin
61
62 TopSM : TopSpecMatrix
63 generic map (Input_SZ)
64 port map(clkm,rstn,Matrix_Write,Matrix_Read,FifoIN_Full,Data_IN,TopSM_Start,Read,TopSM_Statu,TopSM_Data1,TopSM_Data2);
65
66 SM : SpectralMatrix
67 generic map (Input_SZ,Result_SZ)
68 port map(clkm,rstn,TopSM_Start,TopSM_Data1,TopSM_Data2,TopSM_Statu,Matrix_Read,Matrix_Write,Matrix_Result);
69
70 DISP : Dispatch
71 generic map(Result_SZ)
72 port map(clkm,rstn,ACQ,Matrix_Result,Matrix_Write,FifoOUT_Full,Data_OUT,Write,Pong,FlagError);
73
74
75 end architecture;
76
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22
22
23 LIBRARY IEEE;
23 LIBRARY IEEE;
24 USE IEEE.numeric_std.ALL;
24 USE IEEE.numeric_std.ALL;
25 USE IEEE.std_logic_1164.ALL;
25 USE IEEE.std_logic_1164.ALL;
26
26
27 LIBRARY techmap;
27 LIBRARY techmap;
28 USE techmap.gencomp.ALL;
28 USE techmap.gencomp.ALL;
29
29
30 LIBRARY lpp;
30 LIBRARY lpp;
31 USE lpp.iir_filter.ALL;
31 USE lpp.iir_filter.ALL;
32 USE lpp.general_purpose.ALL;
32 USE lpp.general_purpose.ALL;
33
33
34 ENTITY IIR_CEL_CTRLR_v2 IS
34 ENTITY IIR_CEL_CTRLR_v2 IS
35 GENERIC (
35 GENERIC (
36 tech : INTEGER := apa3;
36 tech : INTEGER := apa3;
37 Mem_use : INTEGER := use_RAM;
37 Mem_use : INTEGER := use_RAM;
38 Sample_SZ : INTEGER := 18;
38 Sample_SZ : INTEGER := 18;
39 Coef_SZ : INTEGER := 9;
39 Coef_SZ : INTEGER := 9;
40 Coef_Nb : INTEGER := 25;
40 Coef_Nb : INTEGER := 25;
41 Coef_sel_SZ : INTEGER := 5;
41 Coef_sel_SZ : INTEGER := 5;
42 Cels_count : INTEGER := 5;
42 Cels_count : INTEGER := 5;
43 ChanelsCount : INTEGER := 8);
43 ChanelsCount : INTEGER := 8);
44 PORT (
44 PORT (
45 rstn : IN STD_LOGIC;
45 rstn : IN STD_LOGIC;
46 clk : IN STD_LOGIC;
46 clk : IN STD_LOGIC;
47
47
48 virg_pos : IN INTEGER;
48 virg_pos : IN INTEGER;
49 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
49 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
50
50
51 sample_in_val : IN STD_LOGIC;
51 sample_in_val : IN STD_LOGIC;
52 sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
52 sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
53
53
54 sample_out_val : OUT STD_LOGIC;
54 sample_out_val : OUT STD_LOGIC;
55 sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0));
55 sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0));
56 END IIR_CEL_CTRLR_v2;
56 END IIR_CEL_CTRLR_v2;
57
57
58 ARCHITECTURE ar_IIR_CEL_CTRLR_v2 OF IIR_CEL_CTRLR_v2 IS
58 ARCHITECTURE ar_IIR_CEL_CTRLR_v2 OF IIR_CEL_CTRLR_v2 IS
59
59
60 COMPONENT IIR_CEL_CTRLR_v2_DATAFLOW
60 COMPONENT IIR_CEL_CTRLR_v2_DATAFLOW
61 GENERIC (
61 GENERIC (
62 tech : INTEGER;
62 tech : INTEGER;
63 Mem_use : INTEGER;
63 Mem_use : INTEGER;
64 Sample_SZ : INTEGER;
64 Sample_SZ : INTEGER;
65 Coef_SZ : INTEGER;
65 Coef_SZ : INTEGER;
66 Coef_Nb : INTEGER;
66 Coef_Nb : INTEGER;
67 Coef_sel_SZ : INTEGER);
67 Coef_sel_SZ : INTEGER);
68 PORT (
68 PORT (
69 rstn : IN STD_LOGIC;
69 rstn : IN STD_LOGIC;
70 clk : IN STD_LOGIC;
70 clk : IN STD_LOGIC;
71 virg_pos : IN INTEGER;
71 virg_pos : IN INTEGER;
72 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
72 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
73 in_sel_src : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
73 in_sel_src : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
74 ram_sel_Wdata : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
74 ram_sel_Wdata : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
75 ram_write : IN STD_LOGIC;
75 ram_write : IN STD_LOGIC;
76 ram_read : IN STD_LOGIC;
76 ram_read : IN STD_LOGIC;
77 raddr_rst : IN STD_LOGIC;
77 raddr_rst : IN STD_LOGIC;
78 raddr_add1 : IN STD_LOGIC;
78 raddr_add1 : IN STD_LOGIC;
79 waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
79 waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
80 alu_sel_input : IN STD_LOGIC;
80 alu_sel_input : IN STD_LOGIC;
81 alu_sel_coeff : IN STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
81 alu_sel_coeff : IN STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
82 alu_ctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
82 alu_ctrl : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
83 alu_comp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
83 sample_in : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
84 sample_in : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
84 sample_out : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0));
85 sample_out : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0));
85 END COMPONENT;
86 END COMPONENT;
86
87
87 COMPONENT IIR_CEL_CTRLR_v2_CONTROL
88 COMPONENT IIR_CEL_CTRLR_v2_CONTROL
88 GENERIC (
89 GENERIC (
89 Coef_sel_SZ : INTEGER;
90 Coef_sel_SZ : INTEGER;
90 Cels_count : INTEGER;
91 Cels_count : INTEGER;
91 ChanelsCount : INTEGER);
92 ChanelsCount : INTEGER);
92 PORT (
93 PORT (
93 rstn : IN STD_LOGIC;
94 rstn : IN STD_LOGIC;
94 clk : IN STD_LOGIC;
95 clk : IN STD_LOGIC;
95 sample_in_val : IN STD_LOGIC;
96 sample_in_val : IN STD_LOGIC;
96 sample_in_rot : OUT STD_LOGIC;
97 sample_in_rot : OUT STD_LOGIC;
97 sample_out_val : OUT STD_LOGIC;
98 sample_out_val : OUT STD_LOGIC;
98 sample_out_rot : OUT STD_LOGIC;
99 sample_out_rot : OUT STD_LOGIC;
99 in_sel_src : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
100 in_sel_src : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
100 ram_sel_Wdata : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
101 ram_sel_Wdata : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
101 ram_write : OUT STD_LOGIC;
102 ram_write : OUT STD_LOGIC;
102 ram_read : OUT STD_LOGIC;
103 ram_read : OUT STD_LOGIC;
103 raddr_rst : OUT STD_LOGIC;
104 raddr_rst : OUT STD_LOGIC;
104 raddr_add1 : OUT STD_LOGIC;
105 raddr_add1 : OUT STD_LOGIC;
105 waddr_previous : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
106 waddr_previous : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
106 alu_sel_input : OUT STD_LOGIC;
107 alu_sel_input : OUT STD_LOGIC;
107 alu_sel_coeff : OUT STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
108 alu_sel_coeff : OUT STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
108 alu_ctrl : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
109 alu_ctrl : OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
109 END COMPONENT;
110 END COMPONENT;
110
111
111 SIGNAL in_sel_src : STD_LOGIC_VECTOR(1 DOWNTO 0);
112 SIGNAL in_sel_src : STD_LOGIC_VECTOR(1 DOWNTO 0);
112 SIGNAL ram_sel_Wdata : STD_LOGIC_VECTOR(1 DOWNTO 0);
113 SIGNAL ram_sel_Wdata : STD_LOGIC_VECTOR(1 DOWNTO 0);
113 SIGNAL ram_write : STD_LOGIC;
114 SIGNAL ram_write : STD_LOGIC;
114 SIGNAL ram_read : STD_LOGIC;
115 SIGNAL ram_read : STD_LOGIC;
115 SIGNAL raddr_rst : STD_LOGIC;
116 SIGNAL raddr_rst : STD_LOGIC;
116 SIGNAL raddr_add1 : STD_LOGIC;
117 SIGNAL raddr_add1 : STD_LOGIC;
117 SIGNAL waddr_previous : STD_LOGIC_VECTOR(1 DOWNTO 0);
118 SIGNAL waddr_previous : STD_LOGIC_VECTOR(1 DOWNTO 0);
118 SIGNAL alu_sel_input : STD_LOGIC;
119 SIGNAL alu_sel_input : STD_LOGIC;
119 SIGNAL alu_sel_coeff : STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
120 SIGNAL alu_sel_coeff : STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
120 SIGNAL alu_ctrl : STD_LOGIC_VECTOR(3 DOWNTO 0);
121 SIGNAL alu_ctrl : STD_LOGIC_VECTOR(2 DOWNTO 0);
121
122
122 SIGNAL sample_in_buf : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
123 SIGNAL sample_in_buf : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
123 SIGNAL sample_in_rotate : STD_LOGIC;
124 SIGNAL sample_in_rotate : STD_LOGIC;
124 SIGNAL sample_in_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
125 SIGNAL sample_in_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
125 SIGNAL sample_out_val_s : STD_LOGIC;
126 SIGNAL sample_out_val_s : STD_LOGIC;
126 SIGNAL sample_out_val_s2 : STD_LOGIC;
127 SIGNAL sample_out_val_s2 : STD_LOGIC;
127 SIGNAL sample_out_rot_s : STD_LOGIC;
128 SIGNAL sample_out_rot_s : STD_LOGIC;
128 SIGNAL sample_out_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
129 SIGNAL sample_out_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
129
130
130 SIGNAL sample_out_s2 : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
131 SIGNAL sample_out_s2 : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
131
132
132 BEGIN
133 BEGIN
133
134
134 IIR_CEL_CTRLR_v2_DATAFLOW_1 : IIR_CEL_CTRLR_v2_DATAFLOW
135 IIR_CEL_CTRLR_v2_DATAFLOW_1 : IIR_CEL_CTRLR_v2_DATAFLOW
135 GENERIC MAP (
136 GENERIC MAP (
136 tech => tech,
137 tech => tech,
137 Mem_use => Mem_use,
138 Mem_use => Mem_use,
138 Sample_SZ => Sample_SZ,
139 Sample_SZ => Sample_SZ,
139 Coef_SZ => Coef_SZ,
140 Coef_SZ => Coef_SZ,
140 Coef_Nb => Coef_Nb,
141 Coef_Nb => Coef_Nb,
141 Coef_sel_SZ => Coef_sel_SZ)
142 Coef_sel_SZ => Coef_sel_SZ)
142 PORT MAP (
143 PORT MAP (
143 rstn => rstn,
144 rstn => rstn,
144 clk => clk,
145 clk => clk,
145 virg_pos => virg_pos,
146 virg_pos => virg_pos,
146 coefs => coefs,
147 coefs => coefs,
147 --CTRL
148 --CTRL
148 in_sel_src => in_sel_src,
149 in_sel_src => in_sel_src,
149 ram_sel_Wdata => ram_sel_Wdata,
150 ram_sel_Wdata => ram_sel_Wdata,
150 ram_write => ram_write,
151 ram_write => ram_write,
151 ram_read => ram_read,
152 ram_read => ram_read,
152 raddr_rst => raddr_rst,
153 raddr_rst => raddr_rst,
153 raddr_add1 => raddr_add1,
154 raddr_add1 => raddr_add1,
154 waddr_previous => waddr_previous,
155 waddr_previous => waddr_previous,
155 alu_sel_input => alu_sel_input,
156 alu_sel_input => alu_sel_input,
156 alu_sel_coeff => alu_sel_coeff,
157 alu_sel_coeff => alu_sel_coeff,
157 alu_ctrl => alu_ctrl,
158 alu_ctrl => alu_ctrl,
159 alu_comp => "00",
158 --DATA
160 --DATA
159 sample_in => sample_in_s,
161 sample_in => sample_in_s,
160 sample_out => sample_out_s);
162 sample_out => sample_out_s);
161
163
162
164
163 IIR_CEL_CTRLR_v2_CONTROL_1 : IIR_CEL_CTRLR_v2_CONTROL
165 IIR_CEL_CTRLR_v2_CONTROL_1 : IIR_CEL_CTRLR_v2_CONTROL
164 GENERIC MAP (
166 GENERIC MAP (
165 Coef_sel_SZ => Coef_sel_SZ,
167 Coef_sel_SZ => Coef_sel_SZ,
166 Cels_count => Cels_count,
168 Cels_count => Cels_count,
167 ChanelsCount => ChanelsCount)
169 ChanelsCount => ChanelsCount)
168 PORT MAP (
170 PORT MAP (
169 rstn => rstn,
171 rstn => rstn,
170 clk => clk,
172 clk => clk,
171 sample_in_val => sample_in_val,
173 sample_in_val => sample_in_val,
172 sample_in_rot => sample_in_rotate,
174 sample_in_rot => sample_in_rotate,
173 sample_out_val => sample_out_val_s,
175 sample_out_val => sample_out_val_s,
174 sample_out_rot => sample_out_rot_s,
176 sample_out_rot => sample_out_rot_s,
175
177
176 in_sel_src => in_sel_src,
178 in_sel_src => in_sel_src,
177 ram_sel_Wdata => ram_sel_Wdata,
179 ram_sel_Wdata => ram_sel_Wdata,
178 ram_write => ram_write,
180 ram_write => ram_write,
179 ram_read => ram_read,
181 ram_read => ram_read,
180 raddr_rst => raddr_rst,
182 raddr_rst => raddr_rst,
181 raddr_add1 => raddr_add1,
183 raddr_add1 => raddr_add1,
182 waddr_previous => waddr_previous,
184 waddr_previous => waddr_previous,
183 alu_sel_input => alu_sel_input,
185 alu_sel_input => alu_sel_input,
184 alu_sel_coeff => alu_sel_coeff,
186 alu_sel_coeff => alu_sel_coeff,
185 alu_ctrl => alu_ctrl);
187 alu_ctrl => alu_ctrl);
186
188
187 -----------------------------------------------------------------------------
189 -----------------------------------------------------------------------------
188 -- SAMPLE IN
190 -- SAMPLE IN
189 -----------------------------------------------------------------------------
191 -----------------------------------------------------------------------------
190 loop_all_sample : FOR J IN Sample_SZ-1 DOWNTO 0 GENERATE
192 loop_all_sample : FOR J IN Sample_SZ-1 DOWNTO 0 GENERATE
191
193
192 loop_all_chanel : FOR I IN ChanelsCount-1 DOWNTO 0 GENERATE
194 loop_all_chanel : FOR I IN ChanelsCount-1 DOWNTO 0 GENERATE
193 PROCESS (clk, rstn)
195 PROCESS (clk, rstn)
194 BEGIN -- PROCESS
196 BEGIN -- PROCESS
195 IF rstn = '0' THEN -- asynchronous reset (active low)
197 IF rstn = '0' THEN -- asynchronous reset (active low)
196 sample_in_buf(I, J) <= '0';
198 sample_in_buf(I, J) <= '0';
197 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
199 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
198 IF sample_in_val = '1' THEN
200 IF sample_in_val = '1' THEN
199 sample_in_buf(I, J) <= sample_in(I, J);
201 sample_in_buf(I, J) <= sample_in(I, J);
200 ELSIF sample_in_rotate = '1' THEN
202 ELSIF sample_in_rotate = '1' THEN
201 sample_in_buf(I, J) <= sample_in_buf((I+1) MOD ChanelsCount, J);
203 sample_in_buf(I, J) <= sample_in_buf((I+1) MOD ChanelsCount, J);
202 END IF;
204 END IF;
203 END IF;
205 END IF;
204 END PROCESS;
206 END PROCESS;
205 END GENERATE loop_all_chanel;
207 END GENERATE loop_all_chanel;
206
208
207 sample_in_s(J) <= sample_in(0, J) WHEN sample_in_val = '1' ELSE sample_in_buf(0, J);
209 sample_in_s(J) <= sample_in(0, J) WHEN sample_in_val = '1' ELSE sample_in_buf(0, J);
208
210
209 END GENERATE loop_all_sample;
211 END GENERATE loop_all_sample;
210
212
211 -----------------------------------------------------------------------------
213 -----------------------------------------------------------------------------
212 -- SAMPLE OUT
214 -- SAMPLE OUT
213 -----------------------------------------------------------------------------
215 -----------------------------------------------------------------------------
214 PROCESS (clk, rstn)
216 PROCESS (clk, rstn)
215 BEGIN -- PROCESS
217 BEGIN -- PROCESS
216 IF rstn = '0' THEN -- asynchronous reset (active low)
218 IF rstn = '0' THEN -- asynchronous reset (active low)
217 sample_out_val <= '0';
219 sample_out_val <= '0';
218 sample_out_val_s2 <= '0';
220 sample_out_val_s2 <= '0';
219 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
221 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
220 sample_out_val <= sample_out_val_s2;
222 sample_out_val <= sample_out_val_s2;
221 sample_out_val_s2 <= sample_out_val_s;
223 sample_out_val_s2 <= sample_out_val_s;
222 END IF;
224 END IF;
223 END PROCESS;
225 END PROCESS;
224
226
225 chanel_HIGH : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE
227 chanel_HIGH : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE
226 PROCESS (clk, rstn)
228 PROCESS (clk, rstn)
227 BEGIN -- PROCESS
229 BEGIN -- PROCESS
228 IF rstn = '0' THEN -- asynchronous reset (active low)
230 IF rstn = '0' THEN -- asynchronous reset (active low)
229 sample_out_s2(ChanelsCount-1, I) <= '0';
231 sample_out_s2(ChanelsCount-1, I) <= '0';
230 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
232 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
231 IF sample_out_rot_s = '1' THEN
233 IF sample_out_rot_s = '1' THEN
232 sample_out_s2(ChanelsCount-1, I) <= sample_out_s(I);
234 sample_out_s2(ChanelsCount-1, I) <= sample_out_s(I);
233 END IF;
235 END IF;
234 END IF;
236 END IF;
235 END PROCESS;
237 END PROCESS;
236 END GENERATE chanel_HIGH;
238 END GENERATE chanel_HIGH;
237
239
238 chanel_more : IF ChanelsCount > 1 GENERATE
240 chanel_more : IF ChanelsCount > 1 GENERATE
239 all_chanel : FOR J IN ChanelsCount-1 DOWNTO 1 GENERATE
241 all_chanel : FOR J IN ChanelsCount-1 DOWNTO 1 GENERATE
240 all_bit : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE
242 all_bit : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE
241 PROCESS (clk, rstn)
243 PROCESS (clk, rstn)
242 BEGIN -- PROCESS
244 BEGIN -- PROCESS
243 IF rstn = '0' THEN -- asynchronous reset (active low)
245 IF rstn = '0' THEN -- asynchronous reset (active low)
244 sample_out_s2(J-1, I) <= '0';
246 sample_out_s2(J-1, I) <= '0';
245 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
247 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
246 IF sample_out_rot_s = '1' THEN
248 IF sample_out_rot_s = '1' THEN
247 sample_out_s2(J-1, I) <= sample_out_s2(J, I);
249 sample_out_s2(J-1, I) <= sample_out_s2(J, I);
248 END IF;
250 END IF;
249 END IF;
251 END IF;
250 END PROCESS;
252 END PROCESS;
251 END GENERATE all_bit;
253 END GENERATE all_bit;
252 END GENERATE all_chanel;
254 END GENERATE all_chanel;
253 END GENERATE chanel_more;
255 END GENERATE chanel_more;
254
256
255 sample_out <= sample_out_s2;
257 sample_out <= sample_out_s2;
256 END ar_IIR_CEL_CTRLR_v2;
258 END ar_IIR_CEL_CTRLR_v2;
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@@ -1,313 +1,313
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more Cdetails.
13 -- GNU General Public License for more Cdetails.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22
22
23 LIBRARY IEEE;
23 LIBRARY IEEE;
24 USE IEEE.numeric_std.ALL;
24 USE IEEE.numeric_std.ALL;
25 USE IEEE.std_logic_1164.ALL;
25 USE IEEE.std_logic_1164.ALL;
26 LIBRARY lpp;
26 LIBRARY lpp;
27 USE lpp.iir_filter.ALL;
27 USE lpp.iir_filter.ALL;
28 USE lpp.general_purpose.ALL;
28 USE lpp.general_purpose.ALL;
29
29
30 ENTITY IIR_CEL_CTRLR_v2_CONTROL IS
30 ENTITY IIR_CEL_CTRLR_v2_CONTROL IS
31 GENERIC (
31 GENERIC (
32 Coef_sel_SZ : INTEGER;
32 Coef_sel_SZ : INTEGER;
33 Cels_count : INTEGER := 5;
33 Cels_count : INTEGER := 5;
34 ChanelsCount : INTEGER := 1);
34 ChanelsCount : INTEGER := 1);
35 PORT (
35 PORT (
36 rstn : IN STD_LOGIC;
36 rstn : IN STD_LOGIC;
37 clk : IN STD_LOGIC;
37 clk : IN STD_LOGIC;
38
38
39 sample_in_val : IN STD_LOGIC;
39 sample_in_val : IN STD_LOGIC;
40 sample_in_rot : OUT STD_LOGIC;
40 sample_in_rot : OUT STD_LOGIC;
41 sample_out_val : OUT STD_LOGIC;
41 sample_out_val : OUT STD_LOGIC;
42 sample_out_rot : OUT STD_LOGIC;
42 sample_out_rot : OUT STD_LOGIC;
43
43
44 in_sel_src : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
44 in_sel_src : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
45 ram_sel_Wdata : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
45 ram_sel_Wdata : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
46 ram_write : OUT STD_LOGIC;
46 ram_write : OUT STD_LOGIC;
47 ram_read : OUT STD_LOGIC;
47 ram_read : OUT STD_LOGIC;
48 raddr_rst : OUT STD_LOGIC;
48 raddr_rst : OUT STD_LOGIC;
49 raddr_add1 : OUT STD_LOGIC;
49 raddr_add1 : OUT STD_LOGIC;
50 waddr_previous : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
50 waddr_previous : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
51 alu_sel_input : OUT STD_LOGIC;
51 alu_sel_input : OUT STD_LOGIC;
52 alu_sel_coeff : OUT STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
52 alu_sel_coeff : OUT STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
53 alu_ctrl : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
53 alu_ctrl : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
54 );
54 );
55 END IIR_CEL_CTRLR_v2_CONTROL;
55 END IIR_CEL_CTRLR_v2_CONTROL;
56
56
57 ARCHITECTURE ar_IIR_CEL_CTRLR_v2_CONTROL OF IIR_CEL_CTRLR_v2_CONTROL IS
57 ARCHITECTURE ar_IIR_CEL_CTRLR_v2_CONTROL OF IIR_CEL_CTRLR_v2_CONTROL IS
58
58
59 TYPE fsmIIR_CEL_T IS (waiting,
59 TYPE fsmIIR_CEL_T IS (waiting,
60 first_read,
60 first_read,
61 compute_b0,
61 compute_b0,
62 compute_b1,
62 compute_b1,
63 compute_b2,
63 compute_b2,
64 compute_a1,
64 compute_a1,
65 compute_a2,
65 compute_a2,
66 LAST_CEL,
66 LAST_CEL,
67 wait_valid_last_output,
67 wait_valid_last_output,
68 wait_valid_last_output_2);
68 wait_valid_last_output_2);
69 SIGNAL IIR_CEL_STATE : fsmIIR_CEL_T;
69 SIGNAL IIR_CEL_STATE : fsmIIR_CEL_T;
70
70
71 SIGNAL alu_selected_coeff : INTEGER;
71 SIGNAL alu_selected_coeff : INTEGER;
72 SIGNAL Chanel_ongoing : INTEGER;
72 SIGNAL Chanel_ongoing : INTEGER;
73 SIGNAL Cel_ongoing : INTEGER;
73 SIGNAL Cel_ongoing : INTEGER;
74
74
75 BEGIN
75 BEGIN
76
76
77 alu_sel_coeff <= STD_LOGIC_VECTOR(to_unsigned(alu_selected_coeff, Coef_sel_SZ));
77 alu_sel_coeff <= STD_LOGIC_VECTOR(to_unsigned(alu_selected_coeff, Coef_sel_SZ));
78
78
79 PROCESS (clk, rstn)
79 PROCESS (clk, rstn)
80 BEGIN -- PROCESS
80 BEGIN -- PROCESS
81 IF rstn = '0' THEN -- asynchronous reset (active low)
81 IF rstn = '0' THEN -- asynchronous reset (active low)
82 --REG -------------------------------------------------------------------
82 --REG -------------------------------------------------------------------
83 in_sel_src <= (OTHERS => '0'); --
83 in_sel_src <= (OTHERS => '0'); --
84 --RAM_WRitE -------------------------------------------------------------
84 --RAM_WRitE -------------------------------------------------------------
85 ram_sel_Wdata <= "00"; --
85 ram_sel_Wdata <= "00"; --
86 ram_write <= '0'; --
86 ram_write <= '0'; --
87 waddr_previous <= "00"; --
87 waddr_previous <= "00"; --
88 --RAM_READ --------------------------------------------------------------
88 --RAM_READ --------------------------------------------------------------
89 ram_read <= '0'; --
89 ram_read <= '0'; --
90 raddr_rst <= '0'; --
90 raddr_rst <= '0'; --
91 raddr_add1 <= '0'; --
91 raddr_add1 <= '0'; --
92 --ALU -------------------------------------------------------------------
92 --ALU -------------------------------------------------------------------
93 alu_selected_coeff <= 0; --
93 alu_selected_coeff <= 0; --
94 alu_sel_input <= '0'; --
94 alu_sel_input <= '0'; --
95 alu_ctrl <= (OTHERS => '0'); --
95 alu_ctrl <= ctrl_IDLE; --
96 --OUT
96 --OUT
97 sample_out_val <= '0'; --
97 sample_out_val <= '0'; --
98 sample_out_rot <= '0'; --
98 sample_out_rot <= '0'; --
99
99
100 Chanel_ongoing <= 0; --
100 Chanel_ongoing <= 0; --
101 Cel_ongoing <= 0; --
101 Cel_ongoing <= 0; --
102 sample_in_rot <= '0';
102 sample_in_rot <= '0';
103
103
104 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
104 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
105
105
106 CASE IIR_CEL_STATE IS
106 CASE IIR_CEL_STATE IS
107 WHEN waiting =>
107 WHEN waiting =>
108 sample_out_rot <= '0';
108 sample_out_rot <= '0';
109 sample_in_rot <= '0';
109 sample_in_rot <= '0';
110 sample_out_val <= '0';
110 sample_out_val <= '0';
111 alu_ctrl <= "0100";
111 alu_ctrl <= ctrl_CLRMAC;
112 alu_selected_coeff <= 0;
112 alu_selected_coeff <= 0;
113 in_sel_src <= "01";
113 in_sel_src <= "01";
114 ram_read <= '0';
114 ram_read <= '0';
115 ram_sel_Wdata <= "00";
115 ram_sel_Wdata <= "00";
116 ram_write <= '0';
116 ram_write <= '0';
117 waddr_previous <= "00";
117 waddr_previous <= "00";
118 IF sample_in_val = '1' THEN
118 IF sample_in_val = '1' THEN
119 raddr_rst <= '0';
119 raddr_rst <= '0';
120 alu_sel_input <= '1';
120 alu_sel_input <= '1';
121 ram_read <= '1';
121 ram_read <= '1';
122 raddr_add1 <= '1';
122 raddr_add1 <= '1';
123 IIR_CEL_STATE <= first_read;
123 IIR_CEL_STATE <= first_read;
124 Chanel_ongoing <= Chanel_ongoing + 1;
124 Chanel_ongoing <= Chanel_ongoing + 1;
125 Cel_ongoing <= 1;
125 Cel_ongoing <= 1;
126 ELSE
126 ELSE
127 raddr_add1 <= '0';
127 raddr_add1 <= '0';
128 raddr_rst <= '1';
128 raddr_rst <= '1';
129 Chanel_ongoing <= 0;
129 Chanel_ongoing <= 0;
130 Cel_ongoing <= 0;
130 Cel_ongoing <= 0;
131 END IF;
131 END IF;
132
132
133 WHEN first_read =>
133 WHEN first_read =>
134 IIR_CEL_STATE <= compute_b2;
134 IIR_CEL_STATE <= compute_b2;
135 ram_read <= '1';
135 ram_read <= '1';
136 raddr_add1 <= '1';
136 raddr_add1 <= '1';
137 alu_ctrl <= "0010";
137 alu_ctrl <= ctrl_MULT;
138 alu_sel_input <= '1';
138 alu_sel_input <= '1';
139 in_sel_src <= "01";
139 in_sel_src <= "01";
140
140
141
141
142 WHEN compute_b2 =>
142 WHEN compute_b2 =>
143 sample_out_rot <= '0';
143 sample_out_rot <= '0';
144
144
145 sample_in_rot <= '0';
145 sample_in_rot <= '0';
146 sample_out_val <= '0';
146 sample_out_val <= '0';
147
147
148 alu_sel_input <= '1';
148 alu_sel_input <= '1';
149 --
149 --
150 ram_sel_Wdata <= "10";
150 ram_sel_Wdata <= "10";
151 ram_write <= '1';
151 ram_write <= '1';
152 waddr_previous <= "10";
152 waddr_previous <= "10";
153 --
153 --
154 ram_read <= '1';
154 ram_read <= '1';
155 raddr_rst <= '0';
155 raddr_rst <= '0';
156 raddr_add1 <= '0';
156 raddr_add1 <= '0';
157 IF Cel_ongoing = 1 THEN
157 IF Cel_ongoing = 1 THEN
158 in_sel_src <= "00";
158 in_sel_src <= "00";
159 ELSE
159 ELSE
160 in_sel_src <= "11";
160 in_sel_src <= "11";
161 END IF;
161 END IF;
162 alu_selected_coeff <= alu_selected_coeff+1;
162 alu_selected_coeff <= alu_selected_coeff+1;
163 alu_ctrl <= "0001";
163 alu_ctrl <= ctrl_MAC;
164 IIR_CEL_STATE <= compute_b1;
164 IIR_CEL_STATE <= compute_b1;
165
165
166 WHEN compute_b1 =>
166 WHEN compute_b1 =>
167 sample_in_rot <= '0';
167 sample_in_rot <= '0';
168 alu_sel_input <= '0';
168 alu_sel_input <= '0';
169 --
169 --
170 ram_sel_Wdata <= "00";
170 ram_sel_Wdata <= "00";
171 ram_write <= '1';
171 ram_write <= '1';
172 waddr_previous <= "01";
172 waddr_previous <= "01";
173 --
173 --
174 ram_read <= '1';
174 ram_read <= '1';
175 raddr_rst <= '0';
175 raddr_rst <= '0';
176 raddr_add1 <= '1';
176 raddr_add1 <= '1';
177 sample_out_rot <= '0';
177 sample_out_rot <= '0';
178 IF Cel_ongoing = 1 THEN
178 IF Cel_ongoing = 1 THEN
179 in_sel_src <= "10";
179 in_sel_src <= "10";
180 sample_out_val <= '0';
180 sample_out_val <= '0';
181 ELSE
181 ELSE
182 sample_out_val <= '0';
182 sample_out_val <= '0';
183 in_sel_src <= "00";
183 in_sel_src <= "00";
184 END IF;
184 END IF;
185 alu_selected_coeff <= alu_selected_coeff+1;
185 alu_selected_coeff <= alu_selected_coeff+1;
186 alu_ctrl <= "0001";
186 alu_ctrl <= ctrl_MAC;
187 IIR_CEL_STATE <= compute_b0;
187 IIR_CEL_STATE <= compute_b0;
188
188
189 WHEN compute_b0 =>
189 WHEN compute_b0 =>
190 sample_out_rot <= '0';
190 sample_out_rot <= '0';
191 sample_out_val <= '0';
191 sample_out_val <= '0';
192 sample_in_rot <= '0';
192 sample_in_rot <= '0';
193 alu_sel_input <= '1';
193 alu_sel_input <= '1';
194 ram_sel_Wdata <= "00";
194 ram_sel_Wdata <= "00";
195 ram_write <= '0';
195 ram_write <= '0';
196 waddr_previous <= "01";
196 waddr_previous <= "01";
197 ram_read <= '1';
197 ram_read <= '1';
198 raddr_rst <= '0';
198 raddr_rst <= '0';
199 raddr_add1 <= '0';
199 raddr_add1 <= '0';
200 in_sel_src <= "10";
200 in_sel_src <= "10";
201 alu_selected_coeff <= alu_selected_coeff+1;
201 alu_selected_coeff <= alu_selected_coeff+1;
202 alu_ctrl <= "0001";
202 alu_ctrl <= ctrl_MAC;
203 IIR_CEL_STATE <= compute_a2;
203 IIR_CEL_STATE <= compute_a2;
204 IF Cel_ongoing = Cels_count THEN
204 IF Cel_ongoing = Cels_count THEN
205 sample_in_rot <= '1';
205 sample_in_rot <= '1';
206 ELSE
206 ELSE
207 sample_in_rot <= '0';
207 sample_in_rot <= '0';
208 END IF;
208 END IF;
209
209
210 WHEN compute_a2 =>
210 WHEN compute_a2 =>
211 sample_out_val <= '0';
211 sample_out_val <= '0';
212 sample_out_rot <= '0';
212 sample_out_rot <= '0';
213 alu_sel_input <= '1';
213 alu_sel_input <= '1';
214 ram_sel_Wdata <= "00";
214 ram_sel_Wdata <= "00";
215 ram_write <= '0';
215 ram_write <= '0';
216 waddr_previous <= "01";
216 waddr_previous <= "01";
217 ram_read <= '1';
217 ram_read <= '1';
218 raddr_rst <= '0';
218 raddr_rst <= '0';
219 IF Cel_ongoing = Cels_count THEN
219 IF Cel_ongoing = Cels_count THEN
220 raddr_add1 <= '1';
220 raddr_add1 <= '1';
221 ELSE
221 ELSE
222 raddr_add1 <= '0';
222 raddr_add1 <= '0';
223 END IF;
223 END IF;
224 in_sel_src <= "00";
224 in_sel_src <= "00";
225 alu_selected_coeff <= alu_selected_coeff+1;
225 alu_selected_coeff <= alu_selected_coeff+1;
226 alu_ctrl <= "0001";
226 alu_ctrl <= ctrl_MAC;
227 IIR_CEL_STATE <= compute_a1;
227 IIR_CEL_STATE <= compute_a1;
228 sample_in_rot <= '0';
228 sample_in_rot <= '0';
229
229
230 WHEN compute_a1 =>
230 WHEN compute_a1 =>
231 sample_out_val <= '0';
231 sample_out_val <= '0';
232 sample_out_rot <= '0';
232 sample_out_rot <= '0';
233 alu_sel_input <= '0';
233 alu_sel_input <= '0';
234 ram_sel_Wdata <= "00";
234 ram_sel_Wdata <= "00";
235 ram_write <= '0';
235 ram_write <= '0';
236 waddr_previous <= "01";
236 waddr_previous <= "01";
237 ram_read <= '1';
237 ram_read <= '1';
238 raddr_rst <= '0';
238 raddr_rst <= '0';
239 alu_ctrl <= "0010";
239 alu_ctrl <= ctrl_MULT;
240 sample_in_rot <= '0';
240 sample_in_rot <= '0';
241 IF Cel_ongoing = Cels_count THEN
241 IF Cel_ongoing = Cels_count THEN
242 alu_selected_coeff <= 0;
242 alu_selected_coeff <= 0;
243
243
244 ram_sel_Wdata <= "10";
244 ram_sel_Wdata <= "10";
245 raddr_add1 <= '1';
245 raddr_add1 <= '1';
246 ram_write <= '1';
246 ram_write <= '1';
247 waddr_previous <= "10";
247 waddr_previous <= "10";
248
248
249 IF Chanel_ongoing = ChanelsCount THEN
249 IF Chanel_ongoing = ChanelsCount THEN
250 IIR_CEL_STATE <= wait_valid_last_output;
250 IIR_CEL_STATE <= wait_valid_last_output;
251 ELSE
251 ELSE
252 Chanel_ongoing <= Chanel_ongoing + 1;
252 Chanel_ongoing <= Chanel_ongoing + 1;
253 Cel_ongoing <= 1;
253 Cel_ongoing <= 1;
254 IIR_CEL_STATE <= LAST_CEL;
254 IIR_CEL_STATE <= LAST_CEL;
255 in_sel_src <= "01";
255 in_sel_src <= "01";
256 END IF;
256 END IF;
257 ELSE
257 ELSE
258 raddr_add1 <= '1';
258 raddr_add1 <= '1';
259 alu_selected_coeff <= alu_selected_coeff+1;
259 alu_selected_coeff <= alu_selected_coeff+1;
260 Cel_ongoing <= Cel_ongoing+1;
260 Cel_ongoing <= Cel_ongoing+1;
261 IIR_CEL_STATE <= compute_b2;
261 IIR_CEL_STATE <= compute_b2;
262 END IF;
262 END IF;
263
263
264 WHEN LAST_CEL =>
264 WHEN LAST_CEL =>
265 alu_sel_input <= '1';
265 alu_sel_input <= '1';
266 IIR_CEL_STATE <= compute_b2;
266 IIR_CEL_STATE <= compute_b2;
267 raddr_add1 <= '1';
267 raddr_add1 <= '1';
268 ram_sel_Wdata <= "01";
268 ram_sel_Wdata <= "01";
269 ram_write <= '1';
269 ram_write <= '1';
270 waddr_previous <= "10";
270 waddr_previous <= "10";
271 sample_out_rot <= '1';
271 sample_out_rot <= '1';
272
272
273
273
274 WHEN wait_valid_last_output =>
274 WHEN wait_valid_last_output =>
275 IIR_CEL_STATE <= wait_valid_last_output_2;
275 IIR_CEL_STATE <= wait_valid_last_output_2;
276 sample_in_rot <= '0';
276 sample_in_rot <= '0';
277 alu_ctrl <= "0000";
277 alu_ctrl <= ctrl_IDLE;
278 alu_selected_coeff <= 0;
278 alu_selected_coeff <= 0;
279 in_sel_src <= "01";
279 in_sel_src <= "01";
280 ram_read <= '0';
280 ram_read <= '0';
281 raddr_rst <= '1';
281 raddr_rst <= '1';
282 raddr_add1 <= '1';
282 raddr_add1 <= '1';
283 ram_sel_Wdata <= "01";
283 ram_sel_Wdata <= "01";
284 ram_write <= '1';
284 ram_write <= '1';
285 waddr_previous <= "10";
285 waddr_previous <= "10";
286 Chanel_ongoing <= 0;
286 Chanel_ongoing <= 0;
287 Cel_ongoing <= 0;
287 Cel_ongoing <= 0;
288 sample_out_val <= '0';
288 sample_out_val <= '0';
289 sample_out_rot <= '1';
289 sample_out_rot <= '1';
290
290
291 WHEN wait_valid_last_output_2 =>
291 WHEN wait_valid_last_output_2 =>
292 IIR_CEL_STATE <= waiting;
292 IIR_CEL_STATE <= waiting;
293 sample_in_rot <= '0';
293 sample_in_rot <= '0';
294 alu_ctrl <= "0000";
294 alu_ctrl <= ctrl_IDLE;
295 alu_selected_coeff <= 0;
295 alu_selected_coeff <= 0;
296 in_sel_src <= "01";
296 in_sel_src <= "01";
297 ram_read <= '0';
297 ram_read <= '0';
298 raddr_rst <= '1';
298 raddr_rst <= '1';
299 raddr_add1 <= '1';
299 raddr_add1 <= '1';
300 ram_sel_Wdata <= "10";
300 ram_sel_Wdata <= "10";
301 ram_write <= '1';
301 ram_write <= '1';
302 waddr_previous <= "10";
302 waddr_previous <= "10";
303 Chanel_ongoing <= 0;
303 Chanel_ongoing <= 0;
304 Cel_ongoing <= 0;
304 Cel_ongoing <= 0;
305 sample_out_val <= '1';
305 sample_out_val <= '1';
306 sample_out_rot <= '0';
306 sample_out_rot <= '0';
307 WHEN OTHERS => NULL;
307 WHEN OTHERS => NULL;
308 END CASE;
308 END CASE;
309
309
310 END IF;
310 END IF;
311 END PROCESS;
311 END PROCESS;
312
312
313 END ar_IIR_CEL_CTRLR_v2_CONTROL;
313 END ar_IIR_CEL_CTRLR_v2_CONTROL; No newline at end of file
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY lpp;
25 LIBRARY lpp;
26 USE lpp.iir_filter.ALL;
26 USE lpp.iir_filter.ALL;
27 USE lpp.general_purpose.ALL;
27 USE lpp.general_purpose.ALL;
28
28
29
29
30
30
31 ENTITY IIR_CEL_CTRLR_v2_DATAFLOW IS
31 ENTITY IIR_CEL_CTRLR_v2_DATAFLOW IS
32 GENERIC(
32 GENERIC(
33 tech : INTEGER := 0;
33 tech : INTEGER := 0;
34 Mem_use : INTEGER := use_RAM;
34 Mem_use : INTEGER := use_RAM;
35 Sample_SZ : INTEGER := 16;
35 Sample_SZ : INTEGER := 16;
36 Coef_SZ : INTEGER := 9;
36 Coef_SZ : INTEGER := 9;
37 Coef_Nb : INTEGER := 30;
37 Coef_Nb : INTEGER := 30;
38 Coef_sel_SZ : INTEGER := 5
38 Coef_sel_SZ : INTEGER := 5
39 );
39 );
40 PORT(
40 PORT(
41 rstn : IN STD_LOGIC;
41 rstn : IN STD_LOGIC;
42 clk : IN STD_LOGIC;
42 clk : IN STD_LOGIC;
43 -- PARAMETER
43 -- PARAMETER
44 virg_pos : IN INTEGER;
44 virg_pos : IN INTEGER;
45 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
45 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
46 -- CONTROL
46 -- CONTROL
47 in_sel_src : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
47 in_sel_src : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
48 --
48 --
49 ram_sel_Wdata : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
49 ram_sel_Wdata : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
50 ram_write : IN STD_LOGIC;
50 ram_write : IN STD_LOGIC;
51 ram_read : IN STD_LOGIC;
51 ram_read : IN STD_LOGIC;
52 raddr_rst : IN STD_LOGIC;
52 raddr_rst : IN STD_LOGIC;
53 raddr_add1 : IN STD_LOGIC;
53 raddr_add1 : IN STD_LOGIC;
54 waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
54 waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
55 --
55 --
56 alu_sel_input : IN STD_LOGIC;
56 alu_sel_input : IN STD_LOGIC;
57 alu_sel_coeff : IN STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
57 alu_sel_coeff : IN STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
58 alu_ctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0);--(MAC_op, MULT_with_clear_ADD, IDLE)
58 alu_ctrl : IN STD_LOGIC_VECTOR(2 DOWNTO 0);--(MAC_op, MULT_with_clear_ADD, IDLE)
59 alu_comp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
59 -- DATA
60 -- DATA
60 sample_in : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
61 sample_in : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
61 sample_out : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0)
62 sample_out : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0)
62 );
63 );
63 END IIR_CEL_CTRLR_v2_DATAFLOW;
64 END IIR_CEL_CTRLR_v2_DATAFLOW;
64
65
65 ARCHITECTURE ar_IIR_CEL_CTRLR_v2_DATAFLOW OF IIR_CEL_CTRLR_v2_DATAFLOW IS
66 ARCHITECTURE ar_IIR_CEL_CTRLR_v2_DATAFLOW OF IIR_CEL_CTRLR_v2_DATAFLOW IS
66
67
67 COMPONENT RAM_CTRLR_v2
68 COMPONENT RAM_CTRLR_v2
68 GENERIC (
69 GENERIC (
69 tech : INTEGER;
70 tech : INTEGER;
70 Input_SZ_1 : INTEGER;
71 Input_SZ_1 : INTEGER;
71 Mem_use : INTEGER);
72 Mem_use : INTEGER);
72 PORT (
73 PORT (
73 rstn : IN STD_LOGIC;
74 rstn : IN STD_LOGIC;
74 clk : IN STD_LOGIC;
75 clk : IN STD_LOGIC;
75 ram_write : IN STD_LOGIC;
76 ram_write : IN STD_LOGIC;
76 ram_read : IN STD_LOGIC;
77 ram_read : IN STD_LOGIC;
77 raddr_rst : IN STD_LOGIC;
78 raddr_rst : IN STD_LOGIC;
78 raddr_add1 : IN STD_LOGIC;
79 raddr_add1 : IN STD_LOGIC;
79 waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
80 waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
80 sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
81 sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
81 sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0));
82 sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0));
82 END COMPONENT;
83 END COMPONENT;
83
84
84 SIGNAL reg_sample_in : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
85 SIGNAL reg_sample_in : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
85 SIGNAL ram_output : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
86 SIGNAL ram_output : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
86 SIGNAL alu_output : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
87 SIGNAL alu_output : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
87 SIGNAL ram_input : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
88 SIGNAL ram_input : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
88 SIGNAL alu_sample : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
89 SIGNAL alu_sample : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
89 SIGNAL alu_output_s : STD_LOGIC_VECTOR(Sample_SZ+Coef_SZ-1 DOWNTO 0);
90 SIGNAL alu_output_s : STD_LOGIC_VECTOR(Sample_SZ+Coef_SZ-1 DOWNTO 0);
90
91
91 SIGNAL arrayCoeff : MUX_INPUT_TYPE(0 TO (2**Coef_sel_SZ)-1,Coef_SZ-1 DOWNTO 0);
92 SIGNAL arrayCoeff : MUX_INPUT_TYPE(0 TO (2**Coef_sel_SZ)-1,Coef_SZ-1 DOWNTO 0);
92 SIGNAL alu_coef_s : MUX_OUTPUT_TYPE(Coef_SZ-1 DOWNTO 0);
93 SIGNAL alu_coef_s : MUX_OUTPUT_TYPE(Coef_SZ-1 DOWNTO 0);
93
94
94 SIGNAL alu_coef : STD_LOGIC_VECTOR(Coef_SZ-1 DOWNTO 0);
95 SIGNAL alu_coef : STD_LOGIC_VECTOR(Coef_SZ-1 DOWNTO 0);
95
96
96 BEGIN
97 BEGIN
97
98
98 -----------------------------------------------------------------------------
99 -----------------------------------------------------------------------------
99 -- INPUT
100 -- INPUT
100 -----------------------------------------------------------------------------
101 -----------------------------------------------------------------------------
101 PROCESS (clk, rstn)
102 PROCESS (clk, rstn)
102 BEGIN -- PROCESS
103 BEGIN -- PROCESS
103 IF rstn = '0' THEN -- asynchronous reset (active low)
104 IF rstn = '0' THEN -- asynchronous reset (active low)
104 reg_sample_in <= (OTHERS => '0');
105 reg_sample_in <= (OTHERS => '0');
105 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
106 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
106 CASE in_sel_src IS
107 CASE in_sel_src IS
107 WHEN "00" => reg_sample_in <= reg_sample_in;
108 WHEN "00" => reg_sample_in <= reg_sample_in;
108 WHEN "01" => reg_sample_in <= sample_in;
109 WHEN "01" => reg_sample_in <= sample_in;
109 WHEN "10" => reg_sample_in <= ram_output;
110 WHEN "10" => reg_sample_in <= ram_output;
110 WHEN "11" => reg_sample_in <= alu_output;
111 WHEN "11" => reg_sample_in <= alu_output;
111 WHEN OTHERS => NULL;
112 WHEN OTHERS => NULL;
112 END CASE;
113 END CASE;
113 END IF;
114 END IF;
114 END PROCESS;
115 END PROCESS;
115
116
116
117
117 -----------------------------------------------------------------------------
118 -----------------------------------------------------------------------------
118 -- RAM + CTRL
119 -- RAM + CTRL
119 -----------------------------------------------------------------------------
120 -----------------------------------------------------------------------------
120
121
121 ram_input <= reg_sample_in WHEN ram_sel_Wdata = "00" ELSE
122 ram_input <= reg_sample_in WHEN ram_sel_Wdata = "00" ELSE
122 alu_output WHEN ram_sel_Wdata = "01" ELSE
123 alu_output WHEN ram_sel_Wdata = "01" ELSE
123 ram_output;
124 ram_output;
124
125
125 RAM_CTRLR_v2_1: RAM_CTRLR_v2
126 RAM_CTRLR_v2_1: RAM_CTRLR_v2
126 GENERIC MAP (
127 GENERIC MAP (
127 tech => tech,
128 tech => tech,
128 Input_SZ_1 => Sample_SZ,
129 Input_SZ_1 => Sample_SZ,
129 Mem_use => Mem_use)
130 Mem_use => Mem_use)
130 PORT MAP (
131 PORT MAP (
131 clk => clk,
132 clk => clk,
132 rstn => rstn,
133 rstn => rstn,
133 ram_write => ram_write,
134 ram_write => ram_write,
134 ram_read => ram_read,
135 ram_read => ram_read,
135 raddr_rst => raddr_rst,
136 raddr_rst => raddr_rst,
136 raddr_add1 => raddr_add1,
137 raddr_add1 => raddr_add1,
137 waddr_previous => waddr_previous,
138 waddr_previous => waddr_previous,
138 sample_in => ram_input,
139 sample_in => ram_input,
139 sample_out => ram_output);
140 sample_out => ram_output);
140
141
141 -----------------------------------------------------------------------------
142 -----------------------------------------------------------------------------
142 -- MAC_ACC
143 -- MAC_ACC
143 -----------------------------------------------------------------------------
144 -----------------------------------------------------------------------------
144 -- Control : mac_ctrl (MAC_op, MULT_with_clear_ADD, IDLE)
145 -- Control : mac_ctrl (MAC_op, MULT_with_clear_ADD, IDLE)
145 -- Data In : mac_sample, mac_coef
146 -- Data In : mac_sample, mac_coef
146 -- Data Out: mac_output
147 -- Data Out: mac_output
147
148
148 alu_sample <= reg_sample_in WHEN alu_sel_input = '0' ELSE ram_output;
149 alu_sample <= reg_sample_in WHEN alu_sel_input = '0' ELSE ram_output;
149
150
150 coefftable: FOR I IN 0 TO (2**Coef_sel_SZ)-1 GENERATE
151 coefftable: FOR I IN 0 TO (2**Coef_sel_SZ)-1 GENERATE
151 coeff_in: IF I < Coef_Nb GENERATE
152 coeff_in: IF I < Coef_Nb GENERATE
152 all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE
153 all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE
153 arrayCoeff(I,J) <= coefs(Coef_SZ*I+J);
154 arrayCoeff(I,J) <= coefs(Coef_SZ*I+J);
154 END GENERATE all_bit;
155 END GENERATE all_bit;
155 END GENERATE coeff_in;
156 END GENERATE coeff_in;
156 coeff_null: IF I > (Coef_Nb -1) GENERATE
157 coeff_null: IF I > (Coef_Nb -1) GENERATE
157 all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE
158 all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE
158 arrayCoeff(I,J) <= '0';
159 arrayCoeff(I,J) <= '0';
159 END GENERATE all_bit;
160 END GENERATE all_bit;
160 END GENERATE coeff_null;
161 END GENERATE coeff_null;
161 END GENERATE coefftable;
162 END GENERATE coefftable;
162
163
163 Coeff_Mux : MUXN
164 Coeff_Mux : MUXN
164 GENERIC MAP (
165 GENERIC MAP (
165 Input_SZ => Coef_SZ,
166 Input_SZ => Coef_SZ,
166 NbStage => Coef_sel_SZ)
167 NbStage => Coef_sel_SZ)
167 PORT MAP (
168 PORT MAP (
168 sel => alu_sel_coeff,
169 sel => alu_sel_coeff,
169 INPUT => arrayCoeff,
170 INPUT => arrayCoeff,
170 RES => alu_coef_s);
171 RES => alu_coef_s);
171
172
172
173
173 all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE
174 all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE
174 alu_coef(J) <= alu_coef_s(J);
175 alu_coef(J) <= alu_coef_s(J);
175 END GENERATE all_bit;
176 END GENERATE all_bit;
176
177
177 -----------------------------------------------------------------------------
178 -----------------------------------------------------------------------------
178 -- TODO : just for Synthesis test
179 -- TODO : just for Synthesis test
179
180
180 --PROCESS (clk, rstn)
181 --PROCESS (clk, rstn)
181 --BEGIN
182 --BEGIN
182 -- IF rstn = '0' THEN
183 -- IF rstn = '0' THEN
183 -- alu_coef <= (OTHERS => '0');
184 -- alu_coef <= (OTHERS => '0');
184 -- ELSIF clk'event AND clk = '1' THEN
185 -- ELSIF clk'event AND clk = '1' THEN
185 -- all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 LOOP
186 -- all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 LOOP
186 -- alu_coef(J) <= alu_coef_s(J);
187 -- alu_coef(J) <= alu_coef_s(J);
187 -- END LOOP all_bit;
188 -- END LOOP all_bit;
188 -- END IF;
189 -- END IF;
189 --END PROCESS;
190 --END PROCESS;
190
191
191 -----------------------------------------------------------------------------
192 -----------------------------------------------------------------------------
192
193
193
194
194 ALU_1: ALU
195 ALU_1: ALU
195 GENERIC MAP (
196 GENERIC MAP (
196 Arith_en => 1,
197 Arith_en => 1,
197 Input_SZ_1 => Sample_SZ,
198 Input_SZ_1 => Sample_SZ,
198 Input_SZ_2 => Coef_SZ)
199 Input_SZ_2 => Coef_SZ)
199 PORT MAP (
200 PORT MAP (
200 clk => clk,
201 clk => clk,
201 reset => rstn,
202 reset => rstn,
202 ctrl => alu_ctrl,
203 ctrl => alu_ctrl,
204 comp => alu_comp,
203 OP1 => alu_sample,
205 OP1 => alu_sample,
204 OP2 => alu_coef,
206 OP2 => alu_coef,
205 RES => alu_output_s);
207 RES => alu_output_s);
206
208
207 alu_output <= alu_output_s(Sample_SZ+virg_pos-1 DOWNTO virg_pos);
209 alu_output <= alu_output_s(Sample_SZ+virg_pos-1 DOWNTO virg_pos);
208
210
209 sample_out <= alu_output;
211 sample_out <= alu_output;
210
212
211 END ar_IIR_CEL_CTRLR_v2_DATAFLOW;
213 END ar_IIR_CEL_CTRLR_v2_DATAFLOW;
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@@ -1,244 +1,259
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 library grlib;
24 library grlib;
25 use grlib.amba.all;
25 use grlib.amba.all;
26 use std.textio.all;
26 use std.textio.all;
27 library lpp;
27 library lpp;
28 use lpp.lpp_amba.all;
28 use lpp.lpp_amba.all;
29 use lpp.lpp_memory.all;
30 use work.fft_components.all;
29 use work.fft_components.all;
31
30
32 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
31 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
33
32
34 package lpp_fft is
33 package lpp_fft is
35
34
36 component APB_FFT is
35 component APB_FFT is
37 generic (
36 generic (
38 pindex : integer := 0;
37 pindex : integer := 0;
39 paddr : integer := 0;
38 paddr : integer := 0;
40 pmask : integer := 16#fff#;
39 pmask : integer := 16#fff#;
41 pirq : integer := 0;
40 pirq : integer := 0;
42 abits : integer := 8;
41 abits : integer := 8;
43 Data_sz : integer := 16
42 Data_sz : integer := 16
44 );
43 );
45 port (
44 port (
46 clk : in std_logic;
45 clk : in std_logic;
47 rst : in std_logic; --! Reset general du composant
46 rst : in std_logic; --! Reset general du composant
48 apbi : in apb_slv_in_type;
47 apbi : in apb_slv_in_type;
49 apbo : out apb_slv_out_type
48 apbo : out apb_slv_out_type
50 );
49 );
51 end component;
50 end component;
52
51
53
52
54 component APB_FFT_half is
53 component APB_FFT_half is
55 generic (
54 generic (
56 pindex : integer := 0;
55 pindex : integer := 0;
57 paddr : integer := 0;
56 paddr : integer := 0;
58 pmask : integer := 16#fff#;
57 pmask : integer := 16#fff#;
59 pirq : integer := 0;
58 pirq : integer := 0;
60 abits : integer := 8;
59 abits : integer := 8;
61 Data_sz : integer := 16
60 Data_sz : integer := 16
62 );
61 );
63 port (
62 port (
64 clk : in std_logic; --! Horloge du composant
63 clk : in std_logic; --! Horloge du composant
65 rst : in std_logic; --! Reset general du composant
64 rst : in std_logic; --! Reset general du composant
66 Ren : in std_logic;
65 Ren : in std_logic;
67 ready : out std_logic;
66 ready : out std_logic;
68 valid : out std_logic;
67 valid : out std_logic;
69 DataOut_re : out std_logic_vector(Data_sz-1 downto 0);
68 DataOut_re : out std_logic_vector(Data_sz-1 downto 0);
70 DataOut_im : out std_logic_vector(Data_sz-1 downto 0);
69 DataOut_im : out std_logic_vector(Data_sz-1 downto 0);
71 OUTfill : out std_logic;
70 OUTfill : out std_logic;
72 OUTwrite : out std_logic;
71 OUTwrite : out std_logic;
73 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
72 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
74 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
73 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
75 );
74 );
76 end component;
75 end component;
77
76
77 component FFT is
78 generic(
79 Data_sz : integer := 16;
80 NbData : integer := 256);
81 port(
82 clkm : in std_logic;
83 rstn : in std_logic;
84 FifoIN_Empty : in std_logic_vector(4 downto 0);
85 FifoIN_Data : in std_logic_vector(79 downto 0);
86 FifoOUT_Full : in std_logic_vector(4 downto 0);
87 Read : out std_logic_vector(4 downto 0);
88 Write : out std_logic_vector(4 downto 0);
89 ReUse : out std_logic_vector(4 downto 0);
90 Data : out std_logic_vector(79 downto 0)
91 );
92 end component;
78
93
79 component Flag_Extremum is
94 component Flag_Extremum is
80 port(
95 port(
81 clk,raz : in std_logic; --! Horloge et Reset g�n�ral du composant
96 clk,raz : in std_logic; --! Horloge et Reset g�n�ral du composant
82 load : in std_logic; --! Signal en provenance de CoreFFT
97 load : in std_logic; --! Signal en provenance de CoreFFT
83 y_rdy : in std_logic; --! Signal en provenance de CoreFFT
98 y_rdy : in std_logic; --! Signal en provenance de CoreFFT
84 fill : out std_logic; --! Flag, Va permettre d'autoriser l'�criture (Driver C)
99 fill : out std_logic; --! Flag, Va permettre d'autoriser l'�criture (Driver C)
85 ready : out std_logic --! Flag, Va permettre d'autoriser la lecture (Driver C)
100 ready : out std_logic --! Flag, Va permettre d'autoriser la lecture (Driver C)
86 );
101 );
87 end component;
102 end component;
88
103
89
104
90 component Linker_FFT is
105 component Linker_FFT is
91 generic(
106 generic(
92 Data_sz : integer range 1 to 32 := 16;
107 Data_sz : integer range 1 to 32 := 16;
93 NbData : integer range 1 to 512 := 256
108 NbData : integer range 1 to 512 := 256
94 );
109 );
95 port(
110 port(
96 clk : in std_logic;
111 clk : in std_logic;
97 rstn : in std_logic;
112 rstn : in std_logic;
98 Ready : in std_logic;
113 Ready : in std_logic;
99 Valid : in std_logic;
114 Valid : in std_logic;
100 Full : in std_logic_vector(4 downto 0);
115 Full : in std_logic_vector(4 downto 0);
101 Data_re : in std_logic_vector(Data_sz-1 downto 0);
116 Data_re : in std_logic_vector(Data_sz-1 downto 0);
102 Data_im : in std_logic_vector(Data_sz-1 downto 0);
117 Data_im : in std_logic_vector(Data_sz-1 downto 0);
103 Read : out std_logic;
118 Read : out std_logic;
104 Write : out std_logic_vector(4 downto 0);
119 Write : out std_logic_vector(4 downto 0);
105 ReUse : out std_logic_vector(4 downto 0);
120 ReUse : out std_logic_vector(4 downto 0);
106 DATA : out std_logic_vector((5*Data_sz)-1 downto 0)
121 DATA : out std_logic_vector((5*Data_sz)-1 downto 0)
107 );
122 );
108 end component;
123 end component;
109
124
110
125
111 component Driver_FFT is
126 component Driver_FFT is
112 generic(
127 generic(
113 Data_sz : integer range 1 to 32 := 16;
128 Data_sz : integer range 1 to 32 := 16;
114 NbData : integer range 1 to 512 := 256
129 NbData : integer range 1 to 512 := 256
115 );
130 );
116 port(
131 port(
117 clk : in std_logic;
132 clk : in std_logic;
118 rstn : in std_logic;
133 rstn : in std_logic;
119 Load : in std_logic;
134 Load : in std_logic;
120 Empty : in std_logic_vector(4 downto 0);
135 Empty : in std_logic_vector(4 downto 0);
121 DATA : in std_logic_vector((5*Data_sz)-1 downto 0);
136 DATA : in std_logic_vector((5*Data_sz)-1 downto 0);
122 Valid : out std_logic;
137 Valid : out std_logic;
123 Read : out std_logic_vector(4 downto 0);
138 Read : out std_logic_vector(4 downto 0);
124 Data_re : out std_logic_vector(Data_sz-1 downto 0);
139 Data_re : out std_logic_vector(Data_sz-1 downto 0);
125 Data_im : out std_logic_vector(Data_sz-1 downto 0)
140 Data_im : out std_logic_vector(Data_sz-1 downto 0)
126 );
141 );
127 end component;
142 end component;
128
143
129 component FFTamont is
144 component FFTamont is
130 generic(
145 generic(
131 Data_sz : integer range 1 to 32 := 16;
146 Data_sz : integer range 1 to 32 := 16;
132 NbData : integer range 1 to 512 := 256
147 NbData : integer range 1 to 512 := 256
133 );
148 );
134 port(
149 port(
135 clk : in std_logic;
150 clk : in std_logic;
136 rstn : in std_logic;
151 rstn : in std_logic;
137 Load : in std_logic;
152 Load : in std_logic;
138 Empty : in std_logic;
153 Empty : in std_logic;
139 DATA : in std_logic_vector(Data_sz-1 downto 0);
154 DATA : in std_logic_vector(Data_sz-1 downto 0);
140 Valid : out std_logic;
155 Valid : out std_logic;
141 Read : out std_logic;
156 Read : out std_logic;
142 Data_re : out std_logic_vector(Data_sz-1 downto 0);
157 Data_re : out std_logic_vector(Data_sz-1 downto 0);
143 Data_im : out std_logic_vector(Data_sz-1 downto 0)
158 Data_im : out std_logic_vector(Data_sz-1 downto 0)
144 );
159 );
145 end component;
160 end component;
146
161
147 component FFTaval is
162 component FFTaval is
148 generic(
163 generic(
149 Data_sz : integer range 1 to 32 := 8;
164 Data_sz : integer range 1 to 32 := 8;
150 NbData : integer range 1 to 512 := 256
165 NbData : integer range 1 to 512 := 256
151 );
166 );
152 port(
167 port(
153 clk : in std_logic;
168 clk : in std_logic;
154 rstn : in std_logic;
169 rstn : in std_logic;
155 Ready : in std_logic;
170 Ready : in std_logic;
156 Valid : in std_logic;
171 Valid : in std_logic;
157 Full : in std_logic;
172 Full : in std_logic;
158 Data_re : in std_logic_vector(Data_sz-1 downto 0);
173 Data_re : in std_logic_vector(Data_sz-1 downto 0);
159 Data_im : in std_logic_vector(Data_sz-1 downto 0);
174 Data_im : in std_logic_vector(Data_sz-1 downto 0);
160 Read : out std_logic;
175 Read : out std_logic;
161 Write : out std_logic;
176 Write : out std_logic;
162 ReUse : out std_logic;
177 ReUse : out std_logic;
163 DATA : out std_logic_vector(Data_sz-1 downto 0)
178 DATA : out std_logic_vector(Data_sz-1 downto 0)
164 );
179 );
165 end component;
180 end component;
166 --==============================================================|
181 --==============================================================|
167 --================== IP VHDL de la FFT actel ===================|
182 --================== IP VHDL de la FFT actel ===================|
168 --================ non partag� dans la VHD_Lib =================|
183 --================ non partag� dans la VHD_Lib =================|
169 --==============================================================|
184 --==============================================================|
170
185
171 component CoreFFT IS
186 component CoreFFT IS
172 GENERIC (
187 GENERIC (
173 LOGPTS : integer := gLOGPTS;
188 LOGPTS : integer := gLOGPTS;
174 LOGLOGPTS : integer := gLOGLOGPTS;
189 LOGLOGPTS : integer := gLOGLOGPTS;
175 WSIZE : integer := gWSIZE;
190 WSIZE : integer := gWSIZE;
176 TWIDTH : integer := gTWIDTH;
191 TWIDTH : integer := gTWIDTH;
177 DWIDTH : integer := gDWIDTH;
192 DWIDTH : integer := gDWIDTH;
178 TDWIDTH : integer := gTDWIDTH;
193 TDWIDTH : integer := gTDWIDTH;
179 RND_MODE : integer := gRND_MODE;
194 RND_MODE : integer := gRND_MODE;
180 SCALE_MODE : integer := gSCALE_MODE;
195 SCALE_MODE : integer := gSCALE_MODE;
181 PTS : integer := gPTS;
196 PTS : integer := gPTS;
182 HALFPTS : integer := gHALFPTS;
197 HALFPTS : integer := gHALFPTS;
183 inBuf_RWDLY : integer := gInBuf_RWDLY );
198 inBuf_RWDLY : integer := gInBuf_RWDLY );
184 PORT (
199 PORT (
185 clk,ifiStart,ifiNreset : IN std_logic;
200 clk,ifiStart,ifiNreset : IN std_logic;
186 ifiD_valid, ifiRead_y : IN std_logic;
201 ifiD_valid, ifiRead_y : IN std_logic;
187 ifiD_im, ifiD_re : IN std_logic_vector(WSIZE-1 DOWNTO 0);
202 ifiD_im, ifiD_re : IN std_logic_vector(WSIZE-1 DOWNTO 0);
188 ifoLoad, ifoPong : OUT std_logic;
203 ifoLoad, ifoPong : OUT std_logic;
189 ifoY_im, ifoY_re : OUT std_logic_vector(WSIZE-1 DOWNTO 0);
204 ifoY_im, ifoY_re : OUT std_logic_vector(WSIZE-1 DOWNTO 0);
190 ifoY_valid, ifoY_rdy : OUT std_logic);
205 ifoY_valid, ifoY_rdy : OUT std_logic);
191 END component;
206 END component;
192
207
193
208
194 component actar is
209 component actar is
195 port( DataA : in std_logic_vector(15 downto 0); DataB : in
210 port( DataA : in std_logic_vector(15 downto 0); DataB : in
196 std_logic_vector(15 downto 0); Mult : out
211 std_logic_vector(15 downto 0); Mult : out
197 std_logic_vector(31 downto 0);Clock : in std_logic) ;
212 std_logic_vector(31 downto 0);Clock : in std_logic) ;
198 end component;
213 end component;
199
214
200 component actram is
215 component actram is
201 port( DI : in std_logic_vector(31 downto 0); DO : out
216 port( DI : in std_logic_vector(31 downto 0); DO : out
202 std_logic_vector(31 downto 0);WRB, RDB : in std_logic;
217 std_logic_vector(31 downto 0);WRB, RDB : in std_logic;
203 WADDR : in std_logic_vector(6 downto 0); RADDR : in
218 WADDR : in std_logic_vector(6 downto 0); RADDR : in
204 std_logic_vector(6 downto 0);WCLOCK, RCLOCK : in
219 std_logic_vector(6 downto 0);WCLOCK, RCLOCK : in
205 std_logic) ;
220 std_logic) ;
206 end component;
221 end component;
207
222
208 component switch IS
223 component switch IS
209 GENERIC ( DWIDTH : integer := 32 );
224 GENERIC ( DWIDTH : integer := 32 );
210 PORT (
225 PORT (
211 clk, sel, validIn : IN std_logic;
226 clk, sel, validIn : IN std_logic;
212 inP, inQ : IN std_logic_vector(DWIDTH-1 DOWNTO 0);
227 inP, inQ : IN std_logic_vector(DWIDTH-1 DOWNTO 0);
213 outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0);
228 outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0);
214 validOut : OUT std_logic);
229 validOut : OUT std_logic);
215 END component;
230 END component;
216
231
217 component twid_rA IS
232 component twid_rA IS
218 GENERIC (LOGPTS : integer := 8;
233 GENERIC (LOGPTS : integer := 8;
219 LOGLOGPTS : integer := 3 );
234 LOGLOGPTS : integer := 3 );
220 PORT (clk : IN std_logic;
235 PORT (clk : IN std_logic;
221 timer : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
236 timer : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
222 stage : IN std_logic_vector(LOGLOGPTS-1 DOWNTO 0);
237 stage : IN std_logic_vector(LOGLOGPTS-1 DOWNTO 0);
223 tA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0));
238 tA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0));
224 END component;
239 END component;
225
240
226 component counter IS
241 component counter IS
227 GENERIC (
242 GENERIC (
228 WIDTH : integer := 7;
243 WIDTH : integer := 7;
229 TERMCOUNT : integer := 127 );
244 TERMCOUNT : integer := 127 );
230 PORT (
245 PORT (
231 clk, nGrst, rst, cntEn : IN std_logic;
246 clk, nGrst, rst, cntEn : IN std_logic;
232 tc : OUT std_logic;
247 tc : OUT std_logic;
233 Q : OUT std_logic_vector(WIDTH-1 DOWNTO 0) );
248 Q : OUT std_logic_vector(WIDTH-1 DOWNTO 0) );
234 END component;
249 END component;
235
250
236
251
237 component twiddle IS
252 component twiddle IS
238 PORT (
253 PORT (
239 A : IN std_logic_vector(gLOGPTS-2 DOWNTO 0);
254 A : IN std_logic_vector(gLOGPTS-2 DOWNTO 0);
240 T : OUT std_logic_vector(gTDWIDTH-1 DOWNTO 0));
255 T : OUT std_logic_vector(gTDWIDTH-1 DOWNTO 0));
241 END component;
256 END component;
242
257
243
258
244 end; No newline at end of file
259 end;
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@@ -1,77 +1,63
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Martin Morlot
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 library IEEE;
23 USE IEEE.numeric_std.ALL;
23 use IEEE.numeric_std.all;
24 USE IEEE.std_logic_1164.ALL;
24 use IEEE.std_logic_1164.all;
25 LIBRARY lpp;
25 library lpp;
26 USE lpp.general_purpose.ALL;
26 use lpp.general_purpose.all;
27 --IDLE = 0000
27
28 --MAC = 0001
28 --! Une ALU : Arithmetic and logical unit, permettant de r�aliser une ou plusieurs op�ration
29 --MULT = 0010 and set MULT in ADD reg
29
30 --ADD = 0011
30 entity ALU is
31 --CLRMAC = 0100
31 generic(
32
32 Arith_en : integer := 1;
33
33 Logic_en : integer := 1;
34 ENTITY ALU IS
34 Input_SZ_1 : integer := 16;
35 GENERIC(
35 Input_SZ_2 : integer := 16);
36 Arith_en : INTEGER := 1;
36 port(
37 Logic_en : INTEGER := 1;
37 clk : in std_logic; --! Horloge du composant
38 Input_SZ_1 : INTEGER := 16;
38 reset : in std_logic; --! Reset general du composant
39 Input_SZ_2 : INTEGER := 9
39 ctrl : in std_logic_vector(2 downto 0); --! Permet de s�lectionner la/les op�ration d�sir�e
40
40 comp : in std_logic_vector(1 downto 0); --! (set) Permet de compl�menter les op�randes
41 );
41 OP1 : in std_logic_vector(Input_SZ_1-1 downto 0); --! Premier Op�rande
42 PORT(
42 OP2 : in std_logic_vector(Input_SZ_2-1 downto 0); --! Second Op�rande
43 clk : IN STD_LOGIC;
43 RES : out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0) --! R�sultat de l'op�ration
44 reset : IN STD_LOGIC;
44 );
45 ctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
45 end ALU;
46 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
46
47 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0);
47 --! @details S�lection grace a l'entr�e "ctrl" :
48 RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0)
48 --! Pause : IDLE = 000
49 );
49 --! Multiplieur/Accumulateur : MAC = 001
50 END ENTITY;
50 --! Multiplication : MULT = 010
51
51 --! Addition : ADD = 011
52 ARCHITECTURE ar_ALU OF ALU IS
52 --! Reset du MAC : CLRMAC = 100
53
53 architecture ar_ALU of ALU is
54 SIGNAL clr_MAC : STD_LOGIC := '1';
54
55
55 begin
56 BEGIN
56
57 clr_MAC <= '1' WHEN ctrl = "0100" OR ctrl = "0101" OR ctrl = "0110" ELSE '0';
57 arith : if Arith_en = 1 generate
58
58 MACinst : MAC
59 arith : IF Arith_en = 1 GENERATE
59 generic map(Input_SZ_1,Input_SZ_2)
60 MACinst : MAC
60 port map(clk,reset,ctrl(2),ctrl(1 downto 0),comp,OP1,OP2,RES);
61 GENERIC MAP(Input_SZ_1, Input_SZ_2)
61 end generate;
62 PORT MAP(clk, reset, clr_MAC, ctrl(1 DOWNTO 0), OP1, OP2, RES);
62
63 END GENERATE;
63 end architecture; No newline at end of file
64
65 END ARCHITECTURE;
66
67
68
69
70
71
72
73
74
75
76
77
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@@ -1,262 +1,294
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
21 ----------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY lpp;
25 LIBRARY lpp;
26 USE lpp.general_purpose.ALL;
26 USE lpp.general_purpose.ALL;
27 --TODO
27 --TODO
28 --terminer le testbensh puis changer le resize dans les instanciations
28 --terminer le testbensh puis changer le resize dans les instanciations
29 --par un resize sur un vecteur en combi
29 --par un resize sur un vecteur en combi
30
30
31
31
32 ENTITY MAC IS
32 ENTITY MAC IS
33 GENERIC(
33 GENERIC(
34 Input_SZ_A : INTEGER := 8;
34 Input_SZ_A : INTEGER := 8;
35 Input_SZ_B : INTEGER := 8
35 Input_SZ_B : INTEGER := 8
36
36
37 );
37 );
38 PORT(
38 PORT(
39 clk : IN STD_LOGIC;
39 clk : IN STD_LOGIC;
40 reset : IN STD_LOGIC;
40 reset : IN STD_LOGIC;
41 clr_MAC : IN STD_LOGIC;
41 clr_MAC : IN STD_LOGIC;
42 MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
42 MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
43 Comp_2C : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
43 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
44 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
44 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
45 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
45 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
46 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
46 );
47 );
47 END MAC;
48 END MAC;
48
49
49
50
50
51
51
52
52 ARCHITECTURE ar_MAC OF MAC IS
53 ARCHITECTURE ar_MAC OF MAC IS
53
54
54 SIGNAL add, mult : STD_LOGIC;
55 signal add,mult : std_logic;
55 SIGNAL MULTout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
56 signal MULTout : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
56
57
57 SIGNAL ADDERinA : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
58 signal ADDERinA : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
58 SIGNAL ADDERinB : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
59 signal ADDERinB : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
59 SIGNAL ADDERout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
60 signal ADDERout : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
60
61
62 signal MACMUXsel : std_logic;
63 signal OP1_2C_D_Resz : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
64 signal OP2_2C_D_Resz : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
61
65
62 SIGNAL MACMUXsel : STD_LOGIC;
66 signal OP1_2C : std_logic_vector(Input_SZ_A-1 downto 0);
63 SIGNAL OP1_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
67 signal OP2_2C : std_logic_vector(Input_SZ_B-1 downto 0);
64 SIGNAL OP2_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
65
66
67
68
68 SIGNAL MACMUX2sel : STD_LOGIC;
69 signal MACMUX2sel : std_logic;
69
70
70 SIGNAL add_D : STD_LOGIC;
71 signal add_D : std_logic;
71 SIGNAL OP1_D : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
72 signal OP1_2C_D : std_logic_vector(Input_SZ_A-1 downto 0);
72 SIGNAL OP2_D : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
73 signal OP2_2C_D : std_logic_vector(Input_SZ_B-1 downto 0);
73 SIGNAL MULTout_D : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
74 signal MULTout_D : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
74 SIGNAL MACMUXsel_D : STD_LOGIC;
75 signal MACMUXsel_D : std_logic;
75 SIGNAL MACMUX2sel_D : STD_LOGIC;
76 signal MACMUX2sel_D : std_logic;
76 SIGNAL MACMUX2sel_D_D : STD_LOGIC;
77 signal MACMUX2sel_D_D : std_logic;
77 SIGNAL clr_MAC_D : STD_LOGIC;
78 signal clr_MAC_D : std_logic;
78 SIGNAL clr_MAC_D_D : STD_LOGIC;
79 signal clr_MAC_D_D : std_logic;
80 signal MAC_MUL_ADD_2C_D : std_logic_vector(1 downto 0);
79
81
80 SIGNAL load_mult_result : STD_LOGIC;
82 SIGNAL load_mult_result : STD_LOGIC;
81 SIGNAL load_mult_result_D : STD_LOGIC;
83 SIGNAL load_mult_result_D : STD_LOGIC;
82
84
83 BEGIN
85 BEGIN
84
86
85
87
86
88
87
89
88 --==============================================================
90 --==============================================================
89 --=============M A C C O N T R O L E R=========================
91 --=============M A C C O N T R O L E R=========================
90 --==============================================================
92 --==============================================================
91 MAC_CONTROLER1 : MAC_CONTROLER
93 MAC_CONTROLER1 : MAC_CONTROLER
92 PORT MAP(
94 PORT MAP(
93 ctrl => MAC_MUL_ADD,
95 ctrl => MAC_MUL_ADD,
94 MULT => mult,
96 MULT => mult,
95 ADD => add,
97 ADD => add,
96 LOAD_ADDER => load_mult_result,
98 LOAD_ADDER => load_mult_result,
97 MACMUX_sel => MACMUXsel,
99 MACMUX_sel => MACMUXsel,
98 MACMUX2_sel => MACMUX2sel
100 MACMUX2_sel => MACMUX2sel
99
101
100 );
102 );
101 --==============================================================
103 --==============================================================
102
104
103
105
104
106
105
107
106 --==============================================================
108 --==============================================================
107 --=============M U L T I P L I E R==============================
109 --=============M U L T I P L I E R==============================
108 --==============================================================
110 --==============================================================
109 Multiplieri_nst : Multiplier
111 Multiplieri_nst : Multiplier
110 GENERIC MAP(
112 GENERIC MAP(
111 Input_SZ_A => Input_SZ_A,
113 Input_SZ_A => Input_SZ_A,
112 Input_SZ_B => Input_SZ_B
114 Input_SZ_B => Input_SZ_B
113 )
115 )
114 PORT MAP(
116 port map(
115 clk => clk,
117 clk => clk,
116 reset => reset,
118 reset => reset,
117 mult => mult,
119 mult => mult,
118 OP1 => OP1,
120 OP1 => OP1_2C,
119 OP2 => OP2,
121 OP2 => OP2_2C,
120 RES => MULTout
122 RES => MULTout
121 );
123 );
122 --==============================================================
124 --==============================================================
123
125
124 PROCESS (clk, reset)
126 PROCESS (clk, reset)
125 BEGIN -- PROCESS
127 BEGIN -- PROCESS
126 IF reset = '0' THEN -- asynchronous reset (active low)
128 IF reset = '0' THEN -- asynchronous reset (active low)
127 load_mult_result_D <= '0';
129 load_mult_result_D <= '0';
128 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
130 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
129 load_mult_result_D <= load_mult_result;
131 load_mult_result_D <= load_mult_result;
130 END IF;
132 END IF;
131 END PROCESS;
133 END PROCESS;
132
134
133 --==============================================================
135 --==============================================================
134 --======================A D D E R ==============================
136 --======================A D D E R ==============================
135 --==============================================================
137 --==============================================================
136 adder_inst : Adder
138 adder_inst : Adder
137 GENERIC MAP(
139 GENERIC MAP(
138 Input_SZ_A => Input_SZ_A+Input_SZ_B,
140 Input_SZ_A => Input_SZ_A+Input_SZ_B,
139 Input_SZ_B => Input_SZ_A+Input_SZ_B
141 Input_SZ_B => Input_SZ_A+Input_SZ_B
140 )
142 )
141 PORT MAP(
143 PORT MAP(
142 clk => clk,
144 clk => clk,
143 reset => reset,
145 reset => reset,
144 clr => clr_MAC_D,
146 clr => clr_MAC_D,
145 load => load_mult_result_D,
147 load => load_mult_result_D,
146 add => add_D,
148 add => add_D,
147 OP1 => ADDERinA,
149 OP1 => ADDERinA,
148 OP2 => ADDERinB,
150 OP2 => ADDERinB,
149 RES => ADDERout
151 RES => ADDERout
150 );
152 );
153
151 --==============================================================
154 --==============================================================
155 --===================TWO COMPLEMENTERS==========================
156 --==============================================================
157 TWO_COMPLEMENTER1 : TwoComplementer
158 generic map(
159 Input_SZ => Input_SZ_A
160 )
161 port map(
162 clk => clk,
163 reset => reset,
164 clr => clr_MAC,
165 TwoComp => Comp_2C(0),
166 OP => OP1,
167 RES => OP1_2C
168 );
152
169
153
170
171 TWO_COMPLEMENTER2 : TwoComplementer
172 generic map(
173 Input_SZ => Input_SZ_B
174 )
175 port map(
176 clk => clk,
177 reset => reset,
178 clr => clr_MAC,
179 TwoComp => Comp_2C(1),
180 OP => OP2,
181 RES => OP2_2C
182 );
183 --==============================================================
184
154 clr_MACREG1 : MAC_REG
185 clr_MACREG1 : MAC_REG
155 GENERIC MAP(size => 1)
186 GENERIC MAP(size => 1)
156 PORT MAP(
187 PORT MAP(
157 reset => reset,
188 reset => reset,
158 clk => clk,
189 clk => clk,
159 D(0) => clr_MAC,
190 D(0) => clr_MAC,
160 Q(0) => clr_MAC_D
191 Q(0) => clr_MAC_D
161 );
192 );
162
193
163 addREG : MAC_REG
194 addREG : MAC_REG
164 GENERIC MAP(size => 1)
195 GENERIC MAP(size => 1)
165 PORT MAP(
196 PORT MAP(
166 reset => reset,
197 reset => reset,
167 clk => clk,
198 clk => clk,
168 D(0) => add,
199 D(0) => add,
169 Q(0) => add_D
200 Q(0) => add_D
170 );
201 );
171
202
172 OP1REG : MAC_REG
203 OP1REG : MAC_REG
173 GENERIC MAP(size => Input_SZ_A)
204 generic map(size => Input_SZ_A)
174 PORT MAP(
205 port map(
175 reset => reset,
206 reset => reset,
176 clk => clk,
207 clk => clk,
177 D => OP1,
208 D => OP1_2C,
178 Q => OP1_D
209 Q => OP1_2C_D
179 );
210 );
180
211
181 OP2REG : MAC_REG
212
182 GENERIC MAP(size => Input_SZ_B)
213 OP2REG : MAC_REG
183 PORT MAP(
214 generic map(size => Input_SZ_B)
184 reset => reset,
215 port map(
185 clk => clk,
216 reset => reset,
186 D => OP2,
217 clk => clk,
187 Q => OP2_D
218 D => OP2_2C,
188 );
219 Q => OP2_2C_D
220 );
189
221
190 MULToutREG : MAC_REG
222 MULToutREG : MAC_REG
191 GENERIC MAP(size => Input_SZ_A+Input_SZ_B)
223 GENERIC MAP(size => Input_SZ_A+Input_SZ_B)
192 PORT MAP(
224 PORT MAP(
193 reset => reset,
225 reset => reset,
194 clk => clk,
226 clk => clk,
195 D => MULTout,
227 D => MULTout,
196 Q => MULTout_D
228 Q => MULTout_D
197 );
229 );
198
230
199 MACMUXselREG : MAC_REG
231 MACMUXselREG : MAC_REG
200 GENERIC MAP(size => 1)
232 GENERIC MAP(size => 1)
201 PORT MAP(
233 PORT MAP(
202 reset => reset,
234 reset => reset,
203 clk => clk,
235 clk => clk,
204 D(0) => MACMUXsel,
236 D(0) => MACMUXsel,
205 Q(0) => MACMUXsel_D
237 Q(0) => MACMUXsel_D
206 );
238 );
207
239
208 MACMUX2selREG : MAC_REG
240 MACMUX2selREG : MAC_REG
209 GENERIC MAP(size => 1)
241 GENERIC MAP(size => 1)
210 PORT MAP(
242 PORT MAP(
211 reset => reset,
243 reset => reset,
212 clk => clk,
244 clk => clk,
213 D(0) => MACMUX2sel,
245 D(0) => MACMUX2sel,
214 Q(0) => MACMUX2sel_D
246 Q(0) => MACMUX2sel_D
215 );
247 );
216
248
217 MACMUX2selREG2 : MAC_REG
249 MACMUX2selREG2 : MAC_REG
218 GENERIC MAP(size => 1)
250 GENERIC MAP(size => 1)
219 PORT MAP(
251 PORT MAP(
220 reset => reset,
252 reset => reset,
221 clk => clk,
253 clk => clk,
222 D(0) => MACMUX2sel_D,
254 D(0) => MACMUX2sel_D,
223 Q(0) => MACMUX2sel_D_D
255 Q(0) => MACMUX2sel_D_D
224 );
256 );
225
257
226 --==============================================================
258 --==============================================================
227 --======================M A C M U X ===========================
259 --======================M A C M U X ===========================
228 --==============================================================
260 --==============================================================
229 MACMUX_inst : MAC_MUX
261 MACMUX_inst : MAC_MUX
230 GENERIC MAP(
262 GENERIC MAP(
231 Input_SZ_A => Input_SZ_A+Input_SZ_B,
263 Input_SZ_A => Input_SZ_A+Input_SZ_B,
232 Input_SZ_B => Input_SZ_A+Input_SZ_B
264 Input_SZ_B => Input_SZ_A+Input_SZ_B
233
265
234 )
266 )
235 PORT MAP(
267 PORT MAP(
236 sel => MACMUXsel_D,
268 sel => MACMUXsel_D,
237 INA1 => ADDERout,
269 INA1 => ADDERout,
238 INA2 => OP2_D_Resz,
270 INA2 => OP2_2C_D_Resz,
239 INB1 => MULTout,
271 INB1 => MULTout,
240 INB2 => OP1_D_Resz,
272 INB2 => OP1_2C_D_Resz,
241 OUTA => ADDERinA,
273 OUTA => ADDERinA,
242 OUTB => ADDERinB
274 OUTB => ADDERinB
243 );
275 );
244 OP1_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP1_D), Input_SZ_A+Input_SZ_B));
276 OP1_2C_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP1_2C_D), Input_SZ_A+Input_SZ_B));
245 OP2_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP2_D), Input_SZ_A+Input_SZ_B));
277 OP2_2C_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP2_2C_D), Input_SZ_A+Input_SZ_B));
246 --==============================================================
278 --==============================================================
247
279
248
280
249 --==============================================================
281 --==============================================================
250 --======================M A C M U X2 ==========================
282 --======================M A C M U X2 ==========================
251 --==============================================================
283 --==============================================================
252 MAC_MUX2_inst : MAC_MUX2
284 MAC_MUX2_inst : MAC_MUX2
253 GENERIC MAP(Input_SZ => Input_SZ_A+Input_SZ_B)
285 GENERIC MAP(Input_SZ => Input_SZ_A+Input_SZ_B)
254 PORT MAP(
286 PORT MAP(
255 sel => MACMUX2sel_D_D,
287 sel => MACMUX2sel_D_D,
256 RES2 => MULTout_D,
288 RES2 => MULTout_D,
257 RES1 => ADDERout,
289 RES1 => ADDERout,
258 RES => RES
290 RES => RES
259 );
291 );
260 --==============================================================
292 --==============================================================
261
293
262 END ar_MAC;
294 END ar_MAC;
Show file before | Show file after | Hide comments
@@ -1,248 +1,271
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
21 ----------------------------------------------------------------------------
22 --UPDATE
22 --UPDATE
23 -------------------------------------------------------------------------------
23 -------------------------------------------------------------------------------
24 -- 14-03-2013 - Jean-christophe Pellion
24 -- 14-03-2013 - Jean-christophe Pellion
25 -- ADD MUXN (a parametric multiplexor (N stage of MUX2))
25 -- ADD MUXN (a parametric multiplexor (N stage of MUX2))
26 -------------------------------------------------------------------------------
26 -------------------------------------------------------------------------------
27
27
28 LIBRARY ieee;
28 LIBRARY ieee;
29 USE ieee.std_logic_1164.ALL;
29 USE ieee.std_logic_1164.ALL;
30
30
31
31
32
32
33 PACKAGE general_purpose IS
33 PACKAGE general_purpose IS
34
34
35
35
36
36
37 COMPONENT Clk_divider IS
37 COMPONENT Clk_divider IS
38 GENERIC(OSC_freqHz : INTEGER := 50000000;
38 GENERIC(OSC_freqHz : INTEGER := 50000000;
39 TargetFreq_Hz : INTEGER := 50000);
39 TargetFreq_Hz : INTEGER := 50000);
40 PORT (clk : IN STD_LOGIC;
40 PORT (clk : IN STD_LOGIC;
41 reset : IN STD_LOGIC;
41 reset : IN STD_LOGIC;
42 clk_divided : OUT STD_LOGIC);
42 clk_divided : OUT STD_LOGIC);
43 END COMPONENT;
43 END COMPONENT;
44
44
45
45
46 COMPONENT Clk_divider2 IS
46 COMPONENT Clk_divider2 IS
47 generic(N : integer := 16);
47 generic(N : integer := 16);
48 port(
48 port(
49 clk_in : in std_logic;
49 clk_in : in std_logic;
50 clk_out : out std_logic);
50 clk_out : out std_logic);
51 END COMPONENT;
51 END COMPONENT;
52
52
53 COMPONENT Adder IS
53 COMPONENT Adder IS
54 GENERIC(
54 GENERIC(
55 Input_SZ_A : INTEGER := 16;
55 Input_SZ_A : INTEGER := 16;
56 Input_SZ_B : INTEGER := 16
56 Input_SZ_B : INTEGER := 16
57
57
58 );
58 );
59 PORT(
59 PORT(
60 clk : IN STD_LOGIC;
60 clk : IN STD_LOGIC;
61 reset : IN STD_LOGIC;
61 reset : IN STD_LOGIC;
62 clr : IN STD_LOGIC;
62 clr : IN STD_LOGIC;
63 load : IN STD_LOGIC;
63 load : IN STD_LOGIC;
64 add : IN STD_LOGIC;
64 add : IN STD_LOGIC;
65 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
65 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
66 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
66 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
67 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0)
67 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0)
68 );
68 );
69 END COMPONENT;
69 END COMPONENT;
70
70
71 COMPONENT ADDRcntr IS
71 COMPONENT ADDRcntr IS
72 PORT(
72 PORT(
73 clk : IN STD_LOGIC;
73 clk : IN STD_LOGIC;
74 reset : IN STD_LOGIC;
74 reset : IN STD_LOGIC;
75 count : IN STD_LOGIC;
75 count : IN STD_LOGIC;
76 clr : IN STD_LOGIC;
76 clr : IN STD_LOGIC;
77 Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
77 Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
78 );
78 );
79 END COMPONENT;
79 END COMPONENT;
80
80
81 COMPONENT ALU IS
81 COMPONENT ALU IS
82 GENERIC(
82 GENERIC(
83 Arith_en : INTEGER := 1;
83 Arith_en : INTEGER := 1;
84 Logic_en : INTEGER := 1;
84 Logic_en : INTEGER := 1;
85 Input_SZ_1 : INTEGER := 16;
85 Input_SZ_1 : INTEGER := 16;
86 Input_SZ_2 : INTEGER := 9
86 Input_SZ_2 : INTEGER := 9
87
87
88 );
88 );
89 PORT(
89 PORT(
90 clk : IN STD_LOGIC;
90 clk : IN STD_LOGIC;
91 reset : IN STD_LOGIC;
91 reset : IN STD_LOGIC;
92 ctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
92 ctrl : IN STD_LOGIC_VECTOR(2 downto 0);
93 comp : IN STD_LOGIC_VECTOR(1 downto 0);
93 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
94 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
94 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0);
95 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0);
95 RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0)
96 RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0)
96 );
97 );
97 END COMPONENT;
98 END COMPONENT;
98
99
100 ---------------------------------------------------------
101 -------- // S�lection grace a l'entr�e "ctrl" \\ --------
102 ---------------------------------------------------------
103 Constant ctrl_IDLE : std_logic_vector(2 downto 0) := "000";
104 Constant ctrl_MAC : std_logic_vector(2 downto 0) := "001";
105 Constant ctrl_MULT : std_logic_vector(2 downto 0) := "010";
106 Constant ctrl_ADD : std_logic_vector(2 downto 0) := "011";
107 Constant ctrl_CLRMAC : std_logic_vector(2 downto 0) := "100";
108 ---------------------------------------------------------
99
109
100 COMPONENT MAC IS
110 COMPONENT MAC IS
101 GENERIC(
111 GENERIC(
102 Input_SZ_A : INTEGER := 8;
112 Input_SZ_A : INTEGER := 8;
103 Input_SZ_B : INTEGER := 8
113 Input_SZ_B : INTEGER := 8
104
114
105 );
115 );
106 PORT(
116 PORT(
107 clk : IN STD_LOGIC;
117 clk : IN STD_LOGIC;
108 reset : IN STD_LOGIC;
118 reset : IN STD_LOGIC;
109 clr_MAC : IN STD_LOGIC;
119 clr_MAC : IN STD_LOGIC;
110 MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
120 MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
121 Comp_2C : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
111 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
122 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
112 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
123 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
113 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
124 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
114 );
125 );
115 END COMPONENT;
126 END COMPONENT;
116
127
128 COMPONENT TwoComplementer is
129 generic(
130 Input_SZ : integer := 16);
131 port(
132 clk : in std_logic; --! Horloge du composant
133 reset : in std_logic; --! Reset general du composant
134 clr : in std_logic; --! Un reset sp�cifique au programme
135 TwoComp : in std_logic; --! Autorise l'utilisation du compl�ment
136 OP : in std_logic_vector(Input_SZ-1 downto 0); --! Op�rande d'entr�e
137 RES : out std_logic_vector(Input_SZ-1 downto 0) --! R�sultat, op�rande compl�ment� ou non
138 );
139 end COMPONENT;
117
140
118 COMPONENT MAC_CONTROLER IS
141 COMPONENT MAC_CONTROLER IS
119 PORT(
142 PORT(
120 ctrl : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
143 ctrl : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
121 MULT : OUT STD_LOGIC;
144 MULT : OUT STD_LOGIC;
122 ADD : OUT STD_LOGIC;
145 ADD : OUT STD_LOGIC;
123 LOAD_ADDER : out std_logic;
146 LOAD_ADDER : out std_logic;
124 MACMUX_sel : OUT STD_LOGIC;
147 MACMUX_sel : OUT STD_LOGIC;
125 MACMUX2_sel : OUT STD_LOGIC
148 MACMUX2_sel : OUT STD_LOGIC
126 );
149 );
127 END COMPONENT;
150 END COMPONENT;
128
151
129 COMPONENT MAC_MUX IS
152 COMPONENT MAC_MUX IS
130 GENERIC(
153 GENERIC(
131 Input_SZ_A : INTEGER := 16;
154 Input_SZ_A : INTEGER := 16;
132 Input_SZ_B : INTEGER := 16
155 Input_SZ_B : INTEGER := 16
133
156
134 );
157 );
135 PORT(
158 PORT(
136 sel : IN STD_LOGIC;
159 sel : IN STD_LOGIC;
137 INA1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
160 INA1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
138 INA2 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
161 INA2 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
139 INB1 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
162 INB1 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
140 INB2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
163 INB2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
141 OUTA : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
164 OUTA : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
142 OUTB : OUT STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0)
165 OUTB : OUT STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0)
143 );
166 );
144 END COMPONENT;
167 END COMPONENT;
145
168
146
169
147 COMPONENT MAC_MUX2 IS
170 COMPONENT MAC_MUX2 IS
148 GENERIC(Input_SZ : INTEGER := 16);
171 GENERIC(Input_SZ : INTEGER := 16);
149 PORT(
172 PORT(
150 sel : IN STD_LOGIC;
173 sel : IN STD_LOGIC;
151 RES1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
174 RES1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
152 RES2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
175 RES2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
153 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
176 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
154 );
177 );
155 END COMPONENT;
178 END COMPONENT;
156
179
157
180
158 COMPONENT MAC_REG IS
181 COMPONENT MAC_REG IS
159 GENERIC(size : INTEGER := 16);
182 GENERIC(size : INTEGER := 16);
160 PORT(
183 PORT(
161 reset : IN STD_LOGIC;
184 reset : IN STD_LOGIC;
162 clk : IN STD_LOGIC;
185 clk : IN STD_LOGIC;
163 D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
186 D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
164 Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)
187 Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)
165 );
188 );
166 END COMPONENT;
189 END COMPONENT;
167
190
168
191
169 COMPONENT MUX2 IS
192 COMPONENT MUX2 IS
170 GENERIC(Input_SZ : INTEGER := 16);
193 GENERIC(Input_SZ : INTEGER := 16);
171 PORT(
194 PORT(
172 sel : IN STD_LOGIC;
195 sel : IN STD_LOGIC;
173 IN1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
196 IN1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
174 IN2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
197 IN2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
175 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
198 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
176 );
199 );
177 END COMPONENT;
200 END COMPONENT;
178
201
179 TYPE MUX_INPUT_TYPE IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC;
202 TYPE MUX_INPUT_TYPE IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC;
180 TYPE MUX_OUTPUT_TYPE IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC;
203 TYPE MUX_OUTPUT_TYPE IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC;
181
204
182 COMPONENT MUXN
205 COMPONENT MUXN
183 GENERIC (
206 GENERIC (
184 Input_SZ : INTEGER;
207 Input_SZ : INTEGER;
185 NbStage : INTEGER);
208 NbStage : INTEGER);
186 PORT (
209 PORT (
187 sel : IN STD_LOGIC_VECTOR(NbStage-1 DOWNTO 0);
210 sel : IN STD_LOGIC_VECTOR(NbStage-1 DOWNTO 0);
188 INPUT : IN MUX_INPUT_TYPE(0 TO (2**NbStage)-1,Input_SZ-1 DOWNTO 0);
211 INPUT : IN MUX_INPUT_TYPE(0 TO (2**NbStage)-1,Input_SZ-1 DOWNTO 0);
189 --INPUT : IN ARRAY (0 TO (2**NbStage)-1) OF STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
212 --INPUT : IN ARRAY (0 TO (2**NbStage)-1) OF STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
190 RES : OUT MUX_OUTPUT_TYPE(Input_SZ-1 DOWNTO 0));
213 RES : OUT MUX_OUTPUT_TYPE(Input_SZ-1 DOWNTO 0));
191 END COMPONENT;
214 END COMPONENT;
192
215
193
216
194
217
195 COMPONENT Multiplier IS
218 COMPONENT Multiplier IS
196 GENERIC(
219 GENERIC(
197 Input_SZ_A : INTEGER := 16;
220 Input_SZ_A : INTEGER := 16;
198 Input_SZ_B : INTEGER := 16
221 Input_SZ_B : INTEGER := 16
199
222
200 );
223 );
201 PORT(
224 PORT(
202 clk : IN STD_LOGIC;
225 clk : IN STD_LOGIC;
203 reset : IN STD_LOGIC;
226 reset : IN STD_LOGIC;
204 mult : IN STD_LOGIC;
227 mult : IN STD_LOGIC;
205 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
228 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
206 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
229 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
207 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
230 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
208 );
231 );
209 END COMPONENT;
232 END COMPONENT;
210
233
211 COMPONENT REG IS
234 COMPONENT REG IS
212 GENERIC(size : INTEGER := 16; initial_VALUE : INTEGER := 0);
235 GENERIC(size : INTEGER := 16; initial_VALUE : INTEGER := 0);
213 PORT(
236 PORT(
214 reset : IN STD_LOGIC;
237 reset : IN STD_LOGIC;
215 clk : IN STD_LOGIC;
238 clk : IN STD_LOGIC;
216 D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
239 D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
217 Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)
240 Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)
218 );
241 );
219 END COMPONENT;
242 END COMPONENT;
220
243
221
244
222
245
223 COMPONENT RShifter IS
246 COMPONENT RShifter IS
224 GENERIC(
247 GENERIC(
225 Input_SZ : INTEGER := 16;
248 Input_SZ : INTEGER := 16;
226 shift_SZ : INTEGER := 4
249 shift_SZ : INTEGER := 4
227 );
250 );
228 PORT(
251 PORT(
229 clk : IN STD_LOGIC;
252 clk : IN STD_LOGIC;
230 reset : IN STD_LOGIC;
253 reset : IN STD_LOGIC;
231 shift : IN STD_LOGIC;
254 shift : IN STD_LOGIC;
232 OP : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
255 OP : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
233 cnt : IN STD_LOGIC_VECTOR(shift_SZ-1 DOWNTO 0);
256 cnt : IN STD_LOGIC_VECTOR(shift_SZ-1 DOWNTO 0);
234 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
257 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
235 );
258 );
236 END COMPONENT;
259 END COMPONENT;
237
260
238 COMPONENT SYNC_FF
261 COMPONENT SYNC_FF
239 GENERIC (
262 GENERIC (
240 NB_FF_OF_SYNC : INTEGER);
263 NB_FF_OF_SYNC : INTEGER);
241 PORT (
264 PORT (
242 clk : IN STD_LOGIC;
265 clk : IN STD_LOGIC;
243 rstn : IN STD_LOGIC;
266 rstn : IN STD_LOGIC;
244 A : IN STD_LOGIC;
267 A : IN STD_LOGIC;
245 A_sync : OUT STD_LOGIC);
268 A_sync : OUT STD_LOGIC);
246 END COMPONENT;
269 END COMPONENT;
247
270
248 END;
271 END;
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@@ -1,612 +1,619
1 -----------------------------------------------------------------------------
1 -----------------------------------------------------------------------------
2 -- LEON3 Demonstration design
2 -- LEON3 Demonstration design
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
7 -- the Free Software Foundation; either version 2 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19
19
20
20
21 library ieee;
21 library ieee;
22 use ieee.std_logic_1164.all;
22 use ieee.std_logic_1164.all;
23 library grlib;
23 library grlib;
24 use grlib.amba.all;
24 use grlib.amba.all;
25 use grlib.stdlib.all;
25 use grlib.stdlib.all;
26 library techmap;
26 library techmap;
27 use techmap.gencomp.all;
27 use techmap.gencomp.all;
28 library gaisler;
28 library gaisler;
29 use gaisler.memctrl.all;
29 use gaisler.memctrl.all;
30 use gaisler.leon3.all;
30 use gaisler.leon3.all;
31 use gaisler.uart.all;
31 use gaisler.uart.all;
32 use gaisler.misc.all;
32 use gaisler.misc.all;
33 library esa;
33 library esa;
34 use esa.memoryctrl.all;
34 use esa.memoryctrl.all;
35 use work.config.all;
35 use work.config.all;
36 library lpp;
36 library lpp;
37 use lpp.lpp_amba.all;
37 use lpp.lpp_amba.all;
38 use lpp.lpp_memory.all;
38 use lpp.lpp_memory.all;
39 use lpp.lpp_uart.all;
39 use lpp.lpp_uart.all;
40 use lpp.lpp_matrix.all;
40 use lpp.lpp_matrix.all;
41 use lpp.lpp_delay.all;
41 use lpp.lpp_delay.all;
42 use lpp.lpp_fft.all;
42 use lpp.lpp_fft.all;
43 use lpp.fft_components.all;
43 use lpp.fft_components.all;
44 use lpp.lpp_ad_conv.all;
44 use lpp.lpp_ad_conv.all;
45 use lpp.iir_filter.all;
45 use lpp.iir_filter.all;
46 use lpp.general_purpose.all;
46 use lpp.general_purpose.all;
47 use lpp.Filtercfg.all;
47 use lpp.Filtercfg.all;
48 use lpp.lpp_demux.all;
49 use lpp.lpp_top_lfr_pkg.all;
48
50
49 entity leon3mp is
51 entity leon3mp is
50 generic (
52 generic (
51 fabtech : integer := CFG_FABTECH;
53 fabtech : integer := CFG_FABTECH;
52 memtech : integer := CFG_MEMTECH;
54 memtech : integer := CFG_MEMTECH;
53 padtech : integer := CFG_PADTECH;
55 padtech : integer := CFG_PADTECH;
54 clktech : integer := CFG_CLKTECH;
56 clktech : integer := CFG_CLKTECH;
55 disas : integer := CFG_DISAS; -- Enable disassembly to console
57 disas : integer := CFG_DISAS; -- Enable disassembly to console
56 dbguart : integer := CFG_DUART; -- Print UART on console
58 dbguart : integer := CFG_DUART; -- Print UART on console
57 pclow : integer := CFG_PCLOW
59 pclow : integer := CFG_PCLOW
58 );
60 );
59 port (
61 port (
60 clk50MHz : in std_ulogic;
62 clk50MHz : in std_ulogic;
61 reset : in std_ulogic;
63 reset : in std_ulogic;
62 ramclk : out std_logic;
64 ramclk : out std_logic;
63
65
64 ahbrxd : in std_ulogic; -- DSU rx data
66 ahbrxd : in std_ulogic; -- DSU rx data
65 ahbtxd : out std_ulogic; -- DSU tx data
67 ahbtxd : out std_ulogic; -- DSU tx data
66 dsubre : in std_ulogic;
68 dsubre : in std_ulogic;
67 dsuact : out std_ulogic;
69 dsuact : out std_ulogic;
68 urxd1 : in std_ulogic; -- UART1 rx data
70 urxd1 : in std_ulogic; -- UART1 rx data
69 utxd1 : out std_ulogic; -- UART1 tx data
71 utxd1 : out std_ulogic; -- UART1 tx data
70 errorn : out std_ulogic;
72 errorn : out std_ulogic;
71
73
72 address : out std_logic_vector(18 downto 0);
74 address : out std_logic_vector(18 downto 0);
73 data : inout std_logic_vector(31 downto 0);
75 data : inout std_logic_vector(31 downto 0);
74 gpio : inout std_logic_vector(6 downto 0); -- I/O port
76 gpio : inout std_logic_vector(6 downto 0); -- I/O port
75
77
76 nBWa : out std_logic;
78 nBWa : out std_logic;
77 nBWb : out std_logic;
79 nBWb : out std_logic;
78 nBWc : out std_logic;
80 nBWc : out std_logic;
79 nBWd : out std_logic;
81 nBWd : out std_logic;
80 nBWE : out std_logic;
82 nBWE : out std_logic;
81 nADSC : out std_logic;
83 nADSC : out std_logic;
82 nADSP : out std_logic;
84 nADSP : out std_logic;
83 nADV : out std_logic;
85 nADV : out std_logic;
84 nGW : out std_logic;
86 nGW : out std_logic;
85 nCE1 : out std_logic;
87 nCE1 : out std_logic;
86 CE2 : out std_logic;
88 CE2 : out std_logic;
87 nCE3 : out std_logic;
89 nCE3 : out std_logic;
88 nOE : out std_logic;
90 nOE : out std_logic;
89 MODE : out std_logic;
91 MODE : out std_logic;
90 SSRAM_CLK : out std_logic;
92 SSRAM_CLK : out std_logic;
91 ZZ : out std_logic;
93 ZZ : out std_logic;
92 ---------------------------------------------------------------------
94 ---------------------------------------------------------------------
93 --- AJOUT TEST ------------------------In/Out-----------------------
95 --- AJOUT TEST ------------------------In/Out-----------------------
94 ---------------------------------------------------------------------
96 ---------------------------------------------------------------------
95 -- UART
97 -- UART
96 UART_RXD : in std_logic;
98 UART_RXD : in std_logic;
97 UART_TXD : out std_logic;
99 UART_TXD : out std_logic;
100 -- ACQ
101 Clk_49Mhz : IN STD_LOGIC;
102 CNV_CH1 : OUT STD_LOGIC;
103 SCK_CH1 : OUT STD_LOGIC;
104 SDO_CH1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
98 -- ADC
105 -- ADC
99 -- ADC_in : in AD7688_in(4 downto 0);
106 -- ADC_in : in AD7688_in(4 downto 0);
100 -- ADC_out : out AD7688_out;
107 -- ADC_out : out AD7688_out;
101 -- Bias_Fails : out std_logic;
108 -- Bias_Fails : out std_logic;
102 -- CNA
109 -- CNA
103 -- DAC_SYNC : out std_logic;
110 -- DAC_SYNC : out std_logic;
104 -- DAC_SCLK : out std_logic;
111 -- DAC_SCLK : out std_logic;
105 -- DAC_DATA : out std_logic;
112 -- DAC_DATA : out std_logic;
106 -- Diver
113 -- Diver
107 SPW1_EN : out std_logic;
114 SPW1_EN : out std_logic;
108 SPW2_EN : out std_logic;
115 SPW2_EN : out std_logic;
109 TEST : out std_logic_vector(3 downto 0);
116 TEST : out std_logic_vector(3 downto 0);
110
117
111 BP : in std_logic;
118 BP : in std_logic;
112 ---------------------------------------------------------------------
119 ---------------------------------------------------------------------
113 led : out std_logic_vector(1 downto 0)
120 led : out std_logic_vector(1 downto 0)
114 );
121 );
115 end;
122 end;
116
123
117 architecture Behavioral of leon3mp is
124 architecture Behavioral of leon3mp is
118
125
119 constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
126 constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
120 CFG_GRETH+CFG_AHB_JTAG;
127 CFG_GRETH+CFG_AHB_JTAG;
121 constant maxahbm : integer := maxahbmsp;
128 constant maxahbm : integer := maxahbmsp;
122
129
123 --Clk & Rst g�n�
130 --Clk & Rst g�n�
124 signal vcc : std_logic_vector(4 downto 0);
131 signal vcc : std_logic_vector(4 downto 0);
125 signal gnd : std_logic_vector(4 downto 0);
132 signal gnd : std_logic_vector(4 downto 0);
126 signal resetnl : std_ulogic;
133 signal resetnl : std_ulogic;
127 signal clk2x : std_ulogic;
134 signal clk2x : std_ulogic;
128 signal lclk : std_ulogic;
135 signal lclk : std_ulogic;
129 signal lclk2x : std_ulogic;
136 signal lclk2x : std_ulogic;
130 signal clkm : std_ulogic;
137 signal clkm : std_ulogic;
131 signal rstn : std_ulogic;
138 signal rstn : std_ulogic;
132 signal rstraw : std_ulogic;
139 signal rstraw : std_ulogic;
133 signal pciclk : std_ulogic;
140 signal pciclk : std_ulogic;
134 signal sdclkl : std_ulogic;
141 signal sdclkl : std_ulogic;
135 signal cgi : clkgen_in_type;
142 signal cgi : clkgen_in_type;
136 signal cgo : clkgen_out_type;
143 signal cgo : clkgen_out_type;
137 --- AHB / APB
144 --- AHB / APB
138 signal apbi : apb_slv_in_type;
145 signal apbi : apb_slv_in_type;
139 signal apbo : apb_slv_out_vector := (others => apb_none);
146 signal apbo : apb_slv_out_vector := (others => apb_none);
140 signal ahbsi : ahb_slv_in_type;
147 signal ahbsi : ahb_slv_in_type;
141 signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
148 signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
142 signal ahbmi : ahb_mst_in_type;
149 signal ahbmi : ahb_mst_in_type;
143 signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
150 signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
144 --UART
151 --UART
145 signal ahbuarti : uart_in_type;
152 signal ahbuarti : uart_in_type;
146 signal ahbuarto : uart_out_type;
153 signal ahbuarto : uart_out_type;
147 signal apbuarti : uart_in_type;
154 signal apbuarti : uart_in_type;
148 signal apbuarto : uart_out_type;
155 signal apbuarto : uart_out_type;
149 --MEM CTRLR
156 --MEM CTRLR
150 signal memi : memory_in_type;
157 signal memi : memory_in_type;
151 signal memo : memory_out_type;
158 signal memo : memory_out_type;
152 signal wpo : wprot_out_type;
159 signal wpo : wprot_out_type;
153 signal sdo : sdram_out_type;
160 signal sdo : sdram_out_type;
154 --IRQ
161 --IRQ
155 signal irqi : irq_in_vector(0 to CFG_NCPU-1);
162 signal irqi : irq_in_vector(0 to CFG_NCPU-1);
156 signal irqo : irq_out_vector(0 to CFG_NCPU-1);
163 signal irqo : irq_out_vector(0 to CFG_NCPU-1);
157 --Timer
164 --Timer
158 signal gpti : gptimer_in_type;
165 signal gpti : gptimer_in_type;
159 signal gpto : gptimer_out_type;
166 signal gpto : gptimer_out_type;
160 --GPIO
167 --GPIO
161 signal gpioi : gpio_in_type;
168 signal gpioi : gpio_in_type;
162 signal gpioo : gpio_out_type;
169 signal gpioo : gpio_out_type;
163 --DSU
170 --DSU
164 signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
171 signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
165 signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
172 signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
166 signal dsui : dsu_in_type;
173 signal dsui : dsu_in_type;
167 signal dsuo : dsu_out_type;
174 signal dsuo : dsu_out_type;
168
175
169 ---------------------------------------------------------------------
176 ---------------------------------------------------------------------
170 --- AJOUT TEST ------------------------Signaux----------------------
177 --- AJOUT TEST ------------------------Signaux----------------------
171 ---------------------------------------------------------------------
178 ---------------------------------------------------------------------
172 -- FIFOs
179 -- FIFOs
173 signal FifoIN_Full : std_logic_vector(4 downto 0);
180 signal FifoF0a_Full : std_logic_vector(4 downto 0);
174 signal FifoIN_Empty : std_logic_vector(4 downto 0);
181 signal FifoF0a_Empty : std_logic_vector(4 downto 0);
175 signal FifoIN_Data : std_logic_vector(79 downto 0);
182 signal FifoF0a_Data : std_logic_vector(79 downto 0);
183 signal FifoF0b_Full : std_logic_vector(4 downto 0);
184 signal FifoF0b_Empty : std_logic_vector(4 downto 0);
185 signal FifoF0b_Data : std_logic_vector(79 downto 0);
186 signal FifoF1_Full : std_logic_vector(4 downto 0);
187 signal FifoF1_Empty : std_logic_vector(4 downto 0);
188 signal FifoF1_Data : std_logic_vector(79 downto 0);
189 signal FifoF3_Full : std_logic_vector(4 downto 0);
190 signal FifoF3_Empty : std_logic_vector(4 downto 0);
191 signal FifoF3_Data : std_logic_vector(79 downto 0);
176
192
177 signal FifoINT_Full : std_logic_vector(4 downto 0);
193 signal FifoINT_Full : std_logic_vector(4 downto 0);
178 signal FifoINT_Data : std_logic_vector(79 downto 0);
194 signal FifoINT_Data : std_logic_vector(79 downto 0);
179
195
180 signal FifoOUT_FullV : std_logic;
196 --signal FifoOUT_FullV : std_logic;
181 signal FifoOUT_Full : std_logic_vector(1 downto 0);
197 signal FifoOUT_Full : std_logic_vector(1 downto 0);
182 signal Matrix_WriteV : std_logic_vector(0 downto 0);
198 --signal Matrix_WriteV : std_logic_vector(0 downto 0);
183
199
184 -- MATRICE SPECTRALE
200 -- MATRICE SPECTRALE
185 signal Matrix_Write : std_logic;
201 signal SM_FlagError : std_logic;
186 signal Matrix_Read : std_logic_vector(1 downto 0);
202 signal SM_Pong : std_logic;
187 signal Matrix_Result : std_logic_vector(31 downto 0);
203 signal SM_Read : std_logic_vector(4 downto 0);
204 signal SM_Write : std_logic_vector(1 downto 0);
205 signal SM_Data : std_logic_vector(63 downto 0);
188
206
189 signal TopSM_Start : std_logic;
207 signal Dma_acq : std_logic;
190 signal TopSM_Statu : std_logic_vector(3 downto 0);
191 signal TopSM_Read : std_logic_vector(4 downto 0);
192 signal TopSM_Data1 : std_logic_vector(15 downto 0);
193 signal TopSM_Data2 : std_logic_vector(15 downto 0);
194
195 signal Disp_FlagError : std_logic;
196 signal Disp_Pong : std_logic;
197 signal Disp_Write : std_logic_vector(1 downto 0);--
198 signal Disp_Data : std_logic_vector(63 downto 0);--
199 signal Dma_acq : std_logic;
200
208
201 -- FFT
209 -- FFT
202 signal Drive_Write : std_logic;
210 signal FFT_Read : std_logic_vector(4 downto 0);
203 signal Drive_Read : std_logic_vector(4 downto 0);
211 signal FFT_Write : std_logic_vector(4 downto 0);
204 signal Drive_DataRE : std_logic_vector(15 downto 0);
212 signal FFT_ReUse : std_logic_vector(4 downto 0);
205 signal Drive_DataIM : std_logic_vector(15 downto 0);
213 signal FFT_Data : std_logic_vector(79 downto 0);
206
214
207 signal Start : std_logic;
215 -- DEMUX
208 signal RstnFFT : std_logic;
216 signal DEMU_Read : std_logic_vector(19 downto 0);
209 signal FFT_Load : std_logic;
217 signal DEMU_Empty : std_logic_vector(4 downto 0);
210 signal FFT_Ready : std_logic;
218 signal DEMU_Data : std_logic_vector(79 downto 0);
211 signal FFT_Valid : std_logic;
212 signal FFT_DataRE : std_logic_vector(15 downto 0);
213 signal FFT_DataIM : std_logic_vector(15 downto 0);
214
219
215 signal Link_Read : std_logic;
220 -- ACQ
216 signal Link_Write : std_logic_vector(4 downto 0);
221 signal TopACQ_WenF0a : STD_LOGIC_VECTOR(4 DOWNTO 0);
217 signal Link_ReUse : std_logic_vector(4 downto 0);
222 signal TopACQ_WenF0b : STD_LOGIC_VECTOR(4 DOWNTO 0);
218 signal Link_Data : std_logic_vector(79 downto 0);
223 signal TopACQ_DataF0 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
224 signal TopACQ_WenF1 : STD_LOGIC_VECTOR(4 DOWNTO 0);
225 signal TopACQ_DataF1 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
226 signal TopACQ_WenF3 : STD_LOGIC_VECTOR(4 DOWNTO 0);
227 signal TopACQ_DataF3 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
219
228
220 -- ADC
229 -- ADC
221 signal SmplClk : std_logic;
230 --signal SmplClk : std_logic;
222 signal ADC_DataReady : std_logic;
231 --signal ADC_DataReady : std_logic;
223 signal ADC_SmplOut : Samples_out(4 downto 0);
232 --signal ADC_SmplOut : Samples_out(4 downto 0);
224 signal enableADC : std_logic;
233 --signal enableADC : std_logic;
225
234 --
226 signal WG_Write : std_logic_vector(4 downto 0);
235 --signal WG_Write : std_logic_vector(4 downto 0);
227 signal WG_ReUse : std_logic_vector(4 downto 0);
236 --signal WG_ReUse : std_logic_vector(4 downto 0);
228 signal WG_DATA : std_logic_vector(79 downto 0);
237 --signal WG_DATA : std_logic_vector(79 downto 0);
229 signal s_out : std_logic_vector(79 downto 0);
238 --signal s_out : std_logic_vector(79 downto 0);
230
239 --
231 signal fuller : std_logic_vector(4 downto 0);
240 --signal fuller : std_logic_vector(4 downto 0);
232 signal reader : std_logic_vector(4 downto 0);
241 --signal reader : std_logic_vector(4 downto 0);
233 signal try : std_logic_vector(1 downto 0);
242 --signal try : std_logic_vector(1 downto 0);
234 signal TXDint : std_logic;
243 --signal TXDint : std_logic;
235
244 --
236 -- IIR Filter
245 ---- IIR Filter
237 signal sample_clk_out : std_logic;
246 --signal sample_clk_out : std_logic;
238
247 --
239 signal Rd : std_logic_vector(0 downto 0);
248 --signal Rd : std_logic_vector(0 downto 0);
240 signal Ept : std_logic_vector(4 downto 0);
249 --signal Ept : std_logic_vector(4 downto 0);
241
250 --
242 signal Bwr : std_logic_vector(0 downto 0);
251 --signal Bwr : std_logic_vector(0 downto 0);
243 signal Bre : std_logic_vector(0 downto 0);
252 --signal Bre : std_logic_vector(0 downto 0);
244 signal DataTMP : std_logic_vector(15 downto 0);
253 --signal DataTMP : std_logic_vector(15 downto 0);
245 signal FullUp : std_logic_vector(0 downto 0);
254 --signal FullUp : std_logic_vector(0 downto 0);
246 signal EmptyUp : std_logic_vector(0 downto 0);
255 --signal EmptyUp : std_logic_vector(0 downto 0);
247 signal FullDown : std_logic_vector(0 downto 0);
256 --signal FullDown : std_logic_vector(0 downto 0);
248 signal EmptyDown : std_logic_vector(0 downto 0);
257 --signal EmptyDown : std_logic_vector(0 downto 0);
249 ---------------------------------------------------------------------
258 ---------------------------------------------------------------------
250 constant IOAEN : integer := CFG_CAN;
259 constant IOAEN : integer := CFG_CAN;
251 constant boardfreq : integer := 50000;
260 constant boardfreq : integer := 50000;
252
261
253 begin
262 begin
254
263
255 ---------------------------------------------------------------------
264 ---------------------------------------------------------------------
256 --- AJOUT TEST -------------------------------------IPs-------------
265 --- AJOUT TEST -------------------------------------IPs-------------
257 ---------------------------------------------------------------------
266 ---------------------------------------------------------------------
258 led(1 downto 0) <= gpio(1 downto 0);
267 led(1 downto 0) <= gpio(1 downto 0);
259
268
260 --- COM USB ---------------------------------------------------------
269 --- COM USB ---------------------------------------------------------
261 -- MemIn0 : APB_FifoWrite
270 -- MemIn0 : APB_FifoWrite
262 -- generic map (5,5, Data_sz => 8, Addr_sz => 8, addr_max_int => 256)
271 -- generic map (5,5, Data_sz => 8, Addr_sz => 8, addr_max_int => 256)
263 -- port map (clkm,rstn,apbi,USB_Read,open,open,InOutData,apbo(5));
272 -- port map (clkm,rstn,apbi,USB_Read,open,open,InOutData,apbo(5));
264 --
273 --
265 -- BUF0 : APB_USB
274 -- BUF0 : APB_USB
266 -- generic map (6,6,DataMax => 1024)
275 -- generic map (6,6,DataMax => 1024)
267 -- port map(clkm,rstn,flagC,flagB,ifclk,sloe,USB_Read,USB_Write,pktend,fifoadr,InOutData,apbi,apbo(6));
276 -- port map(clkm,rstn,flagC,flagB,ifclk,sloe,USB_Read,USB_Write,pktend,fifoadr,InOutData,apbi,apbo(6));
268 --
277 --
269 -- MemOut0 : APB_FifoRead
278 -- MemOut0 : APB_FifoRead
270 -- generic map (7,7, Data_sz => 8, Addr_sz => 8, addr_max_int => 256)
279 -- generic map (7,7, Data_sz => 8, Addr_sz => 8, addr_max_int => 256)
271 -- port map (clkm,rstn,apbi,USB_Write,open,open,InOutData,apbo(7));
280 -- port map (clkm,rstn,apbi,USB_Write,open,open,InOutData,apbo(7));
272 --
281 --
273 --slrd <= usb_Read;
282 --slrd <= usb_Read;
274 --slwr <= usb_Write;
283 --slwr <= usb_Write;
275
284
276 --- CNA -------------------------------------------------------------
285 --- CNA -------------------------------------------------------------
277
286
278 -- CONV : APB_CNA
287 -- CONV : APB_CNA
279 -- generic map (5,5)
288 -- generic map (5,5)
280 -- port map(clkm,rstn,apbi,apbo(5),DAC_SYNC,DAC_SCLK,DAC_DATA);
289 -- port map(clkm,rstn,apbi,apbo(5),DAC_SYNC,DAC_SCLK,DAC_DATA);
281
290
282 --TEST(0) <= SmplClk;
291 --TEST(0) <= SmplClk;
283 --TEST(1) <= WG_Write(0);
292 --TEST(1) <= WG_Write(0);
284 --TEST(2) <= Fuller(0);
293 --TEST(2) <= Fuller(0);
285 --TEST(3) <= s_out(s_out'length-1);
294 --TEST(3) <= s_out(s_out'length-1);
286
295
287
296
288 --SPW1_EN <= '1';
297 --SPW1_EN <= '1';
289 --SPW2_EN <= '0';
298 --SPW2_EN <= '0';
290
299
291 --- CAN -------------------------------------------------------------
300 --- CAN -------------------------------------------------------------
292
301
293 -- Divider : Clk_divider
302 -- Divider : Clk_divider
294 -- generic map(OSC_freqHz => 24_576_000, TargetFreq_Hz => 24_576)
303 -- generic map(OSC_freqHz => 24_576_000, TargetFreq_Hz => 24_576)
295 -- Port map(clkm,rstn,SmplClk);
304 -- Port map(clkm,rstn,SmplClk);
296 --
305 --
297 -- ADC : AD7688_drvr
306 -- ADC : AD7688_drvr
298 -- generic map (ChanelCount => 5, clkkHz => 24_576)
307 -- generic map (ChanelCount => 5, clkkHz => 24_576)
299 -- port map (clkm,rstn,enableADC,SmplClk,ADC_DataReady,ADC_SmplOut,ADC_in,ADC_out);
308 -- port map (clkm,rstn,enableADC,SmplClk,ADC_DataReady,ADC_SmplOut,ADC_in,ADC_out);
300 --
309 --
301 -- WG : WriteGen_ADC
310 -- WG : WriteGen_ADC
302 -- port map (clkm,rstn,SmplClk,ADC_DataReady,Fuller,WG_ReUse,WG_Write);
311 -- port map (clkm,rstn,SmplClk,ADC_DataReady,Fuller,WG_ReUse,WG_Write);
303 --
312 --
304 --enableADC <= gpio(0);
313 --enableADC <= gpio(0);
305 --Bias_Fails <= '0';
314 --Bias_Fails <= '0';
306 --WG_DATA <= ADC_SmplOut(4) & ADC_SmplOut(3) & ADC_SmplOut(2) & ADC_SmplOut(1) & ADC_SmplOut(0);
315 --WG_DATA <= ADC_SmplOut(4) & ADC_SmplOut(3) & ADC_SmplOut(2) & ADC_SmplOut(1) & ADC_SmplOut(0);
307 --
316 --
308 --
317 --
309 -- MemIn1 : APB_FIFO
318 -- MemIn1 : APB_FIFO
310 -- generic map (pindex => 6, paddr => 6, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
319 -- generic map (pindex => 6, paddr => 6, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
311 -- port map (clkm,rstn,clkm,clkm,WG_ReUse,(others => '1'),WG_Write,open,Fuller,open,WG_DATA,open,open,apbi,apbo(6));
320 -- port map (clkm,rstn,clkm,clkm,WG_ReUse,(others => '1'),WG_Write,open,Fuller,open,WG_DATA,open,open,apbi,apbo(6));
321
322 TopACQ : lpp_top_acq
323 port map('1',CNV_CH1,SCK_CH1,SDO_CH1,Clk_49Mhz,rstn,clkm,rstn,TopACQ_WenF0a,TopACQ_WenF0b,TopACQ_DataF0,TopACQ_WenF1,TopACQ_DataF1,open,open,TopACQ_WenF3,TopACQ_DataF3);
324
325 --- FIFO IN -------------------------------------------------------------
326
327 Memf0a : lppFIFOxN
328 generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '0')
329 port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF0a,DEMU_Read(4 downto 0),TopACQ_DataF0,FifoF0a_Data,FifoF0a_Full,FifoF0a_Empty);
330
331 Memf0b : lppFIFOxN
332 generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '0')
333 port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF0b,DEMU_Read(9 downto 5),TopACQ_DataF0,FifoF0b_Data,FifoF0b_Full,FifoF0b_Empty);
334
335 Memf1 : lppFIFOxN
336 generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '0')
337 port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF1,DEMU_Read(14 downto 10),TopACQ_DataF1,FifoF1_Data,FifoF1_Full,FifoF1_Empty);
338
339 Memf3 : lppFIFOxN
340 generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '0')
341 port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF3,DEMU_Read(19 downto 15),TopACQ_DataF3,FifoF3_Data,FifoF3_Full,FifoF3_Empty);
342
343 --- DEMUX -------------------------------------------------------------
344
345 DEMUX0 : Demultiplex
346 generic map(Data_sz => 16)
347 port map(clkm,rstn,FFT_Read,FifoF0a_Empty,FifoF0b_Empty,FifoF1_Empty,FifoF3_Empty,FifoF0a_Data,FifoF0b_Data,FifoF1_Data,FifoF3_Data,DEMU_Read,DEMU_Empty,DEMU_Data);
312
348
313 --- FFT -------------------------------------------------------------
349 --- FFT -------------------------------------------------------------
314
350
315 MemIn : APB_FIFO
351 -- MemIn : APB_FIFO
316 generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1)
352 -- generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1)
317 port map (clkm,rstn,clkm,clkm,(others => '0'),Drive_Read,(others => '1'),FifoIN_Empty,FifoIN_Full,FifoIN_Data,(others => '0'),open,open,apbi,apbo(8));
353 -- port map (clkm,rstn,clkm,clkm,(others => '0'),FFT_Read,(others => '1'),FifoIN_Empty,FifoIN_Full,FifoIN_Data,(others => '0'),open,open,apbi,apbo(8));
318
319 DRIVE : Driver_FFT
320 generic map(Data_sz => 16)
321 port map(clkm,rstn,FFT_Load,FifoIN_Empty,FifoIN_Data,Drive_Write,Drive_Read,Drive_DataRE,Drive_DataIM);
322
354
323 Start <= '0';
355 FFT0 : FFT
324
356 generic map(Data_sz => 16,NbData => 256)
325 FFT : CoreFFT
357 port map(clkm,rstn,DEMU_Empty,DEMU_Data,FifoINT_Full,FFT_Read,FFT_Write,FFT_ReUse,FFT_Data);
326 generic map(
327 LOGPTS => gLOGPTS,
328 LOGLOGPTS => gLOGLOGPTS,
329 WSIZE => gWSIZE,
330 TWIDTH => gTWIDTH,
331 DWIDTH => gDWIDTH,
332 TDWIDTH => gTDWIDTH,
333 RND_MODE => gRND_MODE,
334 SCALE_MODE => gSCALE_MODE,
335 PTS => gPTS,
336 HALFPTS => gHALFPTS,
337 inBuf_RWDLY => gInBuf_RWDLY)
338 port map(clkm,start,rstn,Drive_Write,Link_Read,Drive_DataIM,Drive_DataRE,FFT_Load,open,FFT_DataIM,FFT_DataRE,FFT_Valid,FFT_Ready);
339
340 LINK : Linker_FFT
341 generic map(Data_sz => 16)
342 port map(clkm,rstn,FFT_Ready,FFT_Valid,FifoINT_Full,FFT_DataRE,FFT_DataIM,Link_Read,Link_Write,Link_ReUse,Link_Data);
343
358
344 ----- LINK MEMORY -------------------------------------------------------
359 ----- LINK MEMORY -------------------------------------------------------
345
360
346 -- MemOut : APB_FIFO
361 -- MemOut : APB_FIFO
347 -- generic map (pindex => 9, paddr => 9, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 0)
362 -- generic map (pindex => 9, paddr => 9, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 0)
348 -- port map (clkm,rstn,clkm,clkm,Link_ReUse,(others =>'1'),Link_Write,Ept,FifoOUT_Full,open,Link_Data,open,open,apbi,apbo(9));
363 -- port map (clkm,rstn,clkm,clkm,Link_ReUse,(others =>'1'),Link_Write,Ept,FifoOUT_Full,open,Link_Data,open,open,apbi,apbo(9));
349
364
350 MemInt : lppFIFOxN
365 MemInt : lppFIFOxN
351 generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '1')
366 generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '1')
352 port map(rstn,clkm,clkm,Link_ReUse,Link_Write,TopSM_Read,Link_Data,FifoINT_Data,FifoINT_Full,open);
367 port map(rstn,clkm,clkm,FFT_ReUse,FFT_Write,SM_Read,FFT_Data,FifoINT_Data,FifoINT_Full,open);
353
368
354 -- MemIn : APB_FIFO
369 -- MemIn : APB_FIFO
355 -- generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 0, W => 1)
370 -- generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 0, W => 1)
356 -- port map (clkm,rstn,clkm,clkm,(others => '0'),TopSM_Read,(others => '1'),open,FifoINT_Full,FifoINT_Data,(others => '0'),open,open,apbi,apbo(8));
371 -- port map (clkm,rstn,clkm,clkm,(others => '0'),TopSM_Read,(others => '1'),open,FifoINT_Full,FifoINT_Data,(others => '0'),open,open,apbi,apbo(8));
357
372
358 ----- MATRICE SPECTRALE ---------------------5 FIFO Input---------------
373 ----- MATRICE SPECTRALE ---------------------5 FIFO Input---------------
359
374
360 TopSM : TopSpecMatrix
375 SM0 : MatriceSpectrale
361 generic map (Input_SZ => 16)
376 generic map(Input_SZ => 16,Result_SZ => 32)
362 port map(clkm,rstn,Matrix_Write,Matrix_Read,FifoINT_Full,FifoINT_Data,TopSM_Start,TopSM_Read,TopSM_Statu,TopSM_Data1,TopSM_Data2);
377 port map(clkm,rstn,FifoINT_Full,FifoOUT_Full,FifoINT_Data,Dma_acq,SM_FlagError,SM_Pong,SM_Write,SM_Read,SM_Data);
363
364 SM : SpectralMatrix
365 generic map (Input_SZ => 16, Result_SZ => 32)
366 port map(clkm,rstn,TopSM_Start,TopSM_Data1,TopSM_Data2,TopSM_Statu,Matrix_Read,Matrix_Write,Matrix_Result);
367
378
368 Dma_acq <= '1';
379 Dma_acq <= '1';
369
370 DISP : Dispatch
371 generic map(Data_SZ => 32)
372 port map(clkm,rstn,Dma_acq,Matrix_Result,Matrix_Write,FifoOUT_Full,Disp_Data,Disp_Write,Disp_Pong,Disp_FlagError);
373
380
374 MemOut : APB_FIFO
381 MemOut : APB_FIFO
375 generic map (pindex => 9, paddr => 9, FifoCnt => 2, Data_sz => 32, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
382 generic map (pindex => 9, paddr => 9, FifoCnt => 2, Data_sz => 32, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
376 port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),Disp_Write,open,FifoOUT_Full,open,Disp_Data,open,open,apbi,apbo(9));
383 port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),SM_Write,open,FifoOUT_Full,open,SM_Data,open,open,apbi,apbo(9));
377
384
378 ----- FIFO -------------------------------------------------------------
385 ----- FIFO -------------------------------------------------------------
379
386
380 Memtest : APB_FIFO
387 Memtest : APB_FIFO
381 generic map (pindex => 5, paddr => 5, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 1)
388 generic map (pindex => 5, paddr => 5, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 1)
382 port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),(others => '1'),open,open,open,(others => '0'),open,open,apbi,apbo(5));
389 port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),(others => '1'),open,open,open,(others => '0'),open,open,apbi,apbo(5));
383
390
384 --***************************************TEST DEMI-FIFO********************************************************************************
391 --***************************************TEST DEMI-FIFO********************************************************************************
385 -- MemIn : APB_FIFO
392 -- MemIn : APB_FIFO
386 -- generic map (pindex => 8, paddr => 8, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1)
393 -- generic map (pindex => 8, paddr => 8, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1)
387 -- port map (clkm,rstn,clkm,clkm,(others => '0'),Bre,(others => '1'),EmptyUp,FullUp,DataTMP,(others => '0'),open,open,apbi,apbo(8));
394 -- port map (clkm,rstn,clkm,clkm,(others => '0'),Bre,(others => '1'),EmptyUp,FullUp,DataTMP,(others => '0'),open,open,apbi,apbo(8));
388 --
395 --
389 -- Pont : Bridge
396 -- Pont : Bridge
390 -- port map(clkm,rstn,EmptyUp(0),FullDown(0),Bwr(0),Bre(0));
397 -- port map(clkm,rstn,EmptyUp(0),FullDown(0),Bwr(0),Bre(0));
391 --
398 --
392 -- MemOut : APB_FIFO
399 -- MemOut : APB_FIFO
393 -- generic map (pindex => 9, paddr => 9, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
400 -- generic map (pindex => 9, paddr => 9, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
394 -- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),Bwr,EmptyDown,FullDown,open,DataTMP,open,open,apbi,apbo(9));
401 -- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),Bwr,EmptyDown,FullDown,open,DataTMP,open,open,apbi,apbo(9));
395 --*************************************************************************************************************************************
402 --*************************************************************************************************************************************
396
403
397 --- UART -------------------------------------------------------------
404 --- UART -------------------------------------------------------------
398
405
399 COM0 : APB_UART
406 COM0 : APB_UART
400 generic map (pindex => 4, paddr => 4)
407 generic map (pindex => 4, paddr => 4)
401 port map (clkm,rstn,apbi,apbo(4),UART_TXD,UART_RXD);
408 port map (clkm,rstn,apbi,apbo(4),UART_TXD,UART_RXD);
402
409
403 --- DELAY ------------------------------------------------------------
410 --- DELAY ------------------------------------------------------------
404
411
405 -- Delay0 : APB_Delay
412 -- Delay0 : APB_Delay
406 -- generic map (pindex => 4, paddr => 4)
413 -- generic map (pindex => 4, paddr => 4)
407 -- port map (clkm,rstn,apbi,apbo(4));
414 -- port map (clkm,rstn,apbi,apbo(4));
408
415
409 --- IIR Filter -------------------------------------------------------
416 --- IIR Filter -------------------------------------------------------
410 --Test(0) <= sample_clk_out;
417 --Test(0) <= sample_clk_out;
411 --
418 --
412 --
419 --
413 -- IIR1: APB_IIR_Filter
420 -- IIR1: APB_IIR_Filter
414 -- generic map(
421 -- generic map(
415 -- tech => CFG_MEMTECH,
422 -- tech => CFG_MEMTECH,
416 -- pindex => 8,
423 -- pindex => 8,
417 -- paddr => 8,
424 -- paddr => 8,
418 -- Sample_SZ => Sample_SZ,
425 -- Sample_SZ => Sample_SZ,
419 -- ChanelsCount => ChanelsCount,
426 -- ChanelsCount => ChanelsCount,
420 -- Coef_SZ => Coef_SZ,
427 -- Coef_SZ => Coef_SZ,
421 -- CoefCntPerCel => CoefCntPerCel,
428 -- CoefCntPerCel => CoefCntPerCel,
422 -- Cels_count => Cels_count,
429 -- Cels_count => Cels_count,
423 -- virgPos => virgPos
430 -- virgPos => virgPos
424 -- )
431 -- )
425 -- port map(
432 -- port map(
426 -- rst => rstn,
433 -- rst => rstn,
427 -- clk => clkm,
434 -- clk => clkm,
428 -- apbi => apbi,
435 -- apbi => apbi,
429 -- apbo => apbo(8),
436 -- apbo => apbo(8),
430 -- sample_clk_out => sample_clk_out,
437 -- sample_clk_out => sample_clk_out,
431 -- GOtest => Test(1),
438 -- GOtest => Test(1),
432 -- CoefsInitVal => (others => '1')
439 -- CoefsInitVal => (others => '1')
433 -- );
440 -- );
434 ----------------------------------------------------------------------
441 ----------------------------------------------------------------------
435
442
436 ----------------------------------------------------------------------
443 ----------------------------------------------------------------------
437 --- Reset and Clock generation -------------------------------------
444 --- Reset and Clock generation -------------------------------------
438 ----------------------------------------------------------------------
445 ----------------------------------------------------------------------
439
446
440 vcc <= (others => '1'); gnd <= (others => '0');
447 vcc <= (others => '1'); gnd <= (others => '0');
441 cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
448 cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
442
449
443 rst0 : rstgen port map (reset, clkm, cgo.clklock, rstn, rstraw);
450 rst0 : rstgen port map (reset, clkm, cgo.clklock, rstn, rstraw);
444
451
445
452
446 clk_pad : clkpad generic map (tech => padtech) port map (clk50MHz, lclk2x);
453 clk_pad : clkpad generic map (tech => padtech) port map (clk50MHz, lclk2x);
447
454
448 clkgen0 : clkgen -- clock generator
455 clkgen0 : clkgen -- clock generator
449 generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
456 generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
450 CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV)
457 CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV)
451 port map (lclk, lclk, clkm, open, clk2x, sdclkl, pciclk, cgi, cgo);
458 port map (lclk, lclk, clkm, open, clk2x, sdclkl, pciclk, cgi, cgo);
452
459
453 ramclk <= clkm;
460 ramclk <= clkm;
454 process(lclk2x)
461 process(lclk2x)
455 begin
462 begin
456 if lclk2x'event and lclk2x = '1' then
463 if lclk2x'event and lclk2x = '1' then
457 lclk <= not lclk;
464 lclk <= not lclk;
458 end if;
465 end if;
459 end process;
466 end process;
460
467
461 ----------------------------------------------------------------------
468 ----------------------------------------------------------------------
462 --- LEON3 processor / DSU / IRQ ------------------------------------
469 --- LEON3 processor / DSU / IRQ ------------------------------------
463 ----------------------------------------------------------------------
470 ----------------------------------------------------------------------
464
471
465 l3 : if CFG_LEON3 = 1 generate
472 l3 : if CFG_LEON3 = 1 generate
466 cpu : for i in 0 to CFG_NCPU-1 generate
473 cpu : for i in 0 to CFG_NCPU-1 generate
467 u0 : leon3s -- LEON3 processor
474 u0 : leon3s -- LEON3 processor
468 generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
475 generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
469 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
476 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
470 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
477 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
471 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
478 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
472 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
479 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
473 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
480 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
474 port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
481 port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
475 irqi(i), irqo(i), dbgi(i), dbgo(i));
482 irqi(i), irqo(i), dbgi(i), dbgo(i));
476 end generate;
483 end generate;
477 errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
484 errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
478
485
479 dsugen : if CFG_DSU = 1 generate
486 dsugen : if CFG_DSU = 1 generate
480 dsu0 : dsu3 -- LEON3 Debug Support Unit
487 dsu0 : dsu3 -- LEON3 Debug Support Unit
481 generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
488 generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
482 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
489 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
483 port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
490 port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
484 -- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
491 -- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
485 dsui.enable <= '1';
492 dsui.enable <= '1';
486 dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
493 dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
487 dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
494 dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
488 end generate;
495 end generate;
489 end generate;
496 end generate;
490
497
491 nodsu : if CFG_DSU = 0 generate
498 nodsu : if CFG_DSU = 0 generate
492 ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
499 ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
493 end generate;
500 end generate;
494
501
495 irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
502 irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
496 irqctrl0 : irqmp -- interrupt controller
503 irqctrl0 : irqmp -- interrupt controller
497 generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
504 generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
498 port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
505 port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
499 end generate;
506 end generate;
500 irq3 : if CFG_IRQ3_ENABLE = 0 generate
507 irq3 : if CFG_IRQ3_ENABLE = 0 generate
501 x : for i in 0 to CFG_NCPU-1 generate
508 x : for i in 0 to CFG_NCPU-1 generate
502 irqi(i).irl <= "0000";
509 irqi(i).irl <= "0000";
503 end generate;
510 end generate;
504 apbo(2) <= apb_none;
511 apbo(2) <= apb_none;
505 end generate;
512 end generate;
506
513
507 ----------------------------------------------------------------------
514 ----------------------------------------------------------------------
508 --- Memory controllers ---------------------------------------------
515 --- Memory controllers ---------------------------------------------
509 ----------------------------------------------------------------------
516 ----------------------------------------------------------------------
510
517
511 memctrlr : mctrl generic map (hindex => 0,pindex => 0, paddr => 0)
518 memctrlr : mctrl generic map (hindex => 0,pindex => 0, paddr => 0)
512 port map (rstn, clkm, memi, memo, ahbsi, ahbso(0),apbi,apbo(0),wpo, sdo);
519 port map (rstn, clkm, memi, memo, ahbsi, ahbso(0),apbi,apbo(0),wpo, sdo);
513
520
514 memi.brdyn <= '1'; memi.bexcn <= '1';
521 memi.brdyn <= '1'; memi.bexcn <= '1';
515 memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10";
522 memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10";
516
523
517 bdr : for i in 0 to 3 generate
524 bdr : for i in 0 to 3 generate
518 data_pad : iopadv generic map (tech => padtech, width => 8)
525 data_pad : iopadv generic map (tech => padtech, width => 8)
519 port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
526 port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
520 memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
527 memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
521 end generate;
528 end generate;
522
529
523
530
524 addr_pad : outpadv generic map (width => 19, tech => padtech)
531 addr_pad : outpadv generic map (width => 19, tech => padtech)
525 port map (address, memo.address(20 downto 2));
532 port map (address, memo.address(20 downto 2));
526
533
527
534
528 SSRAM_0:entity ssram_plugin
535 SSRAM_0:entity ssram_plugin
529 generic map (tech => padtech)
536 generic map (tech => padtech)
530 port map
537 port map
531 (lclk2x,memo,SSRAM_CLK,nBWa,nBWb,nBWc,nBWd,nBWE,nADSC,nADSP,nADV,nGW,nCE1,CE2,nCE3,nOE,MODE,ZZ);
538 (lclk2x,memo,SSRAM_CLK,nBWa,nBWb,nBWc,nBWd,nBWE,nADSC,nADSP,nADV,nGW,nCE1,CE2,nCE3,nOE,MODE,ZZ);
532
539
533 ----------------------------------------------------------------------
540 ----------------------------------------------------------------------
534 --- AHB CONTROLLER -------------------------------------------------
541 --- AHB CONTROLLER -------------------------------------------------
535 ----------------------------------------------------------------------
542 ----------------------------------------------------------------------
536
543
537 ahb0 : ahbctrl -- AHB arbiter/multiplexer
544 ahb0 : ahbctrl -- AHB arbiter/multiplexer
538 generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
545 generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
539 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
546 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
540 ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
547 ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
541 port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
548 port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
542
549
543 ----------------------------------------------------------------------
550 ----------------------------------------------------------------------
544 --- AHB UART -------------------------------------------------------
551 --- AHB UART -------------------------------------------------------
545 ----------------------------------------------------------------------
552 ----------------------------------------------------------------------
546
553
547 dcomgen : if CFG_AHB_UART = 1 generate
554 dcomgen : if CFG_AHB_UART = 1 generate
548 dcom0: ahbuart -- Debug UART
555 dcom0: ahbuart -- Debug UART
549 generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
556 generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
550 port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
557 port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
551 dsurx_pad : inpad generic map (tech => padtech) port map (ahbrxd, ahbuarti.rxd);
558 dsurx_pad : inpad generic map (tech => padtech) port map (ahbrxd, ahbuarti.rxd);
552 dsutx_pad : outpad generic map (tech => padtech) port map (ahbtxd, ahbuarto.txd);
559 dsutx_pad : outpad generic map (tech => padtech) port map (ahbtxd, ahbuarto.txd);
553 -- led(0) <= not ahbuarti.rxd; led(1) <= not ahbuarto.txd;
560 -- led(0) <= not ahbuarti.rxd; led(1) <= not ahbuarto.txd;
554 end generate;
561 end generate;
555 nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
562 nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
556
563
557 ----------------------------------------------------------------------
564 ----------------------------------------------------------------------
558 --- APB Bridge -----------------------------------------------------
565 --- APB Bridge -----------------------------------------------------
559 ----------------------------------------------------------------------
566 ----------------------------------------------------------------------
560
567
561 apb0 : apbctrl -- AHB/APB bridge
568 apb0 : apbctrl -- AHB/APB bridge
562 generic map (hindex => 1, haddr => CFG_APBADDR)
569 generic map (hindex => 1, haddr => CFG_APBADDR)
563 port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
570 port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
564
571
565 ----------------------------------------------------------------------
572 ----------------------------------------------------------------------
566 --- GPT Timer ------------------------------------------------------
573 --- GPT Timer ------------------------------------------------------
567 ----------------------------------------------------------------------
574 ----------------------------------------------------------------------
568
575
569 gpt : if CFG_GPT_ENABLE /= 0 generate
576 gpt : if CFG_GPT_ENABLE /= 0 generate
570 timer0 : gptimer -- timer unit
577 timer0 : gptimer -- timer unit
571 generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
578 generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
572 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
579 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
573 nbits => CFG_GPT_TW)
580 nbits => CFG_GPT_TW)
574 port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
581 port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
575 gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
582 gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
576 -- led(4) <= gpto.wdog;
583 -- led(4) <= gpto.wdog;
577 end generate;
584 end generate;
578 notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
585 notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
579
586
580
587
581 ----------------------------------------------------------------------
588 ----------------------------------------------------------------------
582 --- APB UART -------------------------------------------------------
589 --- APB UART -------------------------------------------------------
583 ----------------------------------------------------------------------
590 ----------------------------------------------------------------------
584
591
585 ua1 : if CFG_UART1_ENABLE /= 0 generate
592 ua1 : if CFG_UART1_ENABLE /= 0 generate
586 uart1 : apbuart -- UART 1
593 uart1 : apbuart -- UART 1
587 generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
594 generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
588 fifosize => CFG_UART1_FIFO)
595 fifosize => CFG_UART1_FIFO)
589 port map (rstn, clkm, apbi, apbo(1), ahbuarti, apbuarto);
596 port map (rstn, clkm, apbi, apbo(1), ahbuarti, apbuarto);
590 apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd;
597 apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd;
591 apbuarti.ctsn <= '0'; --rtsn1 <= apbuarto.rtsn;
598 apbuarti.ctsn <= '0'; --rtsn1 <= apbuarto.rtsn;
592 -- led(0) <= not apbuarti.rxd; led(1) <= not apbuarto.txd;
599 -- led(0) <= not apbuarti.rxd; led(1) <= not apbuarto.txd;
593 end generate;
600 end generate;
594 noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
601 noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
595
602
596 ----------------------------------------------------------------------
603 ----------------------------------------------------------------------
597 --- GPIO -----------------------------------------------------------
604 --- GPIO -----------------------------------------------------------
598 ----------------------------------------------------------------------
605 ----------------------------------------------------------------------
599
606
600 gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
607 gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
601 grgpio0: grgpio
608 grgpio0: grgpio
602 generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 7)
609 generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 7)
603 port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
610 port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
604
611
605 pio_pads : for i in 0 to 6 generate
612 pio_pads : for i in 0 to 6 generate
606 pio_pad : iopad generic map (tech => padtech)
613 pio_pad : iopad generic map (tech => padtech)
607 port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
614 port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
608 end generate;
615 end generate;
609 end generate;
616 end generate;
610
617
611
618
612 end Behavioral; No newline at end of file
619 end Behavioral;
Show file before | Show file after | Hide comments
@@ -1,65 +1,81
1 -- WatchFlag.vhd
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
2 library IEEE;
22 library IEEE;
3 use IEEE.std_logic_1164.all;
23 use IEEE.std_logic_1164.all;
4 use IEEE.numeric_std.all;
24 use IEEE.numeric_std.all;
5
25
6 entity WatchFlag is
26 entity WatchFlag is
7 port(
27 port(
8 clk : in std_logic;
28 clk : in std_logic;
9 rstn : in std_logic;
29 rstn : in std_logic;
10
30
11 FullF0a : in std_logic_vector(4 downto 0);
12 FullF0b : in std_logic_vector(4 downto 0);
13 FullF1 : in std_logic_vector(4 downto 0);
14 FullF2 : in std_logic_vector(4 downto 0);
15
16 EmptyF0a : in std_logic_vector(4 downto 0);
31 EmptyF0a : in std_logic_vector(4 downto 0);
17 EmptyF0b : in std_logic_vector(4 downto 0);
32 EmptyF0b : in std_logic_vector(4 downto 0);
18 EmptyF1 : in std_logic_vector(4 downto 0);
33 EmptyF1 : in std_logic_vector(4 downto 0);
19 EmptyF2 : in std_logic_vector(4 downto 0);
34 EmptyF2 : in std_logic_vector(4 downto 0);
20
35
21 DataCpt : out std_logic_vector(3 downto 0) -- f2 f1 f0b f0a
36 DataCpt : out std_logic_vector(3 downto 0) -- f2 f1 f0b f0a
22 );
37 );
23 end entity;
38 end entity;
24
39
25
40
26 architecture ar_WatchFlag of WatchFlag is
41 architecture ar_WatchFlag of WatchFlag is
27
42
28 constant FlagSet : std_logic_vector(4 downto 0) := (others =>'1');
43 constant FlagSet : std_logic_vector(4 downto 0) := (others =>'1');
44 constant OneToSet : std_logic_vector(4 downto 0) := "01111";
29
45
30 begin
46 begin
31 process(clk,rstn)
47 process(clk,rstn)
32 begin
48 begin
33 if(rstn='0')then
49 if(rstn='0')then
34 DataCpt <= (others => '0');
50 DataCpt <= (others => '0');
35
51
36 elsif(clk'event and clk='1')then
52 elsif(clk'event and clk='1')then
37
53
38 if(FullF0a = FlagSet)then
54 if(EmptyF0a = OneToSet)then
39 DataCpt(0) <= '1';
55 DataCpt(0) <= '1';
40 elsif(EmptyF0a = FlagSet)then
56 elsif(EmptyF0a = FlagSet)then
41 DataCpt(0) <= '0';
57 DataCpt(0) <= '0';
42 end if;
58 end if;
43
59
44 if(FullF0b = FlagSet)then
60 if(EmptyF0b = OneToSet)then
45 DataCpt(1) <= '1';
61 DataCpt(1) <= '1';
46 elsif(EmptyF0b = FlagSet)then
62 elsif(EmptyF0b = FlagSet)then
47 DataCpt(1) <= '0';
63 DataCpt(1) <= '0';
48 end if;
64 end if;
49
65
50 if(FullF1 = FlagSet)then
66 if(EmptyF1 = OneToSet)then
51 DataCpt(2) <= '1';
67 DataCpt(2) <= '1';
52 elsif(EmptyF1 = FlagSet)then
68 elsif(EmptyF1 = FlagSet)then
53 DataCpt(2) <= '0';
69 DataCpt(2) <= '0';
54 end if;
70 end if;
55
71
56 if(FullF2 = FlagSet)then
72 if(EmptyF2 = OneToSet)then
57 DataCpt(3) <= '1';
73 DataCpt(3) <= '1';
58 elsif(EmptyF2 = FlagSet)then
74 elsif(EmptyF2 = FlagSet)then
59 DataCpt(3) <= '0';
75 DataCpt(3) <= '0';
60 end if;
76 end if;
61
77
62 end if;
78 end if;
63 end process;
79 end process;
64
80
65 end architecture; No newline at end of file
81 end architecture;
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@@ -1,81 +1,103
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 library grlib;
24 library grlib;
25 use grlib.amba.all;
25 use grlib.amba.all;
26 use std.textio.all;
26 use std.textio.all;
27 library lpp;
27 library lpp;
28 use lpp.lpp_amba.all;
28 use lpp.lpp_amba.all;
29
29
30 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
30 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
31
31
32 package lpp_demux is
32 package lpp_demux is
33
33
34
35 component Demultiplex is
36 generic(
37 Data_sz : integer range 1 to 32 := 16);
38 port(
39 clk : in std_logic;
40 rstn : in std_logic;
41
42 Read : in std_logic_vector(4 downto 0);
43
44 EmptyF0a : in std_logic_vector(4 downto 0);
45 EmptyF0b : in std_logic_vector(4 downto 0);
46 EmptyF1 : in std_logic_vector(4 downto 0);
47 EmptyF2 : in std_logic_vector(4 downto 0);
48
49 DataF0a : in std_logic_vector((5*Data_sz)-1 downto 0);
50 DataF0b : in std_logic_vector((5*Data_sz)-1 downto 0);
51 DataF1 : in std_logic_vector((5*Data_sz)-1 downto 0);
52 DataF2 : in std_logic_vector((5*Data_sz)-1 downto 0);
53
54 Read_DEMUX : out std_logic_vector(19 downto 0);
55 Empty : out std_logic_vector(4 downto 0);
56 Data : out std_logic_vector((5*Data_sz)-1 downto 0)
57 );
58 end component;
59
60
34 component DEMUX is
61 component DEMUX is
35 generic(
62 generic(
36 Data_sz : integer range 1 to 32 := 16);
63 Data_sz : integer range 1 to 32 := 16);
37 port(
64 port(
38 clk : in std_logic;
65 clk : in std_logic;
39 rstn : in std_logic;
66 rstn : in std_logic;
40
67
41 Read : in std_logic_vector(4 downto 0);
68 Read : in std_logic_vector(4 downto 0);
42 DataCpt : in std_logic_vector(3 downto 0); -- f2 f1 f0b f0a
69 DataCpt : in std_logic_vector(3 downto 0); -- f2 f1 f0b f0a
43
70
44 EmptyF0a : in std_logic_vector(4 downto 0);
71 EmptyF0a : in std_logic_vector(4 downto 0);
45 EmptyF0b : in std_logic_vector(4 downto 0);
72 EmptyF0b : in std_logic_vector(4 downto 0);
46 EmptyF1 : in std_logic_vector(4 downto 0);
73 EmptyF1 : in std_logic_vector(4 downto 0);
47 EmptyF2 : in std_logic_vector(4 downto 0);
74 EmptyF2 : in std_logic_vector(4 downto 0);
48
75
49 DataF0a : in std_logic_vector((5*Data_sz)-1 downto 0);
76 DataF0a : in std_logic_vector((5*Data_sz)-1 downto 0);
50 DataF0b : in std_logic_vector((5*Data_sz)-1 downto 0);
77 DataF0b : in std_logic_vector((5*Data_sz)-1 downto 0);
51 DataF1 : in std_logic_vector((5*Data_sz)-1 downto 0);
78 DataF1 : in std_logic_vector((5*Data_sz)-1 downto 0);
52 DataF2 : in std_logic_vector((5*Data_sz)-1 downto 0);
79 DataF2 : in std_logic_vector((5*Data_sz)-1 downto 0);
53
80
54 Read_DEMUX : out std_logic_vector(19 downto 0);
81 Read_DEMUX : out std_logic_vector(19 downto 0);
55 Empty : out std_logic_vector(4 downto 0);
82 Empty : out std_logic_vector(4 downto 0);
56 Data : out std_logic_vector((5*Data_sz)-1 downto 0)
83 Data : out std_logic_vector((5*Data_sz)-1 downto 0)
57 );
84 );
58 end component;
85 end component;
59
86
60
87
61 component WatchFlag is
88 component WatchFlag is
62 port(
89 port(
63 clk : in std_logic;
90 clk : in std_logic;
64 rstn : in std_logic;
91 rstn : in std_logic;
65
92
66 FullF0a : in std_logic_vector(4 downto 0);
67 FullF0b : in std_logic_vector(4 downto 0);
68 FullF1 : in std_logic_vector(4 downto 0);
69 FullF2 : in std_logic_vector(4 downto 0);
70
71 EmptyF0a : in std_logic_vector(4 downto 0);
93 EmptyF0a : in std_logic_vector(4 downto 0);
72 EmptyF0b : in std_logic_vector(4 downto 0);
94 EmptyF0b : in std_logic_vector(4 downto 0);
73 EmptyF1 : in std_logic_vector(4 downto 0);
95 EmptyF1 : in std_logic_vector(4 downto 0);
74 EmptyF2 : in std_logic_vector(4 downto 0);
96 EmptyF2 : in std_logic_vector(4 downto 0);
75
97
76 DataCpt : out std_logic_vector(3 downto 0) -- f2 f1 f0b f0a
98 DataCpt : out std_logic_vector(3 downto 0) -- f2 f1 f0b f0a
77 );
99 );
78 end component;
100 end component;
79
101
80
102
81 end; No newline at end of file
103 end;
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@@ -1,212 +1,217
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.numeric_std.all;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
24 use IEEE.std_logic_1164.all;
25 library lpp;
26 use lpp.general_purpose.all;
25
27
26 --! Driver de l'ALU
28 --! Driver de l'ALU
27
29
28 entity ALU_Driver is
30 entity ALU_Driver is
29 generic(
31 generic(
30 Input_SZ_1 : integer := 16;
32 Input_SZ_1 : integer := 16;
31 Input_SZ_2 : integer := 16);
33 Input_SZ_2 : integer := 16);
32 port(
34 port(
33 clk : in std_logic; --! Horloge du composant
35 clk : in std_logic; --! Horloge du composant
34 reset : in std_logic; --! Reset general du composant
36 reset : in std_logic; --! Reset general du composant
35 IN1 : in std_logic_vector(Input_SZ_1-1 downto 0); --! Donn�e d'entr�e
37 IN1 : in std_logic_vector(Input_SZ_1-1 downto 0); --! Donn�e d'entr�e
36 IN2 : in std_logic_vector(Input_SZ_2-1 downto 0); --! Donn�e d'entr�e
38 IN2 : in std_logic_vector(Input_SZ_2-1 downto 0); --! Donn�e d'entr�e
37 Take : in std_logic; --! Flag, op�rande r�cup�r�
39 Take : in std_logic; --! Flag, op�rande r�cup�r�
38 Received : in std_logic; --! Flag, R�sultat bien ressu
40 Received : in std_logic; --! Flag, R�sultat bien ressu
39 Conjugate : in std_logic; --! Flag, Calcul sur un complexe et son conjugu�
41 Conjugate : in std_logic; --! Flag, Calcul sur un complexe et son conjugu�
40 Valid : out std_logic; --! Flag, R�sultat disponible
42 Valid : out std_logic; --! Flag, R�sultat disponible
41 Read : out std_logic; --! Flag, op�rande disponible
43 Read : out std_logic; --! Flag, op�rande disponible
42 CTRL : out std_logic_vector(4 downto 0); --! Permet de s�lectionner la/les op�ration d�sir�e
44 CTRL : out std_logic_vector(2 downto 0); --! Permet de s�lectionner la/les op�ration d�sir�e
45 COMP : out std_logic_vector(1 downto 0); --! (set) Permet de compl�menter les op�randes
43 OP1 : out std_logic_vector(Input_SZ_1-1 downto 0); --! Premier Op�rande
46 OP1 : out std_logic_vector(Input_SZ_1-1 downto 0); --! Premier Op�rande
44 OP2 : out std_logic_vector(Input_SZ_2-1 downto 0) --! Second Op�rande
47 OP2 : out std_logic_vector(Input_SZ_2-1 downto 0) --! Second Op�rande
45 );
48 );
46 end ALU_Driver;
49 end ALU_Driver;
47
50
48 --! @details Les op�randes sont issue des donn�es d'entr�es et associ� aux bonnes valeurs sur CTRL, les diff�rentes op�rations sont effectu�es
51 --! @details Les op�randes sont issue des donn�es d'entr�es et associ� aux bonnes valeurs sur CTRL, les diff�rentes op�rations sont effectu�es
49
52
50 architecture ar_ALU_Driver of ALU_Driver is
53 architecture ar_ALU_Driver of ALU_Driver is
51
54
52 signal OP1re : std_logic_vector(Input_SZ_1-1 downto 0);
55 signal OP1re : std_logic_vector(Input_SZ_1-1 downto 0);
53 signal OP1im : std_logic_vector(Input_SZ_1-1 downto 0);
56 signal OP1im : std_logic_vector(Input_SZ_1-1 downto 0);
54 signal OP2re : std_logic_vector(Input_SZ_2-1 downto 0);
57 signal OP2re : std_logic_vector(Input_SZ_2-1 downto 0);
55 signal OP2im : std_logic_vector(Input_SZ_2-1 downto 0);
58 signal OP2im : std_logic_vector(Input_SZ_2-1 downto 0);
56
59
57 signal go_st : std_logic;
60 signal go_st : std_logic;
58 signal Take_reg : std_logic;
61 signal Take_reg : std_logic;
59 signal Received_reg : std_logic;
62 signal Received_reg : std_logic;
60
63
61 type etat is (eX,e0,e1,e2,e3,e4,e5,idle,idle2,idle3);
64 type etat is (eX,e0,e1,e2,e3,e4,e5,eY,eZ,eW);
62 signal ect : etat;
65 signal ect : etat;
63 signal st : etat;
66 signal st : etat;
64
67
65 begin
68 begin
66 process(clk,reset)
69 process(clk,reset)
67 begin
70 begin
68
71
69 if(reset='0')then
72 if(reset='0')then
70 ect <= eX;
73 ect <= eX;
71 st <= e0;
74 st <= e0;
72 go_st <= '0';
75 go_st <= '0';
73 CTRL <= "10000";
76 CTRL <= ctrl_CLRMAC;
77 COMP <= "00"; -- pas de complement
74 Read <= '0';
78 Read <= '0';
75 Valid <= '0';
79 Valid <= '0';
76 Take_reg <= '0';
80 Take_reg <= '0';
77 Received_reg <= '0';
81 Received_reg <= '0';
78
82
79 elsif(clk'event and clk='1')then
83 elsif(clk'event and clk='1')then
80 Take_reg <= Take;
84 Take_reg <= Take;
81 Received_reg <= Received;
85 Received_reg <= Received;
82
86
83 case ect is
87 case ect is
84 when eX =>
88 when eX =>
85 go_st <= '0';
89 go_st <= '0';
86 Read <= '1';
90 Read <= '1';
87 CTRL <= "10000";
91 CTRL <= ctrl_CLRMAC;
88 ect <= e0;
92 ect <= e0;
89
93
90 when e0 =>
94 when e0 =>
91 OP1re <= IN1;
95 OP1re <= IN1;
92 if(Conjugate='1')then --
96 if(Conjugate='1')then --
93 OP2re <= IN1; --
97 OP2re <= IN1; --
94 else --
98 else --
95 OP2re <= IN2; -- modif 23/06/11
99 OP2re <= IN2; -- modif 23/06/11
96 end if; --
100 end if; --
97 if(Take_reg='0' and Take='1')then
101 if(Take_reg='0' and Take='1')then
98 read <= '0';
102 read <= '0';
99 ect <= e1;
103 ect <= e1;
100 end if;
104 end if;
101
105
102 when e1 =>
106 when e1 =>
103 OP1 <= OP1re;
107 OP1 <= OP1re;
104 OP2 <= OP2re;
108 OP2 <= OP2re;
105 CTRL <= "00001";
109 CTRL <= ctrl_MAC;
106 Read <= '1';
110 Read <= '1';
107 ect <= idle;
111 ect <= eY;
108
112
109 when idle =>
113 when eY =>
110 OP1im <= IN1;
114 OP1im <= IN1;
111 if(Conjugate='1')then --
115 if(Conjugate='1')then --
112 OP2im <= IN1; --
116 OP2im <= IN1; --
113 else --
117 else --
114 OP2im <= IN2; -- modif 23/06/11
118 OP2im <= IN2; -- modif 23/06/11
115 end if; --
119 end if; --
116 CTRL <= "00000";
120 CTRL <= ctrl_IDLE;
117 if(Take_reg='1' and Take='0')then
121 if(Take_reg='1' and Take='0')then
118 Read <= '0';
122 Read <= '0';
119 ect <= e2;
123 ect <= e2;
120 end if;
124 end if;
121
125
122 when e2 =>
126 when e2 =>
123 OP1 <= OP1im;
127 OP1 <= OP1im;
124 OP2 <= OP2im;
128 OP2 <= OP2im;
125 CTRL <= "00001";
129 CTRL <= ctrl_MAC;
126 ect <= idle2;
130 ect <= eZ;
127
131
128 when idle2 =>
132 when eZ =>
129 CTRL <= "00000";
133 CTRL <= ctrl_IDLE;
130 go_st <= '1';
134 go_st <= '1';
131 if(Received_reg='0' and Received='1')then
135 if(Received_reg='0' and Received='1')then
132 if(Conjugate='1')then
136 if(Conjugate='1')then
133 ect <= eX;
137 ect <= eX;
134 else
138 else
135 ect <= e3;
139 ect <= e3;
136 end if;
140 end if;
137 end if;
141 end if;
138
142
139 when e3 =>
143 when e3 =>
140 CTRL <= "10000";
144 CTRL <= ctrl_CLRMAC;
141 go_st <= '0';
145 go_st <= '0';
142 ect <= e4;
146 ect <= e4;
143
147
144 when e4 =>
148 when e4 =>
145 OP1 <= OP1im;
149 OP1 <= OP1im;
146 OP2 <= OP2re;
150 OP2 <= OP2re;
147 CTRL <= "00001";
151 CTRL <= ctrl_MAC;
148 ect <= e5;
152 ect <= e5;
149
153
150 when e5 =>
154 when e5 =>
151 OP1 <= OP1re;
155 OP1 <= OP1re;
152 OP2 <= OP2im;
156 OP2 <= OP2im;
153 CTRL <= "01001";
157 COMP <= "10";
154 ect <= idle3;
158 ect <= eW;
155
159
156 when idle3 =>
160 when eW =>
157 CTRL <= "00000";
161 CTRL <= ctrl_IDLE;
162 COMP <= "00";
158 go_st <= '1';
163 go_st <= '1';
159 if(Received_reg='1' and Received='0')then
164 if(Received_reg='1' and Received='0')then
160 ect <= eX;
165 ect <= eX;
161 end if;
166 end if;
162 end case;
167 end case;
163 ---------------------------------------------------------------------------------
168 ---------------------------------------------------------------------------------
164 case st is
169 case st is
165 when e0 =>
170 when e0 =>
166 if(go_st='1')then
171 if(go_st='1')then
167 st <= e1;
172 st <= e1;
168 end if;
173 end if;
169
174
170 when e1 =>
175 when e1 =>
171 Valid <= '1';
176 Valid <= '1';
172 st <= e2;
177 st <= e2;
173
178
174 when e2 =>
179 when e2 =>
175 if(Received_reg='0' and Received='1')then
180 if(Received_reg='0' and Received='1')then
176 Valid <= '0';
181 Valid <= '0';
177 if(Conjugate='1')then
182 if(Conjugate='1')then
178 st <= idle2;
183 st <= eY;
179 else
184 else
180 st <= idle;
185 st <= eX;
181 end if;
186 end if;
182 end if;
187 end if;
183
188
184 when idle =>
189 when eX =>
185 st <= e3;
190 st <= e3;
186
191
187 when e3 =>
192 when e3 =>
188 if(go_st='1')then
193 if(go_st='1')then
189 st <= e4;
194 st <= e4;
190 end if;
195 end if;
191
196
192 when e4 =>
197 when e4 =>
193 Valid <= '1';
198 Valid <= '1';
194 st <= e5;
199 st <= e5;
195
200
196 when e5 =>
201 when e5 =>
197 if(Received_reg='1' and Received='0')then
202 if(Received_reg='1' and Received='0')then
198 Valid <= '0';
203 Valid <= '0';
199 st <= idle2;
204 st <= eY;
200 end if;
205 end if;
201
206
202 when idle2 =>
207 when eY =>
203 st <= e0;
208 st <= e0;
204
209
205 when others =>
210 when others =>
206 null;
211 null;
207 end case;
212 end case;
208
213
209 end if;
214 end if;
210 end process;
215 end process;
211
216
212 end ar_ALU_Driver; No newline at end of file
217 end ar_ALU_Driver;
Show file before | Show file after | Hide comments
@@ -1,66 +1,68
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.numeric_std.all;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
24 use IEEE.std_logic_1164.all;
25 library lpp;
25 use lpp.lpp_matrix.all;
26 use lpp.lpp_matrix.all;
27 use lpp.general_purpose.all;
26
28
27 --! Programme de calcule de Matrice Spectral, compos� d'une ALU et de son Driver
29 --! Programme de calcule de Matrice Spectral, compos� d'une ALU et de son Driver
28
30
29 entity Matrix is
31 entity Matrix is
30 generic(
32 generic(
31 Input_SZ : integer := 16);
33 Input_SZ : integer := 16);
32 port(
34 port(
33 clk : in std_logic; --! Horloge du composant
35 clk : in std_logic; --! Horloge du composant
34 raz : in std_logic; --! Reset general du composant
36 raz : in std_logic; --! Reset general du composant
35 IN1 : in std_logic_vector(Input_SZ-1 downto 0); --! Donn�e d'entr�e
37 IN1 : in std_logic_vector(Input_SZ-1 downto 0); --! Donn�e d'entr�e
36 IN2 : in std_logic_vector(Input_SZ-1 downto 0); --! Donn�e d'entr�e
38 IN2 : in std_logic_vector(Input_SZ-1 downto 0); --! Donn�e d'entr�e
37 Take : in std_logic; --! Flag, op�rande r�cup�r�
39 Take : in std_logic; --! Flag, op�rande r�cup�r�
38 Received : in std_logic; --! Flag, R�sultat bien ressu
40 Received : in std_logic; --! Flag, R�sultat bien ressu
39 Conjugate : in std_logic; --! Flag, Calcul sur un complexe et son conjugu�
41 Conjugate : in std_logic; --! Flag, Calcul sur un complexe et son conjugu�
40 Valid : out std_logic; --! Flag, R�sultat disponible
42 Valid : out std_logic; --! Flag, R�sultat disponible
41 Read : out std_logic; --! Flag, op�rande disponible
43 Read : out std_logic; --! Flag, op�rande disponible
42 Result : out std_logic_vector(2*Input_SZ-1 downto 0) --! R�sultat du calcul
44 Result : out std_logic_vector(2*Input_SZ-1 downto 0) --! R�sultat du calcul
43 );
45 );
44 end Matrix;
46 end Matrix;
45
47
46
48
47 architecture ar_Matrix of Matrix is
49 architecture ar_Matrix of Matrix is
48
50
49 signal CTRL : std_logic_vector(4 downto 0);
51 signal CTRL : std_logic_vector(2 downto 0);
52 signal COMP : std_logic_vector(1 downto 0);
50 signal OP1 : std_logic_vector(Input_SZ-1 downto 0);
53 signal OP1 : std_logic_vector(Input_SZ-1 downto 0);
51 signal OP2 : std_logic_vector(Input_SZ-1 downto 0);
54 signal OP2 : std_logic_vector(Input_SZ-1 downto 0);
52
55
53 begin
56 begin
54
57
55 DRIVE : ALU_Driver
58 DRIVE : ALU_Driver
56 generic map(Input_SZ,Input_SZ)
59 generic map(Input_SZ,Input_SZ)
57 port map(clk,raz,IN1,IN2,Take,Received,Conjugate,Valid,Read,CTRL,OP1,OP2);
60 port map(clk,raz,IN1,IN2,Take,Received,Conjugate,Valid,Read,CTRL,COMP,OP1,OP2);
58
61
59
62
60 ALU : ALU_v2
63 ALU0 : ALU
61 generic map(1,0,Input_SZ,Input_SZ)
64 generic map(1,0,Input_SZ,Input_SZ)
62 port map(clk,raz,CTRL,OP1,OP2,Result);
65 port map(clk,raz,CTRL,COMP,OP1,OP2,Result);
63
66
64
67
65 end ar_Matrix;
68 end ar_Matrix;
66
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@@ -1,278 +1,253
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 library grlib;
24 library grlib;
25 use grlib.amba.all;
25 use grlib.amba.all;
26 use std.textio.all;
26 use std.textio.all;
27 library lpp;
27 library lpp;
28 use lpp.lpp_amba.all;
28 use lpp.lpp_amba.all;
29
29
30 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
30 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
31
31
32 package lpp_matrix is
32 package lpp_matrix is
33
33
34 component APB_Matrix is
34 component APB_Matrix is
35 generic (
35 generic (
36 pindex : integer := 0;
36 pindex : integer := 0;
37 paddr : integer := 0;
37 paddr : integer := 0;
38 pmask : integer := 16#fff#;
38 pmask : integer := 16#fff#;
39 pirq : integer := 0;
39 pirq : integer := 0;
40 abits : integer := 8;
40 abits : integer := 8;
41 Input_SZ : integer := 16;
41 Input_SZ : integer := 16;
42 Result_SZ : integer := 32);
42 Result_SZ : integer := 32);
43 port (
43 port (
44 clk : in std_logic;
44 clk : in std_logic;
45 rst : in std_logic;
45 rst : in std_logic;
46 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
46 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
47 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
47 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
48 Full : in std_logic_vector(1 downto 0);
48 Full : in std_logic_vector(1 downto 0);
49 Empty : in std_logic_vector(1 downto 0);
49 Empty : in std_logic_vector(1 downto 0);
50 ReadFIFO : out std_logic_vector(1 downto 0);
50 ReadFIFO : out std_logic_vector(1 downto 0);
51 FullFIFO : in std_logic;
51 FullFIFO : in std_logic;
52 WriteFIFO : out std_logic;
52 WriteFIFO : out std_logic;
53 Result : out std_logic_vector(Result_SZ-1 downto 0);
53 Result : out std_logic_vector(Result_SZ-1 downto 0);
54 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
54 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
55 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
55 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
56 );
56 );
57 end component;
57 end component;
58
58
59 component MatriceSpectrale is
60 generic(
61 Input_SZ : integer := 16;
62 Result_SZ : integer := 32);
63 port(
64 clkm : in std_logic;
65 rstn : in std_logic;
66
67 FifoIN_Full : in std_logic_vector(4 downto 0);
68 FifoOUT_Full : in std_logic_vector(1 downto 0);
69 Data_IN : in std_logic_vector(79 downto 0);
70 ACQ : in std_logic;
71 FlagError : out std_logic;
72 Pong : out std_logic;
73 Write : out std_logic_vector(1 downto 0);
74 Read : out std_logic_vector(4 downto 0);
75 Data_OUT : out std_logic_vector(63 downto 0)
76 );
77 end component;
78
79
59 component TopSpecMatrix is
80 component TopSpecMatrix is
60 generic(
81 generic(
61 Input_SZ : integer := 16);
82 Input_SZ : integer := 16);
62 port(
83 port(
63 clk : in std_logic;
84 clk : in std_logic;
64 rstn : in std_logic;
85 rstn : in std_logic;
65 Write : in std_logic;
86 Write : in std_logic;
66 ReadIn : in std_logic_vector(1 downto 0);
87 ReadIn : in std_logic_vector(1 downto 0);
67 Full : in std_logic_vector(4 downto 0);
88 Full : in std_logic_vector(4 downto 0);
68 Data : in std_logic_vector((5*Input_SZ)-1 downto 0);
89 Data : in std_logic_vector((5*Input_SZ)-1 downto 0);
69 Start : out std_logic;
90 Start : out std_logic;
70 ReadOut : out std_logic_vector(4 downto 0);
91 ReadOut : out std_logic_vector(4 downto 0);
71 Statu : out std_logic_vector(3 downto 0);
92 Statu : out std_logic_vector(3 downto 0);
72 DATA1 : out std_logic_vector(Input_SZ-1 downto 0);
93 DATA1 : out std_logic_vector(Input_SZ-1 downto 0);
73 DATA2 : out std_logic_vector(Input_SZ-1 downto 0)
94 DATA2 : out std_logic_vector(Input_SZ-1 downto 0)
74 );
95 );
75 end component;
96 end component;
76
97
77
98
78 component Top_MatrixSpec is
99 component Top_MatrixSpec is
79 generic(
100 generic(
80 Input_SZ : integer := 16;
101 Input_SZ : integer := 16;
81 Result_SZ : integer := 32);
102 Result_SZ : integer := 32);
82 port(
103 port(
83 clk : in std_logic;
104 clk : in std_logic;
84 reset : in std_logic;
105 reset : in std_logic;
85 Statu : in std_logic_vector(3 downto 0);
106 Statu : in std_logic_vector(3 downto 0);
86 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
107 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
87 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
108 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
88 Full : in std_logic_vector(1 downto 0);
109 Full : in std_logic_vector(1 downto 0);
89 Empty : in std_logic_vector(1 downto 0);
110 Empty : in std_logic_vector(1 downto 0);
90 ReadFIFO : out std_logic_vector(1 downto 0);
111 ReadFIFO : out std_logic_vector(1 downto 0);
91 FullFIFO : in std_logic;
112 FullFIFO : in std_logic;
92 WriteFIFO : out std_logic;
113 WriteFIFO : out std_logic;
93 Result : out std_logic_vector(Result_SZ-1 downto 0)
114 Result : out std_logic_vector(Result_SZ-1 downto 0)
94 );
115 );
95 end component;
116 end component;
96
117
97 component SpectralMatrix is
118 component SpectralMatrix is
98 generic(
119 generic(
99 Input_SZ : integer := 16;
120 Input_SZ : integer := 16;
100 Result_SZ : integer := 32);
121 Result_SZ : integer := 32);
101 port(
122 port(
102 clk : in std_logic;
123 clk : in std_logic;
103 reset : in std_logic;
124 reset : in std_logic;
104 Start : in std_logic;
125 Start : in std_logic;
105 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
126 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
106 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
127 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
107 Statu : in std_logic_vector(3 downto 0);
128 Statu : in std_logic_vector(3 downto 0);
108 -- FullFIFO : in std_logic;
129 -- FullFIFO : in std_logic;
109 ReadFIFO : out std_logic_vector(1 downto 0);
130 ReadFIFO : out std_logic_vector(1 downto 0);
110 WriteFIFO : out std_logic;
131 WriteFIFO : out std_logic;
111 Result : out std_logic_vector(Result_SZ-1 downto 0)
132 Result : out std_logic_vector(Result_SZ-1 downto 0)
112 );
133 );
113 end component;
134 end component;
114
135
115
136
116 component Matrix is
137 component Matrix is
117 generic(
138 generic(
118 Input_SZ : integer := 16);
139 Input_SZ : integer := 16);
119 port(
140 port(
120 clk : in std_logic;
141 clk : in std_logic;
121 raz : in std_logic;
142 raz : in std_logic;
122 IN1 : in std_logic_vector(Input_SZ-1 downto 0);
143 IN1 : in std_logic_vector(Input_SZ-1 downto 0);
123 IN2 : in std_logic_vector(Input_SZ-1 downto 0);
144 IN2 : in std_logic_vector(Input_SZ-1 downto 0);
124 Take : in std_logic;
145 Take : in std_logic;
125 Received : in std_logic;
146 Received : in std_logic;
126 Conjugate : in std_logic;
147 Conjugate : in std_logic;
127 Valid : out std_logic;
148 Valid : out std_logic;
128 Read : out std_logic;
149 Read : out std_logic;
129 Result : out std_logic_vector(2*Input_SZ-1 downto 0)
150 Result : out std_logic_vector(2*Input_SZ-1 downto 0)
130 );
151 );
131 end component;
152 end component;
132
153
133 component GetResult is
154 component GetResult is
134 generic(
155 generic(
135 Result_SZ : integer := 32);
156 Result_SZ : integer := 32);
136 port(
157 port(
137 clk : in std_logic;
158 clk : in std_logic;
138 raz : in std_logic;
159 raz : in std_logic;
139 Valid : in std_logic;
160 Valid : in std_logic;
140 Conjugate : in std_logic;
161 Conjugate : in std_logic;
141 Res : in std_logic_vector(Result_SZ-1 downto 0);
162 Res : in std_logic_vector(Result_SZ-1 downto 0);
142 -- Full : in std_logic;
163 -- Full : in std_logic;
143 WriteFIFO : out std_logic;
164 WriteFIFO : out std_logic;
144 Received : out std_logic;
165 Received : out std_logic;
145 Result : out std_logic_vector(Result_SZ-1 downto 0)
166 Result : out std_logic_vector(Result_SZ-1 downto 0)
146 );
167 );
147 end component;
168 end component;
148
169
149
170
150 component TopMatrix_PDR is
171 component TopMatrix_PDR is
151 generic(
172 generic(
152 Input_SZ : integer := 16;
173 Input_SZ : integer := 16;
153 Result_SZ : integer := 32);
174 Result_SZ : integer := 32);
154 port(
175 port(
155 clk : in std_logic;
176 clk : in std_logic;
156 reset : in std_logic;
177 reset : in std_logic;
157 Data : in std_logic_vector((5*Input_SZ)-1 downto 0);
178 Data : in std_logic_vector((5*Input_SZ)-1 downto 0);
158 FULLin : in std_logic_vector(4 downto 0);
179 FULLin : in std_logic_vector(4 downto 0);
159 READin : in std_logic_vector(1 downto 0);
180 READin : in std_logic_vector(1 downto 0);
160 WRITEin : in std_logic;
181 WRITEin : in std_logic;
161 FIFO1 : out std_logic_vector(Input_SZ-1 downto 0);
182 FIFO1 : out std_logic_vector(Input_SZ-1 downto 0);
162 FIFO2 : out std_logic_vector(Input_SZ-1 downto 0);
183 FIFO2 : out std_logic_vector(Input_SZ-1 downto 0);
163 Start : out std_logic;
184 Start : out std_logic;
164 Read : out std_logic_vector(4 downto 0);
185 Read : out std_logic_vector(4 downto 0);
165 Statu : out std_logic_vector(3 downto 0)
186 Statu : out std_logic_vector(3 downto 0)
166 );
187 );
167 end component;
188 end component;
168
189
169
190
170 component Dispatch is
191 component Dispatch is
171 generic(
192 generic(
172 Data_SZ : integer := 32);
193 Data_SZ : integer := 32);
173 port(
194 port(
174 clk : in std_logic;
195 clk : in std_logic;
175 reset : in std_logic;
196 reset : in std_logic;
176 Acq : in std_logic;
197 Acq : in std_logic;
177 Data : in std_logic_vector(Data_SZ-1 downto 0);
198 Data : in std_logic_vector(Data_SZ-1 downto 0);
178 Write : in std_logic;
199 Write : in std_logic;
179 Full : in std_logic_vector(1 downto 0);
200 Full : in std_logic_vector(1 downto 0);
180 FifoData : out std_logic_vector(2*Data_SZ-1 downto 0);
201 FifoData : out std_logic_vector(2*Data_SZ-1 downto 0);
181 FifoWrite : out std_logic_vector(1 downto 0);
202 FifoWrite : out std_logic_vector(1 downto 0);
182 Pong : out std_logic;
203 Pong : out std_logic;
183 Error : out std_logic
204 Error : out std_logic
184 );
205 );
185 end component;
206 end component;
186
207
187
208
188 component DriveInputs is
209 component DriveInputs is
189 port(
210 port(
190 clk : in std_logic;
211 clk : in std_logic;
191 raz : in std_logic;
212 raz : in std_logic;
192 Read : in std_logic;
213 Read : in std_logic;
193 Conjugate : in std_logic;
214 Conjugate : in std_logic;
194 Take : out std_logic;
215 Take : out std_logic;
195 ReadFIFO : out std_logic_vector(1 downto 0)
216 ReadFIFO : out std_logic_vector(1 downto 0)
196 );
217 );
197 end component;
218 end component;
198
219
199 component Starter is
220 component Starter is
200 port(
221 port(
201 clk : in std_logic;
222 clk : in std_logic;
202 raz : in std_logic;
223 raz : in std_logic;
203 Full : in std_logic_vector(1 downto 0);
224 Full : in std_logic_vector(1 downto 0);
204 Empty : in std_logic_vector(1 downto 0);
225 Empty : in std_logic_vector(1 downto 0);
205 Statu : in std_logic_vector(3 downto 0);
226 Statu : in std_logic_vector(3 downto 0);
206 Write : in std_logic;
227 Write : in std_logic;
207 Start : out std_logic
228 Start : out std_logic
208 );
229 );
209 end component;
230 end component;
210
231
211 component ALU_Driver is
232 component ALU_Driver is
212 generic(
233 generic(
213 Input_SZ_1 : integer := 16;
234 Input_SZ_1 : integer := 16;
214 Input_SZ_2 : integer := 16);
235 Input_SZ_2 : integer := 16);
215 port(
236 port(
216 clk : in std_logic;
237 clk : in std_logic;
217 reset : in std_logic;
238 reset : in std_logic;
218 IN1 : in std_logic_vector(Input_SZ_1-1 downto 0);
239 IN1 : in std_logic_vector(Input_SZ_1-1 downto 0);
219 IN2 : in std_logic_vector(Input_SZ_2-1 downto 0);
240 IN2 : in std_logic_vector(Input_SZ_2-1 downto 0);
220 Take : in std_logic;
241 Take : in std_logic;
221 Received : in std_logic;
242 Received : in std_logic;
222 Conjugate : in std_logic;
243 Conjugate : in std_logic;
223 Valid : out std_logic;
244 Valid : out std_logic;
224 Read : out std_logic;
245 Read : out std_logic;
225 CTRL : out std_logic_vector(4 downto 0);
246 CTRL : out std_logic_vector(2 downto 0);
247 COMP : out std_logic_vector(1 downto 0);
226 OP1 : out std_logic_vector(Input_SZ_1-1 downto 0);
248 OP1 : out std_logic_vector(Input_SZ_1-1 downto 0);
227 OP2 : out std_logic_vector(Input_SZ_2-1 downto 0)
249 OP2 : out std_logic_vector(Input_SZ_2-1 downto 0)
228 );
250 );
229 end component;
251 end component;
230
252
231
232 component ALU_v2 is
233 generic(
234 Arith_en : integer := 1;
235 Logic_en : integer := 1;
236 Input_SZ_1 : integer := 16;
237 Input_SZ_2 : integer := 9);
238 port(
239 clk : in std_logic;
240 reset : in std_logic;
241 ctrl : in std_logic_vector(4 downto 0);
242 OP1 : in std_logic_vector(Input_SZ_1-1 downto 0);
243 OP2 : in std_logic_vector(Input_SZ_2-1 downto 0);
244 RES : out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0)
245 );
246 end component;
247
248
249 component MAC_v2 is
250 generic(
251 Input_SZ_A : integer := 8;
252 Input_SZ_B : integer := 8);
253 port(
254 clk : in std_logic;
255 reset : in std_logic;
256 clr_MAC : in std_logic;
257 MAC_MUL_ADD_2C : in std_logic_vector(3 downto 0);
258 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
259 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
260 RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
261 );
262 end component;
263
264
265 component TwoComplementer is
266 generic(
267 Input_SZ : integer := 16);
268 port(
269 clk : in std_logic;
270 reset : in std_logic;
271 clr : in std_logic;
272 TwoComp : in std_logic;
273 OP : in std_logic_vector(Input_SZ-1 downto 0);
274 RES : out std_logic_vector(Input_SZ-1 downto 0)
275 );
276 end component;
277
278 end; No newline at end of file
253 end;
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@@ -1,354 +1,354
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 LIBRARY lpp;
3 LIBRARY lpp;
4 USE lpp.lpp_ad_conv.ALL;
4 USE lpp.lpp_ad_conv.ALL;
5 USE lpp.iir_filter.ALL;
5 USE lpp.iir_filter.ALL;
6 USE lpp.FILTERcfg.ALL;
6 USE lpp.FILTERcfg.ALL;
7 USE lpp.lpp_memory.ALL;
7 USE lpp.lpp_memory.ALL;
8 USE lpp.lpp_top_lfr_pkg.ALL;
8 USE lpp.lpp_top_lfr_pkg.ALL;
9 LIBRARY techmap;
9 LIBRARY techmap;
10 USE techmap.gencomp.ALL;
10 USE techmap.gencomp.ALL;
11
11
12 ENTITY lpp_top_acq IS
12 ENTITY lpp_top_acq IS
13 GENERIC(
13 GENERIC(
14 tech : INTEGER := 0
14 tech : INTEGER := 0
15 );
15 );
16 PORT (
16 PORT (
17 -- ADS7886
17 -- ADS7886
18 cnv_run : IN STD_LOGIC;
18 cnv_run : IN STD_LOGIC;
19 cnv : OUT STD_LOGIC;
19 cnv : OUT STD_LOGIC;
20 sck : OUT STD_LOGIC;
20 sck : OUT STD_LOGIC;
21 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
21 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
22 --
22 --
23 cnv_clk : IN STD_LOGIC; -- clk 49 MHz
23 cnv_clk : IN STD_LOGIC; -- clk 49 MHz
24 cnv_rstn : IN STD_LOGIC;
24 cnv_rstn : IN STD_LOGIC;
25 --
25 --
26 clk : IN STD_LOGIC;
26 clk : IN STD_LOGIC;
27 rstn : IN STD_LOGIC;
27 rstn : IN STD_LOGIC;
28 --
28 --
29 sample_f0_0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
29 sample_f0_0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
30 sample_f0_1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
30 sample_f0_1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
31 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
31 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
32 --
32 --
33 sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
33 sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
34 sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
34 sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
35 --
35 --
36 sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
36 sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
37 sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
37 sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
38 --
38 --
39 sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
39 sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
40 sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0)
40 sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0)
41 );
41 );
42 END lpp_top_acq;
42 END lpp_top_acq;
43
43
44 ARCHITECTURE tb OF lpp_top_acq IS
44 ARCHITECTURE tb OF lpp_top_acq IS
45
45
46 COMPONENT Downsampling
46 COMPONENT Downsampling
47 GENERIC (
47 GENERIC (
48 ChanelCount : INTEGER;
48 ChanelCount : INTEGER;
49 SampleSize : INTEGER;
49 SampleSize : INTEGER;
50 DivideParam : INTEGER);
50 DivideParam : INTEGER);
51 PORT (
51 PORT (
52 clk : IN STD_LOGIC;
52 clk : IN STD_LOGIC;
53 rstn : IN STD_LOGIC;
53 rstn : IN STD_LOGIC;
54 sample_in_val : IN STD_LOGIC;
54 sample_in_val : IN STD_LOGIC;
55 sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0);
55 sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0);
56 sample_out_val : OUT STD_LOGIC;
56 sample_out_val : OUT STD_LOGIC;
57 sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0));
57 sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0));
58 END COMPONENT;
58 END COMPONENT;
59
59
60 -----------------------------------------------------------------------------
60 -----------------------------------------------------------------------------
61 CONSTANT ChanelCount : INTEGER := 8;
61 CONSTANT ChanelCount : INTEGER := 8;
62 CONSTANT ncycle_cnv_high : INTEGER := 79;
62 CONSTANT ncycle_cnv_high : INTEGER := 79;
63 CONSTANT ncycle_cnv : INTEGER := 500;
63 CONSTANT ncycle_cnv : INTEGER := 500;
64
64
65 -----------------------------------------------------------------------------
65 -----------------------------------------------------------------------------
66 SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0);
66 SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0);
67 SIGNAL sample_val : STD_LOGIC;
67 SIGNAL sample_val : STD_LOGIC;
68 SIGNAL sample_val_delay : STD_LOGIC;
68 SIGNAL sample_val_delay : STD_LOGIC;
69 -----------------------------------------------------------------------------
69 -----------------------------------------------------------------------------
70 CONSTANT Coef_SZ : INTEGER := 9;
70 CONSTANT Coef_SZ : INTEGER := 9;
71 CONSTANT CoefCntPerCel : INTEGER := 6;
71 CONSTANT CoefCntPerCel : INTEGER := 6;
72 CONSTANT CoefPerCel : INTEGER := 5;
72 CONSTANT CoefPerCel : INTEGER := 5;
73 CONSTANT Cels_count : INTEGER := 5;
73 CONSTANT Cels_count : INTEGER := 5;
74
74
75 -- SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0);
75 -- SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0);
76 SIGNAL coefs_JC : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
76 SIGNAL coefs_JC : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
77 SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
77 SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
78 -- SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
78 -- SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
79 --
79 --
80 SIGNAL sample_filter_JC_out_val : STD_LOGIC;
80 SIGNAL sample_filter_JC_out_val : STD_LOGIC;
81 SIGNAL sample_filter_JC_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
81 SIGNAL sample_filter_JC_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
82 --
82 --
83 SIGNAL sample_filter_JC_out_r_val : STD_LOGIC;
83 SIGNAL sample_filter_JC_out_r_val : STD_LOGIC;
84 SIGNAL sample_filter_JC_out_r : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
84 SIGNAL sample_filter_JC_out_r : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
85 -----------------------------------------------------------------------------
85 -----------------------------------------------------------------------------
86 SIGNAL downsampling_cnt : STD_LOGIC_VECTOR(1 DOWNTO 0);
86 SIGNAL downsampling_cnt : STD_LOGIC_VECTOR(1 DOWNTO 0);
87 SIGNAL sample_downsampling_out_val : STD_LOGIC;
87 SIGNAL sample_downsampling_out_val : STD_LOGIC;
88 SIGNAL sample_downsampling_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
88 SIGNAL sample_downsampling_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
89 --
89 --
90 SIGNAL sample_f0_val : STD_LOGIC;
90 SIGNAL sample_f0_val : STD_LOGIC;
91 SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
91 SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
92 --
92 --
93 SIGNAL sample_f0_0_val : STD_LOGIC;
93 SIGNAL sample_f0_0_val : STD_LOGIC;
94 SIGNAL sample_f0_1_val : STD_LOGIC;
94 SIGNAL sample_f0_1_val : STD_LOGIC;
95 SIGNAL counter_f0 : INTEGER;
95 SIGNAL counter_f0 : INTEGER;
96 -----------------------------------------------------------------------------
96 -----------------------------------------------------------------------------
97 SIGNAL sample_f1_val : STD_LOGIC;
97 SIGNAL sample_f1_val : STD_LOGIC;
98 SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
98 SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
99 --
99 --
100 SIGNAL sample_f2_val : STD_LOGIC;
100 SIGNAL sample_f2_val : STD_LOGIC;
101 SIGNAL sample_f2 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
101 SIGNAL sample_f2 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
102 --
102 --
103 SIGNAL sample_f3_val : STD_LOGIC;
103 SIGNAL sample_f3_val : STD_LOGIC;
104 SIGNAL sample_f3 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
104 SIGNAL sample_f3 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
105
105
106 BEGIN
106 BEGIN
107
107
108 -- component instantiation
108 -- component instantiation
109 -----------------------------------------------------------------------------
109 -----------------------------------------------------------------------------
110 DIGITAL_acquisition : ADS7886_drvr
110 DIGITAL_acquisition : ADS7886_drvr
111 GENERIC MAP (
111 GENERIC MAP (
112 ChanelCount => ChanelCount,
112 ChanelCount => ChanelCount,
113 ncycle_cnv_high => ncycle_cnv_high,
113 ncycle_cnv_high => ncycle_cnv_high,
114 ncycle_cnv => ncycle_cnv)
114 ncycle_cnv => ncycle_cnv)
115 PORT MAP (
115 PORT MAP (
116 cnv_clk => cnv_clk, --
116 cnv_clk => cnv_clk, --
117 cnv_rstn => cnv_rstn, --
117 cnv_rstn => cnv_rstn, --
118 cnv_run => cnv_run, --
118 cnv_run => cnv_run, --
119 cnv => cnv, --
119 cnv => cnv, --
120 clk => clk, --
120 clk => clk, --
121 rstn => rstn, --
121 rstn => rstn, --
122 sck => sck, --
122 sck => sck, --
123 sdo => sdo(ChanelCount-1 DOWNTO 0), --
123 sdo => sdo(ChanelCount-1 DOWNTO 0), --
124 sample => sample,
124 sample => sample,
125 sample_val => sample_val);
125 sample_val => sample_val);
126
126
127 -----------------------------------------------------------------------------
127 -----------------------------------------------------------------------------
128
128
129 PROCESS (clk, rstn)
129 PROCESS (clk, rstn)
130 BEGIN -- PROCESS
130 BEGIN -- PROCESS
131 IF rstn = '0' THEN -- asynchronous reset (active low)
131 IF rstn = '0' THEN -- asynchronous reset (active low)
132 sample_val_delay <= '0';
132 sample_val_delay <= '0';
133 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
133 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
134 sample_val_delay <= sample_val;
134 sample_val_delay <= sample_val;
135 END IF;
135 END IF;
136 END PROCESS;
136 END PROCESS;
137
137
138 -----------------------------------------------------------------------------
138 -----------------------------------------------------------------------------
139 ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
139 ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
140 SampleLoop : FOR j IN 0 TO 15 GENERATE
140 SampleLoop : FOR j IN 0 TO 15 GENERATE
141 sample_filter_in(i, j) <= sample(i)(j);
141 sample_filter_in(i, j) <= sample(i)(j);
142 END GENERATE;
142 END GENERATE;
143
143
144 sample_filter_in(i, 16) <= sample(i)(15);
144 sample_filter_in(i, 16) <= sample(i)(15);
145 sample_filter_in(i, 17) <= sample(i)(15);
145 sample_filter_in(i, 17) <= sample(i)(15);
146 END GENERATE;
146 END GENERATE;
147
147
148 -- coefs <= CoefsInitValCst;
148 -- coefs <= CoefsInitValCst;
149 coefs_JC <= CoefsInitValCst_JC;
149 coefs_JC <= CoefsInitValCst_JC;
150
150
151 --FILTER : IIR_CEL_CTRLR
151 --FILTER : IIR_CEL_CTRLR
152 -- GENERIC MAP (
152 -- GENERIC MAP (
153 -- tech => 0,
153 -- tech => 0,
154 -- Sample_SZ => 18,
154 -- Sample_SZ => 18,
155 -- ChanelsCount => ChanelCount,
155 -- ChanelsCount => ChanelCount,
156 -- Coef_SZ => Coef_SZ,
156 -- Coef_SZ => Coef_SZ,
157 -- CoefCntPerCel => CoefCntPerCel,
157 -- CoefCntPerCel => CoefCntPerCel,
158 -- Cels_count => Cels_count,
158 -- Cels_count => Cels_count,
159 -- Mem_use => use_CEL) -- use_CEL for SIMU, use_RAM for synthesis
159 -- Mem_use => use_CEL) -- use_CEL for SIMU, use_RAM for synthesis
160 -- PORT MAP (
160 -- PORT MAP (
161 -- reset => rstn,
161 -- reset => rstn,
162 -- clk => clk,
162 -- clk => clk,
163 -- sample_clk => sample_val_delay,
163 -- sample_clk => sample_val_delay,
164 -- sample_in => sample_filter_in,
164 -- sample_in => sample_filter_in,
165 -- sample_out => sample_filter_out,
165 -- sample_out => sample_filter_out,
166 -- virg_pos => 7,
166 -- virg_pos => 7,
167 -- GOtest => OPEN,
167 -- GOtest => OPEN,
168 -- coefs => coefs);
168 -- coefs => coefs);
169
169
170 IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
170 IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
171 GENERIC MAP (
171 GENERIC MAP (
172 tech => 0,
172 tech => 0,
173 Mem_use => use_CEL,
173 Mem_use => use_RAM,
174 Sample_SZ => 18,
174 Sample_SZ => 18,
175 Coef_SZ => Coef_SZ,
175 Coef_SZ => Coef_SZ,
176 Coef_Nb => 25, -- TODO
176 Coef_Nb => 25, -- TODO
177 Coef_sel_SZ => 5, -- TODO
177 Coef_sel_SZ => 5, -- TODO
178 Cels_count => Cels_count,
178 Cels_count => Cels_count,
179 ChanelsCount => ChanelCount)
179 ChanelsCount => ChanelCount)
180 PORT MAP (
180 PORT MAP (
181 rstn => rstn,
181 rstn => rstn,
182 clk => clk,
182 clk => clk,
183 virg_pos => 7,
183 virg_pos => 7,
184 coefs => coefs_JC,
184 coefs => coefs_JC,
185 sample_in_val => sample_val_delay,
185 sample_in_val => sample_val_delay,
186 sample_in => sample_filter_in,
186 sample_in => sample_filter_in,
187 sample_out_val => sample_filter_JC_out_val,
187 sample_out_val => sample_filter_JC_out_val,
188 sample_out => sample_filter_JC_out);
188 sample_out => sample_filter_JC_out);
189
189
190 -----------------------------------------------------------------------------
190 -----------------------------------------------------------------------------
191 PROCESS (clk, rstn)
191 PROCESS (clk, rstn)
192 BEGIN -- PROCESS
192 BEGIN -- PROCESS
193 IF rstn = '0' THEN -- asynchronous reset (active low)
193 IF rstn = '0' THEN -- asynchronous reset (active low)
194 sample_filter_JC_out_r_val <= '0';
194 sample_filter_JC_out_r_val <= '0';
195 rst_all_chanel : FOR I IN ChanelCount-1 DOWNTO 0 LOOP
195 rst_all_chanel : FOR I IN ChanelCount-1 DOWNTO 0 LOOP
196 rst_all_bits : FOR J IN 17 DOWNTO 0 LOOP
196 rst_all_bits : FOR J IN 17 DOWNTO 0 LOOP
197 sample_filter_JC_out_r(I, J) <= '0';
197 sample_filter_JC_out_r(I, J) <= '0';
198 END LOOP rst_all_bits;
198 END LOOP rst_all_bits;
199 END LOOP rst_all_chanel;
199 END LOOP rst_all_chanel;
200 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
200 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
201 sample_filter_JC_out_r_val <= sample_filter_JC_out_val;
201 sample_filter_JC_out_r_val <= sample_filter_JC_out_val;
202 IF sample_filter_JC_out_val = '1' THEN
202 IF sample_filter_JC_out_val = '1' THEN
203 sample_filter_JC_out_r <= sample_filter_JC_out;
203 sample_filter_JC_out_r <= sample_filter_JC_out;
204 END IF;
204 END IF;
205 END IF;
205 END IF;
206 END PROCESS;
206 END PROCESS;
207
207
208 -----------------------------------------------------------------------------
208 -----------------------------------------------------------------------------
209 -- F0 -- @24.576 kHz
209 -- F0 -- @24.576 kHz
210 -----------------------------------------------------------------------------
210 -----------------------------------------------------------------------------
211 Downsampling_f0 : Downsampling
211 Downsampling_f0 : Downsampling
212 GENERIC MAP (
212 GENERIC MAP (
213 ChanelCount => ChanelCount,
213 ChanelCount => ChanelCount,
214 SampleSize => 18,
214 SampleSize => 18,
215 DivideParam => 4)
215 DivideParam => 4)
216 PORT MAP (
216 PORT MAP (
217 clk => clk,
217 clk => clk,
218 rstn => rstn,
218 rstn => rstn,
219 sample_in_val => sample_filter_JC_out_val ,
219 sample_in_val => sample_filter_JC_out_val ,
220 sample_in => sample_filter_JC_out,
220 sample_in => sample_filter_JC_out,
221 sample_out_val => sample_f0_val,
221 sample_out_val => sample_f0_val,
222 sample_out => sample_f0);
222 sample_out => sample_f0);
223
223
224 all_bit_sample_f0 : FOR I IN 17 DOWNTO 0 GENERATE
224 all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE
225 sample_f0_wdata(I) <= sample_f0(0, I);
225 sample_f0_wdata(I) <= sample_f0(0, I);
226 sample_f0_wdata(18*1+I) <= sample_f0(1, I);
226 sample_f0_wdata(16*1+I) <= sample_f0(1, I);
227 sample_f0_wdata(18*2+I) <= sample_f0(2, I);
227 sample_f0_wdata(16*2+I) <= sample_f0(2, I);
228 sample_f0_wdata(18*3+I) <= sample_f0(6, I);
228 sample_f0_wdata(16*3+I) <= sample_f0(6, I);
229 sample_f0_wdata(18*4+I) <= sample_f0(7, I);
229 sample_f0_wdata(16*4+I) <= sample_f0(7, I);
230 END GENERATE all_bit_sample_f0;
230 END GENERATE all_bit_sample_f0;
231
231
232 PROCESS (clk, rstn)
232 PROCESS (clk, rstn)
233 BEGIN -- PROCESS
233 BEGIN -- PROCESS
234 IF rstn = '0' THEN -- asynchronous reset (active low)
234 IF rstn = '0' THEN -- asynchronous reset (active low)
235 counter_f0 <= 0;
235 counter_f0 <= 0;
236 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
236 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
237 IF sample_f0_val = '1' THEN
237 IF sample_f0_val = '1' THEN
238 IF counter_f0 = 511 THEN
238 IF counter_f0 = 511 THEN
239 counter_f0 <= 0;
239 counter_f0 <= 0;
240 ELSE
240 ELSE
241 counter_f0 <= counter_f0 + 1;
241 counter_f0 <= counter_f0 + 1;
242 END IF;
242 END IF;
243 END IF;
243 END IF;
244 END IF;
244 END IF;
245 END PROCESS;
245 END PROCESS;
246
246
247 sample_f0_0_val <= sample_f0_val WHEN counter_f0 < 256 ELSE '0';
247 sample_f0_0_val <= sample_f0_val WHEN counter_f0 < 256 ELSE '0';
248 sample_f0_0_wen <= NOT(sample_f0_0_val) &
248 sample_f0_0_wen <= NOT(sample_f0_0_val) &
249 NOT(sample_f0_0_val) &
249 NOT(sample_f0_0_val) &
250 NOT(sample_f0_0_val) &
250 NOT(sample_f0_0_val) &
251 NOT(sample_f0_0_val) &
251 NOT(sample_f0_0_val) &
252 NOT(sample_f0_0_val);
252 NOT(sample_f0_0_val);
253
253
254 sample_f0_1_val <= sample_f0_val WHEN counter_f0 > 255 ELSE '0';
254 sample_f0_1_val <= sample_f0_val WHEN counter_f0 > 255 ELSE '0';
255 sample_f0_1_wen <= NOT(sample_f0_1_val) &
255 sample_f0_1_wen <= NOT(sample_f0_1_val) &
256 NOT(sample_f0_1_val) &
256 NOT(sample_f0_1_val) &
257 NOT(sample_f0_1_val) &
257 NOT(sample_f0_1_val) &
258 NOT(sample_f0_1_val) &
258 NOT(sample_f0_1_val) &
259 NOT(sample_f0_1_val);
259 NOT(sample_f0_1_val);
260
260
261
261
262 -----------------------------------------------------------------------------
262 -----------------------------------------------------------------------------
263 -- F1 -- @4096 Hz
263 -- F1 -- @4096 Hz
264 -----------------------------------------------------------------------------
264 -----------------------------------------------------------------------------
265 Downsampling_f1 : Downsampling
265 Downsampling_f1 : Downsampling
266 GENERIC MAP (
266 GENERIC MAP (
267 ChanelCount => ChanelCount,
267 ChanelCount => ChanelCount,
268 SampleSize => 18,
268 SampleSize => 18,
269 DivideParam => 6)
269 DivideParam => 6)
270 PORT MAP (
270 PORT MAP (
271 clk => clk,
271 clk => clk,
272 rstn => rstn,
272 rstn => rstn,
273 sample_in_val => sample_f0_val ,
273 sample_in_val => sample_f0_val ,
274 sample_in => sample_f0,
274 sample_in => sample_f0,
275 sample_out_val => sample_f1_val,
275 sample_out_val => sample_f1_val,
276 sample_out => sample_f1);
276 sample_out => sample_f1);
277
277
278 sample_f1_wen <= NOT(sample_f1_val) &
278 sample_f1_wen <= NOT(sample_f1_val) &
279 NOT(sample_f1_val) &
279 NOT(sample_f1_val) &
280 NOT(sample_f1_val) &
280 NOT(sample_f1_val) &
281 NOT(sample_f1_val) &
281 NOT(sample_f1_val) &
282 NOT(sample_f1_val);
282 NOT(sample_f1_val);
283
283
284 all_bit_sample_f1 : FOR I IN 17 DOWNTO 0 GENERATE
284 all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE
285 sample_f1_wdata(I) <= sample_f1(0, I);
285 sample_f1_wdata(I) <= sample_f1(0, I);
286 sample_f1_wdata(18*1+I) <= sample_f1(1, I);
286 sample_f1_wdata(16*1+I) <= sample_f1(1, I);
287 sample_f1_wdata(18*2+I) <= sample_f1(2, I);
287 sample_f1_wdata(16*2+I) <= sample_f1(2, I);
288 sample_f1_wdata(18*3+I) <= sample_f1(6, I);
288 sample_f1_wdata(16*3+I) <= sample_f1(6, I);
289 sample_f1_wdata(18*4+I) <= sample_f1(7, I);
289 sample_f1_wdata(16*4+I) <= sample_f1(7, I);
290 END GENERATE all_bit_sample_f1;
290 END GENERATE all_bit_sample_f1;
291
291
292 -----------------------------------------------------------------------------
292 -----------------------------------------------------------------------------
293 -- F2 -- @16 Hz
293 -- F2 -- @16 Hz
294 -----------------------------------------------------------------------------
294 -----------------------------------------------------------------------------
295 Downsampling_f2 : Downsampling
295 Downsampling_f2 : Downsampling
296 GENERIC MAP (
296 GENERIC MAP (
297 ChanelCount => ChanelCount,
297 ChanelCount => ChanelCount,
298 SampleSize => 18,
298 SampleSize => 18,
299 DivideParam => 256)
299 DivideParam => 256)
300 PORT MAP (
300 PORT MAP (
301 clk => clk,
301 clk => clk,
302 rstn => rstn,
302 rstn => rstn,
303 sample_in_val => sample_f1_val ,
303 sample_in_val => sample_f1_val ,
304 sample_in => sample_f1,
304 sample_in => sample_f1,
305 sample_out_val => sample_f2_val,
305 sample_out_val => sample_f2_val,
306 sample_out => sample_f2);
306 sample_out => sample_f2);
307
307
308 sample_f2_wen <= NOT(sample_f2_val) &
308 sample_f2_wen <= NOT(sample_f2_val) &
309 NOT(sample_f2_val) &
309 NOT(sample_f2_val) &
310 NOT(sample_f2_val) &
310 NOT(sample_f2_val) &
311 NOT(sample_f2_val) &
311 NOT(sample_f2_val) &
312 NOT(sample_f2_val);
312 NOT(sample_f2_val);
313
313
314 all_bit_sample_f2 : FOR I IN 17 DOWNTO 0 GENERATE
314 all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE
315 sample_f2_wdata(I) <= sample_f2(0, I);
315 sample_f2_wdata(I) <= sample_f2(0, I);
316 sample_f2_wdata(18*1+I) <= sample_f2(1, I);
316 sample_f2_wdata(16*1+I) <= sample_f2(1, I);
317 sample_f2_wdata(18*2+I) <= sample_f2(2, I);
317 sample_f2_wdata(16*2+I) <= sample_f2(2, I);
318 sample_f2_wdata(18*3+I) <= sample_f2(6, I);
318 sample_f2_wdata(16*3+I) <= sample_f2(6, I);
319 sample_f2_wdata(18*4+I) <= sample_f2(7, I);
319 sample_f2_wdata(16*4+I) <= sample_f2(7, I);
320 END GENERATE all_bit_sample_f2;
320 END GENERATE all_bit_sample_f2;
321
321
322 -----------------------------------------------------------------------------
322 -----------------------------------------------------------------------------
323 -- F3 -- @256 Hz
323 -- F3 -- @256 Hz
324 -----------------------------------------------------------------------------
324 -----------------------------------------------------------------------------
325 Downsampling_f3 : Downsampling
325 Downsampling_f3 : Downsampling
326 GENERIC MAP (
326 GENERIC MAP (
327 ChanelCount => ChanelCount,
327 ChanelCount => ChanelCount,
328 SampleSize => 18,
328 SampleSize => 18,
329 DivideParam => 96)
329 DivideParam => 96)
330 PORT MAP (
330 PORT MAP (
331 clk => clk,
331 clk => clk,
332 rstn => rstn,
332 rstn => rstn,
333 sample_in_val => sample_f0_val ,
333 sample_in_val => sample_f0_val ,
334 sample_in => sample_f0,
334 sample_in => sample_f0,
335 sample_out_val => sample_f3_val,
335 sample_out_val => sample_f3_val,
336 sample_out => sample_f3);
336 sample_out => sample_f3);
337
337
338 sample_f3_wen <= (NOT sample_f3_val) &
338 sample_f3_wen <= (NOT sample_f3_val) &
339 (NOT sample_f3_val) &
339 (NOT sample_f3_val) &
340 (NOT sample_f3_val) &
340 (NOT sample_f3_val) &
341 (NOT sample_f3_val) &
341 (NOT sample_f3_val) &
342 (NOT sample_f3_val);
342 (NOT sample_f3_val);
343
343
344 all_bit_sample_f3 : FOR I IN 17 DOWNTO 0 GENERATE
344 all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE
345 sample_f3_wdata(I) <= sample_f3(0, I);
345 sample_f3_wdata(I) <= sample_f3(0, I);
346 sample_f3_wdata(18*1+I) <= sample_f3(1, I);
346 sample_f3_wdata(16*1+I) <= sample_f3(1, I);
347 sample_f3_wdata(18*2+I) <= sample_f3(2, I);
347 sample_f3_wdata(16*2+I) <= sample_f3(2, I);
348 sample_f3_wdata(18*3+I) <= sample_f3(6, I);
348 sample_f3_wdata(16*3+I) <= sample_f3(6, I);
349 sample_f3_wdata(18*4+I) <= sample_f3(7, I);
349 sample_f3_wdata(16*4+I) <= sample_f3(7, I);
350 END GENERATE all_bit_sample_f3;
350 END GENERATE all_bit_sample_f3;
351
351
352
352
353
353
354 END tb;
354 END tb;
Show file before | Show file after | Hide comments
@@ -1,36 +1,36
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 LIBRARY lpp;
3 LIBRARY lpp;
4 USE lpp.lpp_ad_conv.ALL;
4 USE lpp.lpp_ad_conv.ALL;
5 USE lpp.iir_filter.ALL;
5 USE lpp.iir_filter.ALL;
6 USE lpp.FILTERcfg.ALL;
6 USE lpp.FILTERcfg.ALL;
7 USE lpp.lpp_memory.ALL;
7 USE lpp.lpp_memory.ALL;
8 LIBRARY techmap;
8 LIBRARY techmap;
9 USE techmap.gencomp.ALL;
9 USE techmap.gencomp.ALL;
10
10
11 PACKAGE lpp_top_lfr_pkg IS
11 PACKAGE lpp_top_lfr_pkg IS
12
12
13 COMPONENT lpp_top_acq
13 COMPONENT lpp_top_acq
14 GENERIC (
14 GENERIC (
15 tech : integer);
15 tech : integer);
16 PORT (
16 PORT (
17 cnv_run : IN STD_LOGIC;
17 cnv_run : IN STD_LOGIC;
18 cnv : OUT STD_LOGIC;
18 cnv : OUT STD_LOGIC;
19 sck : OUT STD_LOGIC;
19 sck : OUT STD_LOGIC;
20 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
20 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
21 cnv_clk : IN STD_LOGIC;
21 cnv_clk : IN STD_LOGIC;
22 cnv_rstn : IN STD_LOGIC;
22 cnv_rstn : IN STD_LOGIC;
23 clk : IN STD_LOGIC;
23 clk : IN STD_LOGIC;
24 rstn : IN STD_LOGIC;
24 rstn : IN STD_LOGIC;
25 sample_f0_0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
25 sample_f0_0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
26 sample_f0_1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
26 sample_f0_1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
27 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
27 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
28 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
28 sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
29 sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
29 sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
30 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
30 sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
31 sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
31 sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
32 sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
32 sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
33 sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0));
33 sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0));
34 END COMPONENT;
34 END COMPONENT;
35
35
36 END lpp_top_lfr_pkg;
36 END lpp_top_lfr_pkg; No newline at end of file
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