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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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-- Author : Martin Morlot
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-- Mail : martin.morlot@lpp.polytechnique.fr
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.amba.all;
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use std.textio.all;
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library lpp;
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use lpp.lpp_amba.all;
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--! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
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package lpp_demux is
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component Demultiplex is
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generic(
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Data_sz : integer range 1 to 32 := 16);
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port(
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clk : in std_logic;
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rstn : in std_logic;
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Read : in std_logic_vector(4 downto 0);
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EmptyF0a : in std_logic_vector(4 downto 0);
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EmptyF0b : in std_logic_vector(4 downto 0);
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EmptyF1 : in std_logic_vector(4 downto 0);
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EmptyF2 : in std_logic_vector(4 downto 0);
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DataF0a : in std_logic_vector((5*Data_sz)-1 downto 0);
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DataF0b : in std_logic_vector((5*Data_sz)-1 downto 0);
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DataF1 : in std_logic_vector((5*Data_sz)-1 downto 0);
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DataF2 : in std_logic_vector((5*Data_sz)-1 downto 0);
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Read_DEMUX : out std_logic_vector(19 downto 0);
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Empty : out std_logic_vector(4 downto 0);
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Data : out std_logic_vector((5*Data_sz)-1 downto 0)
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);
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end component;
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component DEMUX is
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generic(
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Data_sz : integer range 1 to 32 := 16);
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port(
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clk : in std_logic;
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rstn : in std_logic;
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Read : in std_logic_vector(4 downto 0);
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DataCpt : in std_logic_vector(3 downto 0); -- f2 f1 f0b f0a
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EmptyF0a : in std_logic_vector(4 downto 0);
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EmptyF0b : in std_logic_vector(4 downto 0);
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EmptyF1 : in std_logic_vector(4 downto 0);
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EmptyF2 : in std_logic_vector(4 downto 0);
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DataF0a : in std_logic_vector((5*Data_sz)-1 downto 0);
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DataF0b : in std_logic_vector((5*Data_sz)-1 downto 0);
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DataF1 : in std_logic_vector((5*Data_sz)-1 downto 0);
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DataF2 : in std_logic_vector((5*Data_sz)-1 downto 0);
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Read_DEMUX : out std_logic_vector(19 downto 0);
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Empty : out std_logic_vector(4 downto 0);
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Data : out std_logic_vector((5*Data_sz)-1 downto 0)
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);
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end component;
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component WatchFlag is
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port(
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clk : in std_logic;
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rstn : in std_logic;
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EmptyF0a : in std_logic_vector(4 downto 0);
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EmptyF0b : in std_logic_vector(4 downto 0);
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EmptyF1 : in std_logic_vector(4 downto 0);
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EmptyF2 : in std_logic_vector(4 downto 0);
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DataCpt : out std_logic_vector(3 downto 0) -- f2 f1 f0b f0a
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);
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end component;
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end;
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