# HG changeset patch # User martin # Date 2013-04-15 14:16:36 # Node ID 22d60c2dfe8c3ba362cc0df1a3be203197f07be4 # Parent e09c526b7abe16479a79eff10cf5a7770ca2772b Modif ALU Top de la chaine de traitement, Synthesis = OK, cf "leon3mp.vhd" diff --git a/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd b/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd --- a/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd +++ b/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd @@ -79,7 +79,8 @@ ARCHITECTURE ar_IIR_CEL_CTRLR_v2 OF IIR_ waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0); alu_sel_input : IN STD_LOGIC; alu_sel_coeff : IN STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0); - alu_ctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + alu_ctrl : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + alu_comp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); sample_in : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); sample_out : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0)); END COMPONENT; @@ -105,7 +106,7 @@ ARCHITECTURE ar_IIR_CEL_CTRLR_v2 OF IIR_ waddr_previous : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); alu_sel_input : OUT STD_LOGIC; alu_sel_coeff : OUT STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0); - alu_ctrl : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); + alu_ctrl : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)); END COMPONENT; SIGNAL in_sel_src : STD_LOGIC_VECTOR(1 DOWNTO 0); @@ -117,7 +118,7 @@ ARCHITECTURE ar_IIR_CEL_CTRLR_v2 OF IIR_ SIGNAL waddr_previous : STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL alu_sel_input : STD_LOGIC; SIGNAL alu_sel_coeff : STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0); - SIGNAL alu_ctrl : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL alu_ctrl : STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL sample_in_buf : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); SIGNAL sample_in_rotate : STD_LOGIC; @@ -155,6 +156,7 @@ BEGIN alu_sel_input => alu_sel_input, alu_sel_coeff => alu_sel_coeff, alu_ctrl => alu_ctrl, + alu_comp => "00", --DATA sample_in => sample_in_s, sample_out => sample_out_s); diff --git a/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd b/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd --- a/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd +++ b/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd @@ -50,7 +50,7 @@ ENTITY IIR_CEL_CTRLR_v2_CONTROL IS waddr_previous : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); alu_sel_input : OUT STD_LOGIC; alu_sel_coeff : OUT STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0); - alu_ctrl : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) + alu_ctrl : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) ); END IIR_CEL_CTRLR_v2_CONTROL; @@ -92,7 +92,7 @@ BEGIN --ALU ------------------------------------------------------------------- alu_selected_coeff <= 0; -- alu_sel_input <= '0'; -- - alu_ctrl <= (OTHERS => '0'); -- + alu_ctrl <= ctrl_IDLE; -- --OUT sample_out_val <= '0'; -- sample_out_rot <= '0'; -- @@ -108,7 +108,7 @@ BEGIN sample_out_rot <= '0'; sample_in_rot <= '0'; sample_out_val <= '0'; - alu_ctrl <= "0100"; + alu_ctrl <= ctrl_CLRMAC; alu_selected_coeff <= 0; in_sel_src <= "01"; ram_read <= '0'; @@ -134,7 +134,7 @@ BEGIN IIR_CEL_STATE <= compute_b2; ram_read <= '1'; raddr_add1 <= '1'; - alu_ctrl <= "0010"; + alu_ctrl <= ctrl_MULT; alu_sel_input <= '1'; in_sel_src <= "01"; @@ -160,7 +160,7 @@ BEGIN in_sel_src <= "11"; END IF; alu_selected_coeff <= alu_selected_coeff+1; - alu_ctrl <= "0001"; + alu_ctrl <= ctrl_MAC; IIR_CEL_STATE <= compute_b1; WHEN compute_b1 => @@ -183,7 +183,7 @@ BEGIN in_sel_src <= "00"; END IF; alu_selected_coeff <= alu_selected_coeff+1; - alu_ctrl <= "0001"; + alu_ctrl <= ctrl_MAC; IIR_CEL_STATE <= compute_b0; WHEN compute_b0 => @@ -199,7 +199,7 @@ BEGIN raddr_add1 <= '0'; in_sel_src <= "10"; alu_selected_coeff <= alu_selected_coeff+1; - alu_ctrl <= "0001"; + alu_ctrl <= ctrl_MAC; IIR_CEL_STATE <= compute_a2; IF Cel_ongoing = Cels_count THEN sample_in_rot <= '1'; @@ -223,7 +223,7 @@ BEGIN END IF; in_sel_src <= "00"; alu_selected_coeff <= alu_selected_coeff+1; - alu_ctrl <= "0001"; + alu_ctrl <= ctrl_MAC; IIR_CEL_STATE <= compute_a1; sample_in_rot <= '0'; @@ -236,7 +236,7 @@ BEGIN waddr_previous <= "01"; ram_read <= '1'; raddr_rst <= '0'; - alu_ctrl <= "0010"; + alu_ctrl <= ctrl_MULT; sample_in_rot <= '0'; IF Cel_ongoing = Cels_count THEN alu_selected_coeff <= 0; @@ -274,7 +274,7 @@ BEGIN WHEN wait_valid_last_output => IIR_CEL_STATE <= wait_valid_last_output_2; sample_in_rot <= '0'; - alu_ctrl <= "0000"; + alu_ctrl <= ctrl_IDLE; alu_selected_coeff <= 0; in_sel_src <= "01"; ram_read <= '0'; @@ -291,7 +291,7 @@ BEGIN WHEN wait_valid_last_output_2 => IIR_CEL_STATE <= waiting; sample_in_rot <= '0'; - alu_ctrl <= "0000"; + alu_ctrl <= ctrl_IDLE; alu_selected_coeff <= 0; in_sel_src <= "01"; ram_read <= '0'; @@ -310,4 +310,4 @@ BEGIN END IF; END PROCESS; -END ar_IIR_CEL_CTRLR_v2_CONTROL; +END ar_IIR_CEL_CTRLR_v2_CONTROL; \ No newline at end of file diff --git a/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd b/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd --- a/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd +++ b/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd @@ -55,7 +55,8 @@ ENTITY IIR_CEL_CTRLR_v2_DATAFLOW IS -- alu_sel_input : IN STD_LOGIC; alu_sel_coeff : IN STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0); - alu_ctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0);--(MAC_op, MULT_with_clear_ADD, IDLE) + alu_ctrl : IN STD_LOGIC_VECTOR(2 DOWNTO 0);--(MAC_op, MULT_with_clear_ADD, IDLE) + alu_comp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); -- DATA sample_in : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); sample_out : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0) @@ -200,6 +201,7 @@ BEGIN clk => clk, reset => rstn, ctrl => alu_ctrl, + comp => alu_comp, OP1 => alu_sample, OP2 => alu_coef, RES => alu_output_s); diff --git a/lib/lpp/dsp/lpp_fft/FFT.vhd b/lib/lpp/dsp/lpp_fft/FFT.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/dsp/lpp_fft/FFT.vhd @@ -0,0 +1,91 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +library lpp; +use lpp.lpp_fft.all; +use work.fft_components.all; + +entity FFT is + generic( + Data_sz : integer := 16; + NbData : integer := 256); + port( + clkm : in std_logic; + rstn : in std_logic; + FifoIN_Empty : in std_logic_vector(4 downto 0); + FifoIN_Data : in std_logic_vector(79 downto 0); + FifoOUT_Full : in std_logic_vector(4 downto 0); + Read : out std_logic_vector(4 downto 0); + Write : out std_logic_vector(4 downto 0); + ReUse : out std_logic_vector(4 downto 0); + Data : out std_logic_vector(79 downto 0) + ); +end entity; + + +architecture ar_FFT of FFT is + +signal Drive_Write : std_logic; +signal Drive_DataRE : std_logic_vector(15 downto 0); +signal Drive_DataIM : std_logic_vector(15 downto 0); + +signal Start : std_logic; +signal FFT_Load : std_logic; +signal FFT_Ready : std_logic; +signal FFT_Valid : std_logic; +signal FFT_DataRE : std_logic_vector(15 downto 0); +signal FFT_DataIM : std_logic_vector(15 downto 0); + +signal Link_Read : std_logic; + +begin + +Start <= '0'; + + DRIVE : Driver_FFT + generic map(Data_sz,NbData) + port map(clkm,rstn,FFT_Load,FifoIN_Empty,FifoIN_Data,Drive_Write,Read,Drive_DataRE,Drive_DataIM); + + FFT0 : CoreFFT + generic map( + LOGPTS => gLOGPTS, + LOGLOGPTS => gLOGLOGPTS, + WSIZE => gWSIZE, + TWIDTH => gTWIDTH, + DWIDTH => gDWIDTH, + TDWIDTH => gTDWIDTH, + RND_MODE => gRND_MODE, + SCALE_MODE => gSCALE_MODE, + PTS => gPTS, + HALFPTS => gHALFPTS, + inBuf_RWDLY => gInBuf_RWDLY) + port map(clkm,start,rstn,Drive_Write,Link_Read,Drive_DataIM,Drive_DataRE,FFT_Load,open,FFT_DataIM,FFT_DataRE,FFT_Valid,FFT_Ready); + + + LINK : Linker_FFT + generic map(Data_sz,NbData) + port map(clkm,rstn,FFT_Ready,FFT_Valid,FifoOUT_Full,FFT_DataRE,FFT_DataIM,Link_Read,Write,ReUse,Data); + + +end architecture; \ No newline at end of file diff --git a/lib/lpp/dsp/lpp_fft/lpp_fft.vhd b/lib/lpp/dsp/lpp_fft/lpp_fft.vhd --- a/lib/lpp/dsp/lpp_fft/lpp_fft.vhd +++ b/lib/lpp/dsp/lpp_fft/lpp_fft.vhd @@ -26,7 +26,6 @@ use grlib.amba.all; use std.textio.all; library lpp; use lpp.lpp_amba.all; -use lpp.lpp_memory.all; use work.fft_components.all; --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on @@ -75,6 +74,22 @@ component APB_FFT_half is ); end component; +component FFT is + generic( + Data_sz : integer := 16; + NbData : integer := 256); + port( + clkm : in std_logic; + rstn : in std_logic; + FifoIN_Empty : in std_logic_vector(4 downto 0); + FifoIN_Data : in std_logic_vector(79 downto 0); + FifoOUT_Full : in std_logic_vector(4 downto 0); + Read : out std_logic_vector(4 downto 0); + Write : out std_logic_vector(4 downto 0); + ReUse : out std_logic_vector(4 downto 0); + Data : out std_logic_vector(79 downto 0) + ); +end component; component Flag_Extremum is port( diff --git a/lib/lpp/general_purpose/ALU.vhd b/lib/lpp/general_purpose/ALU.vhd --- a/lib/lpp/general_purpose/ALU.vhd +++ b/lib/lpp/general_purpose/ALU.vhd @@ -1,77 +1,63 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Alexis Jeandet --- Mail : alexis.jeandet@lpp.polytechnique.fr ----------------------------------------------------------------------------- -LIBRARY IEEE; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_1164.ALL; -LIBRARY lpp; -USE lpp.general_purpose.ALL; ---IDLE = 0000 ---MAC = 0001 ---MULT = 0010 and set MULT in ADD reg ---ADD = 0011 ---CLRMAC = 0100 - - -ENTITY ALU IS - GENERIC( - Arith_en : INTEGER := 1; - Logic_en : INTEGER := 1; - Input_SZ_1 : INTEGER := 16; - Input_SZ_2 : INTEGER := 9 - - ); - PORT( - clk : IN STD_LOGIC; - reset : IN STD_LOGIC; - ctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); - OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0); - RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0) - ); -END ENTITY; - -ARCHITECTURE ar_ALU OF ALU IS - - SIGNAL clr_MAC : STD_LOGIC := '1'; - -BEGIN - clr_MAC <= '1' WHEN ctrl = "0100" OR ctrl = "0101" OR ctrl = "0110" ELSE '0'; - - arith : IF Arith_en = 1 GENERATE - MACinst : MAC - GENERIC MAP(Input_SZ_1, Input_SZ_2) - PORT MAP(clk, reset, clr_MAC, ctrl(1 DOWNTO 0), OP1, OP2, RES); - END GENERATE; - -END ARCHITECTURE; - - - - - - - - - - - - +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------- +library IEEE; +use IEEE.numeric_std.all; +use IEEE.std_logic_1164.all; +library lpp; +use lpp.general_purpose.all; + +--! Une ALU : Arithmetic and logical unit, permettant de r�aliser une ou plusieurs op�ration + +entity ALU is +generic( + Arith_en : integer := 1; + Logic_en : integer := 1; + Input_SZ_1 : integer := 16; + Input_SZ_2 : integer := 16); +port( + clk : in std_logic; --! Horloge du composant + reset : in std_logic; --! Reset general du composant + ctrl : in std_logic_vector(2 downto 0); --! Permet de s�lectionner la/les op�ration d�sir�e + comp : in std_logic_vector(1 downto 0); --! (set) Permet de compl�menter les op�randes + OP1 : in std_logic_vector(Input_SZ_1-1 downto 0); --! Premier Op�rande + OP2 : in std_logic_vector(Input_SZ_2-1 downto 0); --! Second Op�rande + RES : out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0) --! R�sultat de l'op�ration +); +end ALU; + +--! @details S�lection grace a l'entr�e "ctrl" : +--! Pause : IDLE = 000 +--! Multiplieur/Accumulateur : MAC = 001 +--! Multiplication : MULT = 010 +--! Addition : ADD = 011 +--! Reset du MAC : CLRMAC = 100 +architecture ar_ALU of ALU is + +begin + +arith : if Arith_en = 1 generate +MACinst : MAC +generic map(Input_SZ_1,Input_SZ_2) +port map(clk,reset,ctrl(2),ctrl(1 downto 0),comp,OP1,OP2,RES); +end generate; + +end architecture; \ No newline at end of file diff --git a/lib/lpp/general_purpose/MAC.vhd b/lib/lpp/general_purpose/MAC.vhd --- a/lib/lpp/general_purpose/MAC.vhd +++ b/lib/lpp/general_purpose/MAC.vhd @@ -40,6 +40,7 @@ ENTITY MAC IS reset : IN STD_LOGIC; clr_MAC : IN STD_LOGIC; MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + Comp_2C : IN STD_LOGIC_VECTOR(1 DOWNTO 0); OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0) @@ -51,34 +52,35 @@ END MAC; ARCHITECTURE ar_MAC OF MAC IS - SIGNAL add, mult : STD_LOGIC; - SIGNAL MULTout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); +signal add,mult : std_logic; +signal MULTout : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); - SIGNAL ADDERinA : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); - SIGNAL ADDERinB : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); - SIGNAL ADDERout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); +signal ADDERinA : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); +signal ADDERinB : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); +signal ADDERout : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); +signal MACMUXsel : std_logic; +signal OP1_2C_D_Resz : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); +signal OP2_2C_D_Resz : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); - SIGNAL MACMUXsel : STD_LOGIC; - SIGNAL OP1_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); - SIGNAL OP2_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); - - +signal OP1_2C : std_logic_vector(Input_SZ_A-1 downto 0); +signal OP2_2C : std_logic_vector(Input_SZ_B-1 downto 0); - SIGNAL MACMUX2sel : STD_LOGIC; +signal MACMUX2sel : std_logic; - SIGNAL add_D : STD_LOGIC; - SIGNAL OP1_D : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); - SIGNAL OP2_D : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); - SIGNAL MULTout_D : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); - SIGNAL MACMUXsel_D : STD_LOGIC; - SIGNAL MACMUX2sel_D : STD_LOGIC; - SIGNAL MACMUX2sel_D_D : STD_LOGIC; - SIGNAL clr_MAC_D : STD_LOGIC; - SIGNAL clr_MAC_D_D : STD_LOGIC; +signal add_D : std_logic; +signal OP1_2C_D : std_logic_vector(Input_SZ_A-1 downto 0); +signal OP2_2C_D : std_logic_vector(Input_SZ_B-1 downto 0); +signal MULTout_D : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); +signal MACMUXsel_D : std_logic; +signal MACMUX2sel_D : std_logic; +signal MACMUX2sel_D_D : std_logic; +signal clr_MAC_D : std_logic; +signal clr_MAC_D_D : std_logic; +signal MAC_MUL_ADD_2C_D : std_logic_vector(1 downto 0); - SIGNAL load_mult_result : STD_LOGIC; - SIGNAL load_mult_result_D : STD_LOGIC; +SIGNAL load_mult_result : STD_LOGIC; +SIGNAL load_mult_result_D : STD_LOGIC; BEGIN @@ -111,14 +113,14 @@ BEGIN Input_SZ_A => Input_SZ_A, Input_SZ_B => Input_SZ_B ) - PORT MAP( - clk => clk, - reset => reset, - mult => mult, - OP1 => OP1, - OP2 => OP2, - RES => MULTout - ); +port map( + clk => clk, + reset => reset, + mult => mult, + OP1 => OP1_2C, + OP2 => OP2_2C, + RES => MULTout +); --============================================================== PROCESS (clk, reset) @@ -148,9 +150,38 @@ BEGIN OP2 => ADDERinB, RES => ADDERout ); + --============================================================== +--===================TWO COMPLEMENTERS========================== +--============================================================== +TWO_COMPLEMENTER1 : TwoComplementer +generic map( + Input_SZ => Input_SZ_A +) +port map( + clk => clk, + reset => reset, + clr => clr_MAC, + TwoComp => Comp_2C(0), + OP => OP1, + RES => OP1_2C +); +TWO_COMPLEMENTER2 : TwoComplementer +generic map( + Input_SZ => Input_SZ_B +) +port map( + clk => clk, + reset => reset, + clr => clr_MAC, + TwoComp => Comp_2C(1), + OP => OP2, + RES => OP2_2C +); +--============================================================== + clr_MACREG1 : MAC_REG GENERIC MAP(size => 1) PORT MAP( @@ -169,23 +200,24 @@ BEGIN Q(0) => add_D ); - OP1REG : MAC_REG - GENERIC MAP(size => Input_SZ_A) - PORT MAP( - reset => reset, - clk => clk, - D => OP1, - Q => OP1_D - ); +OP1REG : MAC_REG +generic map(size => Input_SZ_A) +port map( + reset => reset, + clk => clk, + D => OP1_2C, + Q => OP1_2C_D +); - OP2REG : MAC_REG - GENERIC MAP(size => Input_SZ_B) - PORT MAP( - reset => reset, - clk => clk, - D => OP2, - Q => OP2_D - ); + +OP2REG : MAC_REG +generic map(size => Input_SZ_B) +port map( + reset => reset, + clk => clk, + D => OP2_2C, + Q => OP2_2C_D +); MULToutREG : MAC_REG GENERIC MAP(size => Input_SZ_A+Input_SZ_B) @@ -235,14 +267,14 @@ BEGIN PORT MAP( sel => MACMUXsel_D, INA1 => ADDERout, - INA2 => OP2_D_Resz, + INA2 => OP2_2C_D_Resz, INB1 => MULTout, - INB2 => OP1_D_Resz, + INB2 => OP1_2C_D_Resz, OUTA => ADDERinA, OUTB => ADDERinB ); - OP1_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP1_D), Input_SZ_A+Input_SZ_B)); - OP2_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP2_D), Input_SZ_A+Input_SZ_B)); + OP1_2C_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP1_2C_D), Input_SZ_A+Input_SZ_B)); + OP2_2C_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP2_2C_D), Input_SZ_A+Input_SZ_B)); --============================================================== diff --git a/lib/lpp/general_purpose/TwoComplementer.vhd b/lib/lpp/general_purpose/TwoComplementer.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/general_purpose/TwoComplementer.vhd @@ -0,0 +1,72 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------- +library IEEE; +use IEEE.numeric_std.all; +use IEEE.std_logic_1164.all; + +--! Programme permetant de compl�menter ou non les entr�es de l'ALU, et ainsi de travailler avec des nombres n�gatifs + +entity TwoComplementer is +generic( + Input_SZ : integer := 16); +port( + clk : in std_logic; --! Horloge du composant + reset : in std_logic; --! Reset general du composant + clr : in std_logic; --! Un reset sp�cifique au programme + TwoComp : in std_logic; --! Autorise l'utilisation du compl�ment + OP : in std_logic_vector(Input_SZ-1 downto 0); --! Op�rande d'entr�e + RES : out std_logic_vector(Input_SZ-1 downto 0) --! R�sultat, op�rande compl�ment� ou non +); +end TwoComplementer; + + +architecture ar_TwoComplementer of TwoComplementer is + +signal REG : std_logic_vector(Input_SZ-1 downto 0); +signal OPinteger : integer; +signal RESCOMP : std_logic_vector(Input_SZ-1 downto 0); + +begin + +RES <= REG; +OPinteger <= to_integer(signed(OP)); +RESCOMP <= std_logic_vector(to_signed(-OPinteger,Input_SZ)); + + process(clk,reset) + begin + + if(reset='0')then + REG <= (others => '0'); + elsif(clk'event and clk='1')then + + if(clr='1')then + REG <= (others => '0'); + elsif(TwoComp='1')then + REG <= RESCOMP; + else + REG <= OP; + end if; + + end if; + + end process; +end ar_TwoComplementer; \ No newline at end of file diff --git a/lib/lpp/general_purpose/general_purpose.vhd b/lib/lpp/general_purpose/general_purpose.vhd --- a/lib/lpp/general_purpose/general_purpose.vhd +++ b/lib/lpp/general_purpose/general_purpose.vhd @@ -89,13 +89,23 @@ PACKAGE general_purpose IS PORT( clk : IN STD_LOGIC; reset : IN STD_LOGIC; - ctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + ctrl : IN STD_LOGIC_VECTOR(2 downto 0); + comp : IN STD_LOGIC_VECTOR(1 downto 0); OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0); RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0) ); END COMPONENT; +--------------------------------------------------------- +-------- // S�lection grace a l'entr�e "ctrl" \\ -------- +--------------------------------------------------------- +Constant ctrl_IDLE : std_logic_vector(2 downto 0) := "000"; +Constant ctrl_MAC : std_logic_vector(2 downto 0) := "001"; +Constant ctrl_MULT : std_logic_vector(2 downto 0) := "010"; +Constant ctrl_ADD : std_logic_vector(2 downto 0) := "011"; +Constant ctrl_CLRMAC : std_logic_vector(2 downto 0) := "100"; +--------------------------------------------------------- COMPONENT MAC IS GENERIC( @@ -108,12 +118,25 @@ PACKAGE general_purpose IS reset : IN STD_LOGIC; clr_MAC : IN STD_LOGIC; MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + Comp_2C : IN STD_LOGIC_VECTOR(1 DOWNTO 0); OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0) ); END COMPONENT; + COMPONENT TwoComplementer is + generic( + Input_SZ : integer := 16); + port( + clk : in std_logic; --! Horloge du composant + reset : in std_logic; --! Reset general du composant + clr : in std_logic; --! Un reset sp�cifique au programme + TwoComp : in std_logic; --! Autorise l'utilisation du compl�ment + OP : in std_logic_vector(Input_SZ-1 downto 0); --! Op�rande d'entr�e + RES : out std_logic_vector(Input_SZ-1 downto 0) --! R�sultat, op�rande compl�ment� ou non + ); + end COMPONENT; COMPONENT MAC_CONTROLER IS PORT( diff --git a/lib/lpp/leon3mp.vhd b/lib/lpp/leon3mp.vhd --- a/lib/lpp/leon3mp.vhd +++ b/lib/lpp/leon3mp.vhd @@ -45,6 +45,8 @@ use lpp.lpp_ad_conv.all; use lpp.iir_filter.all; use lpp.general_purpose.all; use lpp.Filtercfg.all; +use lpp.lpp_demux.all; +use lpp.lpp_top_lfr_pkg.all; entity leon3mp is generic ( @@ -95,6 +97,11 @@ entity leon3mp is -- UART UART_RXD : in std_logic; UART_TXD : out std_logic; +-- ACQ + Clk_49Mhz : IN STD_LOGIC; + CNV_CH1 : OUT STD_LOGIC; + SCK_CH1 : OUT STD_LOGIC; + SDO_CH1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- ADC -- ADC_in : in AD7688_in(4 downto 0); -- ADC_out : out AD7688_out; @@ -170,82 +177,84 @@ signal dsuo : dsu_out_type; --- AJOUT TEST ------------------------Signaux---------------------- --------------------------------------------------------------------- -- FIFOs -signal FifoIN_Full : std_logic_vector(4 downto 0); -signal FifoIN_Empty : std_logic_vector(4 downto 0); -signal FifoIN_Data : std_logic_vector(79 downto 0); +signal FifoF0a_Full : std_logic_vector(4 downto 0); +signal FifoF0a_Empty : std_logic_vector(4 downto 0); +signal FifoF0a_Data : std_logic_vector(79 downto 0); +signal FifoF0b_Full : std_logic_vector(4 downto 0); +signal FifoF0b_Empty : std_logic_vector(4 downto 0); +signal FifoF0b_Data : std_logic_vector(79 downto 0); +signal FifoF1_Full : std_logic_vector(4 downto 0); +signal FifoF1_Empty : std_logic_vector(4 downto 0); +signal FifoF1_Data : std_logic_vector(79 downto 0); +signal FifoF3_Full : std_logic_vector(4 downto 0); +signal FifoF3_Empty : std_logic_vector(4 downto 0); +signal FifoF3_Data : std_logic_vector(79 downto 0); signal FifoINT_Full : std_logic_vector(4 downto 0); signal FifoINT_Data : std_logic_vector(79 downto 0); -signal FifoOUT_FullV : std_logic; +--signal FifoOUT_FullV : std_logic; signal FifoOUT_Full : std_logic_vector(1 downto 0); -signal Matrix_WriteV : std_logic_vector(0 downto 0); +--signal Matrix_WriteV : std_logic_vector(0 downto 0); -- MATRICE SPECTRALE -signal Matrix_Write : std_logic; -signal Matrix_Read : std_logic_vector(1 downto 0); -signal Matrix_Result : std_logic_vector(31 downto 0); +signal SM_FlagError : std_logic; +signal SM_Pong : std_logic; +signal SM_Read : std_logic_vector(4 downto 0); +signal SM_Write : std_logic_vector(1 downto 0); +signal SM_Data : std_logic_vector(63 downto 0); -signal TopSM_Start : std_logic; -signal TopSM_Statu : std_logic_vector(3 downto 0); -signal TopSM_Read : std_logic_vector(4 downto 0); -signal TopSM_Data1 : std_logic_vector(15 downto 0); -signal TopSM_Data2 : std_logic_vector(15 downto 0); - -signal Disp_FlagError : std_logic; -signal Disp_Pong : std_logic; -signal Disp_Write : std_logic_vector(1 downto 0);-- -signal Disp_Data : std_logic_vector(63 downto 0);-- -signal Dma_acq : std_logic; +signal Dma_acq : std_logic; -- FFT -signal Drive_Write : std_logic; -signal Drive_Read : std_logic_vector(4 downto 0); -signal Drive_DataRE : std_logic_vector(15 downto 0); -signal Drive_DataIM : std_logic_vector(15 downto 0); +signal FFT_Read : std_logic_vector(4 downto 0); +signal FFT_Write : std_logic_vector(4 downto 0); +signal FFT_ReUse : std_logic_vector(4 downto 0); +signal FFT_Data : std_logic_vector(79 downto 0); -signal Start : std_logic; -signal RstnFFT : std_logic; -signal FFT_Load : std_logic; -signal FFT_Ready : std_logic; -signal FFT_Valid : std_logic; -signal FFT_DataRE : std_logic_vector(15 downto 0); -signal FFT_DataIM : std_logic_vector(15 downto 0); +-- DEMUX +signal DEMU_Read : std_logic_vector(19 downto 0); +signal DEMU_Empty : std_logic_vector(4 downto 0); +signal DEMU_Data : std_logic_vector(79 downto 0); -signal Link_Read : std_logic; -signal Link_Write : std_logic_vector(4 downto 0); -signal Link_ReUse : std_logic_vector(4 downto 0); -signal Link_Data : std_logic_vector(79 downto 0); +-- ACQ +signal TopACQ_WenF0a : STD_LOGIC_VECTOR(4 DOWNTO 0); +signal TopACQ_WenF0b : STD_LOGIC_VECTOR(4 DOWNTO 0); +signal TopACQ_DataF0 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); +signal TopACQ_WenF1 : STD_LOGIC_VECTOR(4 DOWNTO 0); +signal TopACQ_DataF1 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); +signal TopACQ_WenF3 : STD_LOGIC_VECTOR(4 DOWNTO 0); +signal TopACQ_DataF3 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); -- ADC -signal SmplClk : std_logic; -signal ADC_DataReady : std_logic; -signal ADC_SmplOut : Samples_out(4 downto 0); -signal enableADC : std_logic; - -signal WG_Write : std_logic_vector(4 downto 0); -signal WG_ReUse : std_logic_vector(4 downto 0); -signal WG_DATA : std_logic_vector(79 downto 0); -signal s_out : std_logic_vector(79 downto 0); - -signal fuller : std_logic_vector(4 downto 0); -signal reader : std_logic_vector(4 downto 0); -signal try : std_logic_vector(1 downto 0); -signal TXDint : std_logic; - --- IIR Filter -signal sample_clk_out : std_logic; - -signal Rd : std_logic_vector(0 downto 0); -signal Ept : std_logic_vector(4 downto 0); - -signal Bwr : std_logic_vector(0 downto 0); -signal Bre : std_logic_vector(0 downto 0); -signal DataTMP : std_logic_vector(15 downto 0); -signal FullUp : std_logic_vector(0 downto 0); -signal EmptyUp : std_logic_vector(0 downto 0); -signal FullDown : std_logic_vector(0 downto 0); -signal EmptyDown : std_logic_vector(0 downto 0); +--signal SmplClk : std_logic; +--signal ADC_DataReady : std_logic; +--signal ADC_SmplOut : Samples_out(4 downto 0); +--signal enableADC : std_logic; +-- +--signal WG_Write : std_logic_vector(4 downto 0); +--signal WG_ReUse : std_logic_vector(4 downto 0); +--signal WG_DATA : std_logic_vector(79 downto 0); +--signal s_out : std_logic_vector(79 downto 0); +-- +--signal fuller : std_logic_vector(4 downto 0); +--signal reader : std_logic_vector(4 downto 0); +--signal try : std_logic_vector(1 downto 0); +--signal TXDint : std_logic; +-- +---- IIR Filter +--signal sample_clk_out : std_logic; +-- +--signal Rd : std_logic_vector(0 downto 0); +--signal Ept : std_logic_vector(4 downto 0); +-- +--signal Bwr : std_logic_vector(0 downto 0); +--signal Bre : std_logic_vector(0 downto 0); +--signal DataTMP : std_logic_vector(15 downto 0); +--signal FullUp : std_logic_vector(0 downto 0); +--signal EmptyUp : std_logic_vector(0 downto 0); +--signal FullDown : std_logic_vector(0 downto 0); +--signal EmptyDown : std_logic_vector(0 downto 0); --------------------------------------------------------------------- constant IOAEN : integer := CFG_CAN; constant boardfreq : integer := 50000; @@ -309,37 +318,43 @@ led(1 downto 0) <= gpio(1 downto 0); -- MemIn1 : APB_FIFO -- generic map (pindex => 6, paddr => 6, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) -- port map (clkm,rstn,clkm,clkm,WG_ReUse,(others => '1'),WG_Write,open,Fuller,open,WG_DATA,open,open,apbi,apbo(6)); + + TopACQ : lpp_top_acq + port map('1',CNV_CH1,SCK_CH1,SDO_CH1,Clk_49Mhz,rstn,clkm,rstn,TopACQ_WenF0a,TopACQ_WenF0b,TopACQ_DataF0,TopACQ_WenF1,TopACQ_DataF1,open,open,TopACQ_WenF3,TopACQ_DataF3); + +--- FIFO IN ------------------------------------------------------------- + + Memf0a : lppFIFOxN + generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '0') + port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF0a,DEMU_Read(4 downto 0),TopACQ_DataF0,FifoF0a_Data,FifoF0a_Full,FifoF0a_Empty); + + Memf0b : lppFIFOxN + generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '0') + port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF0b,DEMU_Read(9 downto 5),TopACQ_DataF0,FifoF0b_Data,FifoF0b_Full,FifoF0b_Empty); + + Memf1 : lppFIFOxN + generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '0') + port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF1,DEMU_Read(14 downto 10),TopACQ_DataF1,FifoF1_Data,FifoF1_Full,FifoF1_Empty); + + Memf3 : lppFIFOxN + generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '0') + port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF3,DEMU_Read(19 downto 15),TopACQ_DataF3,FifoF3_Data,FifoF3_Full,FifoF3_Empty); + +--- DEMUX ------------------------------------------------------------- + + DEMUX0 : Demultiplex + generic map(Data_sz => 16) + port map(clkm,rstn,FFT_Read,FifoF0a_Empty,FifoF0b_Empty,FifoF1_Empty,FifoF3_Empty,FifoF0a_Data,FifoF0b_Data,FifoF1_Data,FifoF3_Data,DEMU_Read,DEMU_Empty,DEMU_Data); --- FFT ------------------------------------------------------------- - MemIn : APB_FIFO - generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1) - port map (clkm,rstn,clkm,clkm,(others => '0'),Drive_Read,(others => '1'),FifoIN_Empty,FifoIN_Full,FifoIN_Data,(others => '0'),open,open,apbi,apbo(8)); - - DRIVE : Driver_FFT - generic map(Data_sz => 16) - port map(clkm,rstn,FFT_Load,FifoIN_Empty,FifoIN_Data,Drive_Write,Drive_Read,Drive_DataRE,Drive_DataIM); +-- MemIn : APB_FIFO +-- generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1) +-- port map (clkm,rstn,clkm,clkm,(others => '0'),FFT_Read,(others => '1'),FifoIN_Empty,FifoIN_Full,FifoIN_Data,(others => '0'),open,open,apbi,apbo(8)); -Start <= '0'; - - FFT : CoreFFT - generic map( - LOGPTS => gLOGPTS, - LOGLOGPTS => gLOGLOGPTS, - WSIZE => gWSIZE, - TWIDTH => gTWIDTH, - DWIDTH => gDWIDTH, - TDWIDTH => gTDWIDTH, - RND_MODE => gRND_MODE, - SCALE_MODE => gSCALE_MODE, - PTS => gPTS, - HALFPTS => gHALFPTS, - inBuf_RWDLY => gInBuf_RWDLY) - port map(clkm,start,rstn,Drive_Write,Link_Read,Drive_DataIM,Drive_DataRE,FFT_Load,open,FFT_DataIM,FFT_DataRE,FFT_Valid,FFT_Ready); - - LINK : Linker_FFT - generic map(Data_sz => 16) - port map(clkm,rstn,FFT_Ready,FFT_Valid,FifoINT_Full,FFT_DataRE,FFT_DataIM,Link_Read,Link_Write,Link_ReUse,Link_Data); + FFT0 : FFT + generic map(Data_sz => 16,NbData => 256) + port map(clkm,rstn,DEMU_Empty,DEMU_Data,FifoINT_Full,FFT_Read,FFT_Write,FFT_ReUse,FFT_Data); ----- LINK MEMORY ------------------------------------------------------- @@ -349,7 +364,7 @@ Start <= '0'; MemInt : lppFIFOxN generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '1') - port map(rstn,clkm,clkm,Link_ReUse,Link_Write,TopSM_Read,Link_Data,FifoINT_Data,FifoINT_Full,open); + port map(rstn,clkm,clkm,FFT_ReUse,FFT_Write,SM_Read,FFT_Data,FifoINT_Data,FifoINT_Full,open); -- MemIn : APB_FIFO -- generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 0, W => 1) @@ -357,23 +372,15 @@ Start <= '0'; ----- MATRICE SPECTRALE ---------------------5 FIFO Input--------------- - TopSM : TopSpecMatrix - generic map (Input_SZ => 16) - port map(clkm,rstn,Matrix_Write,Matrix_Read,FifoINT_Full,FifoINT_Data,TopSM_Start,TopSM_Read,TopSM_Statu,TopSM_Data1,TopSM_Data2); - - SM : SpectralMatrix - generic map (Input_SZ => 16, Result_SZ => 32) - port map(clkm,rstn,TopSM_Start,TopSM_Data1,TopSM_Data2,TopSM_Statu,Matrix_Read,Matrix_Write,Matrix_Result); + SM0 : MatriceSpectrale + generic map(Input_SZ => 16,Result_SZ => 32) + port map(clkm,rstn,FifoINT_Full,FifoOUT_Full,FifoINT_Data,Dma_acq,SM_FlagError,SM_Pong,SM_Write,SM_Read,SM_Data); Dma_acq <= '1'; - - DISP : Dispatch - generic map(Data_SZ => 32) - port map(clkm,rstn,Dma_acq,Matrix_Result,Matrix_Write,FifoOUT_Full,Disp_Data,Disp_Write,Disp_Pong,Disp_FlagError); MemOut : APB_FIFO generic map (pindex => 9, paddr => 9, FifoCnt => 2, Data_sz => 32, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) - port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),Disp_Write,open,FifoOUT_Full,open,Disp_Data,open,open,apbi,apbo(9)); + port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),SM_Write,open,FifoOUT_Full,open,SM_Data,open,open,apbi,apbo(9)); ----- FIFO ------------------------------------------------------------- diff --git a/lib/lpp/lpp_demux/Demultiplex.vhd b/lib/lpp/lpp_demux/Demultiplex.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_demux/Demultiplex.vhd @@ -0,0 +1,87 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +library lpp; +use lpp.lpp_demux.all; + +entity Demultiplex is +generic( + Data_sz : integer range 1 to 32 := 16); +port( + clk : in std_logic; + rstn : in std_logic; + + Read : in std_logic_vector(4 downto 0); + + EmptyF0a : in std_logic_vector(4 downto 0); + EmptyF0b : in std_logic_vector(4 downto 0); + EmptyF1 : in std_logic_vector(4 downto 0); + EmptyF2 : in std_logic_vector(4 downto 0); + + DataF0a : in std_logic_vector((5*Data_sz)-1 downto 0); + DataF0b : in std_logic_vector((5*Data_sz)-1 downto 0); + DataF1 : in std_logic_vector((5*Data_sz)-1 downto 0); + DataF2 : in std_logic_vector((5*Data_sz)-1 downto 0); + + Read_DEMUX : out std_logic_vector(19 downto 0); + Empty : out std_logic_vector(4 downto 0); + Data : out std_logic_vector((5*Data_sz)-1 downto 0) +); +end entity; + + +architecture ar_Demultiplex of Demultiplex is + +signal DataCpt : std_logic_vector(3 downto 0); + +begin + + FLG0 : WatchFlag + port map(clk,rstn,EmptyF0a,EmptyF0b,EmptyF1,EmptyF2,DataCpt); + + DEM : DEMUX + generic map(Data_sz) + port map(clk,rstn,Read,DataCpt,EmptyF0a,EmptyF0b,EmptyF1,EmptyF2,DataF0a,DataF0b,DataF1,DataF2,Read_DEMUX,Empty,Data); + +end architecture; + + + + + + + + + + + + + + + + + + + + diff --git a/lib/lpp/lpp_demux/WatchFlag.vhd b/lib/lpp/lpp_demux/WatchFlag.vhd --- a/lib/lpp/lpp_demux/WatchFlag.vhd +++ b/lib/lpp/lpp_demux/WatchFlag.vhd @@ -1,4 +1,24 @@ --- WatchFlag.vhd +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; @@ -8,11 +28,6 @@ port( clk : in std_logic; rstn : in std_logic; - FullF0a : in std_logic_vector(4 downto 0); - FullF0b : in std_logic_vector(4 downto 0); - FullF1 : in std_logic_vector(4 downto 0); - FullF2 : in std_logic_vector(4 downto 0); - EmptyF0a : in std_logic_vector(4 downto 0); EmptyF0b : in std_logic_vector(4 downto 0); EmptyF1 : in std_logic_vector(4 downto 0); @@ -26,6 +41,7 @@ end entity; architecture ar_WatchFlag of WatchFlag is constant FlagSet : std_logic_vector(4 downto 0) := (others =>'1'); +constant OneToSet : std_logic_vector(4 downto 0) := "01111"; begin process(clk,rstn) @@ -35,25 +51,25 @@ begin elsif(clk'event and clk='1')then - if(FullF0a = FlagSet)then + if(EmptyF0a = OneToSet)then DataCpt(0) <= '1'; elsif(EmptyF0a = FlagSet)then DataCpt(0) <= '0'; end if; - if(FullF0b = FlagSet)then + if(EmptyF0b = OneToSet)then DataCpt(1) <= '1'; elsif(EmptyF0b = FlagSet)then DataCpt(1) <= '0'; end if; - if(FullF1 = FlagSet)then + if(EmptyF1 = OneToSet)then DataCpt(2) <= '1'; elsif(EmptyF1 = FlagSet)then DataCpt(2) <= '0'; end if; - if(FullF2 = FlagSet)then + if(EmptyF2 = OneToSet)then DataCpt(3) <= '1'; elsif(EmptyF2 = FlagSet)then DataCpt(3) <= '0'; diff --git a/lib/lpp/lpp_demux/lpp_demux.vhd b/lib/lpp/lpp_demux/lpp_demux.vhd --- a/lib/lpp/lpp_demux/lpp_demux.vhd +++ b/lib/lpp/lpp_demux/lpp_demux.vhd @@ -31,6 +31,33 @@ use lpp.lpp_amba.all; package lpp_demux is + +component Demultiplex is +generic( + Data_sz : integer range 1 to 32 := 16); +port( + clk : in std_logic; + rstn : in std_logic; + + Read : in std_logic_vector(4 downto 0); + + EmptyF0a : in std_logic_vector(4 downto 0); + EmptyF0b : in std_logic_vector(4 downto 0); + EmptyF1 : in std_logic_vector(4 downto 0); + EmptyF2 : in std_logic_vector(4 downto 0); + + DataF0a : in std_logic_vector((5*Data_sz)-1 downto 0); + DataF0b : in std_logic_vector((5*Data_sz)-1 downto 0); + DataF1 : in std_logic_vector((5*Data_sz)-1 downto 0); + DataF2 : in std_logic_vector((5*Data_sz)-1 downto 0); + + Read_DEMUX : out std_logic_vector(19 downto 0); + Empty : out std_logic_vector(4 downto 0); + Data : out std_logic_vector((5*Data_sz)-1 downto 0) +); +end component; + + component DEMUX is generic( Data_sz : integer range 1 to 32 := 16); @@ -63,11 +90,6 @@ port( clk : in std_logic; rstn : in std_logic; - FullF0a : in std_logic_vector(4 downto 0); - FullF0b : in std_logic_vector(4 downto 0); - FullF1 : in std_logic_vector(4 downto 0); - FullF2 : in std_logic_vector(4 downto 0); - EmptyF0a : in std_logic_vector(4 downto 0); EmptyF0b : in std_logic_vector(4 downto 0); EmptyF1 : in std_logic_vector(4 downto 0); diff --git a/lib/lpp/lpp_matrix/ALU_Driver.vhd b/lib/lpp/lpp_matrix/ALU_Driver.vhd --- a/lib/lpp/lpp_matrix/ALU_Driver.vhd +++ b/lib/lpp/lpp_matrix/ALU_Driver.vhd @@ -22,6 +22,8 @@ library IEEE; use IEEE.numeric_std.all; use IEEE.std_logic_1164.all; +library lpp; +use lpp.general_purpose.all; --! Driver de l'ALU @@ -39,7 +41,8 @@ entity ALU_Driver is Conjugate : in std_logic; --! Flag, Calcul sur un complexe et son conjugu� Valid : out std_logic; --! Flag, R�sultat disponible Read : out std_logic; --! Flag, op�rande disponible - CTRL : out std_logic_vector(4 downto 0); --! Permet de s�lectionner la/les op�ration d�sir�e + CTRL : out std_logic_vector(2 downto 0); --! Permet de s�lectionner la/les op�ration d�sir�e + COMP : out std_logic_vector(1 downto 0); --! (set) Permet de compl�menter les op�randes OP1 : out std_logic_vector(Input_SZ_1-1 downto 0); --! Premier Op�rande OP2 : out std_logic_vector(Input_SZ_2-1 downto 0) --! Second Op�rande ); @@ -58,7 +61,7 @@ signal go_st : std_logic; signal Take_reg : std_logic; signal Received_reg : std_logic; -type etat is (eX,e0,e1,e2,e3,e4,e5,idle,idle2,idle3); +type etat is (eX,e0,e1,e2,e3,e4,e5,eY,eZ,eW); signal ect : etat; signal st : etat; @@ -70,7 +73,8 @@ begin ect <= eX; st <= e0; go_st <= '0'; - CTRL <= "10000"; + CTRL <= ctrl_CLRMAC; + COMP <= "00"; -- pas de complement Read <= '0'; Valid <= '0'; Take_reg <= '0'; @@ -84,7 +88,7 @@ begin when eX => go_st <= '0'; Read <= '1'; - CTRL <= "10000"; + CTRL <= ctrl_CLRMAC; ect <= e0; when e0 => @@ -102,18 +106,18 @@ begin when e1 => OP1 <= OP1re; OP2 <= OP2re; - CTRL <= "00001"; + CTRL <= ctrl_MAC; Read <= '1'; - ect <= idle; + ect <= eY; - when idle => + when eY => OP1im <= IN1; if(Conjugate='1')then -- OP2im <= IN1; -- else -- OP2im <= IN2; -- modif 23/06/11 end if; -- - CTRL <= "00000"; + CTRL <= ctrl_IDLE; if(Take_reg='1' and Take='0')then Read <= '0'; ect <= e2; @@ -122,11 +126,11 @@ begin when e2 => OP1 <= OP1im; OP2 <= OP2im; - CTRL <= "00001"; - ect <= idle2; + CTRL <= ctrl_MAC; + ect <= eZ; - when idle2 => - CTRL <= "00000"; + when eZ => + CTRL <= ctrl_IDLE; go_st <= '1'; if(Received_reg='0' and Received='1')then if(Conjugate='1')then @@ -137,24 +141,25 @@ begin end if; when e3 => - CTRL <= "10000"; + CTRL <= ctrl_CLRMAC; go_st <= '0'; ect <= e4; when e4 => OP1 <= OP1im; OP2 <= OP2re; - CTRL <= "00001"; + CTRL <= ctrl_MAC; ect <= e5; when e5 => OP1 <= OP1re; OP2 <= OP2im; - CTRL <= "01001"; - ect <= idle3; - - when idle3 => - CTRL <= "00000"; + COMP <= "10"; + ect <= eW; + + when eW => + CTRL <= ctrl_IDLE; + COMP <= "00"; go_st <= '1'; if(Received_reg='1' and Received='0')then ect <= eX; @@ -175,13 +180,13 @@ begin if(Received_reg='0' and Received='1')then Valid <= '0'; if(Conjugate='1')then - st <= idle2; + st <= eY; else - st <= idle; + st <= eX; end if; end if; - when idle => + when eX => st <= e3; when e3 => @@ -196,10 +201,10 @@ begin when e5 => if(Received_reg='1' and Received='0')then Valid <= '0'; - st <= idle2; + st <= eY; end if; - when idle2 => + when eY => st <= e0; when others => diff --git a/lib/lpp/lpp_matrix/ALU_v2.vhd b/lib/lpp/lpp_matrix/ALU_v2.vhd deleted file mode 100644 --- a/lib/lpp/lpp_matrix/ALU_v2.vhd +++ /dev/null @@ -1,67 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Martin Morlot --- Mail : martin.morlot@lpp.polytechnique.fr -------------------------------------------------------------------------------- -library IEEE; -use IEEE.numeric_std.all; -use IEEE.std_logic_1164.all; -use lpp.lpp_matrix.all; - ---! Une ALU : Arithmetic and logical unit, permettant de r�aliser une ou plusieurs op�ration - -entity ALU_v2 is -generic( - Arith_en : integer := 1; - Logic_en : integer := 1; - Input_SZ_1 : integer := 16; - Input_SZ_2 : integer := 9); -port( - clk : in std_logic; --! Horloge du composant - reset : in std_logic; --! Reset general du composant - ctrl : in std_logic_vector(4 downto 0); --! Permet de s�lectionner la/les op�ration d�sir�e - OP1 : in std_logic_vector(Input_SZ_1-1 downto 0); --! Premier Op�rande - OP2 : in std_logic_vector(Input_SZ_2-1 downto 0); --! Second Op�rande - RES : out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0) --! R�sultat de l'op�ration -); -end ALU_v2; - ---! @details S�lection grace a l'entr�e "ctrl" : ---! Pause : IDLE = 00000 ---! Multiplieur/Accumulateur : MAC = 0XX01 ---! Multiplication : MULT = 0XX10 ---! Addition : ADD = 0XX11 ---! Complement a 2 : 2C = 011XX ---! Reset du MAC : CLRMAC = 10000 - -architecture ar_ALU_v2 of ALU_v2 is - -signal clr_MAC : std_logic:='1'; - -begin - -clr_MAC <= '1' when ctrl = "10000" else '0'; - -arith : if Arith_en = 1 generate -MACinst : MAC_v2 -generic map(Input_SZ_1,Input_SZ_2) -port map(clk,reset,clr_MAC,ctrl(3 downto 0),OP1,OP2,RES); -end generate; - -end ar_ALU_v2; \ No newline at end of file diff --git a/lib/lpp/lpp_matrix/MAC_v2.vhd b/lib/lpp/lpp_matrix/MAC_v2.vhd deleted file mode 100644 --- a/lib/lpp/lpp_matrix/MAC_v2.vhd +++ /dev/null @@ -1,310 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Martin Morlot --- Mail : martin.morlot@lpp.polytechnique.fr -------------------------------------------------------------------------------- -library IEEE; -use IEEE.numeric_std.all; -use IEEE.std_logic_1164.all; -use lpp.lpp_matrix.all; -use lpp.general_purpose.all; - ---! Un MAC : Multiplier Accumulator Chip - -entity MAC_v2 is -generic( - Input_SZ_A : integer := 8; - Input_SZ_B : integer := 8); -port( - clk : in std_logic; --! Horloge du composant - reset : in std_logic; --! Reset general du composant - clr_MAC : in std_logic; --! Un reset sp�cifique au programme - MAC_MUL_ADD_2C : in std_logic_vector(3 downto 0); --! Permet de s�lectionner la/les fonctionnalit� d�sir� - OP1 : in std_logic_vector(Input_SZ_A-1 downto 0); --! Premier Op�rande - OP2 : in std_logic_vector(Input_SZ_B-1 downto 0); --! Second Op�rande - RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0) --! R�sultat du MAC -); -end MAC_v2; - - -architecture ar_MAC_v2 of MAC_v2 is - - -signal add,mult : std_logic; -signal MULTout : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); - -signal ADDERinA : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); -signal ADDERinB : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); -signal ADDERout : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); - -signal MACMUXsel : std_logic; -signal OP1_Resz : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); -signal OP2_Resz : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); - -signal OP1_2C : std_logic_vector(Input_SZ_A-1 downto 0); -signal OP2_2C : std_logic_vector(Input_SZ_B-1 downto 0); - -signal MACMUX2sel : std_logic; - -signal add_D : std_logic; -signal OP1_2C_D : std_logic_vector(Input_SZ_A-1 downto 0); -signal OP2_2C_D : std_logic_vector(Input_SZ_B-1 downto 0); -signal MULTout_D : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); -signal MACMUXsel_D : std_logic; -signal MACMUX2sel_D : std_logic; -signal MACMUX2sel_D_D : std_logic; -signal clr_MAC_D : std_logic; -signal clr_MAC_D_D : std_logic; -signal MAC_MUL_ADD_2C_D : std_logic_vector(3 downto 0); - - -begin - - - ---============================================================== ---=============M A C C O N T R O L E R========================= ---============================================================== -MAC_CONTROLER1 : MAC_CONTROLER -port map( - ctrl => MAC_MUL_ADD_2C_D(1 downto 0), - MULT => mult, - ADD => add, - MACMUX_sel => MACMUXsel, - MACMUX2_sel => MACMUX2sel - -); ---============================================================== - - - - ---============================================================== ---=============M U L T I P L I E R============================== ---============================================================== -Multiplieri_nst : Multiplier -generic map( - Input_SZ_A => Input_SZ_A, - Input_SZ_B => Input_SZ_B -) -port map( - clk => clk, - reset => reset, - mult => mult, - OP1 => OP1_2C, - OP2 => OP2_2C, - RES => MULTout -); - ---============================================================== - - - - ---============================================================== ---======================A D D E R ============================== ---============================================================== -adder_inst : Adder -generic map( - Input_SZ_A => Input_SZ_A+Input_SZ_B, - Input_SZ_B => Input_SZ_A+Input_SZ_B -) -port map( - clk => clk, - reset => reset, - clr => clr_MAC_D_D, - add => add_D, - OP1 => ADDERinA, - OP2 => ADDERinB, - RES => ADDERout -); - ---============================================================== - - - - ---============================================================== ---===================TWO COMPLEMENTERS========================== ---============================================================== -TWO_COMPLEMENTER1 : TwoComplementer -generic map( - Input_SZ => Input_SZ_A -) -port map( - clk => clk, - reset => reset, - clr => clr_MAC, - TwoComp => MAC_MUL_ADD_2C(2), - OP => OP1, - RES => OP1_2C -); - - -TWO_COMPLEMENTER2 : TwoComplementer -generic map( - Input_SZ => Input_SZ_B -) -port map( - clk => clk, - reset => reset, - clr => clr_MAC, - TwoComp => MAC_MUL_ADD_2C(3), - OP => OP2, - RES => OP2_2C -); ---============================================================== - -CTRL : MAC_REG -generic map(size => 2) -port map( - reset => reset, - clk => clk, - D => MAC_MUL_ADD_2C(1 downto 0), - Q => MAC_MUL_ADD_2C_D(1 downto 0) -); - -clr_MACREG1 : MAC_REG -generic map(size => 1) -port map( - reset => reset, - clk => clk, - D(0) => clr_MAC, - Q(0) => clr_MAC_D -); - -clr_MACREG2 : MAC_REG -generic map(size => 1) -port map( - reset => reset, - clk => clk, - D(0) => clr_MAC_D, - Q(0) => clr_MAC_D_D -); - -addREG : MAC_REG -generic map(size => 1) -port map( - reset => reset, - clk => clk, - D(0) => add, - Q(0) => add_D -); - - -OP1REG : MAC_REG -generic map(size => Input_SZ_A) -port map( - reset => reset, - clk => clk, - D => OP1_2C, - Q => OP1_2C_D -); - - -OP2REG : MAC_REG -generic map(size => Input_SZ_B) -port map( - reset => reset, - clk => clk, - D => OP2_2C, - Q => OP2_2C_D -); - - -MULToutREG : MAC_REG -generic map(size => Input_SZ_A+Input_SZ_B) -port map( - reset => reset, - clk => clk, - D => MULTout, - Q => MULTout_D -); - - -MACMUXselREG : MAC_REG -generic map(size => 1) -port map( - reset => reset, - clk => clk, - D(0) => MACMUXsel, - Q(0) => MACMUXsel_D -); - - - -MACMUX2selREG : MAC_REG -generic map(size => 1) -port map( - reset => reset, - clk => clk, - D(0) => MACMUX2sel, - Q(0) => MACMUX2sel_D -); - - -MACMUX2selREG2 : MAC_REG -generic map(size => 1) -port map( - reset => reset, - clk => clk, - D(0) => MACMUX2sel_D, - Q(0) => MACMUX2sel_D_D -); - - ---============================================================== ---======================M A C M U X =========================== ---============================================================== -MACMUX_inst : MAC_MUX -generic map( - Input_SZ_A => Input_SZ_A+Input_SZ_B, - Input_SZ_B => Input_SZ_A+Input_SZ_B - -) -port map( - sel => MACMUXsel_D, - INA1 => ADDERout, - INA2 => OP2_Resz, - INB1 => MULTout, - INB2 => OP1_Resz, - OUTA => ADDERinA, - OUTB => ADDERinB -); -OP1_Resz <= std_logic_vector(resize(signed(OP1_2C_D),Input_SZ_A+Input_SZ_B)); -OP2_Resz <= std_logic_vector(resize(signed(OP2_2C_D),Input_SZ_A+Input_SZ_B)); ---============================================================== - - ---============================================================== ---======================M A C M U X2 ========================== ---============================================================== -MAC_MUX2_inst : MAC_MUX2 -generic map(Input_SZ => Input_SZ_A+Input_SZ_B) -port map( - sel => MACMUX2sel_D_D, - RES2 => MULTout_D, - RES1 => ADDERout, - RES => RES -); - - ---============================================================== - -end ar_MAC_v2; diff --git a/lib/lpp/lpp_matrix/MatriceSpectrale.vhd b/lib/lpp/lpp_matrix/MatriceSpectrale.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_matrix/MatriceSpectrale.vhd @@ -0,0 +1,76 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +library lpp; +use lpp.lpp_matrix.all; + +entity MatriceSpectrale is + generic( + Input_SZ : integer := 16; + Result_SZ : integer := 32); + port( + clkm : in std_logic; + rstn : in std_logic; + + FifoIN_Full : in std_logic_vector(4 downto 0); + FifoOUT_Full : in std_logic_vector(1 downto 0); + Data_IN : in std_logic_vector(79 downto 0); + ACQ : in std_logic; + FlagError : out std_logic; + Pong : out std_logic; + Write : out std_logic_vector(1 downto 0); + Read : out std_logic_vector(4 downto 0); + Data_OUT : out std_logic_vector(63 downto 0) + ); +end entity; + + +architecture ar_MatriceSpectrale of MatriceSpectrale is + +signal Matrix_Write : std_logic; +signal Matrix_Read : std_logic_vector(1 downto 0); +signal Matrix_Result : std_logic_vector(31 downto 0); + +signal TopSM_Start : std_logic; +signal TopSM_Statu : std_logic_vector(3 downto 0); +signal TopSM_Data1 : std_logic_vector(15 downto 0); +signal TopSM_Data2 : std_logic_vector(15 downto 0); + +begin + + TopSM : TopSpecMatrix + generic map (Input_SZ) + port map(clkm,rstn,Matrix_Write,Matrix_Read,FifoIN_Full,Data_IN,TopSM_Start,Read,TopSM_Statu,TopSM_Data1,TopSM_Data2); + + SM : SpectralMatrix + generic map (Input_SZ,Result_SZ) + port map(clkm,rstn,TopSM_Start,TopSM_Data1,TopSM_Data2,TopSM_Statu,Matrix_Read,Matrix_Write,Matrix_Result); + + DISP : Dispatch + generic map(Result_SZ) + port map(clkm,rstn,ACQ,Matrix_Result,Matrix_Write,FifoOUT_Full,Data_OUT,Write,Pong,FlagError); + + +end architecture; + diff --git a/lib/lpp/lpp_matrix/Matrix.vhd b/lib/lpp/lpp_matrix/Matrix.vhd --- a/lib/lpp/lpp_matrix/Matrix.vhd +++ b/lib/lpp/lpp_matrix/Matrix.vhd @@ -22,7 +22,9 @@ library IEEE; use IEEE.numeric_std.all; use IEEE.std_logic_1164.all; +library lpp; use lpp.lpp_matrix.all; +use lpp.general_purpose.all; --! Programme de calcule de Matrice Spectral, compos� d'une ALU et de son Driver @@ -46,7 +48,8 @@ end Matrix; architecture ar_Matrix of Matrix is -signal CTRL : std_logic_vector(4 downto 0); +signal CTRL : std_logic_vector(2 downto 0); +signal COMP : std_logic_vector(1 downto 0); signal OP1 : std_logic_vector(Input_SZ-1 downto 0); signal OP2 : std_logic_vector(Input_SZ-1 downto 0); @@ -54,13 +57,12 @@ begin DRIVE : ALU_Driver generic map(Input_SZ,Input_SZ) - port map(clk,raz,IN1,IN2,Take,Received,Conjugate,Valid,Read,CTRL,OP1,OP2); + port map(clk,raz,IN1,IN2,Take,Received,Conjugate,Valid,Read,CTRL,COMP,OP1,OP2); -ALU : ALU_v2 +ALU0 : ALU generic map(1,0,Input_SZ,Input_SZ) - port map(clk,raz,CTRL,OP1,OP2,Result); + port map(clk,raz,CTRL,COMP,OP1,OP2,Result); end ar_Matrix; - diff --git a/lib/lpp/lpp_matrix/TwoComplementer.vhd b/lib/lpp/lpp_matrix/TwoComplementer.vhd deleted file mode 100644 --- a/lib/lpp/lpp_matrix/TwoComplementer.vhd +++ /dev/null @@ -1,72 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Martin Morlot --- Mail : martin.morlot@lpp.polytechnique.fr -------------------------------------------------------------------------------- -library IEEE; -use IEEE.numeric_std.all; -use IEEE.std_logic_1164.all; - ---! Programme permetant de compl�menter ou non les entr�es de l'ALU, et ainsi de travailler avec des nombres n�gatifs - -entity TwoComplementer is -generic( - Input_SZ : integer := 16); -port( - clk : in std_logic; --! Horloge du composant - reset : in std_logic; --! Reset general du composant - clr : in std_logic; --! Un reset sp�cifique au programme - TwoComp : in std_logic; --! Autorise l'utilisation du compl�ment - OP : in std_logic_vector(Input_SZ-1 downto 0); --! Op�rande d'entr�e - RES : out std_logic_vector(Input_SZ-1 downto 0) --! R�sultat, op�rande compl�ment� ou non -); -end TwoComplementer; - - -architecture ar_TwoComplementer of TwoComplementer is - -signal REG : std_logic_vector(Input_SZ-1 downto 0); -signal OPinteger : integer; -signal RESCOMP : std_logic_vector(Input_SZ-1 downto 0); - -begin - -RES <= REG; -OPinteger <= to_integer(signed(OP)); -RESCOMP <= std_logic_vector(to_signed(-OPinteger,Input_SZ)); - - process(clk,reset) - begin - - if(reset='0')then - REG <= (others => '0'); - elsif(clk'event and clk='1')then - - if(clr='1')then - REG <= (others => '0'); - elsif(TwoComp='1')then - REG <= RESCOMP; - else - REG <= OP; - end if; - - end if; - - end process; -end ar_TwoComplementer; \ No newline at end of file diff --git a/lib/lpp/lpp_matrix/lpp_matrix.vhd b/lib/lpp/lpp_matrix/lpp_matrix.vhd --- a/lib/lpp/lpp_matrix/lpp_matrix.vhd +++ b/lib/lpp/lpp_matrix/lpp_matrix.vhd @@ -56,6 +56,27 @@ component APB_Matrix is ); end component; +component MatriceSpectrale is + generic( + Input_SZ : integer := 16; + Result_SZ : integer := 32); + port( + clkm : in std_logic; + rstn : in std_logic; + + FifoIN_Full : in std_logic_vector(4 downto 0); + FifoOUT_Full : in std_logic_vector(1 downto 0); + Data_IN : in std_logic_vector(79 downto 0); + ACQ : in std_logic; + FlagError : out std_logic; + Pong : out std_logic; + Write : out std_logic_vector(1 downto 0); + Read : out std_logic_vector(4 downto 0); + Data_OUT : out std_logic_vector(63 downto 0) + ); +end component; + + component TopSpecMatrix is generic( Input_SZ : integer := 16); @@ -222,57 +243,11 @@ component ALU_Driver is Conjugate : in std_logic; Valid : out std_logic; Read : out std_logic; - CTRL : out std_logic_vector(4 downto 0); + CTRL : out std_logic_vector(2 downto 0); + COMP : out std_logic_vector(1 downto 0); OP1 : out std_logic_vector(Input_SZ_1-1 downto 0); OP2 : out std_logic_vector(Input_SZ_2-1 downto 0) ); end component; - -component ALU_v2 is -generic( - Arith_en : integer := 1; - Logic_en : integer := 1; - Input_SZ_1 : integer := 16; - Input_SZ_2 : integer := 9); -port( - clk : in std_logic; - reset : in std_logic; - ctrl : in std_logic_vector(4 downto 0); - OP1 : in std_logic_vector(Input_SZ_1-1 downto 0); - OP2 : in std_logic_vector(Input_SZ_2-1 downto 0); - RES : out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0) -); -end component; - - -component MAC_v2 is -generic( - Input_SZ_A : integer := 8; - Input_SZ_B : integer := 8); -port( - clk : in std_logic; - reset : in std_logic; - clr_MAC : in std_logic; - MAC_MUL_ADD_2C : in std_logic_vector(3 downto 0); - OP1 : in std_logic_vector(Input_SZ_A-1 downto 0); - OP2 : in std_logic_vector(Input_SZ_B-1 downto 0); - RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0) -); -end component; - - -component TwoComplementer is -generic( - Input_SZ : integer := 16); -port( - clk : in std_logic; - reset : in std_logic; - clr : in std_logic; - TwoComp : in std_logic; - OP : in std_logic_vector(Input_SZ-1 downto 0); - RES : out std_logic_vector(Input_SZ-1 downto 0) -); -end component; - end; \ No newline at end of file diff --git a/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd b/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd --- a/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd @@ -28,16 +28,16 @@ ENTITY lpp_top_acq IS -- sample_f0_0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); sample_f0_1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); + sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); -- sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); + sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); -- sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); + sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); -- sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0) + sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0) ); END lpp_top_acq; @@ -170,7 +170,7 @@ BEGIN IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 GENERIC MAP ( tech => 0, - Mem_use => use_CEL, + Mem_use => use_RAM, Sample_SZ => 18, Coef_SZ => Coef_SZ, Coef_Nb => 25, -- TODO @@ -221,12 +221,12 @@ BEGIN sample_out_val => sample_f0_val, sample_out => sample_f0); - all_bit_sample_f0 : FOR I IN 17 DOWNTO 0 GENERATE + all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE sample_f0_wdata(I) <= sample_f0(0, I); - sample_f0_wdata(18*1+I) <= sample_f0(1, I); - sample_f0_wdata(18*2+I) <= sample_f0(2, I); - sample_f0_wdata(18*3+I) <= sample_f0(6, I); - sample_f0_wdata(18*4+I) <= sample_f0(7, I); + sample_f0_wdata(16*1+I) <= sample_f0(1, I); + sample_f0_wdata(16*2+I) <= sample_f0(2, I); + sample_f0_wdata(16*3+I) <= sample_f0(6, I); + sample_f0_wdata(16*4+I) <= sample_f0(7, I); END GENERATE all_bit_sample_f0; PROCESS (clk, rstn) @@ -281,12 +281,12 @@ BEGIN NOT(sample_f1_val) & NOT(sample_f1_val); - all_bit_sample_f1 : FOR I IN 17 DOWNTO 0 GENERATE + all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE sample_f1_wdata(I) <= sample_f1(0, I); - sample_f1_wdata(18*1+I) <= sample_f1(1, I); - sample_f1_wdata(18*2+I) <= sample_f1(2, I); - sample_f1_wdata(18*3+I) <= sample_f1(6, I); - sample_f1_wdata(18*4+I) <= sample_f1(7, I); + sample_f1_wdata(16*1+I) <= sample_f1(1, I); + sample_f1_wdata(16*2+I) <= sample_f1(2, I); + sample_f1_wdata(16*3+I) <= sample_f1(6, I); + sample_f1_wdata(16*4+I) <= sample_f1(7, I); END GENERATE all_bit_sample_f1; ----------------------------------------------------------------------------- @@ -311,12 +311,12 @@ BEGIN NOT(sample_f2_val) & NOT(sample_f2_val); - all_bit_sample_f2 : FOR I IN 17 DOWNTO 0 GENERATE + all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE sample_f2_wdata(I) <= sample_f2(0, I); - sample_f2_wdata(18*1+I) <= sample_f2(1, I); - sample_f2_wdata(18*2+I) <= sample_f2(2, I); - sample_f2_wdata(18*3+I) <= sample_f2(6, I); - sample_f2_wdata(18*4+I) <= sample_f2(7, I); + sample_f2_wdata(16*1+I) <= sample_f2(1, I); + sample_f2_wdata(16*2+I) <= sample_f2(2, I); + sample_f2_wdata(16*3+I) <= sample_f2(6, I); + sample_f2_wdata(16*4+I) <= sample_f2(7, I); END GENERATE all_bit_sample_f2; ----------------------------------------------------------------------------- @@ -341,12 +341,12 @@ BEGIN (NOT sample_f3_val) & (NOT sample_f3_val); - all_bit_sample_f3 : FOR I IN 17 DOWNTO 0 GENERATE + all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE sample_f3_wdata(I) <= sample_f3(0, I); - sample_f3_wdata(18*1+I) <= sample_f3(1, I); - sample_f3_wdata(18*2+I) <= sample_f3(2, I); - sample_f3_wdata(18*3+I) <= sample_f3(6, I); - sample_f3_wdata(18*4+I) <= sample_f3(7, I); + sample_f3_wdata(16*1+I) <= sample_f3(1, I); + sample_f3_wdata(16*2+I) <= sample_f3(2, I); + sample_f3_wdata(16*3+I) <= sample_f3(6, I); + sample_f3_wdata(16*4+I) <= sample_f3(7, I); END GENERATE all_bit_sample_f3; diff --git a/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd b/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd --- a/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd @@ -22,15 +22,15 @@ PACKAGE lpp_top_lfr_pkg IS cnv_rstn : IN STD_LOGIC; clk : IN STD_LOGIC; rstn : IN STD_LOGIC; - sample_f0_0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f0_1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); - sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); - sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); - sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0)); + sample_f0_0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f0_1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0)); END COMPONENT; -END lpp_top_lfr_pkg; +END lpp_top_lfr_pkg; \ No newline at end of file