HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r150:17327dd65850

correction ADS

pellion -

r150:17327dd65850 JC

parent child

Context file:

r150:17327dd65850

Collapse all files

designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/Top_Data_Acquisition.vhd +21 -21

@@ -159,32 +159,32 BEGIN
159	sample_filter_in(i, 17) <= sample(i)(15);	159	sample_filter_in(i, 17) <= sample(i)(15);
160	END GENERATE;	160	END GENERATE;
161		161
162	coefs <= CoefsInitValCst;	162	--coefs <= CoefsInitValCst;
163	coefs_JC <= CoefsInitValCst_JC;	163	coefs_JC <= CoefsInitValCst_v2;
164		164
165	FILTER : IIR_CEL_CTRLR	165	--FILTER : IIR_CEL_CTRLR
166	GENERIC MAP (	166	-- GENERIC MAP (
167	tech => 0,	167	-- tech => 0,
168	Sample_SZ => 18,	168	-- Sample_SZ => 18,
169	~~ChanelsCount~~ => ChanelCount,	169	-- ChanelsCount => ChanelCount,
170	Coef_SZ => Coef_SZ,	170	-- Coef_SZ => Coef_SZ,
171	CoefCntPerCel => CoefCntPerCel,	171	-- CoefCntPerCel => CoefCntPerCel,
172	Cels_count => Cels_count,	172	-- Cels_count => Cels_count,
173	~~Mem_use~~ => ~~use_CEL~~) -- use_CEL for SIMU, use_RAM for synthesis	173	-- Mem_use => use_CEL) -- use_CEL for SIMU, use_RAM for synthesis
174	PORT MAP (	174	-- PORT MAP (
175	reset => rstn,	175	-- reset => rstn,
176	clk => clk,	176	-- clk => clk,
177	sample_clk => sample_val_delay,	177	-- sample_clk => sample_val_delay,
178	~~sample_in~~ => sample_filter_in,	178	-- sample_in => sample_filter_in,
179	sample_out => sample_filter_out,	179	-- sample_out => sample_filter_out,
180	virg_pos => 7,	180	-- virg_pos => 7,
181	GOtest => OPEN,	181	-- GOtest => OPEN,
182	coefs => coefs);	182	-- coefs => coefs);
183		183
184	IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2	184	IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
185	GENERIC MAP (	185	GENERIC MAP (
186	tech => 0,	186	tech => 0,
187	Mem_use => use_~~CEL~~,	187	Mem_use => use_RAM,
188	Sample_SZ => 18,	188	Sample_SZ => 18,
189	Coef_SZ => Coef_SZ,	189	Coef_SZ => Coef_SZ,
190	Coef_Nb => 25, -- TODO	190	Coef_Nb => 25, -- TODO

designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/run_sim_data_acquisition.do +1 -1

             vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/FILTERcfg.vhd
             vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CEL.vhd
             vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR2.vhd
-            vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR.vhd
+            #vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR.vhd
             vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd
             vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd

lib/lpp/dsp/iir_filter/FILTERcfg.vhd +1 -1

             constant CoefsInitValCst  :   std_logic_vector((Cels_count*CoefCntPerCel*Coef_SZ)-1 downto 0) := (a4_2 & a4_1 & a4_0 & b4_2 & b4_1 & b4_0 & a3_2 & a3_1 & a3_0 & b3_2 & b3_1 & b3_0 & a2_2 & a2_1 & a2_0 & b2_2 & b2_1 & b2_0 & a1_2 & a1_1 & a1_0 & b1_2 & b1_1 &  b1_0 & a0_2 & a0_1 & a0_0 & b0_2 & b0_1 & b0_0);
-            constant CoefsInitValCst_JC  :   std_logic_vector((Cels_count*CoefPerCel*Coef_SZ)-1 downto 0) :=
+            constant CoefsInitValCst_v2  :   std_logic_vector((Cels_count*CoefPerCel*Coef_SZ)-1 downto 0) :=
               (a4_1 & a4_2 & b4_0 & b4_1 & b4_2 &
                a3_1 & a3_2 & b3_0 & b3_1 & b3_2 &
                a2_1 & a2_2 & b2_0 & b2_1 & b2_2 &

lib/lpp/lpp_ad_Conv/ADS7886_drvr.vhd +8 -4

                   IF (sample_bit_counter MOD 2) = 1 THEN
                     FOR l IN 0 TO ChanelCount-1 LOOP
-                      shift_reg(l)(15)          <= sdo(l);
+                      --shift_reg(l)(15)          <= sdo(l);
-                      shift_reg(l)(14 DOWNTO 0) <= shift_reg(l)(15 DOWNTO 1);
+                      --shift_reg(l)(14 DOWNTO 0) <= shift_reg(l)(15 DOWNTO 1);
+                      shift_reg(l)(0)           <= sdo(l);
+                      shift_reg(l)(15 DOWNTO 1) <= shift_reg(l)(14 DOWNTO 0);
                     END LOOP;
                     SCK <= '0';
                   ELSE
                   IF sample_bit_counter = 31 THEN
                     sample_val <= '1';
                     FOR l IN 0 TO ChanelCount-1 LOOP
-                      sample(l)(15)           <= sdo(l);
+                      --sample(l)(15)          <= sdo(l);
-                      sample(l)(14 DOWNTO 0) <= shift_reg(l)(15 DOWNTO 1);
+                      --sample(l)(14 DOWNTO 0) <= shift_reg(l)(15 DOWNTO 1);
+                      sample(l)(0)           <= sdo(l);
+                      sample(l)(15 DOWNTO 1) <= shift_reg(l)(14 DOWNTO 0);
                     END LOOP;
                   ELSE
                     sample_val <= '0';

lib/lpp/lpp_top_lfr/lpp_top_lfr.vhd +112 -19

             USE lpp.lpp_memory.ALL;
             USE lpp.lpp_top_lfr_pkg.ALL;
             USE lpp.lpp_dma_pkg.ALL;
+            USE lpp.lpp_demux.ALL;
+            USE lpp.lpp_fft.ALL;
+            use lpp.lpp_matrix.all;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
               -- f0
               SIGNAL sample_f0_0_wen   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f0_1_wen   : STD_LOGIC_VECTOR(4 DOWNTO 0);
-              SIGNAL sample_f0_wdata   : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
+              SIGNAL sample_f0_wdata   : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               --
               SIGNAL sample_f0_0_ren   : STD_LOGIC_VECTOR(4 DOWNTO 0);
-              SIGNAL sample_f0_0_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
+              SIGNAL sample_f0_0_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL sample_f0_0_full  : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f0_0_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
               --
               SIGNAL sample_f0_1_ren   : STD_LOGIC_VECTOR(4 DOWNTO 0);
-              SIGNAL sample_f0_1_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
+              SIGNAL sample_f0_1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL sample_f0_1_full  : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f0_1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- f1
               SIGNAL sample_f1_wen     : STD_LOGIC_VECTOR(4 DOWNTO 0);
-              SIGNAL sample_f1_wdata   : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
+              SIGNAL sample_f1_wdata   : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               --
               SIGNAL sample_f1_ren     : STD_LOGIC_VECTOR(4 DOWNTO 0);
-              SIGNAL sample_f1_rdata   : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
+              SIGNAL sample_f1_rdata   : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL sample_f1_full    : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f1_empty   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- f2
               SIGNAL sample_f2_wen     : STD_LOGIC_VECTOR(4 DOWNTO 0);
-              SIGNAL sample_f2_wdata   : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
+              SIGNAL sample_f2_wdata   : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- f3
               SIGNAL sample_f3_wen     : STD_LOGIC_VECTOR(4 DOWNTO 0);
-              SIGNAL sample_f3_wdata   : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
+              SIGNAL sample_f3_wdata   : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               --
               SIGNAL sample_f3_ren     : STD_LOGIC_VECTOR(4 DOWNTO 0);
-              SIGNAL sample_f3_rdata   : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
+              SIGNAL sample_f3_rdata   : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL sample_f3_full    : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f3_empty   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               -- SPECTRAL MATRIX
               -----------------------------------------------------------------------------
+              SIGNAL sample_ren : STD_LOGIC_VECTOR(19 DOWNTO 0);
+              SIGNAL demux_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
+              SIGNAL demux_ren   : STD_LOGIC_VECTOR(4 DOWNTO 0);
+              SIGNAL demux_data  : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
+              SIGNAL fft_fifo_full  : STD_LOGIC_VECTOR(4 DOWNTO 0);
+              SIGNAL fft_fifo_data  : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
+              SIGNAL fft_fifo_wen   : STD_LOGIC_VECTOR(4 DOWNTO 0);
+              SIGNAL fft_fifo_reuse : STD_LOGIC_VECTOR(4 DOWNTO 0);
+              SIGNAL SP_fifo_data  : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
+              SIGNAL SP_fifo_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL fifo_data  : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL fifo_empty : STD_LOGIC;
               SIGNAL fifo_ren   : STD_LOGIC;
               lppFIFO_f0_0 : lppFIFOxN
                 GENERIC MAP (
                   tech         => tech,
-                  Data_sz      => 18,
+                  Data_sz      => 16,
                   FifoCnt      => 5,
                   Enable_ReUse => '0')
                 PORT MAP (
               lppFIFO_f0_1 : lppFIFOxN
                 GENERIC MAP (
                   tech         => tech,
-                  Data_sz      => 18,
+                  Data_sz      => 16,
                   FifoCnt      => 5,
                   Enable_ReUse => '0')
                 PORT MAP (
               lppFIFO_f1 : lppFIFOxN
                 GENERIC MAP (
                   tech         => tech,
-                  Data_sz      => 18,
+                  Data_sz      => 16,
                   FifoCnt      => 5,
                   Enable_ReUse => '0')
                 PORT MAP (
               lppFIFO_f3 : lppFIFOxN
                 GENERIC MAP (
                   tech         => tech,
-                  Data_sz      => 18,
+                  Data_sz      => 16,
                   FifoCnt      => 5,
                   Enable_ReUse => '0')
                 PORT MAP (
               -----------------------------------------------------------------------------
               -- SPECTRAL MATRIX
               -----------------------------------------------------------------------------
+              sample_f0_0_ren <= sample_ren(4 DOWNTO 0);
+              sample_f0_1_ren <= sample_ren(9 DOWNTO 5);
+              sample_f1_ren   <= sample_ren(14 DOWNTO 10);
+              sample_f3_ren   <= sample_ren(19 DOWNTO 15);
+              Demultiplex_1 : Demultiplex
+                GENERIC MAP (
+                  Data_sz => 16)
+                PORT MAP (
+                  clk  => clk,
+                  rstn => rstn,
+                  Read       => demux_ren,
+                  EmptyF0a   => sample_f0_0_empty,
+                  EmptyF0b   => sample_f0_0_empty,
+                  EmptyF1    => sample_f1_empty,
+                  EmptyF2    => sample_f3_empty,
+                  DataF0a    => sample_f0_0_rdata,
+                  DataF0b    => sample_f0_1_rdata,
+                  DataF1     => sample_f1_rdata,
+                  DataF2     => sample_f3_rdata,
+                  Read_DEMUX => sample_ren,
+                  Empty      => demux_empty,
+                  Data       => demux_data);
+              FFT_1 : FFT
+                GENERIC MAP (
+                  Data_sz => 16,
+                  NbData  => 256)
+                PORT MAP (
+                  clkm         => clk,
+                  rstn         => rstn,
+                  FifoIN_Empty => demux_empty,
+                  FifoIN_Data  => demux_data,
+                  FifoOUT_Full => fft_fifo_full,
+                  Read         => demux_ren,
+                  Write        => fft_fifo_wen,
+                  ReUse        => fft_fifo_reuse,
+                  Data         => fft_fifo_data);
+              lppFIFO_fft : lppFIFOxN
+                GENERIC MAP (
+                  tech         => tech,
+                  Data_sz      => 16,
+                  FifoCnt      => 5,
+                  Enable_ReUse => '1')
+                PORT MAP (
+                  rst   => rstn,
+                  wclk  => clk,
+                  rclk  => clk,
+                  ReUse => fft_fifo_reuse,
+                  wen   => fft_fifo_wen,
+                  ren   => SP_fifo_ren,
+                  wdata => fft_fifo_data,
+                  rdata => SP_fifo_data,
+                  full  => fft_fifo_full,
+                  empty => OPEN);
+              MatriceSpectrale_1: MatriceSpectrale
+                GENERIC MAP (
+                  Input_SZ  => 16,
+                  Result_SZ => 32)
+                PORT MAP (
+                  clkm         => clk,
+                  rstn         => rstn,
+                  FifoIN_Full  => fft_fifo_full,
+                  FifoOUT_Full => ,                 -- TODO
+                  Data_IN      => SP_fifo_data,
+                  ACQ          => ,                 -- TODO
+                  FlagError    => ,                 -- TODO
+                  Pong         => ,                 -- TODO
+                  Write        => ,                 -- TODO
+                  Read         => SP_fifo_ren,
+                  Data_OUT     => );                -- TODO
               -----------------------------------------------------------------------------
               -- DMA SPECTRAL MATRIX
                   pmask  => pmask,
                   pirq   => pirq)
                 PORT MAP (
-                  HCLK                                   => clk,
+                  HCLK    => clk,
-                  HRESETn                                => rstn,
+                  HRESETn => rstn,
-                  apbi                                   => apbi,
+                  apbi    => apbi,
-                  apbo                                   => apbo,
+                  apbo    => apbo,
                   ready_matrix_f0_0                      => ready_matrix_f0_0,
                   ready_matrix_f0_1                      => ready_matrix_f0_1,
                   ready_matrix_f1                        => ready_matrix_f1,
                   addr_matrix_f1                         => addr_matrix_f1,
                   addr_matrix_f2                         => addr_matrix_f2);
               --TODO : add the irq alert for DMA matrix transfert ending
               --TODO : add 5 bit register into APB to control the DATA SHIPING
               --TODO : add Spectral Matrix (FFT + SP)
               --TODO : add DMA for WaveForms Picker
               --TODO : add APB Reg to control WaveForms Picker
               --TODO : add WaveForms Picker
             END tb;

lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd +71 -67

@@ -1,68 +1,72
1	LIBRARY ieee;	1	LIBRARY ieee;
2	USE ieee.std_logic_1164.ALL;	2	USE ieee.std_logic_1164.ALL;
3	LIBRARY lpp;	3
4	USE lpp.lpp_ad_conv.ALL;	4	LIBRARY grlib;
5	USE lpp.iir_filter.ALL;	5	USE grlib.amba.ALL;
6	USE lpp.FILTERcfg.ALL;	6
7	USE lpp.lpp_memory.ALL;	7	LIBRARY lpp;
8	LIBRARY techmap;	8	USE lpp.lpp_ad_conv.ALL;
9	USE techmap.gencomp.ALL;	9	USE lpp.iir_filter.ALL;
10		10	USE lpp.FILTERcfg.ALL;
11	PACKAGE lpp_top_lfr_pkg IS	11	USE lpp.lpp_memory.ALL;
12		12	LIBRARY techmap;
13	COMPONENT lpp_top_acq	13	USE techmap.gencomp.ALL;
14	GENERIC (	14
15	tech : integer);	15	PACKAGE lpp_top_lfr_pkg IS
16	PORT (	16
17	cnv_run : IN STD_LOGIC;	17	COMPONENT lpp_top_acq
18	cnv : OUT STD_LOGIC;	18	GENERIC (
19	sck : OUT STD_LOGIC;	19	tech : integer);
20	sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);	20	PORT (
21	cnv_~~clk~~ : IN STD_LOGIC;	21	cnv_run : IN STD_LOGIC;
22	cnv~~_rstn~~ : IN STD_LOGIC;	22	cnv : OUT STD_LOGIC;
23	clk : IN STD_LOGIC;	23	sck : OUT STD_LOGIC;
24	~~rstn~~ : IN STD_LOGIC;	24	sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
25	sample_f0_0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);	25	cnv_clk : IN STD_LOGIC;
26	sample_f0_1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);	26	cnv_rstn : IN STD_LOGIC;
27	sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);	27	clk : IN STD_LOGIC;
28	sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);	28	rstn : IN STD_LOGIC;
29	sample_f~~1_wdata~~ : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);	29	sample_f0_0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
30	sample_f~~2_wen~~ : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);	30	sample_f0_1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
31	sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);	31	sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
32	sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);	32	sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
33	sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0));	33	sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
34	END COMPONENT;	34	sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
35		35	sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
36	COMPONENT lpp_top_apbreg	36	sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
37	GENERIC (	37	sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0));
38	pindex : INTEGER;	38	END COMPONENT;
39	paddr : INTEGER;	39
40	pmask : INTEGER;	40	COMPONENT lpp_top_apbreg
41	pirq : INTEGER);	41	GENERIC (
42	PORT (	42	pindex : INTEGER;
43	HCLK : IN STD_ULOGIC;	43	paddr : INTEGER;
44	HRESETn : IN STD_ULOGIC;	44	pmask : INTEGER;
45	apbi : IN apb_slv_in_type;	45	pirq : INTEGER);
46	apbo : OUT apb_slv_out_type;	46	PORT (
47	~~ready_matrix_f0_0~~ : IN STD_LOGIC;	47	HCLK : IN STD_ULOGIC;
48	~~ready_matrix_f0_1~~ : IN STD_LOGIC;	48	HRESETn : IN STD_ULOGIC;
49	~~ready_matrix_f1~~ : IN ~~STD_LOGIC~~;	49	apbi : IN apb_slv_in_type;
50	ready_matrix_f2 : IN STD_LOGIC;	50	apbo : OUT apb_slv_out_type;
51	~~error_anticipating_empty_fifo~~ : IN STD_LOGIC;	51	ready_matrix_f0_0 : IN STD_LOGIC;
52	~~error_bad_component_error~~ : IN STD_LOGIC;	52	ready_matrix_f0_1 : IN STD_LOGIC;
53	~~debug_reg~~ : IN STD_LOGIC~~_VECTOR~~(31 ~~DOWNTO~~ 0);	53	ready_matrix_f1 : IN STD_LOGIC;
54	~~status_~~ready_matrix_f~~0_0~~ : ~~OUT~~ STD_LOGIC;	54	ready_matrix_f2 : IN STD_LOGIC;
55	~~status_ready_matrix_f0_1~~ : ~~OUT~~ STD_LOGIC;	55	error_anticipating_empty_fifo : IN STD_LOGIC;
56	~~status_ready_matrix_f1~~ : ~~OUT~~ STD_LOGIC;	56	error_bad_component_error : IN STD_LOGIC;
57	status_ready_matrix_f2 : OUT STD_LOGIC;	57	debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
58	status_~~error_anticipating_empty_fifo~~ : OUT STD_LOGIC;	58	status_ready_matrix_f0_0 : OUT STD_LOGIC;
59	status_~~error_bad_component_error~~ : OUT STD_LOGIC;	59	status_ready_matrix_f0_1 : OUT STD_LOGIC;
60	config_active_interruption_onNewMatrix : OUT STD_LOGIC;	60	status_ready_matrix_f1 : OUT STD_LOGIC;
61	config_active_interruption_onError : OUT STD_LOGIC;	61	status_ready_matrix_f2 : OUT STD_LOGIC;
62	addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);	62	status_error_anticipating_empty_fifo : OUT STD_LOGIC;
63	addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);	63	status_error_bad_component_error : OUT STD_LOGIC;
64	addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);	64	config_active_interruption_onNewMatrix : OUT STD_LOGIC;
65	addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));	65	config_active_interruption_onError : OUT STD_LOGIC;
66	END COMPONENT;	66	addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
67		67	addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
		68	addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
		69	addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
		70	END COMPONENT;
		71
68	END lpp_top_lfr_pkg; No newline at end of file	72	END lpp_top_lfr_pkg;

General Comments 0

Write
Preview

You need to be logged in to leave comments. Login now

No TODOs yet

	Site-wide shortcuts
/	Use quick search box
g h	Goto home page
g g	Goto my private gists page
g G	Goto my public gists page
g 0-9	Goto bookmarked items from 0-9
n r	New repository page
n g	New gist page

	Repositories
g s	Goto summary page
g c	Goto changelog page
g f	Goto files page
g F	Goto files page with file search activated
g p	Goto pull requests page
g o	Goto repository settings
g O	Goto repository access permissions settings
t s	Toggle sidebar on some pages