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correction ADS
pellion -
r150:17327dd65850 JC
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@@ -159,32 +159,32 BEGIN
159 159 sample_filter_in(i, 17) <= sample(i)(15);
160 160 END GENERATE;
161 161
162 coefs <= CoefsInitValCst;
163 coefs_JC <= CoefsInitValCst_JC;
162 --coefs <= CoefsInitValCst;
163 coefs_JC <= CoefsInitValCst_v2;
164 164
165 FILTER : IIR_CEL_CTRLR
166 GENERIC MAP (
167 tech => 0,
168 Sample_SZ => 18,
169 ChanelsCount => ChanelCount,
170 Coef_SZ => Coef_SZ,
171 CoefCntPerCel => CoefCntPerCel,
172 Cels_count => Cels_count,
173 Mem_use => use_CEL) -- use_CEL for SIMU, use_RAM for synthesis
174 PORT MAP (
175 reset => rstn,
176 clk => clk,
177 sample_clk => sample_val_delay,
178 sample_in => sample_filter_in,
179 sample_out => sample_filter_out,
180 virg_pos => 7,
181 GOtest => OPEN,
182 coefs => coefs);
165 --FILTER : IIR_CEL_CTRLR
166 -- GENERIC MAP (
167 -- tech => 0,
168 -- Sample_SZ => 18,
169 -- ChanelsCount => ChanelCount,
170 -- Coef_SZ => Coef_SZ,
171 -- CoefCntPerCel => CoefCntPerCel,
172 -- Cels_count => Cels_count,
173 -- Mem_use => use_CEL) -- use_CEL for SIMU, use_RAM for synthesis
174 -- PORT MAP (
175 -- reset => rstn,
176 -- clk => clk,
177 -- sample_clk => sample_val_delay,
178 -- sample_in => sample_filter_in,
179 -- sample_out => sample_filter_out,
180 -- virg_pos => 7,
181 -- GOtest => OPEN,
182 -- coefs => coefs);
183 183
184 184 IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
185 185 GENERIC MAP (
186 186 tech => 0,
187 Mem_use => use_CEL,
187 Mem_use => use_RAM,
188 188 Sample_SZ => 18,
189 189 Coef_SZ => Coef_SZ,
190 190 Coef_Nb => 25, -- TODO
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@@ -19,7 +19,7 vcom -quiet -93 -work lpp ../../lib/lpp/
19 19 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/FILTERcfg.vhd
20 20 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CEL.vhd
21 21 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR2.vhd
22 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR.vhd
22 #vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR.vhd
23 23
24 24 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd
25 25 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd
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@@ -108,7 +108,7 constant a4_2 : std_logic_vector
108 108
109 109 constant CoefsInitValCst : std_logic_vector((Cels_count*CoefCntPerCel*Coef_SZ)-1 downto 0) := (a4_2 & a4_1 & a4_0 & b4_2 & b4_1 & b4_0 & a3_2 & a3_1 & a3_0 & b3_2 & b3_1 & b3_0 & a2_2 & a2_1 & a2_0 & b2_2 & b2_1 & b2_0 & a1_2 & a1_1 & a1_0 & b1_2 & b1_1 & b1_0 & a0_2 & a0_1 & a0_0 & b0_2 & b0_1 & b0_0);
110 110
111 constant CoefsInitValCst_JC : std_logic_vector((Cels_count*CoefPerCel*Coef_SZ)-1 downto 0) :=
111 constant CoefsInitValCst_v2 : std_logic_vector((Cels_count*CoefPerCel*Coef_SZ)-1 downto 0) :=
112 112 (a4_1 & a4_2 & b4_0 & b4_1 & b4_2 &
113 113 a3_1 & a3_2 & b3_0 & b3_1 & b3_2 &
114 114 a2_1 & a2_2 & b2_0 & b2_1 & b2_2 &
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@@ -169,8 +169,10 BEGIN
169 169
170 170 IF (sample_bit_counter MOD 2) = 1 THEN
171 171 FOR l IN 0 TO ChanelCount-1 LOOP
172 shift_reg(l)(15) <= sdo(l);
173 shift_reg(l)(14 DOWNTO 0) <= shift_reg(l)(15 DOWNTO 1);
172 --shift_reg(l)(15) <= sdo(l);
173 --shift_reg(l)(14 DOWNTO 0) <= shift_reg(l)(15 DOWNTO 1);
174 shift_reg(l)(0) <= sdo(l);
175 shift_reg(l)(15 DOWNTO 1) <= shift_reg(l)(14 DOWNTO 0);
174 176 END LOOP;
175 177 SCK <= '0';
176 178 ELSE
@@ -180,8 +182,10 BEGIN
180 182 IF sample_bit_counter = 31 THEN
181 183 sample_val <= '1';
182 184 FOR l IN 0 TO ChanelCount-1 LOOP
183 sample(l)(15) <= sdo(l);
184 sample(l)(14 DOWNTO 0) <= shift_reg(l)(15 DOWNTO 1);
185 --sample(l)(15) <= sdo(l);
186 --sample(l)(14 DOWNTO 0) <= shift_reg(l)(15 DOWNTO 1);
187 sample(l)(0) <= sdo(l);
188 sample(l)(15 DOWNTO 1) <= shift_reg(l)(14 DOWNTO 0);
185 189 END LOOP;
186 190 ELSE
187 191 sample_val <= '0';
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@@ -12,6 +12,9 USE lpp.FILTERcfg.ALL;
12 12 USE lpp.lpp_memory.ALL;
13 13 USE lpp.lpp_top_lfr_pkg.ALL;
14 14 USE lpp.lpp_dma_pkg.ALL;
15 USE lpp.lpp_demux.ALL;
16 USE lpp.lpp_fft.ALL;
17 use lpp.lpp_matrix.all;
15 18 LIBRARY techmap;
16 19 USE techmap.gencomp.ALL;
17 20
@@ -52,37 +55,37 ARCHITECTURE tb OF lpp_top_lfr IS
52 55 -- f0
53 56 SIGNAL sample_f0_0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
54 57 SIGNAL sample_f0_1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
55 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
58 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
56 59 --
57 60 SIGNAL sample_f0_0_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
58 SIGNAL sample_f0_0_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
61 SIGNAL sample_f0_0_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
59 62 SIGNAL sample_f0_0_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
60 63 SIGNAL sample_f0_0_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
61 64 --
62 65 SIGNAL sample_f0_1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
63 SIGNAL sample_f0_1_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
66 SIGNAL sample_f0_1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
64 67 SIGNAL sample_f0_1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
65 68 SIGNAL sample_f0_1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
66 69 -----------------------------------------------------------------------------
67 70 -- f1
68 71 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
69 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
72 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
70 73 --
71 74 SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
72 SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
75 SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
73 76 SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
74 77 SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
75 78 -----------------------------------------------------------------------------
76 79 -- f2
77 80 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
78 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
81 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
79 82 -----------------------------------------------------------------------------
80 83 -- f3
81 84 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
82 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
85 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
83 86 --
84 87 SIGNAL sample_f3_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
85 SIGNAL sample_f3_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
88 SIGNAL sample_f3_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
86 89 SIGNAL sample_f3_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
87 90 SIGNAL sample_f3_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
88 91 -----------------------------------------------------------------------------
@@ -90,6 +93,20 ARCHITECTURE tb OF lpp_top_lfr IS
90 93 -----------------------------------------------------------------------------
91 94 -- SPECTRAL MATRIX
92 95 -----------------------------------------------------------------------------
96 SIGNAL sample_ren : STD_LOGIC_VECTOR(19 DOWNTO 0);
97
98 SIGNAL demux_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
99 SIGNAL demux_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
100 SIGNAL demux_data : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
101
102 SIGNAL fft_fifo_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
103 SIGNAL fft_fifo_data : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
104 SIGNAL fft_fifo_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
105 SIGNAL fft_fifo_reuse : STD_LOGIC_VECTOR(4 DOWNTO 0);
106
107 SIGNAL SP_fifo_data : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
108 SIGNAL SP_fifo_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
109
93 110 SIGNAL fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
94 111 SIGNAL fifo_empty : STD_LOGIC;
95 112 SIGNAL fifo_ren : STD_LOGIC;
@@ -155,7 +172,7 BEGIN
155 172 lppFIFO_f0_0 : lppFIFOxN
156 173 GENERIC MAP (
157 174 tech => tech,
158 Data_sz => 18,
175 Data_sz => 16,
159 176 FifoCnt => 5,
160 177 Enable_ReUse => '0')
161 178 PORT MAP (
@@ -174,7 +191,7 BEGIN
174 191 lppFIFO_f0_1 : lppFIFOxN
175 192 GENERIC MAP (
176 193 tech => tech,
177 Data_sz => 18,
194 Data_sz => 16,
178 195 FifoCnt => 5,
179 196 Enable_ReUse => '0')
180 197 PORT MAP (
@@ -193,7 +210,7 BEGIN
193 210 lppFIFO_f1 : lppFIFOxN
194 211 GENERIC MAP (
195 212 tech => tech,
196 Data_sz => 18,
213 Data_sz => 16,
197 214 FifoCnt => 5,
198 215 Enable_ReUse => '0')
199 216 PORT MAP (
@@ -212,7 +229,7 BEGIN
212 229 lppFIFO_f3 : lppFIFOxN
213 230 GENERIC MAP (
214 231 tech => tech,
215 Data_sz => 18,
232 Data_sz => 16,
216 233 FifoCnt => 5,
217 234 Enable_ReUse => '0')
218 235 PORT MAP (
@@ -231,6 +248,82 BEGIN
231 248 -----------------------------------------------------------------------------
232 249 -- SPECTRAL MATRIX
233 250 -----------------------------------------------------------------------------
251 sample_f0_0_ren <= sample_ren(4 DOWNTO 0);
252 sample_f0_1_ren <= sample_ren(9 DOWNTO 5);
253 sample_f1_ren <= sample_ren(14 DOWNTO 10);
254 sample_f3_ren <= sample_ren(19 DOWNTO 15);
255
256 Demultiplex_1 : Demultiplex
257 GENERIC MAP (
258 Data_sz => 16)
259 PORT MAP (
260 clk => clk,
261 rstn => rstn,
262
263 Read => demux_ren,
264 EmptyF0a => sample_f0_0_empty,
265 EmptyF0b => sample_f0_0_empty,
266 EmptyF1 => sample_f1_empty,
267 EmptyF2 => sample_f3_empty,
268 DataF0a => sample_f0_0_rdata,
269 DataF0b => sample_f0_1_rdata,
270 DataF1 => sample_f1_rdata,
271 DataF2 => sample_f3_rdata,
272 Read_DEMUX => sample_ren,
273 Empty => demux_empty,
274 Data => demux_data);
275
276 FFT_1 : FFT
277 GENERIC MAP (
278 Data_sz => 16,
279 NbData => 256)
280 PORT MAP (
281 clkm => clk,
282 rstn => rstn,
283 FifoIN_Empty => demux_empty,
284 FifoIN_Data => demux_data,
285 FifoOUT_Full => fft_fifo_full,
286 Read => demux_ren,
287 Write => fft_fifo_wen,
288 ReUse => fft_fifo_reuse,
289 Data => fft_fifo_data);
290
291 lppFIFO_fft : lppFIFOxN
292 GENERIC MAP (
293 tech => tech,
294 Data_sz => 16,
295 FifoCnt => 5,
296 Enable_ReUse => '1')
297 PORT MAP (
298 rst => rstn,
299 wclk => clk,
300 rclk => clk,
301 ReUse => fft_fifo_reuse,
302 wen => fft_fifo_wen,
303 ren => SP_fifo_ren,
304 wdata => fft_fifo_data,
305 rdata => SP_fifo_data,
306 full => fft_fifo_full,
307 empty => OPEN);
308
309 MatriceSpectrale_1: MatriceSpectrale
310 GENERIC MAP (
311 Input_SZ => 16,
312 Result_SZ => 32)
313 PORT MAP (
314 clkm => clk,
315 rstn => rstn,
316
317 FifoIN_Full => fft_fifo_full,
318 FifoOUT_Full => , -- TODO
319 Data_IN => SP_fifo_data,
320 ACQ => , -- TODO
321 FlagError => , -- TODO
322 Pong => , -- TODO
323 Write => , -- TODO
324 Read => SP_fifo_ren,
325 Data_OUT => ); -- TODO
326
234 327
235 328 -----------------------------------------------------------------------------
236 329 -- DMA SPECTRAL MATRIX
@@ -282,11 +375,11 BEGIN
282 375 pmask => pmask,
283 376 pirq => pirq)
284 377 PORT MAP (
285 HCLK => clk,
286 HRESETn => rstn,
287 apbi => apbi,
288 apbo => apbo,
289
378 HCLK => clk,
379 HRESETn => rstn,
380 apbi => apbi,
381 apbo => apbo,
382
290 383 ready_matrix_f0_0 => ready_matrix_f0_0,
291 384 ready_matrix_f0_1 => ready_matrix_f0_1,
292 385 ready_matrix_f1 => ready_matrix_f1,
@@ -307,12 +400,12 BEGIN
307 400 addr_matrix_f1 => addr_matrix_f1,
308 401 addr_matrix_f2 => addr_matrix_f2);
309 402
310
403
311 404 --TODO : add the irq alert for DMA matrix transfert ending
312 405 --TODO : add 5 bit register into APB to control the DATA SHIPING
313 406 --TODO : add Spectral Matrix (FFT + SP)
314 407 --TODO : add DMA for WaveForms Picker
315 408 --TODO : add APB Reg to control WaveForms Picker
316 409 --TODO : add WaveForms Picker
317
410
318 411 END tb;
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@@ -1,68 +1,72
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3 LIBRARY lpp;
4 USE lpp.lpp_ad_conv.ALL;
5 USE lpp.iir_filter.ALL;
6 USE lpp.FILTERcfg.ALL;
7 USE lpp.lpp_memory.ALL;
8 LIBRARY techmap;
9 USE techmap.gencomp.ALL;
10
11 PACKAGE lpp_top_lfr_pkg IS
12
13 COMPONENT lpp_top_acq
14 GENERIC (
15 tech : integer);
16 PORT (
17 cnv_run : IN STD_LOGIC;
18 cnv : OUT STD_LOGIC;
19 sck : OUT STD_LOGIC;
20 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
21 cnv_clk : IN STD_LOGIC;
22 cnv_rstn : IN STD_LOGIC;
23 clk : IN STD_LOGIC;
24 rstn : IN STD_LOGIC;
25 sample_f0_0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
26 sample_f0_1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
27 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
28 sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
29 sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
30 sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
31 sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
32 sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
33 sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0));
34 END COMPONENT;
35
36 COMPONENT lpp_top_apbreg
37 GENERIC (
38 pindex : INTEGER;
39 paddr : INTEGER;
40 pmask : INTEGER;
41 pirq : INTEGER);
42 PORT (
43 HCLK : IN STD_ULOGIC;
44 HRESETn : IN STD_ULOGIC;
45 apbi : IN apb_slv_in_type;
46 apbo : OUT apb_slv_out_type;
47 ready_matrix_f0_0 : IN STD_LOGIC;
48 ready_matrix_f0_1 : IN STD_LOGIC;
49 ready_matrix_f1 : IN STD_LOGIC;
50 ready_matrix_f2 : IN STD_LOGIC;
51 error_anticipating_empty_fifo : IN STD_LOGIC;
52 error_bad_component_error : IN STD_LOGIC;
53 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
54 status_ready_matrix_f0_0 : OUT STD_LOGIC;
55 status_ready_matrix_f0_1 : OUT STD_LOGIC;
56 status_ready_matrix_f1 : OUT STD_LOGIC;
57 status_ready_matrix_f2 : OUT STD_LOGIC;
58 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
59 status_error_bad_component_error : OUT STD_LOGIC;
60 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
61 config_active_interruption_onError : OUT STD_LOGIC;
62 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
63 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
65 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
66 END COMPONENT;
67
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3
4 LIBRARY grlib;
5 USE grlib.amba.ALL;
6
7 LIBRARY lpp;
8 USE lpp.lpp_ad_conv.ALL;
9 USE lpp.iir_filter.ALL;
10 USE lpp.FILTERcfg.ALL;
11 USE lpp.lpp_memory.ALL;
12 LIBRARY techmap;
13 USE techmap.gencomp.ALL;
14
15 PACKAGE lpp_top_lfr_pkg IS
16
17 COMPONENT lpp_top_acq
18 GENERIC (
19 tech : integer);
20 PORT (
21 cnv_run : IN STD_LOGIC;
22 cnv : OUT STD_LOGIC;
23 sck : OUT STD_LOGIC;
24 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
25 cnv_clk : IN STD_LOGIC;
26 cnv_rstn : IN STD_LOGIC;
27 clk : IN STD_LOGIC;
28 rstn : IN STD_LOGIC;
29 sample_f0_0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
30 sample_f0_1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
31 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
32 sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
33 sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
34 sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
35 sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
36 sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
37 sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0));
38 END COMPONENT;
39
40 COMPONENT lpp_top_apbreg
41 GENERIC (
42 pindex : INTEGER;
43 paddr : INTEGER;
44 pmask : INTEGER;
45 pirq : INTEGER);
46 PORT (
47 HCLK : IN STD_ULOGIC;
48 HRESETn : IN STD_ULOGIC;
49 apbi : IN apb_slv_in_type;
50 apbo : OUT apb_slv_out_type;
51 ready_matrix_f0_0 : IN STD_LOGIC;
52 ready_matrix_f0_1 : IN STD_LOGIC;
53 ready_matrix_f1 : IN STD_LOGIC;
54 ready_matrix_f2 : IN STD_LOGIC;
55 error_anticipating_empty_fifo : IN STD_LOGIC;
56 error_bad_component_error : IN STD_LOGIC;
57 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
58 status_ready_matrix_f0_0 : OUT STD_LOGIC;
59 status_ready_matrix_f0_1 : OUT STD_LOGIC;
60 status_ready_matrix_f1 : OUT STD_LOGIC;
61 status_ready_matrix_f2 : OUT STD_LOGIC;
62 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
63 status_error_bad_component_error : OUT STD_LOGIC;
64 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
65 config_active_interruption_onError : OUT STD_LOGIC;
66 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
67 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
68 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
69 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
70 END COMPONENT;
71
68 72 END lpp_top_lfr_pkg; No newline at end of file
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