# HG changeset patch # User pellion # Date 2013-04-18 08:00:00 # Node ID 17327dd65850b53923fff2528580bb11bfc3ad96 # Parent 67e77b1cb356ab2294f5f8a47d161125c713396e correction ADS diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/Top_Data_Acquisition.vhd b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/Top_Data_Acquisition.vhd --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/Top_Data_Acquisition.vhd +++ b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/Top_Data_Acquisition.vhd @@ -159,32 +159,32 @@ BEGIN sample_filter_in(i, 17) <= sample(i)(15); END GENERATE; - coefs <= CoefsInitValCst; - coefs_JC <= CoefsInitValCst_JC; + --coefs <= CoefsInitValCst; + coefs_JC <= CoefsInitValCst_v2; - FILTER : IIR_CEL_CTRLR - GENERIC MAP ( - tech => 0, - Sample_SZ => 18, - ChanelsCount => ChanelCount, - Coef_SZ => Coef_SZ, - CoefCntPerCel => CoefCntPerCel, - Cels_count => Cels_count, - Mem_use => use_CEL) -- use_CEL for SIMU, use_RAM for synthesis - PORT MAP ( - reset => rstn, - clk => clk, - sample_clk => sample_val_delay, - sample_in => sample_filter_in, - sample_out => sample_filter_out, - virg_pos => 7, - GOtest => OPEN, - coefs => coefs); + --FILTER : IIR_CEL_CTRLR + -- GENERIC MAP ( + -- tech => 0, + -- Sample_SZ => 18, + -- ChanelsCount => ChanelCount, + -- Coef_SZ => Coef_SZ, + -- CoefCntPerCel => CoefCntPerCel, + -- Cels_count => Cels_count, + -- Mem_use => use_CEL) -- use_CEL for SIMU, use_RAM for synthesis + -- PORT MAP ( + -- reset => rstn, + -- clk => clk, + -- sample_clk => sample_val_delay, + -- sample_in => sample_filter_in, + -- sample_out => sample_filter_out, + -- virg_pos => 7, + -- GOtest => OPEN, + -- coefs => coefs); IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 GENERIC MAP ( tech => 0, - Mem_use => use_CEL, + Mem_use => use_RAM, Sample_SZ => 18, Coef_SZ => Coef_SZ, Coef_Nb => 25, -- TODO diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/run_sim_data_acquisition.do b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/run_sim_data_acquisition.do --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/run_sim_data_acquisition.do +++ b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/run_sim_data_acquisition.do @@ -19,7 +19,7 @@ vcom -quiet -93 -work lpp ../../lib/lpp/ vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/FILTERcfg.vhd vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CEL.vhd vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR2.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR.vhd +#vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR.vhd vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd diff --git a/lib/lpp/dsp/iir_filter/FILTERcfg.vhd b/lib/lpp/dsp/iir_filter/FILTERcfg.vhd --- a/lib/lpp/dsp/iir_filter/FILTERcfg.vhd +++ b/lib/lpp/dsp/iir_filter/FILTERcfg.vhd @@ -108,7 +108,7 @@ constant a4_2 : std_logic_vector constant CoefsInitValCst : std_logic_vector((Cels_count*CoefCntPerCel*Coef_SZ)-1 downto 0) := (a4_2 & a4_1 & a4_0 & b4_2 & b4_1 & b4_0 & a3_2 & a3_1 & a3_0 & b3_2 & b3_1 & b3_0 & a2_2 & a2_1 & a2_0 & b2_2 & b2_1 & b2_0 & a1_2 & a1_1 & a1_0 & b1_2 & b1_1 & b1_0 & a0_2 & a0_1 & a0_0 & b0_2 & b0_1 & b0_0); -constant CoefsInitValCst_JC : std_logic_vector((Cels_count*CoefPerCel*Coef_SZ)-1 downto 0) := +constant CoefsInitValCst_v2 : std_logic_vector((Cels_count*CoefPerCel*Coef_SZ)-1 downto 0) := (a4_1 & a4_2 & b4_0 & b4_1 & b4_2 & a3_1 & a3_2 & b3_0 & b3_1 & b3_2 & a2_1 & a2_2 & b2_0 & b2_1 & b2_2 & diff --git a/lib/lpp/lpp_ad_Conv/ADS7886_drvr.vhd b/lib/lpp/lpp_ad_Conv/ADS7886_drvr.vhd --- a/lib/lpp/lpp_ad_Conv/ADS7886_drvr.vhd +++ b/lib/lpp/lpp_ad_Conv/ADS7886_drvr.vhd @@ -169,8 +169,10 @@ BEGIN IF (sample_bit_counter MOD 2) = 1 THEN FOR l IN 0 TO ChanelCount-1 LOOP - shift_reg(l)(15) <= sdo(l); - shift_reg(l)(14 DOWNTO 0) <= shift_reg(l)(15 DOWNTO 1); + --shift_reg(l)(15) <= sdo(l); + --shift_reg(l)(14 DOWNTO 0) <= shift_reg(l)(15 DOWNTO 1); + shift_reg(l)(0) <= sdo(l); + shift_reg(l)(15 DOWNTO 1) <= shift_reg(l)(14 DOWNTO 0); END LOOP; SCK <= '0'; ELSE @@ -180,8 +182,10 @@ BEGIN IF sample_bit_counter = 31 THEN sample_val <= '1'; FOR l IN 0 TO ChanelCount-1 LOOP - sample(l)(15) <= sdo(l); - sample(l)(14 DOWNTO 0) <= shift_reg(l)(15 DOWNTO 1); + --sample(l)(15) <= sdo(l); + --sample(l)(14 DOWNTO 0) <= shift_reg(l)(15 DOWNTO 1); + sample(l)(0) <= sdo(l); + sample(l)(15 DOWNTO 1) <= shift_reg(l)(14 DOWNTO 0); END LOOP; ELSE sample_val <= '0'; diff --git a/lib/lpp/lpp_top_lfr/lpp_top_lfr.vhd b/lib/lpp/lpp_top_lfr/lpp_top_lfr.vhd --- a/lib/lpp/lpp_top_lfr/lpp_top_lfr.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_top_lfr.vhd @@ -12,6 +12,9 @@ USE lpp.FILTERcfg.ALL; USE lpp.lpp_memory.ALL; USE lpp.lpp_top_lfr_pkg.ALL; USE lpp.lpp_dma_pkg.ALL; +USE lpp.lpp_demux.ALL; +USE lpp.lpp_fft.ALL; +use lpp.lpp_matrix.all; LIBRARY techmap; USE techmap.gencomp.ALL; @@ -52,37 +55,37 @@ ARCHITECTURE tb OF lpp_top_lfr IS -- f0 SIGNAL sample_f0_0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); SIGNAL sample_f0_1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); + SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); -- SIGNAL sample_f0_0_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f0_0_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); + SIGNAL sample_f0_0_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); SIGNAL sample_f0_0_full : STD_LOGIC_VECTOR(4 DOWNTO 0); SIGNAL sample_f0_0_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); -- SIGNAL sample_f0_1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f0_1_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); + SIGNAL sample_f0_1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); SIGNAL sample_f0_1_full : STD_LOGIC_VECTOR(4 DOWNTO 0); SIGNAL sample_f0_1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); ----------------------------------------------------------------------------- -- f1 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); + SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); -- SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); + SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0); SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); ----------------------------------------------------------------------------- -- f2 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); + SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); ----------------------------------------------------------------------------- -- f3 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); + SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); -- SIGNAL sample_f3_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f3_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); + SIGNAL sample_f3_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); SIGNAL sample_f3_full : STD_LOGIC_VECTOR(4 DOWNTO 0); SIGNAL sample_f3_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); ----------------------------------------------------------------------------- @@ -90,6 +93,20 @@ ARCHITECTURE tb OF lpp_top_lfr IS ----------------------------------------------------------------------------- -- SPECTRAL MATRIX ----------------------------------------------------------------------------- + SIGNAL sample_ren : STD_LOGIC_VECTOR(19 DOWNTO 0); + + SIGNAL demux_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL demux_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL demux_data : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + + SIGNAL fft_fifo_full : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL fft_fifo_data : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + SIGNAL fft_fifo_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL fft_fifo_reuse : STD_LOGIC_VECTOR(4 DOWNTO 0); + + SIGNAL SP_fifo_data : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + SIGNAL SP_fifo_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL fifo_empty : STD_LOGIC; SIGNAL fifo_ren : STD_LOGIC; @@ -155,7 +172,7 @@ BEGIN lppFIFO_f0_0 : lppFIFOxN GENERIC MAP ( tech => tech, - Data_sz => 18, + Data_sz => 16, FifoCnt => 5, Enable_ReUse => '0') PORT MAP ( @@ -174,7 +191,7 @@ BEGIN lppFIFO_f0_1 : lppFIFOxN GENERIC MAP ( tech => tech, - Data_sz => 18, + Data_sz => 16, FifoCnt => 5, Enable_ReUse => '0') PORT MAP ( @@ -193,7 +210,7 @@ BEGIN lppFIFO_f1 : lppFIFOxN GENERIC MAP ( tech => tech, - Data_sz => 18, + Data_sz => 16, FifoCnt => 5, Enable_ReUse => '0') PORT MAP ( @@ -212,7 +229,7 @@ BEGIN lppFIFO_f3 : lppFIFOxN GENERIC MAP ( tech => tech, - Data_sz => 18, + Data_sz => 16, FifoCnt => 5, Enable_ReUse => '0') PORT MAP ( @@ -231,6 +248,82 @@ BEGIN ----------------------------------------------------------------------------- -- SPECTRAL MATRIX ----------------------------------------------------------------------------- + sample_f0_0_ren <= sample_ren(4 DOWNTO 0); + sample_f0_1_ren <= sample_ren(9 DOWNTO 5); + sample_f1_ren <= sample_ren(14 DOWNTO 10); + sample_f3_ren <= sample_ren(19 DOWNTO 15); + + Demultiplex_1 : Demultiplex + GENERIC MAP ( + Data_sz => 16) + PORT MAP ( + clk => clk, + rstn => rstn, + + Read => demux_ren, + EmptyF0a => sample_f0_0_empty, + EmptyF0b => sample_f0_0_empty, + EmptyF1 => sample_f1_empty, + EmptyF2 => sample_f3_empty, + DataF0a => sample_f0_0_rdata, + DataF0b => sample_f0_1_rdata, + DataF1 => sample_f1_rdata, + DataF2 => sample_f3_rdata, + Read_DEMUX => sample_ren, + Empty => demux_empty, + Data => demux_data); + + FFT_1 : FFT + GENERIC MAP ( + Data_sz => 16, + NbData => 256) + PORT MAP ( + clkm => clk, + rstn => rstn, + FifoIN_Empty => demux_empty, + FifoIN_Data => demux_data, + FifoOUT_Full => fft_fifo_full, + Read => demux_ren, + Write => fft_fifo_wen, + ReUse => fft_fifo_reuse, + Data => fft_fifo_data); + + lppFIFO_fft : lppFIFOxN + GENERIC MAP ( + tech => tech, + Data_sz => 16, + FifoCnt => 5, + Enable_ReUse => '1') + PORT MAP ( + rst => rstn, + wclk => clk, + rclk => clk, + ReUse => fft_fifo_reuse, + wen => fft_fifo_wen, + ren => SP_fifo_ren, + wdata => fft_fifo_data, + rdata => SP_fifo_data, + full => fft_fifo_full, + empty => OPEN); + + MatriceSpectrale_1: MatriceSpectrale + GENERIC MAP ( + Input_SZ => 16, + Result_SZ => 32) + PORT MAP ( + clkm => clk, + rstn => rstn, + + FifoIN_Full => fft_fifo_full, + FifoOUT_Full => , -- TODO + Data_IN => SP_fifo_data, + ACQ => , -- TODO + FlagError => , -- TODO + Pong => , -- TODO + Write => , -- TODO + Read => SP_fifo_ren, + Data_OUT => ); -- TODO + ----------------------------------------------------------------------------- -- DMA SPECTRAL MATRIX @@ -282,11 +375,11 @@ BEGIN pmask => pmask, pirq => pirq) PORT MAP ( - HCLK => clk, - HRESETn => rstn, - apbi => apbi, - apbo => apbo, - + HCLK => clk, + HRESETn => rstn, + apbi => apbi, + apbo => apbo, + ready_matrix_f0_0 => ready_matrix_f0_0, ready_matrix_f0_1 => ready_matrix_f0_1, ready_matrix_f1 => ready_matrix_f1, @@ -307,12 +400,12 @@ BEGIN addr_matrix_f1 => addr_matrix_f1, addr_matrix_f2 => addr_matrix_f2); - + --TODO : add the irq alert for DMA matrix transfert ending --TODO : add 5 bit register into APB to control the DATA SHIPING --TODO : add Spectral Matrix (FFT + SP) --TODO : add DMA for WaveForms Picker --TODO : add APB Reg to control WaveForms Picker --TODO : add WaveForms Picker - + END tb; diff --git a/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd b/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd --- a/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd @@ -1,68 +1,72 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -LIBRARY lpp; -USE lpp.lpp_ad_conv.ALL; -USE lpp.iir_filter.ALL; -USE lpp.FILTERcfg.ALL; -USE lpp.lpp_memory.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; - -PACKAGE lpp_top_lfr_pkg IS - - COMPONENT lpp_top_acq - GENERIC ( - tech : integer); - PORT ( - cnv_run : IN STD_LOGIC; - cnv : OUT STD_LOGIC; - sck : OUT STD_LOGIC; - sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - cnv_clk : IN STD_LOGIC; - cnv_rstn : IN STD_LOGIC; - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; - sample_f0_0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f0_1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0)); - END COMPONENT; - - COMPONENT lpp_top_apbreg - GENERIC ( - pindex : INTEGER; - paddr : INTEGER; - pmask : INTEGER; - pirq : INTEGER); - PORT ( - HCLK : IN STD_ULOGIC; - HRESETn : IN STD_ULOGIC; - apbi : IN apb_slv_in_type; - apbo : OUT apb_slv_out_type; - ready_matrix_f0_0 : IN STD_LOGIC; - ready_matrix_f0_1 : IN STD_LOGIC; - ready_matrix_f1 : IN STD_LOGIC; - ready_matrix_f2 : IN STD_LOGIC; - error_anticipating_empty_fifo : IN STD_LOGIC; - error_bad_component_error : IN STD_LOGIC; - debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - status_ready_matrix_f0_0 : OUT STD_LOGIC; - status_ready_matrix_f0_1 : OUT STD_LOGIC; - status_ready_matrix_f1 : OUT STD_LOGIC; - status_ready_matrix_f2 : OUT STD_LOGIC; - status_error_anticipating_empty_fifo : OUT STD_LOGIC; - status_error_bad_component_error : OUT STD_LOGIC; - config_active_interruption_onNewMatrix : OUT STD_LOGIC; - config_active_interruption_onError : OUT STD_LOGIC; - addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); - END COMPONENT; - +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +LIBRARY grlib; +USE grlib.amba.ALL; + +LIBRARY lpp; +USE lpp.lpp_ad_conv.ALL; +USE lpp.iir_filter.ALL; +USE lpp.FILTERcfg.ALL; +USE lpp.lpp_memory.ALL; +LIBRARY techmap; +USE techmap.gencomp.ALL; + +PACKAGE lpp_top_lfr_pkg IS + + COMPONENT lpp_top_acq + GENERIC ( + tech : integer); + PORT ( + cnv_run : IN STD_LOGIC; + cnv : OUT STD_LOGIC; + sck : OUT STD_LOGIC; + sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + cnv_clk : IN STD_LOGIC; + cnv_rstn : IN STD_LOGIC; + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + sample_f0_0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f0_1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0)); + END COMPONENT; + + COMPONENT lpp_top_apbreg + GENERIC ( + pindex : INTEGER; + paddr : INTEGER; + pmask : INTEGER; + pirq : INTEGER); + PORT ( + HCLK : IN STD_ULOGIC; + HRESETn : IN STD_ULOGIC; + apbi : IN apb_slv_in_type; + apbo : OUT apb_slv_out_type; + ready_matrix_f0_0 : IN STD_LOGIC; + ready_matrix_f0_1 : IN STD_LOGIC; + ready_matrix_f1 : IN STD_LOGIC; + ready_matrix_f2 : IN STD_LOGIC; + error_anticipating_empty_fifo : IN STD_LOGIC; + error_bad_component_error : IN STD_LOGIC; + debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + status_ready_matrix_f0_0 : OUT STD_LOGIC; + status_ready_matrix_f0_1 : OUT STD_LOGIC; + status_ready_matrix_f1 : OUT STD_LOGIC; + status_ready_matrix_f2 : OUT STD_LOGIC; + status_error_anticipating_empty_fifo : OUT STD_LOGIC; + status_error_bad_component_error : OUT STD_LOGIC; + config_active_interruption_onNewMatrix : OUT STD_LOGIC; + config_active_interruption_onError : OUT STD_LOGIC; + addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); + END COMPONENT; + END lpp_top_lfr_pkg; \ No newline at end of file