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correction ADS
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1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 LIBRARY lpp;
3 LIBRARY lpp;
4 USE lpp.lpp_ad_conv.ALL;
4 USE lpp.lpp_ad_conv.ALL;
5 USE lpp.iir_filter.ALL;
5 USE lpp.iir_filter.ALL;
6 USE lpp.FILTERcfg.ALL;
6 USE lpp.FILTERcfg.ALL;
7 USE lpp.lpp_memory.ALL;
7 USE lpp.lpp_memory.ALL;
8 LIBRARY techmap;
8 LIBRARY techmap;
9 USE techmap.gencomp.ALL;
9 USE techmap.gencomp.ALL;
10 --USE lpp.ALL;
10 --USE lpp.ALL;
11
11
12 ENTITY Top_Data_Acquisition IS
12 ENTITY Top_Data_Acquisition IS
13 generic(
13 generic(
14 tech : integer := 0
14 tech : integer := 0
15 );
15 );
16 PORT (
16 PORT (
17 -- ADS7886
17 -- ADS7886
18 cnv_run : IN STD_LOGIC;
18 cnv_run : IN STD_LOGIC;
19 cnv : OUT STD_LOGIC;
19 cnv : OUT STD_LOGIC;
20 sck : OUT STD_LOGIC;
20 sck : OUT STD_LOGIC;
21 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
21 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
22 --
22 --
23 cnv_clk : IN STD_LOGIC;
23 cnv_clk : IN STD_LOGIC;
24 cnv_rstn : IN STD_LOGIC;
24 cnv_rstn : IN STD_LOGIC;
25 --
25 --
26 clk : IN STD_LOGIC;
26 clk : IN STD_LOGIC;
27 rstn : IN STD_LOGIC;
27 rstn : IN STD_LOGIC;
28 --
28 --
29 sample_f0_0_ren : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
29 sample_f0_0_ren : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
30 sample_f0_0_rdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
30 sample_f0_0_rdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
31 sample_f0_0_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
31 sample_f0_0_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
32 sample_f0_0_empty : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
32 sample_f0_0_empty : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
33 --
33 --
34 sample_f0_1_ren : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
34 sample_f0_1_ren : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
35 sample_f0_1_rdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
35 sample_f0_1_rdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
36 sample_f0_1_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
36 sample_f0_1_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
37 sample_f0_1_empty : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
37 sample_f0_1_empty : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
38 --
38 --
39 sample_f1_ren : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
39 sample_f1_ren : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
40 sample_f1_rdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
40 sample_f1_rdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
41 sample_f1_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
41 sample_f1_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
42 sample_f1_empty : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
42 sample_f1_empty : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
43 --
43 --
44 sample_f3_ren : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
44 sample_f3_ren : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
45 sample_f3_rdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
45 sample_f3_rdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
46 sample_f3_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
46 sample_f3_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
47 sample_f3_empty : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
47 sample_f3_empty : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
48 );
48 );
49 END Top_Data_Acquisition;
49 END Top_Data_Acquisition;
50
50
51 ARCHITECTURE tb OF Top_Data_Acquisition IS
51 ARCHITECTURE tb OF Top_Data_Acquisition IS
52
52
53 COMPONENT Downsampling
53 COMPONENT Downsampling
54 GENERIC (
54 GENERIC (
55 ChanelCount : INTEGER;
55 ChanelCount : INTEGER;
56 SampleSize : INTEGER;
56 SampleSize : INTEGER;
57 DivideParam : INTEGER);
57 DivideParam : INTEGER);
58 PORT (
58 PORT (
59 clk : IN STD_LOGIC;
59 clk : IN STD_LOGIC;
60 rstn : IN STD_LOGIC;
60 rstn : IN STD_LOGIC;
61 sample_in_val : IN STD_LOGIC;
61 sample_in_val : IN STD_LOGIC;
62 sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0);
62 sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0);
63 sample_out_val : OUT STD_LOGIC;
63 sample_out_val : OUT STD_LOGIC;
64 sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0));
64 sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0));
65 END COMPONENT;
65 END COMPONENT;
66
66
67 -----------------------------------------------------------------------------
67 -----------------------------------------------------------------------------
68 CONSTANT ChanelCount : INTEGER := 8;
68 CONSTANT ChanelCount : INTEGER := 8;
69 CONSTANT ncycle_cnv_high : INTEGER := 79;
69 CONSTANT ncycle_cnv_high : INTEGER := 79;
70 CONSTANT ncycle_cnv : INTEGER := 500;
70 CONSTANT ncycle_cnv : INTEGER := 500;
71
71
72 -----------------------------------------------------------------------------
72 -----------------------------------------------------------------------------
73 SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0);
73 SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0);
74 SIGNAL sample_val : STD_LOGIC;
74 SIGNAL sample_val : STD_LOGIC;
75 SIGNAL sample_val_delay : STD_LOGIC;
75 SIGNAL sample_val_delay : STD_LOGIC;
76 -----------------------------------------------------------------------------
76 -----------------------------------------------------------------------------
77 CONSTANT Coef_SZ : INTEGER := 9;
77 CONSTANT Coef_SZ : INTEGER := 9;
78 CONSTANT CoefCntPerCel : INTEGER := 6;
78 CONSTANT CoefCntPerCel : INTEGER := 6;
79 CONSTANT CoefPerCel : INTEGER := 5;
79 CONSTANT CoefPerCel : INTEGER := 5;
80 CONSTANT Cels_count : INTEGER := 5;
80 CONSTANT Cels_count : INTEGER := 5;
81
81
82 SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0);
82 SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0);
83 SIGNAL coefs_JC : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
83 SIGNAL coefs_JC : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
84 SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
84 SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
85 SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
85 SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
86 --
86 --
87 SIGNAL sample_filter_JC_out_val : STD_LOGIC;
87 SIGNAL sample_filter_JC_out_val : STD_LOGIC;
88 SIGNAL sample_filter_JC_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
88 SIGNAL sample_filter_JC_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
89 --
89 --
90 SIGNAL sample_filter_JC_out_r_val : STD_LOGIC;
90 SIGNAL sample_filter_JC_out_r_val : STD_LOGIC;
91 SIGNAL sample_filter_JC_out_r : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
91 SIGNAL sample_filter_JC_out_r : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
92 -----------------------------------------------------------------------------
92 -----------------------------------------------------------------------------
93 SIGNAL downsampling_cnt : STD_LOGIC_VECTOR(1 DOWNTO 0);
93 SIGNAL downsampling_cnt : STD_LOGIC_VECTOR(1 DOWNTO 0);
94 SIGNAL sample_downsampling_out_val : STD_LOGIC;
94 SIGNAL sample_downsampling_out_val : STD_LOGIC;
95 SIGNAL sample_downsampling_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
95 SIGNAL sample_downsampling_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
96 --
96 --
97 SIGNAL sample_f0_val : STD_LOGIC;
97 SIGNAL sample_f0_val : STD_LOGIC;
98 SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
98 SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
99 SIGNAL sample_f0_0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
99 SIGNAL sample_f0_0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
100 SIGNAL sample_f0_1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
100 SIGNAL sample_f0_1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
101 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
101 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
102 --
102 --
103 SIGNAL sample_f0_0_val : STD_LOGIC;
103 SIGNAL sample_f0_0_val : STD_LOGIC;
104 SIGNAL sample_f0_1_val : STD_LOGIC;
104 SIGNAL sample_f0_1_val : STD_LOGIC;
105 SIGNAL counter_f0 : INTEGER;
105 SIGNAL counter_f0 : INTEGER;
106 -----------------------------------------------------------------------------
106 -----------------------------------------------------------------------------
107 SIGNAL sample_f1_val : STD_LOGIC;
107 SIGNAL sample_f1_val : STD_LOGIC;
108 SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
108 SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
109 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
109 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
110 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
110 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
111 --
111 --
112 SIGNAL sample_f2_val : STD_LOGIC;
112 SIGNAL sample_f2_val : STD_LOGIC;
113 SIGNAL sample_f2 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
113 SIGNAL sample_f2 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
114 --
114 --
115 SIGNAL sample_f3_val : STD_LOGIC;
115 SIGNAL sample_f3_val : STD_LOGIC;
116 SIGNAL sample_f3 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
116 SIGNAL sample_f3 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
117 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
117 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
118 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
118 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
119
119
120 BEGIN
120 BEGIN
121
121
122 -- component instantiation
122 -- component instantiation
123 -----------------------------------------------------------------------------
123 -----------------------------------------------------------------------------
124 DIGITAL_acquisition : ADS7886_drvr
124 DIGITAL_acquisition : ADS7886_drvr
125 GENERIC MAP (
125 GENERIC MAP (
126 ChanelCount => ChanelCount,
126 ChanelCount => ChanelCount,
127 ncycle_cnv_high => ncycle_cnv_high,
127 ncycle_cnv_high => ncycle_cnv_high,
128 ncycle_cnv => ncycle_cnv)
128 ncycle_cnv => ncycle_cnv)
129 PORT MAP (
129 PORT MAP (
130 cnv_clk => cnv_clk, --
130 cnv_clk => cnv_clk, --
131 cnv_rstn => cnv_rstn, --
131 cnv_rstn => cnv_rstn, --
132 cnv_run => cnv_run, --
132 cnv_run => cnv_run, --
133 cnv => cnv, --
133 cnv => cnv, --
134 clk => clk, --
134 clk => clk, --
135 rstn => rstn, --
135 rstn => rstn, --
136 sck => sck, --
136 sck => sck, --
137 sdo => sdo(ChanelCount-1 DOWNTO 0), --
137 sdo => sdo(ChanelCount-1 DOWNTO 0), --
138 sample => sample,
138 sample => sample,
139 sample_val => sample_val);
139 sample_val => sample_val);
140
140
141 -----------------------------------------------------------------------------
141 -----------------------------------------------------------------------------
142
142
143 PROCESS (clk, rstn)
143 PROCESS (clk, rstn)
144 BEGIN -- PROCESS
144 BEGIN -- PROCESS
145 IF rstn = '0' THEN -- asynchronous reset (active low)
145 IF rstn = '0' THEN -- asynchronous reset (active low)
146 sample_val_delay <= '0';
146 sample_val_delay <= '0';
147 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
147 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
148 sample_val_delay <= sample_val;
148 sample_val_delay <= sample_val;
149 END IF;
149 END IF;
150 END PROCESS;
150 END PROCESS;
151
151
152 -----------------------------------------------------------------------------
152 -----------------------------------------------------------------------------
153 ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
153 ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
154 SampleLoop : FOR j IN 0 TO 15 GENERATE
154 SampleLoop : FOR j IN 0 TO 15 GENERATE
155 sample_filter_in(i, j) <= sample(i)(j);
155 sample_filter_in(i, j) <= sample(i)(j);
156 END GENERATE;
156 END GENERATE;
157
157
158 sample_filter_in(i, 16) <= sample(i)(15);
158 sample_filter_in(i, 16) <= sample(i)(15);
159 sample_filter_in(i, 17) <= sample(i)(15);
159 sample_filter_in(i, 17) <= sample(i)(15);
160 END GENERATE;
160 END GENERATE;
161
161
162 coefs <= CoefsInitValCst;
162 --coefs <= CoefsInitValCst;
163 coefs_JC <= CoefsInitValCst_JC;
163 coefs_JC <= CoefsInitValCst_v2;
164
164
165 FILTER : IIR_CEL_CTRLR
165 --FILTER : IIR_CEL_CTRLR
166 GENERIC MAP (
166 -- GENERIC MAP (
167 tech => 0,
167 -- tech => 0,
168 Sample_SZ => 18,
168 -- Sample_SZ => 18,
169 ChanelsCount => ChanelCount,
169 -- ChanelsCount => ChanelCount,
170 Coef_SZ => Coef_SZ,
170 -- Coef_SZ => Coef_SZ,
171 CoefCntPerCel => CoefCntPerCel,
171 -- CoefCntPerCel => CoefCntPerCel,
172 Cels_count => Cels_count,
172 -- Cels_count => Cels_count,
173 Mem_use => use_CEL) -- use_CEL for SIMU, use_RAM for synthesis
173 -- Mem_use => use_CEL) -- use_CEL for SIMU, use_RAM for synthesis
174 PORT MAP (
174 -- PORT MAP (
175 reset => rstn,
175 -- reset => rstn,
176 clk => clk,
176 -- clk => clk,
177 sample_clk => sample_val_delay,
177 -- sample_clk => sample_val_delay,
178 sample_in => sample_filter_in,
178 -- sample_in => sample_filter_in,
179 sample_out => sample_filter_out,
179 -- sample_out => sample_filter_out,
180 virg_pos => 7,
180 -- virg_pos => 7,
181 GOtest => OPEN,
181 -- GOtest => OPEN,
182 coefs => coefs);
182 -- coefs => coefs);
183
183
184 IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
184 IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
185 GENERIC MAP (
185 GENERIC MAP (
186 tech => 0,
186 tech => 0,
187 Mem_use => use_CEL,
187 Mem_use => use_RAM,
188 Sample_SZ => 18,
188 Sample_SZ => 18,
189 Coef_SZ => Coef_SZ,
189 Coef_SZ => Coef_SZ,
190 Coef_Nb => 25, -- TODO
190 Coef_Nb => 25, -- TODO
191 Coef_sel_SZ => 5, -- TODO
191 Coef_sel_SZ => 5, -- TODO
192 Cels_count => Cels_count,
192 Cels_count => Cels_count,
193 ChanelsCount => ChanelCount)
193 ChanelsCount => ChanelCount)
194 PORT MAP (
194 PORT MAP (
195 rstn => rstn,
195 rstn => rstn,
196 clk => clk,
196 clk => clk,
197 virg_pos => 7,
197 virg_pos => 7,
198 coefs => coefs_JC,
198 coefs => coefs_JC,
199 sample_in_val => sample_val_delay,
199 sample_in_val => sample_val_delay,
200 sample_in => sample_filter_in,
200 sample_in => sample_filter_in,
201 sample_out_val => sample_filter_JC_out_val,
201 sample_out_val => sample_filter_JC_out_val,
202 sample_out => sample_filter_JC_out);
202 sample_out => sample_filter_JC_out);
203
203
204 -----------------------------------------------------------------------------
204 -----------------------------------------------------------------------------
205 PROCESS (clk, rstn)
205 PROCESS (clk, rstn)
206 BEGIN -- PROCESS
206 BEGIN -- PROCESS
207 IF rstn = '0' THEN -- asynchronous reset (active low)
207 IF rstn = '0' THEN -- asynchronous reset (active low)
208 sample_filter_JC_out_r_val <= '0';
208 sample_filter_JC_out_r_val <= '0';
209 rst_all_chanel : FOR I IN ChanelCount-1 DOWNTO 0 LOOP
209 rst_all_chanel : FOR I IN ChanelCount-1 DOWNTO 0 LOOP
210 rst_all_bits : FOR J IN 17 DOWNTO 0 LOOP
210 rst_all_bits : FOR J IN 17 DOWNTO 0 LOOP
211 sample_filter_JC_out_r(I, J) <= '0';
211 sample_filter_JC_out_r(I, J) <= '0';
212 END LOOP rst_all_bits;
212 END LOOP rst_all_bits;
213 END LOOP rst_all_chanel;
213 END LOOP rst_all_chanel;
214 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
214 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
215 sample_filter_JC_out_r_val <= sample_filter_JC_out_val;
215 sample_filter_JC_out_r_val <= sample_filter_JC_out_val;
216 IF sample_filter_JC_out_val = '1' THEN
216 IF sample_filter_JC_out_val = '1' THEN
217 sample_filter_JC_out_r <= sample_filter_JC_out;
217 sample_filter_JC_out_r <= sample_filter_JC_out;
218 END IF;
218 END IF;
219 END IF;
219 END IF;
220 END PROCESS;
220 END PROCESS;
221
221
222 -----------------------------------------------------------------------------
222 -----------------------------------------------------------------------------
223 -- F0 -- @24.576 kHz
223 -- F0 -- @24.576 kHz
224 -----------------------------------------------------------------------------
224 -----------------------------------------------------------------------------
225 Downsampling_f0 : Downsampling
225 Downsampling_f0 : Downsampling
226 GENERIC MAP (
226 GENERIC MAP (
227 ChanelCount => ChanelCount,
227 ChanelCount => ChanelCount,
228 SampleSize => 18,
228 SampleSize => 18,
229 DivideParam => 4)
229 DivideParam => 4)
230 PORT MAP (
230 PORT MAP (
231 clk => clk,
231 clk => clk,
232 rstn => rstn,
232 rstn => rstn,
233 sample_in_val => sample_filter_JC_out_val ,
233 sample_in_val => sample_filter_JC_out_val ,
234 sample_in => sample_filter_JC_out,
234 sample_in => sample_filter_JC_out,
235 sample_out_val => sample_f0_val,
235 sample_out_val => sample_f0_val,
236 sample_out => sample_f0);
236 sample_out => sample_f0);
237
237
238 all_bit_sample_f0: FOR I IN 17 DOWNTO 0 GENERATE
238 all_bit_sample_f0: FOR I IN 17 DOWNTO 0 GENERATE
239 sample_f0_wdata( I) <= sample_f0(0,I);
239 sample_f0_wdata( I) <= sample_f0(0,I);
240 sample_f0_wdata(18*1+I) <= sample_f0(1,I);
240 sample_f0_wdata(18*1+I) <= sample_f0(1,I);
241 sample_f0_wdata(18*2+I) <= sample_f0(2,I);
241 sample_f0_wdata(18*2+I) <= sample_f0(2,I);
242 sample_f0_wdata(18*3+I) <= sample_f0(6,I);
242 sample_f0_wdata(18*3+I) <= sample_f0(6,I);
243 sample_f0_wdata(18*4+I) <= sample_f0(7,I);
243 sample_f0_wdata(18*4+I) <= sample_f0(7,I);
244 END GENERATE all_bit_sample_f0;
244 END GENERATE all_bit_sample_f0;
245
245
246 PROCESS (clk, rstn)
246 PROCESS (clk, rstn)
247 BEGIN -- PROCESS
247 BEGIN -- PROCESS
248 IF rstn = '0' THEN -- asynchronous reset (active low)
248 IF rstn = '0' THEN -- asynchronous reset (active low)
249 counter_f0 <= 0;
249 counter_f0 <= 0;
250 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
250 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
251 IF sample_f0_val = '1' THEN
251 IF sample_f0_val = '1' THEN
252 IF counter_f0 = 511 THEN
252 IF counter_f0 = 511 THEN
253 counter_f0 <= 0;
253 counter_f0 <= 0;
254 ELSE
254 ELSE
255 counter_f0 <= counter_f0 + 1;
255 counter_f0 <= counter_f0 + 1;
256 END IF;
256 END IF;
257 END IF;
257 END IF;
258 END IF;
258 END IF;
259 END PROCESS;
259 END PROCESS;
260
260
261 sample_f0_0_val <= sample_f0_val WHEN counter_f0 < 256 ELSE '0';
261 sample_f0_0_val <= sample_f0_val WHEN counter_f0 < 256 ELSE '0';
262 sample_f0_0_wen <= NOT(sample_f0_0_val) &
262 sample_f0_0_wen <= NOT(sample_f0_0_val) &
263 NOT(sample_f0_0_val) &
263 NOT(sample_f0_0_val) &
264 NOT(sample_f0_0_val) &
264 NOT(sample_f0_0_val) &
265 NOT(sample_f0_0_val) &
265 NOT(sample_f0_0_val) &
266 NOT(sample_f0_0_val);
266 NOT(sample_f0_0_val);
267
267
268 lppFIFO_f0_0: lppFIFOxN
268 lppFIFO_f0_0: lppFIFOxN
269 GENERIC MAP (
269 GENERIC MAP (
270 tech => tech,
270 tech => tech,
271 Data_sz => 18,
271 Data_sz => 18,
272 FifoCnt => 5,
272 FifoCnt => 5,
273 Enable_ReUse => '0')
273 Enable_ReUse => '0')
274 PORT MAP (
274 PORT MAP (
275 rst => rstn,
275 rst => rstn,
276 wclk => clk,
276 wclk => clk,
277 rclk => clk,
277 rclk => clk,
278 ReUse => (OTHERS => '0'),
278 ReUse => (OTHERS => '0'),
279
279
280 wen => sample_f0_0_wen,
280 wen => sample_f0_0_wen,
281 ren => sample_f0_0_ren,
281 ren => sample_f0_0_ren,
282 wdata => sample_f0_wdata,
282 wdata => sample_f0_wdata,
283 rdata => sample_f0_0_rdata,
283 rdata => sample_f0_0_rdata,
284 full => sample_f0_0_full,
284 full => sample_f0_0_full,
285 empty => sample_f0_0_empty);
285 empty => sample_f0_0_empty);
286
286
287 sample_f0_1_val <= sample_f0_val WHEN counter_f0 > 255 ELSE '0';
287 sample_f0_1_val <= sample_f0_val WHEN counter_f0 > 255 ELSE '0';
288 sample_f0_1_wen <= NOT(sample_f0_1_val) &
288 sample_f0_1_wen <= NOT(sample_f0_1_val) &
289 NOT(sample_f0_1_val) &
289 NOT(sample_f0_1_val) &
290 NOT(sample_f0_1_val) &
290 NOT(sample_f0_1_val) &
291 NOT(sample_f0_1_val) &
291 NOT(sample_f0_1_val) &
292 NOT(sample_f0_1_val);
292 NOT(sample_f0_1_val);
293
293
294 lppFIFO_f0_1: lppFIFOxN
294 lppFIFO_f0_1: lppFIFOxN
295 GENERIC MAP (
295 GENERIC MAP (
296 tech => tech,
296 tech => tech,
297 Data_sz => 18,
297 Data_sz => 18,
298 FifoCnt => 5,
298 FifoCnt => 5,
299 Enable_ReUse => '0')
299 Enable_ReUse => '0')
300 PORT MAP (
300 PORT MAP (
301 rst => rstn,
301 rst => rstn,
302 wclk => clk,
302 wclk => clk,
303 rclk => clk,
303 rclk => clk,
304 ReUse => (OTHERS => '0'),
304 ReUse => (OTHERS => '0'),
305
305
306 wen => sample_f0_1_wen,
306 wen => sample_f0_1_wen,
307 ren => sample_f0_1_ren,
307 ren => sample_f0_1_ren,
308 wdata => sample_f0_wdata,
308 wdata => sample_f0_wdata,
309 rdata => sample_f0_1_rdata,
309 rdata => sample_f0_1_rdata,
310 full => sample_f0_1_full,
310 full => sample_f0_1_full,
311 empty => sample_f0_1_empty);
311 empty => sample_f0_1_empty);
312
312
313
313
314
314
315 -----------------------------------------------------------------------------
315 -----------------------------------------------------------------------------
316 -- F1 -- @4096 Hz
316 -- F1 -- @4096 Hz
317 -----------------------------------------------------------------------------
317 -----------------------------------------------------------------------------
318 Downsampling_f1 : Downsampling
318 Downsampling_f1 : Downsampling
319 GENERIC MAP (
319 GENERIC MAP (
320 ChanelCount => ChanelCount,
320 ChanelCount => ChanelCount,
321 SampleSize => 18,
321 SampleSize => 18,
322 DivideParam => 6)
322 DivideParam => 6)
323 PORT MAP (
323 PORT MAP (
324 clk => clk,
324 clk => clk,
325 rstn => rstn,
325 rstn => rstn,
326 sample_in_val => sample_f0_val ,
326 sample_in_val => sample_f0_val ,
327 sample_in => sample_f0,
327 sample_in => sample_f0,
328 sample_out_val => sample_f1_val,
328 sample_out_val => sample_f1_val,
329 sample_out => sample_f1);
329 sample_out => sample_f1);
330
330
331 sample_f1_wen <= NOT(sample_f1_val) &
331 sample_f1_wen <= NOT(sample_f1_val) &
332 NOT(sample_f1_val) &
332 NOT(sample_f1_val) &
333 NOT(sample_f1_val) &
333 NOT(sample_f1_val) &
334 NOT(sample_f1_val) &
334 NOT(sample_f1_val) &
335 NOT(sample_f1_val);
335 NOT(sample_f1_val);
336
336
337 all_bit_sample_f1: FOR I IN 17 DOWNTO 0 GENERATE
337 all_bit_sample_f1: FOR I IN 17 DOWNTO 0 GENERATE
338 sample_f1_wdata( I) <= sample_f1(0,I);
338 sample_f1_wdata( I) <= sample_f1(0,I);
339 sample_f1_wdata(18*1+I) <= sample_f1(1,I);
339 sample_f1_wdata(18*1+I) <= sample_f1(1,I);
340 sample_f1_wdata(18*2+I) <= sample_f1(2,I);
340 sample_f1_wdata(18*2+I) <= sample_f1(2,I);
341 sample_f1_wdata(18*3+I) <= sample_f1(6,I);
341 sample_f1_wdata(18*3+I) <= sample_f1(6,I);
342 sample_f1_wdata(18*4+I) <= sample_f1(7,I);
342 sample_f1_wdata(18*4+I) <= sample_f1(7,I);
343 END GENERATE all_bit_sample_f1;
343 END GENERATE all_bit_sample_f1;
344
344
345 lppFIFO_f1: lppFIFOxN
345 lppFIFO_f1: lppFIFOxN
346 GENERIC MAP (
346 GENERIC MAP (
347 tech => tech,
347 tech => tech,
348 Data_sz => 18,
348 Data_sz => 18,
349 FifoCnt => 5,
349 FifoCnt => 5,
350 Enable_ReUse => '0')
350 Enable_ReUse => '0')
351 PORT MAP (
351 PORT MAP (
352 rst => rstn,
352 rst => rstn,
353 wclk => clk,
353 wclk => clk,
354 rclk => clk,
354 rclk => clk,
355 ReUse => (OTHERS => '0'),
355 ReUse => (OTHERS => '0'),
356
356
357 wen => sample_f1_wen,
357 wen => sample_f1_wen,
358 ren => sample_f1_ren,
358 ren => sample_f1_ren,
359 wdata => sample_f1_wdata,
359 wdata => sample_f1_wdata,
360 rdata => sample_f1_rdata,
360 rdata => sample_f1_rdata,
361 full => sample_f1_full,
361 full => sample_f1_full,
362 empty => sample_f1_empty);
362 empty => sample_f1_empty);
363
363
364 -----------------------------------------------------------------------------
364 -----------------------------------------------------------------------------
365 -- F2 -- @16 Hz
365 -- F2 -- @16 Hz
366 -----------------------------------------------------------------------------
366 -----------------------------------------------------------------------------
367 Downsampling_f2 : Downsampling
367 Downsampling_f2 : Downsampling
368 GENERIC MAP (
368 GENERIC MAP (
369 ChanelCount => ChanelCount,
369 ChanelCount => ChanelCount,
370 SampleSize => 18,
370 SampleSize => 18,
371 DivideParam => 256)
371 DivideParam => 256)
372 PORT MAP (
372 PORT MAP (
373 clk => clk,
373 clk => clk,
374 rstn => rstn,
374 rstn => rstn,
375 sample_in_val => sample_f1_val ,
375 sample_in_val => sample_f1_val ,
376 sample_in => sample_f1,
376 sample_in => sample_f1,
377 sample_out_val => sample_f2_val,
377 sample_out_val => sample_f2_val,
378 sample_out => sample_f2);
378 sample_out => sample_f2);
379
379
380 -----------------------------------------------------------------------------
380 -----------------------------------------------------------------------------
381 -- F3 -- @256 Hz
381 -- F3 -- @256 Hz
382 -----------------------------------------------------------------------------
382 -----------------------------------------------------------------------------
383 Downsampling_f3 : Downsampling
383 Downsampling_f3 : Downsampling
384 GENERIC MAP (
384 GENERIC MAP (
385 ChanelCount => ChanelCount,
385 ChanelCount => ChanelCount,
386 SampleSize => 18,
386 SampleSize => 18,
387 DivideParam => 96)
387 DivideParam => 96)
388 PORT MAP (
388 PORT MAP (
389 clk => clk,
389 clk => clk,
390 rstn => rstn,
390 rstn => rstn,
391 sample_in_val => sample_f0_val ,
391 sample_in_val => sample_f0_val ,
392 sample_in => sample_f0,
392 sample_in => sample_f0,
393 sample_out_val => sample_f3_val,
393 sample_out_val => sample_f3_val,
394 sample_out => sample_f3);
394 sample_out => sample_f3);
395
395
396 sample_f3_wen <= (NOT sample_f3_val) &
396 sample_f3_wen <= (NOT sample_f3_val) &
397 (NOT sample_f3_val) &
397 (NOT sample_f3_val) &
398 (NOT sample_f3_val) &
398 (NOT sample_f3_val) &
399 (NOT sample_f3_val) &
399 (NOT sample_f3_val) &
400 (NOT sample_f3_val);
400 (NOT sample_f3_val);
401
401
402 all_bit_sample_f3: FOR I IN 17 DOWNTO 0 GENERATE
402 all_bit_sample_f3: FOR I IN 17 DOWNTO 0 GENERATE
403 sample_f3_wdata( I) <= sample_f3(0,I);
403 sample_f3_wdata( I) <= sample_f3(0,I);
404 sample_f3_wdata(18*1+I) <= sample_f3(1,I);
404 sample_f3_wdata(18*1+I) <= sample_f3(1,I);
405 sample_f3_wdata(18*2+I) <= sample_f3(2,I);
405 sample_f3_wdata(18*2+I) <= sample_f3(2,I);
406 sample_f3_wdata(18*3+I) <= sample_f3(6,I);
406 sample_f3_wdata(18*3+I) <= sample_f3(6,I);
407 sample_f3_wdata(18*4+I) <= sample_f3(7,I);
407 sample_f3_wdata(18*4+I) <= sample_f3(7,I);
408 END GENERATE all_bit_sample_f3;
408 END GENERATE all_bit_sample_f3;
409
409
410 lppFIFO_f3: lppFIFOxN
410 lppFIFO_f3: lppFIFOxN
411 GENERIC MAP (
411 GENERIC MAP (
412 tech => tech,
412 tech => tech,
413 Data_sz => 18,
413 Data_sz => 18,
414 FifoCnt => 5,
414 FifoCnt => 5,
415 Enable_ReUse => '0')
415 Enable_ReUse => '0')
416 PORT MAP (
416 PORT MAP (
417 rst => rstn,
417 rst => rstn,
418 wclk => clk,
418 wclk => clk,
419 rclk => clk,
419 rclk => clk,
420 ReUse => (OTHERS => '0'),
420 ReUse => (OTHERS => '0'),
421
421
422 wen => sample_f3_wen,
422 wen => sample_f3_wen,
423 ren => sample_f3_ren,
423 ren => sample_f3_ren,
424 wdata => sample_f3_wdata,
424 wdata => sample_f3_wdata,
425 rdata => sample_f3_rdata,
425 rdata => sample_f3_rdata,
426 full => sample_f3_full,
426 full => sample_f3_full,
427 empty => sample_f3_empty);
427 empty => sample_f3_empty);
428
428
429
429
430
430
431 END tb;
431 END tb;
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@@ -1,49 +1,49
1
1
2 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/general_purpose.vhd
2 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/general_purpose.vhd
3 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/SYNC_FF.vhd
3 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/SYNC_FF.vhd
4 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MUXN.vhd
4 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MUXN.vhd
5 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MUX2.vhd
5 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MUX2.vhd
6 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/REG.vhd
6 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/REG.vhd
7 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC.vhd
7 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC.vhd
8 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_CONTROLER.vhd
8 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_CONTROLER.vhd
9 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_REG.vhd
9 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_REG.vhd
10 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_MUX.vhd
10 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_MUX.vhd
11 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_MUX2.vhd
11 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_MUX2.vhd
12 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/Shifter.vhd
12 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/Shifter.vhd
13 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MULTIPLIER.vhd
13 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MULTIPLIER.vhd
14 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ADDER.vhd
14 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ADDER.vhd
15 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ALU.vhd
15 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ALU.vhd
16 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ADDRcntr.vhd
16 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ADDRcntr.vhd
17
17
18 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/iir_filter.vhd
18 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/iir_filter.vhd
19 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/FILTERcfg.vhd
19 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/FILTERcfg.vhd
20 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CEL.vhd
20 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CEL.vhd
21 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR2.vhd
21 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR2.vhd
22 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR.vhd
22 #vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR.vhd
23
23
24 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd
24 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd
25 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd
25 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd
26 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd
26 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd
27 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd
27 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd
28
28
29 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lpp_memory.vhd
29 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lpp_memory.vhd
30 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lpp_FIFO.vhd
30 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lpp_FIFO.vhd
31 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lppFIFOxN.vhd
31 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lppFIFOxN.vhd
32
32
33 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/lpp_downsampling/Downsampling.vhd
33 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/lpp_downsampling/Downsampling.vhd
34
34
35 vcom -quiet -93 -work lpp e:/opt/tortoiseHG_vhdlib/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd
35 vcom -quiet -93 -work lpp e:/opt/tortoiseHG_vhdlib/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd
36 vcom -quiet -93 -work lpp e:/opt/tortoiseHG_vhdlib/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd
36 vcom -quiet -93 -work lpp e:/opt/tortoiseHG_vhdlib/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd
37
37
38 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/lpp_ad_conv.vhd
38 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/lpp_ad_conv.vhd
39 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/ADS7886_drvr.vhd
39 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/ADS7886_drvr.vhd
40 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/TestModule_ADS7886.vhd
40 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/TestModule_ADS7886.vhd
41
41
42 vcom -quiet -93 -work work Top_Data_Acquisition.vhd
42 vcom -quiet -93 -work work Top_Data_Acquisition.vhd
43 vcom -quiet -93 -work work TB_Data_Acquisition.vhd
43 vcom -quiet -93 -work work TB_Data_Acquisition.vhd
44
44
45 #vsim work.TB_Data_Acquisition
45 #vsim work.TB_Data_Acquisition
46
46
47 #log -r *
47 #log -r *
48 #do wave_data_acquisition.do
48 #do wave_data_acquisition.do
49 #run 5 ms No newline at end of file
49 #run 5 ms
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@@ -1,156 +1,156
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.numeric_std.all;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
24 use IEEE.std_logic_1164.all;
25
25
26
26
27 package FILTERcfg is
27 package FILTERcfg is
28
28
29
29
30
30
31
31
32 --===========================================================|
32 --===========================================================|
33 --========F I L T E R C O N F I G V A L U E S=============|
33 --========F I L T E R C O N F I G V A L U E S=============|
34 --===========================================================|
34 --===========================================================|
35 --____________________________
35 --____________________________
36 --Bus Width and chanels number|
36 --Bus Width and chanels number|
37 --____________________________|
37 --____________________________|
38 constant ChanelsCount : integer := 1;
38 constant ChanelsCount : integer := 1;
39 constant Sample_SZ : integer := 18;
39 constant Sample_SZ : integer := 18;
40 constant Coef_SZ : integer := 9;
40 constant Coef_SZ : integer := 9;
41 constant CoefCntPerCel: integer := 6;
41 constant CoefCntPerCel: integer := 6;
42 constant CoefPerCel: integer := 5;
42 constant CoefPerCel: integer := 5;
43 constant Cels_count : integer := 5;
43 constant Cels_count : integer := 5;
44 constant virgPos : integer := 7;
44 constant virgPos : integer := 7;
45 constant Mem_use : integer := 1;
45 constant Mem_use : integer := 1;
46
46
47
47
48
48
49 --============================================================
49 --============================================================
50 -- create each initial values for each coefs ============
50 -- create each initial values for each coefs ============
51 --!!!!!!!!!!It should be interfaced with a software !!!!!!!!!!
51 --!!!!!!!!!!It should be interfaced with a software !!!!!!!!!!
52 --============================================================
52 --============================================================
53 constant b0_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(58,Coef_SZ));
53 constant b0_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(58,Coef_SZ));
54 constant b0_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-66,Coef_SZ));
54 constant b0_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-66,Coef_SZ));
55 constant b0_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(58,Coef_SZ));
55 constant b0_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(58,Coef_SZ));
56
56
57 constant b1_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(58,Coef_SZ));
57 constant b1_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(58,Coef_SZ));
58 constant b1_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-57,Coef_SZ));
58 constant b1_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-57,Coef_SZ));
59 constant b1_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(58,Coef_SZ));
59 constant b1_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(58,Coef_SZ));
60
60
61 constant b2_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(29,Coef_SZ));
61 constant b2_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(29,Coef_SZ));
62 constant b2_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-17,Coef_SZ));
62 constant b2_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-17,Coef_SZ));
63 constant b2_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(29,Coef_SZ));
63 constant b2_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(29,Coef_SZ));
64
64
65 constant b3_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(15,Coef_SZ));
65 constant b3_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(15,Coef_SZ));
66 constant b3_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(4,Coef_SZ));
66 constant b3_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(4,Coef_SZ));
67 constant b3_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(15,Coef_SZ));
67 constant b3_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(15,Coef_SZ));
68
68
69 constant b4_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(15,Coef_SZ));
69 constant b4_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(15,Coef_SZ));
70 constant b4_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(24,Coef_SZ));
70 constant b4_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(24,Coef_SZ));
71 constant b4_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(15,Coef_SZ));
71 constant b4_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(15,Coef_SZ));
72
72
73 --constant b5_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-81,Coef_SZ));
73 --constant b5_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-81,Coef_SZ));
74 --constant b5_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-153,Coef_SZ));
74 --constant b5_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-153,Coef_SZ));
75 --constant b5_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-171,Coef_SZ));
75 --constant b5_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-171,Coef_SZ));
76
76
77 --constant b6_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-144,Coef_SZ));
77 --constant b6_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-144,Coef_SZ));
78 --constant b6_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-72,Coef_SZ));
78 --constant b6_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-72,Coef_SZ));
79 --constant b6_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-25,Coef_SZ));
79 --constant b6_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-25,Coef_SZ));
80
80
81
81
82 constant a0_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
82 constant a0_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
83 constant a0_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(189,Coef_SZ));
83 constant a0_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(189,Coef_SZ));
84 constant a0_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-111,Coef_SZ));
84 constant a0_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-111,Coef_SZ));
85
85
86 constant a1_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
86 constant a1_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
87 constant a1_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(162,Coef_SZ));
87 constant a1_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(162,Coef_SZ));
88 constant a1_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-81,Coef_SZ));
88 constant a1_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-81,Coef_SZ));
89
89
90 constant a2_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
90 constant a2_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
91 constant a2_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(136,Coef_SZ));
91 constant a2_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(136,Coef_SZ));
92 constant a2_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-55,Coef_SZ));
92 constant a2_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-55,Coef_SZ));
93
93
94 constant a3_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
94 constant a3_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
95 constant a3_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(114,Coef_SZ));
95 constant a3_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(114,Coef_SZ));
96 constant a3_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-33,Coef_SZ));
96 constant a3_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-33,Coef_SZ));
97
97
98 constant a4_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
98 constant a4_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
99 constant a4_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(100,Coef_SZ));
99 constant a4_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(100,Coef_SZ));
100 constant a4_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-20,Coef_SZ));
100 constant a4_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-20,Coef_SZ));
101
101
102 --constant a5_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(60,Coef_SZ));
102 --constant a5_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(60,Coef_SZ));
103 --constant a5_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
103 --constant a5_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
104 --constant a5_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(87,Coef_SZ));
104 --constant a5_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(87,Coef_SZ));
105 --constant a6_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(60,Coef_SZ));
105 --constant a6_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(60,Coef_SZ));
106 --constant a6_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
106 --constant a6_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
107 --constant a6_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(87,Coef_SZ));
107 --constant a6_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(87,Coef_SZ));
108
108
109 constant CoefsInitValCst : std_logic_vector((Cels_count*CoefCntPerCel*Coef_SZ)-1 downto 0) := (a4_2 & a4_1 & a4_0 & b4_2 & b4_1 & b4_0 & a3_2 & a3_1 & a3_0 & b3_2 & b3_1 & b3_0 & a2_2 & a2_1 & a2_0 & b2_2 & b2_1 & b2_0 & a1_2 & a1_1 & a1_0 & b1_2 & b1_1 & b1_0 & a0_2 & a0_1 & a0_0 & b0_2 & b0_1 & b0_0);
109 constant CoefsInitValCst : std_logic_vector((Cels_count*CoefCntPerCel*Coef_SZ)-1 downto 0) := (a4_2 & a4_1 & a4_0 & b4_2 & b4_1 & b4_0 & a3_2 & a3_1 & a3_0 & b3_2 & b3_1 & b3_0 & a2_2 & a2_1 & a2_0 & b2_2 & b2_1 & b2_0 & a1_2 & a1_1 & a1_0 & b1_2 & b1_1 & b1_0 & a0_2 & a0_1 & a0_0 & b0_2 & b0_1 & b0_0);
110
110
111 constant CoefsInitValCst_JC : std_logic_vector((Cels_count*CoefPerCel*Coef_SZ)-1 downto 0) :=
111 constant CoefsInitValCst_v2 : std_logic_vector((Cels_count*CoefPerCel*Coef_SZ)-1 downto 0) :=
112 (a4_1 & a4_2 & b4_0 & b4_1 & b4_2 &
112 (a4_1 & a4_2 & b4_0 & b4_1 & b4_2 &
113 a3_1 & a3_2 & b3_0 & b3_1 & b3_2 &
113 a3_1 & a3_2 & b3_0 & b3_1 & b3_2 &
114 a2_1 & a2_2 & b2_0 & b2_1 & b2_2 &
114 a2_1 & a2_2 & b2_0 & b2_1 & b2_2 &
115 a1_1 & a1_2 & b1_0 & b1_1 & b1_2 &
115 a1_1 & a1_2 & b1_0 & b1_1 & b1_2 &
116 a0_1 & a0_2 & b0_0 & b0_1 & b0_2 );
116 a0_1 & a0_2 & b0_0 & b0_1 & b0_2 );
117
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118
119 end;
119 end;
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Show file before | Show file after | Hide comments
@@ -1,193 +1,197
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 -- MODIFIED by Jean-christophe PELLION
22 -- MODIFIED by Jean-christophe PELLION
23 -- jean-christophe.pellion@lpp.polytechnique.fr
23 -- jean-christophe.pellion@lpp.polytechnique.fr
24 -------------------------------------------------------------------------------
24 -------------------------------------------------------------------------------
25 LIBRARY IEEE;
25 LIBRARY IEEE;
26 USE IEEE.STD_LOGIC_1164.ALL;
26 USE IEEE.STD_LOGIC_1164.ALL;
27 LIBRARY lpp;
27 LIBRARY lpp;
28 USE lpp.lpp_ad_conv.ALL;
28 USE lpp.lpp_ad_conv.ALL;
29 USE lpp.general_purpose.SYNC_FF;
29 USE lpp.general_purpose.SYNC_FF;
30
30
31 ENTITY ADS7886_drvr IS
31 ENTITY ADS7886_drvr IS
32 GENERIC(
32 GENERIC(
33 ChanelCount : INTEGER;
33 ChanelCount : INTEGER;
34 ncycle_cnv_high : INTEGER := 79;
34 ncycle_cnv_high : INTEGER := 79;
35 ncycle_cnv : INTEGER := 500);
35 ncycle_cnv : INTEGER := 500);
36 PORT (
36 PORT (
37 -- CONV --
37 -- CONV --
38 cnv_clk : IN STD_LOGIC;
38 cnv_clk : IN STD_LOGIC;
39 cnv_rstn : IN STD_LOGIC;
39 cnv_rstn : IN STD_LOGIC;
40 cnv_run : IN STD_LOGIC;
40 cnv_run : IN STD_LOGIC;
41 cnv : OUT STD_LOGIC;
41 cnv : OUT STD_LOGIC;
42
42
43 -- DATA --
43 -- DATA --
44 clk : IN STD_LOGIC;
44 clk : IN STD_LOGIC;
45 rstn : IN STD_LOGIC;
45 rstn : IN STD_LOGIC;
46 sck : OUT STD_LOGIC;
46 sck : OUT STD_LOGIC;
47 sdo : IN STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
47 sdo : IN STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
48
48
49 sample : OUT Samples(ChanelCount-1 DOWNTO 0);
49 sample : OUT Samples(ChanelCount-1 DOWNTO 0);
50 sample_val : OUT STD_LOGIC
50 sample_val : OUT STD_LOGIC
51 );
51 );
52 END ADS7886_drvr;
52 END ADS7886_drvr;
53
53
54 ARCHITECTURE ar_ADS7886_drvr OF ADS7886_drvr IS
54 ARCHITECTURE ar_ADS7886_drvr OF ADS7886_drvr IS
55
55
56 COMPONENT SYNC_FF
56 COMPONENT SYNC_FF
57 GENERIC (
57 GENERIC (
58 NB_FF_OF_SYNC : INTEGER);
58 NB_FF_OF_SYNC : INTEGER);
59 PORT (
59 PORT (
60 clk : IN STD_LOGIC;
60 clk : IN STD_LOGIC;
61 rstn : IN STD_LOGIC;
61 rstn : IN STD_LOGIC;
62 A : IN STD_LOGIC;
62 A : IN STD_LOGIC;
63 A_sync : OUT STD_LOGIC);
63 A_sync : OUT STD_LOGIC);
64 END COMPONENT;
64 END COMPONENT;
65
65
66
66
67 SIGNAL cnv_cycle_counter : INTEGER;
67 SIGNAL cnv_cycle_counter : INTEGER;
68 SIGNAL cnv_s : STD_LOGIC;
68 SIGNAL cnv_s : STD_LOGIC;
69 SIGNAL cnv_sync : STD_LOGIC;
69 SIGNAL cnv_sync : STD_LOGIC;
70 SIGNAL cnv_sync_r : STD_LOGIC;
70 SIGNAL cnv_sync_r : STD_LOGIC;
71 SIGNAL cnv_done : STD_LOGIC;
71 SIGNAL cnv_done : STD_LOGIC;
72 SIGNAL sample_bit_counter : INTEGER;
72 SIGNAL sample_bit_counter : INTEGER;
73 SIGNAL shift_reg : Samples(ChanelCount-1 DOWNTO 0);
73 SIGNAL shift_reg : Samples(ChanelCount-1 DOWNTO 0);
74
74
75 SIGNAL cnv_run_sync : STD_LOGIC;
75 SIGNAL cnv_run_sync : STD_LOGIC;
76
76
77 BEGIN
77 BEGIN
78 -----------------------------------------------------------------------------
78 -----------------------------------------------------------------------------
79 -- CONV
79 -- CONV
80 -----------------------------------------------------------------------------
80 -----------------------------------------------------------------------------
81 PROCESS (cnv_clk, cnv_rstn)
81 PROCESS (cnv_clk, cnv_rstn)
82 BEGIN -- PROCESS
82 BEGIN -- PROCESS
83 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
83 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
84 cnv_cycle_counter <= 0;
84 cnv_cycle_counter <= 0;
85 cnv_s <= '0';
85 cnv_s <= '0';
86 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
86 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
87 IF cnv_run = '1' THEN
87 IF cnv_run = '1' THEN
88 IF cnv_cycle_counter < ncycle_cnv THEN
88 IF cnv_cycle_counter < ncycle_cnv THEN
89 cnv_cycle_counter <= cnv_cycle_counter +1;
89 cnv_cycle_counter <= cnv_cycle_counter +1;
90 IF cnv_cycle_counter < ncycle_cnv_high THEN
90 IF cnv_cycle_counter < ncycle_cnv_high THEN
91 cnv_s <= '1';
91 cnv_s <= '1';
92 ELSE
92 ELSE
93 cnv_s <= '0';
93 cnv_s <= '0';
94 END IF;
94 END IF;
95 ELSE
95 ELSE
96 cnv_s <= '1';
96 cnv_s <= '1';
97 cnv_cycle_counter <= 0;
97 cnv_cycle_counter <= 0;
98 END IF;
98 END IF;
99 ELSE
99 ELSE
100 cnv_s <= '0';
100 cnv_s <= '0';
101 cnv_cycle_counter <= 0;
101 cnv_cycle_counter <= 0;
102 END IF;
102 END IF;
103 END IF;
103 END IF;
104 END PROCESS;
104 END PROCESS;
105
105
106 cnv <= cnv_s;
106 cnv <= cnv_s;
107
107
108 -----------------------------------------------------------------------------
108 -----------------------------------------------------------------------------
109
109
110
110
111 -----------------------------------------------------------------------------
111 -----------------------------------------------------------------------------
112 -- SYNC CNV
112 -- SYNC CNV
113 -----------------------------------------------------------------------------
113 -----------------------------------------------------------------------------
114
114
115 SYNC_FF_cnv : SYNC_FF
115 SYNC_FF_cnv : SYNC_FF
116 GENERIC MAP (
116 GENERIC MAP (
117 NB_FF_OF_SYNC => 2)
117 NB_FF_OF_SYNC => 2)
118 PORT MAP (
118 PORT MAP (
119 clk => clk,
119 clk => clk,
120 rstn => rstn,
120 rstn => rstn,
121 A => cnv_s,
121 A => cnv_s,
122 A_sync => cnv_sync);
122 A_sync => cnv_sync);
123
123
124 PROCESS (clk, rstn)
124 PROCESS (clk, rstn)
125 BEGIN
125 BEGIN
126 IF rstn = '0' THEN
126 IF rstn = '0' THEN
127 cnv_sync_r <= '0';
127 cnv_sync_r <= '0';
128 cnv_done <= '0';
128 cnv_done <= '0';
129 ELSIF clk'EVENT AND clk = '1' THEN
129 ELSIF clk'EVENT AND clk = '1' THEN
130 cnv_sync_r <= cnv_sync;
130 cnv_sync_r <= cnv_sync;
131 cnv_done <= (NOT cnv_sync) AND cnv_sync_r;
131 cnv_done <= (NOT cnv_sync) AND cnv_sync_r;
132 END IF;
132 END IF;
133 END PROCESS;
133 END PROCESS;
134
134
135 -----------------------------------------------------------------------------
135 -----------------------------------------------------------------------------
136
136
137 SYNC_FF_run : SYNC_FF
137 SYNC_FF_run : SYNC_FF
138 GENERIC MAP (
138 GENERIC MAP (
139 NB_FF_OF_SYNC => 2)
139 NB_FF_OF_SYNC => 2)
140 PORT MAP (
140 PORT MAP (
141 clk => clk,
141 clk => clk,
142 rstn => rstn,
142 rstn => rstn,
143 A => cnv_run,
143 A => cnv_run,
144 A_sync => cnv_run_sync);
144 A_sync => cnv_run_sync);
145
145
146
146
147
147
148 -----------------------------------------------------------------------------
148 -----------------------------------------------------------------------------
149 -- DATA
149 -- DATA
150 -----------------------------------------------------------------------------
150 -----------------------------------------------------------------------------
151 PROCESS (clk, rstn)
151 PROCESS (clk, rstn)
152 BEGIN -- PROCESS
152 BEGIN -- PROCESS
153 IF rstn = '0' THEN
153 IF rstn = '0' THEN
154 FOR l IN 0 TO ChanelCount-1 LOOP
154 FOR l IN 0 TO ChanelCount-1 LOOP
155 shift_reg(l) <= (OTHERS => '0');
155 shift_reg(l) <= (OTHERS => '0');
156 END LOOP;
156 END LOOP;
157 sample_bit_counter <= 0;
157 sample_bit_counter <= 0;
158 sample_val <= '0';
158 sample_val <= '0';
159 SCK <= '1';
159 SCK <= '1';
160 ELSIF clk'EVENT AND clk = '1' THEN
160 ELSIF clk'EVENT AND clk = '1' THEN
161
161
162 IF cnv_run_sync = '0' THEN
162 IF cnv_run_sync = '0' THEN
163 sample_bit_counter <= 0;
163 sample_bit_counter <= 0;
164 ELSIF cnv_done = '1' THEN
164 ELSIF cnv_done = '1' THEN
165 sample_bit_counter <= 1;
165 sample_bit_counter <= 1;
166 ELSIF sample_bit_counter > 0 AND sample_bit_counter < 32 THEN
166 ELSIF sample_bit_counter > 0 AND sample_bit_counter < 32 THEN
167 sample_bit_counter <= sample_bit_counter + 1;
167 sample_bit_counter <= sample_bit_counter + 1;
168 END IF;
168 END IF;
169
169
170 IF (sample_bit_counter MOD 2) = 1 THEN
170 IF (sample_bit_counter MOD 2) = 1 THEN
171 FOR l IN 0 TO ChanelCount-1 LOOP
171 FOR l IN 0 TO ChanelCount-1 LOOP
172 shift_reg(l)(15) <= sdo(l);
172 --shift_reg(l)(15) <= sdo(l);
173 shift_reg(l)(14 DOWNTO 0) <= shift_reg(l)(15 DOWNTO 1);
173 --shift_reg(l)(14 DOWNTO 0) <= shift_reg(l)(15 DOWNTO 1);
174 shift_reg(l)(0) <= sdo(l);
175 shift_reg(l)(15 DOWNTO 1) <= shift_reg(l)(14 DOWNTO 0);
174 END LOOP;
176 END LOOP;
175 SCK <= '0';
177 SCK <= '0';
176 ELSE
178 ELSE
177 SCK <= '1';
179 SCK <= '1';
178 END IF;
180 END IF;
179
181
180 IF sample_bit_counter = 31 THEN
182 IF sample_bit_counter = 31 THEN
181 sample_val <= '1';
183 sample_val <= '1';
182 FOR l IN 0 TO ChanelCount-1 LOOP
184 FOR l IN 0 TO ChanelCount-1 LOOP
183 sample(l)(15) <= sdo(l);
185 --sample(l)(15) <= sdo(l);
184 sample(l)(14 DOWNTO 0) <= shift_reg(l)(15 DOWNTO 1);
186 --sample(l)(14 DOWNTO 0) <= shift_reg(l)(15 DOWNTO 1);
187 sample(l)(0) <= sdo(l);
188 sample(l)(15 DOWNTO 1) <= shift_reg(l)(14 DOWNTO 0);
185 END LOOP;
189 END LOOP;
186 ELSE
190 ELSE
187 sample_val <= '0';
191 sample_val <= '0';
188 END IF;
192 END IF;
189 END IF;
193 END IF;
190 END PROCESS;
194 END PROCESS;
191
195
192 END ar_ADS7886_drvr;
196 END ar_ADS7886_drvr;
193
197
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@@ -1,318 +1,411
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 LIBRARY grlib;
3 LIBRARY grlib;
4 USE grlib.amba.ALL;
4 USE grlib.amba.ALL;
5 USE grlib.stdlib.ALL;
5 USE grlib.stdlib.ALL;
6 USE grlib.devices.ALL;
6 USE grlib.devices.ALL;
7 USE GRLIB.DMA2AHB_Package.ALL;
7 USE GRLIB.DMA2AHB_Package.ALL;
8 LIBRARY lpp;
8 LIBRARY lpp;
9 USE lpp.lpp_ad_conv.ALL;
9 USE lpp.lpp_ad_conv.ALL;
10 USE lpp.iir_filter.ALL;
10 USE lpp.iir_filter.ALL;
11 USE lpp.FILTERcfg.ALL;
11 USE lpp.FILTERcfg.ALL;
12 USE lpp.lpp_memory.ALL;
12 USE lpp.lpp_memory.ALL;
13 USE lpp.lpp_top_lfr_pkg.ALL;
13 USE lpp.lpp_top_lfr_pkg.ALL;
14 USE lpp.lpp_dma_pkg.ALL;
14 USE lpp.lpp_dma_pkg.ALL;
15 USE lpp.lpp_demux.ALL;
16 USE lpp.lpp_fft.ALL;
17 use lpp.lpp_matrix.all;
15 LIBRARY techmap;
18 LIBRARY techmap;
16 USE techmap.gencomp.ALL;
19 USE techmap.gencomp.ALL;
17
20
18 ENTITY lpp_top_lfr IS
21 ENTITY lpp_top_lfr IS
19 GENERIC(
22 GENERIC(
20 tech : INTEGER := 0;
23 tech : INTEGER := 0;
21 hindex_SpectralMatrix : INTEGER := 2;
24 hindex_SpectralMatrix : INTEGER := 2;
22 pindex : INTEGER := 4;
25 pindex : INTEGER := 4;
23 paddr : INTEGER := 4;
26 paddr : INTEGER := 4;
24 pmask : INTEGER := 16#fff#;
27 pmask : INTEGER := 16#fff#;
25 pirq : INTEGER := 0
28 pirq : INTEGER := 0
26 );
29 );
27 PORT (
30 PORT (
28 -- ADS7886
31 -- ADS7886
29 cnv_run : IN STD_LOGIC;
32 cnv_run : IN STD_LOGIC;
30 cnv : OUT STD_LOGIC;
33 cnv : OUT STD_LOGIC;
31 sck : OUT STD_LOGIC;
34 sck : OUT STD_LOGIC;
32 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
35 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
33 --
36 --
34 cnv_clk : IN STD_LOGIC; -- 49 MHz
37 cnv_clk : IN STD_LOGIC; -- 49 MHz
35 cnv_rstn : IN STD_LOGIC;
38 cnv_rstn : IN STD_LOGIC;
36 --
39 --
37 clk : IN STD_LOGIC; -- 25 MHz
40 clk : IN STD_LOGIC; -- 25 MHz
38 rstn : IN STD_LOGIC;
41 rstn : IN STD_LOGIC;
39 --
42 --
40 apbi : IN apb_slv_in_type;
43 apbi : IN apb_slv_in_type;
41 apbo : OUT apb_slv_out_type;
44 apbo : OUT apb_slv_out_type;
42
45
43 -- AMBA AHB Master Interface
46 -- AMBA AHB Master Interface
44 AHB_DMA_SpectralMatrix_In : IN AHB_Mst_In_Type;
47 AHB_DMA_SpectralMatrix_In : IN AHB_Mst_In_Type;
45 AHB_DMA_SpectralMatrix_Out : OUT AHB_Mst_Out_Type
48 AHB_DMA_SpectralMatrix_Out : OUT AHB_Mst_Out_Type
46 );
49 );
47 END lpp_top_lfr;
50 END lpp_top_lfr;
48
51
49 ARCHITECTURE tb OF lpp_top_lfr IS
52 ARCHITECTURE tb OF lpp_top_lfr IS
50
53
51 -----------------------------------------------------------------------------
54 -----------------------------------------------------------------------------
52 -- f0
55 -- f0
53 SIGNAL sample_f0_0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
56 SIGNAL sample_f0_0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
54 SIGNAL sample_f0_1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
57 SIGNAL sample_f0_1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
55 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
58 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
56 --
59 --
57 SIGNAL sample_f0_0_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
60 SIGNAL sample_f0_0_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
58 SIGNAL sample_f0_0_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
61 SIGNAL sample_f0_0_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
59 SIGNAL sample_f0_0_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
62 SIGNAL sample_f0_0_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
60 SIGNAL sample_f0_0_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
63 SIGNAL sample_f0_0_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
61 --
64 --
62 SIGNAL sample_f0_1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
65 SIGNAL sample_f0_1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
63 SIGNAL sample_f0_1_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
66 SIGNAL sample_f0_1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
64 SIGNAL sample_f0_1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
67 SIGNAL sample_f0_1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
65 SIGNAL sample_f0_1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
68 SIGNAL sample_f0_1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
66 -----------------------------------------------------------------------------
69 -----------------------------------------------------------------------------
67 -- f1
70 -- f1
68 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
71 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
69 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
72 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
70 --
73 --
71 SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
74 SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
72 SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
75 SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
73 SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
76 SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
74 SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
77 SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
75 -----------------------------------------------------------------------------
78 -----------------------------------------------------------------------------
76 -- f2
79 -- f2
77 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
80 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
78 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
81 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
79 -----------------------------------------------------------------------------
82 -----------------------------------------------------------------------------
80 -- f3
83 -- f3
81 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
84 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
82 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
85 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
83 --
86 --
84 SIGNAL sample_f3_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
87 SIGNAL sample_f3_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
85 SIGNAL sample_f3_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
88 SIGNAL sample_f3_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
86 SIGNAL sample_f3_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
89 SIGNAL sample_f3_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
87 SIGNAL sample_f3_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
90 SIGNAL sample_f3_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
88 -----------------------------------------------------------------------------
91 -----------------------------------------------------------------------------
89
92
90 -----------------------------------------------------------------------------
93 -----------------------------------------------------------------------------
91 -- SPECTRAL MATRIX
94 -- SPECTRAL MATRIX
92 -----------------------------------------------------------------------------
95 -----------------------------------------------------------------------------
96 SIGNAL sample_ren : STD_LOGIC_VECTOR(19 DOWNTO 0);
97
98 SIGNAL demux_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
99 SIGNAL demux_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
100 SIGNAL demux_data : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
101
102 SIGNAL fft_fifo_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
103 SIGNAL fft_fifo_data : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
104 SIGNAL fft_fifo_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
105 SIGNAL fft_fifo_reuse : STD_LOGIC_VECTOR(4 DOWNTO 0);
106
107 SIGNAL SP_fifo_data : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
108 SIGNAL SP_fifo_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
109
93 SIGNAL fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
110 SIGNAL fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
94 SIGNAL fifo_empty : STD_LOGIC;
111 SIGNAL fifo_empty : STD_LOGIC;
95 SIGNAL fifo_ren : STD_LOGIC;
112 SIGNAL fifo_ren : STD_LOGIC;
96 SIGNAL header : STD_LOGIC_VECTOR(31 DOWNTO 0);
113 SIGNAL header : STD_LOGIC_VECTOR(31 DOWNTO 0);
97 SIGNAL header_val : STD_LOGIC;
114 SIGNAL header_val : STD_LOGIC;
98 SIGNAL header_ack : STD_LOGIC;
115 SIGNAL header_ack : STD_LOGIC;
99
116
100 -----------------------------------------------------------------------------
117 -----------------------------------------------------------------------------
101 -- APB REG
118 -- APB REG
102 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
103 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
120 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
104 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
121 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
105 SIGNAL ready_matrix_f1 : STD_LOGIC;
122 SIGNAL ready_matrix_f1 : STD_LOGIC;
106 SIGNAL ready_matrix_f2 : STD_LOGIC;
123 SIGNAL ready_matrix_f2 : STD_LOGIC;
107 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
124 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
108 SIGNAL error_bad_component_error : STD_LOGIC;
125 SIGNAL error_bad_component_error : STD_LOGIC;
109 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
126 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
110 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
127 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
111 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
128 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
112 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
129 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
113 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
130 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
114 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
131 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
115 SIGNAL status_error_bad_component_error : STD_LOGIC;
132 SIGNAL status_error_bad_component_error : STD_LOGIC;
116 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
133 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
117 SIGNAL config_active_interruption_onError : STD_LOGIC;
134 SIGNAL config_active_interruption_onError : STD_LOGIC;
118 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
135 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
119 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
136 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
137 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
138 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
122
139
123 BEGIN
140 BEGIN
124
141
125 -----------------------------------------------------------------------------
142 -----------------------------------------------------------------------------
126 -- CNA + FILTER
143 -- CNA + FILTER
127 -----------------------------------------------------------------------------
144 -----------------------------------------------------------------------------
128 lpp_top_acq_1 : lpp_top_acq
145 lpp_top_acq_1 : lpp_top_acq
129 GENERIC MAP (
146 GENERIC MAP (
130 tech => tech)
147 tech => tech)
131 PORT MAP (
148 PORT MAP (
132 cnv_run => cnv_run,
149 cnv_run => cnv_run,
133 cnv => cnv,
150 cnv => cnv,
134 sck => sck,
151 sck => sck,
135 sdo => sdo,
152 sdo => sdo,
136 cnv_clk => cnv_clk,
153 cnv_clk => cnv_clk,
137 cnv_rstn => cnv_rstn,
154 cnv_rstn => cnv_rstn,
138 clk => clk,
155 clk => clk,
139 rstn => rstn,
156 rstn => rstn,
140
157
141 sample_f0_0_wen => sample_f0_0_wen,
158 sample_f0_0_wen => sample_f0_0_wen,
142 sample_f0_1_wen => sample_f0_1_wen,
159 sample_f0_1_wen => sample_f0_1_wen,
143 sample_f0_wdata => sample_f0_wdata,
160 sample_f0_wdata => sample_f0_wdata,
144 sample_f1_wen => sample_f1_wen,
161 sample_f1_wen => sample_f1_wen,
145 sample_f1_wdata => sample_f1_wdata,
162 sample_f1_wdata => sample_f1_wdata,
146 sample_f2_wen => sample_f2_wen,
163 sample_f2_wen => sample_f2_wen,
147 sample_f2_wdata => sample_f2_wdata,
164 sample_f2_wdata => sample_f2_wdata,
148 sample_f3_wen => sample_f3_wen,
165 sample_f3_wen => sample_f3_wen,
149 sample_f3_wdata => sample_f3_wdata);
166 sample_f3_wdata => sample_f3_wdata);
150
167
151 -----------------------------------------------------------------------------
168 -----------------------------------------------------------------------------
152 -- FIFO
169 -- FIFO
153 -----------------------------------------------------------------------------
170 -----------------------------------------------------------------------------
154
171
155 lppFIFO_f0_0 : lppFIFOxN
172 lppFIFO_f0_0 : lppFIFOxN
156 GENERIC MAP (
173 GENERIC MAP (
157 tech => tech,
174 tech => tech,
158 Data_sz => 18,
175 Data_sz => 16,
159 FifoCnt => 5,
176 FifoCnt => 5,
160 Enable_ReUse => '0')
177 Enable_ReUse => '0')
161 PORT MAP (
178 PORT MAP (
162 rst => rstn,
179 rst => rstn,
163 wclk => clk,
180 wclk => clk,
164 rclk => clk,
181 rclk => clk,
165 ReUse => (OTHERS => '0'),
182 ReUse => (OTHERS => '0'),
166
183
167 wen => sample_f0_0_wen,
184 wen => sample_f0_0_wen,
168 ren => sample_f0_0_ren,
185 ren => sample_f0_0_ren,
169 wdata => sample_f0_wdata,
186 wdata => sample_f0_wdata,
170 rdata => sample_f0_0_rdata,
187 rdata => sample_f0_0_rdata,
171 full => sample_f0_0_full,
188 full => sample_f0_0_full,
172 empty => sample_f0_0_empty);
189 empty => sample_f0_0_empty);
173
190
174 lppFIFO_f0_1 : lppFIFOxN
191 lppFIFO_f0_1 : lppFIFOxN
175 GENERIC MAP (
192 GENERIC MAP (
176 tech => tech,
193 tech => tech,
177 Data_sz => 18,
194 Data_sz => 16,
178 FifoCnt => 5,
195 FifoCnt => 5,
179 Enable_ReUse => '0')
196 Enable_ReUse => '0')
180 PORT MAP (
197 PORT MAP (
181 rst => rstn,
198 rst => rstn,
182 wclk => clk,
199 wclk => clk,
183 rclk => clk,
200 rclk => clk,
184 ReUse => (OTHERS => '0'),
201 ReUse => (OTHERS => '0'),
185
202
186 wen => sample_f0_1_wen,
203 wen => sample_f0_1_wen,
187 ren => sample_f0_1_ren,
204 ren => sample_f0_1_ren,
188 wdata => sample_f0_wdata,
205 wdata => sample_f0_wdata,
189 rdata => sample_f0_1_rdata,
206 rdata => sample_f0_1_rdata,
190 full => sample_f0_1_full,
207 full => sample_f0_1_full,
191 empty => sample_f0_1_empty);
208 empty => sample_f0_1_empty);
192
209
193 lppFIFO_f1 : lppFIFOxN
210 lppFIFO_f1 : lppFIFOxN
194 GENERIC MAP (
211 GENERIC MAP (
195 tech => tech,
212 tech => tech,
196 Data_sz => 18,
213 Data_sz => 16,
197 FifoCnt => 5,
214 FifoCnt => 5,
198 Enable_ReUse => '0')
215 Enable_ReUse => '0')
199 PORT MAP (
216 PORT MAP (
200 rst => rstn,
217 rst => rstn,
201 wclk => clk,
218 wclk => clk,
202 rclk => clk,
219 rclk => clk,
203 ReUse => (OTHERS => '0'),
220 ReUse => (OTHERS => '0'),
204
221
205 wen => sample_f1_wen,
222 wen => sample_f1_wen,
206 ren => sample_f1_ren,
223 ren => sample_f1_ren,
207 wdata => sample_f1_wdata,
224 wdata => sample_f1_wdata,
208 rdata => sample_f1_rdata,
225 rdata => sample_f1_rdata,
209 full => sample_f1_full,
226 full => sample_f1_full,
210 empty => sample_f1_empty);
227 empty => sample_f1_empty);
211
228
212 lppFIFO_f3 : lppFIFOxN
229 lppFIFO_f3 : lppFIFOxN
213 GENERIC MAP (
230 GENERIC MAP (
214 tech => tech,
231 tech => tech,
215 Data_sz => 18,
232 Data_sz => 16,
216 FifoCnt => 5,
233 FifoCnt => 5,
217 Enable_ReUse => '0')
234 Enable_ReUse => '0')
218 PORT MAP (
235 PORT MAP (
219 rst => rstn,
236 rst => rstn,
220 wclk => clk,
237 wclk => clk,
221 rclk => clk,
238 rclk => clk,
222 ReUse => (OTHERS => '0'),
239 ReUse => (OTHERS => '0'),
223
240
224 wen => sample_f3_wen,
241 wen => sample_f3_wen,
225 ren => sample_f3_ren,
242 ren => sample_f3_ren,
226 wdata => sample_f3_wdata,
243 wdata => sample_f3_wdata,
227 rdata => sample_f3_rdata,
244 rdata => sample_f3_rdata,
228 full => sample_f3_full,
245 full => sample_f3_full,
229 empty => sample_f3_empty);
246 empty => sample_f3_empty);
230
247
231 -----------------------------------------------------------------------------
248 -----------------------------------------------------------------------------
232 -- SPECTRAL MATRIX
249 -- SPECTRAL MATRIX
233 -----------------------------------------------------------------------------
250 -----------------------------------------------------------------------------
251 sample_f0_0_ren <= sample_ren(4 DOWNTO 0);
252 sample_f0_1_ren <= sample_ren(9 DOWNTO 5);
253 sample_f1_ren <= sample_ren(14 DOWNTO 10);
254 sample_f3_ren <= sample_ren(19 DOWNTO 15);
255
256 Demultiplex_1 : Demultiplex
257 GENERIC MAP (
258 Data_sz => 16)
259 PORT MAP (
260 clk => clk,
261 rstn => rstn,
262
263 Read => demux_ren,
264 EmptyF0a => sample_f0_0_empty,
265 EmptyF0b => sample_f0_0_empty,
266 EmptyF1 => sample_f1_empty,
267 EmptyF2 => sample_f3_empty,
268 DataF0a => sample_f0_0_rdata,
269 DataF0b => sample_f0_1_rdata,
270 DataF1 => sample_f1_rdata,
271 DataF2 => sample_f3_rdata,
272 Read_DEMUX => sample_ren,
273 Empty => demux_empty,
274 Data => demux_data);
275
276 FFT_1 : FFT
277 GENERIC MAP (
278 Data_sz => 16,
279 NbData => 256)
280 PORT MAP (
281 clkm => clk,
282 rstn => rstn,
283 FifoIN_Empty => demux_empty,
284 FifoIN_Data => demux_data,
285 FifoOUT_Full => fft_fifo_full,
286 Read => demux_ren,
287 Write => fft_fifo_wen,
288 ReUse => fft_fifo_reuse,
289 Data => fft_fifo_data);
290
291 lppFIFO_fft : lppFIFOxN
292 GENERIC MAP (
293 tech => tech,
294 Data_sz => 16,
295 FifoCnt => 5,
296 Enable_ReUse => '1')
297 PORT MAP (
298 rst => rstn,
299 wclk => clk,
300 rclk => clk,
301 ReUse => fft_fifo_reuse,
302 wen => fft_fifo_wen,
303 ren => SP_fifo_ren,
304 wdata => fft_fifo_data,
305 rdata => SP_fifo_data,
306 full => fft_fifo_full,
307 empty => OPEN);
308
309 MatriceSpectrale_1: MatriceSpectrale
310 GENERIC MAP (
311 Input_SZ => 16,
312 Result_SZ => 32)
313 PORT MAP (
314 clkm => clk,
315 rstn => rstn,
316
317 FifoIN_Full => fft_fifo_full,
318 FifoOUT_Full => , -- TODO
319 Data_IN => SP_fifo_data,
320 ACQ => , -- TODO
321 FlagError => , -- TODO
322 Pong => , -- TODO
323 Write => , -- TODO
324 Read => SP_fifo_ren,
325 Data_OUT => ); -- TODO
326
234
327
235 -----------------------------------------------------------------------------
328 -----------------------------------------------------------------------------
236 -- DMA SPECTRAL MATRIX
329 -- DMA SPECTRAL MATRIX
237 -----------------------------------------------------------------------------
330 -----------------------------------------------------------------------------
238 lpp_dma_ip_1 : lpp_dma_ip
331 lpp_dma_ip_1 : lpp_dma_ip
239 GENERIC MAP (
332 GENERIC MAP (
240 tech => tech,
333 tech => tech,
241 hindex => hindex_SpectralMatrix)
334 hindex => hindex_SpectralMatrix)
242 PORT MAP (
335 PORT MAP (
243 HCLK => clk,
336 HCLK => clk,
244 HRESETn => rstn,
337 HRESETn => rstn,
245 AHB_Master_In => AHB_DMA_SpectralMatrix_In,
338 AHB_Master_In => AHB_DMA_SpectralMatrix_In,
246 AHB_Master_Out => AHB_DMA_SpectralMatrix_Out,
339 AHB_Master_Out => AHB_DMA_SpectralMatrix_Out,
247
340
248 -- Connect to Spectral Matrix --
341 -- Connect to Spectral Matrix --
249 fifo_data => fifo_data,
342 fifo_data => fifo_data,
250 fifo_empty => fifo_empty,
343 fifo_empty => fifo_empty,
251 fifo_ren => fifo_ren,
344 fifo_ren => fifo_ren,
252 header => header,
345 header => header,
253 header_val => header_val,
346 header_val => header_val,
254 header_ack => header_ack,
347 header_ack => header_ack,
255
348
256 -- APB REG
349 -- APB REG
257
350
258 ready_matrix_f0_0 => ready_matrix_f0_0,
351 ready_matrix_f0_0 => ready_matrix_f0_0,
259 ready_matrix_f0_1 => ready_matrix_f0_1,
352 ready_matrix_f0_1 => ready_matrix_f0_1,
260 ready_matrix_f1 => ready_matrix_f1,
353 ready_matrix_f1 => ready_matrix_f1,
261 ready_matrix_f2 => ready_matrix_f2,
354 ready_matrix_f2 => ready_matrix_f2,
262 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
355 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
263 error_bad_component_error => error_bad_component_error,
356 error_bad_component_error => error_bad_component_error,
264 debug_reg => debug_reg,
357 debug_reg => debug_reg,
265 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
358 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
266 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
359 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
267 status_ready_matrix_f1 => status_ready_matrix_f1,
360 status_ready_matrix_f1 => status_ready_matrix_f1,
268 status_ready_matrix_f2 => status_ready_matrix_f2,
361 status_ready_matrix_f2 => status_ready_matrix_f2,
269 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
362 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
270 status_error_bad_component_error => status_error_bad_component_error,
363 status_error_bad_component_error => status_error_bad_component_error,
271 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
364 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
272 config_active_interruption_onError => config_active_interruption_onError,
365 config_active_interruption_onError => config_active_interruption_onError,
273 addr_matrix_f0_0 => addr_matrix_f0_0,
366 addr_matrix_f0_0 => addr_matrix_f0_0,
274 addr_matrix_f0_1 => addr_matrix_f0_1,
367 addr_matrix_f0_1 => addr_matrix_f0_1,
275 addr_matrix_f1 => addr_matrix_f1,
368 addr_matrix_f1 => addr_matrix_f1,
276 addr_matrix_f2 => addr_matrix_f2);
369 addr_matrix_f2 => addr_matrix_f2);
277
370
278 lpp_top_apbreg_1 : lpp_top_apbreg
371 lpp_top_apbreg_1 : lpp_top_apbreg
279 GENERIC MAP (
372 GENERIC MAP (
280 pindex => pindex,
373 pindex => pindex,
281 paddr => paddr,
374 paddr => paddr,
282 pmask => pmask,
375 pmask => pmask,
283 pirq => pirq)
376 pirq => pirq)
284 PORT MAP (
377 PORT MAP (
285 HCLK => clk,
378 HCLK => clk,
286 HRESETn => rstn,
379 HRESETn => rstn,
287 apbi => apbi,
380 apbi => apbi,
288 apbo => apbo,
381 apbo => apbo,
289
382
290 ready_matrix_f0_0 => ready_matrix_f0_0,
383 ready_matrix_f0_0 => ready_matrix_f0_0,
291 ready_matrix_f0_1 => ready_matrix_f0_1,
384 ready_matrix_f0_1 => ready_matrix_f0_1,
292 ready_matrix_f1 => ready_matrix_f1,
385 ready_matrix_f1 => ready_matrix_f1,
293 ready_matrix_f2 => ready_matrix_f2,
386 ready_matrix_f2 => ready_matrix_f2,
294 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
387 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
295 error_bad_component_error => error_bad_component_error,
388 error_bad_component_error => error_bad_component_error,
296 debug_reg => debug_reg,
389 debug_reg => debug_reg,
297 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
390 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
298 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
391 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
299 status_ready_matrix_f1 => status_ready_matrix_f1,
392 status_ready_matrix_f1 => status_ready_matrix_f1,
300 status_ready_matrix_f2 => status_ready_matrix_f2,
393 status_ready_matrix_f2 => status_ready_matrix_f2,
301 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
394 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
302 status_error_bad_component_error => status_error_bad_component_error,
395 status_error_bad_component_error => status_error_bad_component_error,
303 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
396 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
304 config_active_interruption_onError => config_active_interruption_onError,
397 config_active_interruption_onError => config_active_interruption_onError,
305 addr_matrix_f0_0 => addr_matrix_f0_0,
398 addr_matrix_f0_0 => addr_matrix_f0_0,
306 addr_matrix_f0_1 => addr_matrix_f0_1,
399 addr_matrix_f0_1 => addr_matrix_f0_1,
307 addr_matrix_f1 => addr_matrix_f1,
400 addr_matrix_f1 => addr_matrix_f1,
308 addr_matrix_f2 => addr_matrix_f2);
401 addr_matrix_f2 => addr_matrix_f2);
309
402
310
403
311 --TODO : add the irq alert for DMA matrix transfert ending
404 --TODO : add the irq alert for DMA matrix transfert ending
312 --TODO : add 5 bit register into APB to control the DATA SHIPING
405 --TODO : add 5 bit register into APB to control the DATA SHIPING
313 --TODO : add Spectral Matrix (FFT + SP)
406 --TODO : add Spectral Matrix (FFT + SP)
314 --TODO : add DMA for WaveForms Picker
407 --TODO : add DMA for WaveForms Picker
315 --TODO : add APB Reg to control WaveForms Picker
408 --TODO : add APB Reg to control WaveForms Picker
316 --TODO : add WaveForms Picker
409 --TODO : add WaveForms Picker
317
410
318 END tb;
411 END tb;
Show file before | Show file after | Hide comments
@@ -1,68 +1,72
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 LIBRARY lpp;
3
4 USE lpp.lpp_ad_conv.ALL;
4 LIBRARY grlib;
5 USE lpp.iir_filter.ALL;
5 USE grlib.amba.ALL;
6 USE lpp.FILTERcfg.ALL;
6
7 USE lpp.lpp_memory.ALL;
7 LIBRARY lpp;
8 LIBRARY techmap;
8 USE lpp.lpp_ad_conv.ALL;
9 USE techmap.gencomp.ALL;
9 USE lpp.iir_filter.ALL;
10
10 USE lpp.FILTERcfg.ALL;
11 PACKAGE lpp_top_lfr_pkg IS
11 USE lpp.lpp_memory.ALL;
12
12 LIBRARY techmap;
13 COMPONENT lpp_top_acq
13 USE techmap.gencomp.ALL;
14 GENERIC (
14
15 tech : integer);
15 PACKAGE lpp_top_lfr_pkg IS
16 PORT (
16
17 cnv_run : IN STD_LOGIC;
17 COMPONENT lpp_top_acq
18 cnv : OUT STD_LOGIC;
18 GENERIC (
19 sck : OUT STD_LOGIC;
19 tech : integer);
20 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
20 PORT (
21 cnv_clk : IN STD_LOGIC;
21 cnv_run : IN STD_LOGIC;
22 cnv_rstn : IN STD_LOGIC;
22 cnv : OUT STD_LOGIC;
23 clk : IN STD_LOGIC;
23 sck : OUT STD_LOGIC;
24 rstn : IN STD_LOGIC;
24 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
25 sample_f0_0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
25 cnv_clk : IN STD_LOGIC;
26 sample_f0_1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
26 cnv_rstn : IN STD_LOGIC;
27 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
27 clk : IN STD_LOGIC;
28 sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
28 rstn : IN STD_LOGIC;
29 sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
29 sample_f0_0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
30 sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
30 sample_f0_1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
31 sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
31 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
32 sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
32 sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
33 sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0));
33 sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
34 END COMPONENT;
34 sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
35
35 sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
36 COMPONENT lpp_top_apbreg
36 sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
37 GENERIC (
37 sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0));
38 pindex : INTEGER;
38 END COMPONENT;
39 paddr : INTEGER;
39
40 pmask : INTEGER;
40 COMPONENT lpp_top_apbreg
41 pirq : INTEGER);
41 GENERIC (
42 PORT (
42 pindex : INTEGER;
43 HCLK : IN STD_ULOGIC;
43 paddr : INTEGER;
44 HRESETn : IN STD_ULOGIC;
44 pmask : INTEGER;
45 apbi : IN apb_slv_in_type;
45 pirq : INTEGER);
46 apbo : OUT apb_slv_out_type;
46 PORT (
47 ready_matrix_f0_0 : IN STD_LOGIC;
47 HCLK : IN STD_ULOGIC;
48 ready_matrix_f0_1 : IN STD_LOGIC;
48 HRESETn : IN STD_ULOGIC;
49 ready_matrix_f1 : IN STD_LOGIC;
49 apbi : IN apb_slv_in_type;
50 ready_matrix_f2 : IN STD_LOGIC;
50 apbo : OUT apb_slv_out_type;
51 error_anticipating_empty_fifo : IN STD_LOGIC;
51 ready_matrix_f0_0 : IN STD_LOGIC;
52 error_bad_component_error : IN STD_LOGIC;
52 ready_matrix_f0_1 : IN STD_LOGIC;
53 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
53 ready_matrix_f1 : IN STD_LOGIC;
54 status_ready_matrix_f0_0 : OUT STD_LOGIC;
54 ready_matrix_f2 : IN STD_LOGIC;
55 status_ready_matrix_f0_1 : OUT STD_LOGIC;
55 error_anticipating_empty_fifo : IN STD_LOGIC;
56 status_ready_matrix_f1 : OUT STD_LOGIC;
56 error_bad_component_error : IN STD_LOGIC;
57 status_ready_matrix_f2 : OUT STD_LOGIC;
57 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
58 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
58 status_ready_matrix_f0_0 : OUT STD_LOGIC;
59 status_error_bad_component_error : OUT STD_LOGIC;
59 status_ready_matrix_f0_1 : OUT STD_LOGIC;
60 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
60 status_ready_matrix_f1 : OUT STD_LOGIC;
61 config_active_interruption_onError : OUT STD_LOGIC;
61 status_ready_matrix_f2 : OUT STD_LOGIC;
62 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
62 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
63 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
63 status_error_bad_component_error : OUT STD_LOGIC;
64 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
65 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
65 config_active_interruption_onError : OUT STD_LOGIC;
66 END COMPONENT;
66 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
67
67 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
68 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
69 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
70 END COMPONENT;
71
68 END lpp_top_lfr_pkg; No newline at end of file
72 END lpp_top_lfr_pkg;
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