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1 | ##------------------------------------------------------------------------------ | |||
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2 | ##-- This file is a part of the LPP VHDL IP LIBRARY | |||
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3 | ##-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
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4 | ##-- | |||
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5 | ##-- This program is free software; you can redistribute it and/or modify | |||
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6 | ##-- it under the terms of the GNU General Public License as published by | |||
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7 | ##-- the Free Software Foundation; either version 3 of the License, or | |||
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8 | ##-- (at your option) any later version. | |||
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9 | ##-- | |||
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10 | ##-- This program is distributed in the hope that it will be useful, | |||
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11 | ##-- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
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12 | ##-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
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13 | ##-- GNU General Public License for more details. | |||
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14 | ##-- | |||
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15 | ##-- You should have received a copy of the GNU General Public License | |||
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16 | ##-- along with this program; if not, write to the Free Software | |||
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17 | ##-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
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18 | ##------------------------------------------------------------------------------- | |||
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19 | ##-- Author : Jean-christophe Pellion | |||
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20 | ##-- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |||
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21 | ##-- jean-christophe.pellion@easii-ic.com | |||
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22 | ##------------------------------------------------------------------------------- | |||
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23 | ||||
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24 | PACKAGE=\"\" | |||
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25 | SPEED=Std | |||
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26 | SYNFREQ=50 | |||
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27 | ||||
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28 | TECHNOLOGY=ProASIC3E | |||
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29 | LIBERO_DIE=IT14X14M4 | |||
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30 | PART=A3PE3000 | |||
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31 | ||||
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32 | DESIGNER_VOLTAGE=COM | |||
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33 | DESIGNER_TEMP=COM | |||
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34 | DESIGNER_PACKAGE=FBGA | |||
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35 | DESIGNER_PINS=324 | |||
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36 | ||||
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37 | MANUFACTURER=Actel | |||
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38 | MGCTECHNOLOGY=Proasic3 | |||
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39 | MGCPART=$(PART) | |||
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40 | MGCPACKAGE= {$(DESIGNER_PINS) $(DESIGNER_PACKAGE)} | |||
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41 | LIBERO_PACKAGE=fg$(DESIGNER_PINS) | |||
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42 |
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1 | ##------------------------------------------------------------------------------ | |||
|
2 | ##-- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | ##-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
4 | ##-- | |||
|
5 | ##-- This program is free software; you can redistribute it and/or modify | |||
|
6 | ##-- it under the terms of the GNU General Public License as published by | |||
|
7 | ##-- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | ##-- (at your option) any later version. | |||
|
9 | ##-- | |||
|
10 | ##-- This program is distributed in the hope that it will be useful, | |||
|
11 | ##-- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | ##-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | ##-- GNU General Public License for more details. | |||
|
14 | ##-- | |||
|
15 | ##-- You should have received a copy of the GNU General Public License | |||
|
16 | ##-- along with this program; if not, write to the Free Software | |||
|
17 | ##-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | ##------------------------------------------------------------------------------- | |||
|
19 | ##-- Author : Jean-christophe Pellion | |||
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20 | ##-- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |||
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21 | ##-- jean-christophe.pellion@easii-ic.com | |||
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22 | ##------------------------------------------------------------------------------- | |||
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23 | ||||
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24 | # Actel Physical design constraints file | |||
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25 | # Generated file | |||
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26 | ||||
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27 | # Version: 9.1 SP3 9.1.3.4 | |||
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28 | # Family: ProASIC3L , Die: A3PE3000L , Package: 324 FBGA | |||
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29 | # Date generated: Tue Oct 18 08:21:45 2011 | |||
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30 | ||||
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31 | ||||
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32 | # | |||
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33 | # IO banks setting | |||
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34 | # | |||
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35 | ||||
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36 | ||||
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37 | # | |||
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38 | # I/O constraints | |||
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39 | # | |||
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40 | ||||
|
41 | set_io clk_50 \ | |||
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42 | -pinname F7 \ | |||
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43 | -fixed yes \ | |||
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44 | -DIRECTION Inout | |||
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45 | ||||
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46 | set_io clk_49 \ | |||
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47 | -pinname K14 \ | |||
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48 | -fixed yes \ | |||
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49 | -DIRECTION Inout | |||
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50 | ||||
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51 | set_io reset \ | |||
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52 | -pinname T2 \ | |||
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53 | -fixed yes \ | |||
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54 | -DIRECTION Inout | |||
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55 | #==================================================================== | |||
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56 | # BPs | |||
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57 | #==================================================================== | |||
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58 | set_io BP0 \ | |||
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59 | -pinname L1 \ | |||
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60 | -fixed yes \ | |||
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61 | -DIRECTION Inout | |||
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62 | ||||
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63 | set_io BP1 \ | |||
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64 | -pinname R1 \ | |||
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65 | -fixed yes \ | |||
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66 | -DIRECTION Inout | |||
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67 | ||||
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68 | #==================================================================== | |||
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69 | # LEDs | |||
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70 | #==================================================================== | |||
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71 | ||||
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72 | set_io LED0 \ | |||
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73 | -pinname V6 \ | |||
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74 | -fixed yes \ | |||
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75 | -DIRECTION Inout | |||
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76 | ||||
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77 | set_io LED1 \ | |||
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78 | -pinname V5 \ | |||
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79 | -fixed yes \ | |||
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80 | -DIRECTION Inout | |||
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81 | ||||
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82 | set_io LED2 \ | |||
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83 | -pinname T4 \ | |||
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84 | -fixed yes \ | |||
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85 | -DIRECTION Inout | |||
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86 | ||||
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87 | #==================================================================== | |||
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88 | # UARTS | |||
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89 | #==================================================================== | |||
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90 | ||||
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91 | set_io TXD1 \ | |||
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92 | -pinname N17 \ | |||
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93 | -fixed yes \ | |||
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94 | -DIRECTION Inout | |||
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95 | ||||
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96 | set_io RXD1 \ | |||
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97 | -pinname N18 \ | |||
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98 | -fixed yes \ | |||
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99 | -DIRECTION Inout | |||
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100 | ||||
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101 | set_io nCTS1 \ | |||
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102 | -pinname P18 \ | |||
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103 | -fixed yes \ | |||
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104 | -DIRECTION Inout | |||
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105 | ||||
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106 | set_io nRTS1 \ | |||
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107 | -pinname P17 \ | |||
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108 | -fixed yes \ | |||
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109 | -DIRECTION Inout | |||
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110 | ||||
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111 | ||||
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112 | set_io TXD2 \ | |||
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113 | -pinname P13 \ | |||
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114 | -fixed yes \ | |||
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115 | -DIRECTION Inout | |||
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116 | ||||
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117 | set_io RXD2 \ | |||
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118 | -pinname T18 \ | |||
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119 | -fixed yes \ | |||
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120 | -DIRECTION Inout | |||
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121 | ||||
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122 | set_io nCTS2 \ | |||
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123 | -pinname V17 \ | |||
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124 | -fixed yes \ | |||
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125 | -DIRECTION Inout | |||
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126 | ||||
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127 | set_io nDTR2 \ | |||
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128 | -pinname L15 \ | |||
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129 | -fixed yes \ | |||
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130 | -DIRECTION Inout | |||
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131 | ||||
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132 | set_io nRTS2 \ | |||
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133 | -pinname M15 \ | |||
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134 | -fixed yes \ | |||
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135 | -DIRECTION Inout | |||
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136 | ||||
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137 | set_io nDCD2 \ | |||
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138 | -pinname N15 \ | |||
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139 | -fixed yes \ | |||
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140 | -DIRECTION Inout | |||
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141 | ||||
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142 | ||||
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143 | #==================================================================== | |||
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144 | # EXT CONNECTOR | |||
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145 | #==================================================================== | |||
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146 | ||||
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147 | set_io IO0 \ | |||
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148 | -pinname E4 \ | |||
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149 | -fixed yes \ | |||
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150 | -DIRECTION Inout | |||
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151 | ||||
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152 | set_io IO1 \ | |||
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153 | -pinname D3 \ | |||
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154 | -fixed yes \ | |||
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155 | -DIRECTION Inout | |||
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156 | ||||
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157 | set_io IO2 \ | |||
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158 | -pinname C2 \ | |||
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159 | -fixed yes \ | |||
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160 | -DIRECTION Inout | |||
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161 | ||||
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162 | set_io IO3 \ | |||
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163 | -pinname D1 \ | |||
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164 | -fixed yes \ | |||
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165 | -DIRECTION Inout | |||
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166 | ||||
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167 | set_io IO4 \ | |||
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168 | -pinname F2 \ | |||
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169 | -fixed yes \ | |||
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170 | -DIRECTION Inout | |||
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171 | ||||
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172 | set_io IO5 \ | |||
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173 | -pinname F3 \ | |||
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174 | -fixed yes \ | |||
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175 | -DIRECTION Inout | |||
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176 | ||||
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177 | set_io IO6 \ | |||
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178 | -pinname G2 \ | |||
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179 | -fixed yes \ | |||
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180 | -DIRECTION Inout | |||
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181 | ||||
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182 | set_io IO7 \ | |||
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183 | -pinname H3 \ | |||
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184 | -fixed yes \ | |||
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185 | -DIRECTION Inout | |||
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186 | ||||
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187 | set_io IO8 \ | |||
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188 | -pinname H4 \ | |||
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189 | -fixed yes \ | |||
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190 | -DIRECTION Inout | |||
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191 | ||||
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192 | set_io IO9 \ | |||
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193 | -pinname J2 \ | |||
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194 | -fixed yes \ | |||
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195 | -DIRECTION Inout | |||
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196 | ||||
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197 | set_io IO10 \ | |||
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198 | -pinname P1 \ | |||
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199 | -fixed yes \ | |||
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200 | -DIRECTION Inout | |||
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201 | ||||
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202 | set_io IO11 \ | |||
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203 | -pinname N1 \ | |||
|
204 | -fixed yes \ | |||
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205 | -DIRECTION Inout | |||
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206 | ||||
|
207 | #==================================================================== | |||
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208 | # SPACE WIRE | |||
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209 | #==================================================================== | |||
|
210 | ||||
|
211 | set_io SPW_EN \ | |||
|
212 | -pinname R12 \ | |||
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213 | -fixed yes \ | |||
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214 | -DIRECTION Inout | |||
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215 | ||||
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216 | #================================ | |||
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217 | # NOMINAL LINK | |||
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218 | #================================ | |||
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219 | ||||
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220 | set_io SPW_NOM_DIN \ | |||
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221 | -pinname R10 \ | |||
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222 | -fixed yes \ | |||
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223 | -DIRECTION Inout | |||
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224 | ||||
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225 | set_io SPW_NOM_SIN \ | |||
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226 | -pinname R13 \ | |||
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227 | -fixed yes \ | |||
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228 | -DIRECTION Inout | |||
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229 | ||||
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230 | set_io SPW_NOM_DOUT \ | |||
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231 | -pinname T13 \ | |||
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232 | -fixed yes \ | |||
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233 | -DIRECTION Inout | |||
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234 | ||||
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235 | set_io SPW_NOM_SOUT \ | |||
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236 | -pinname T10 \ | |||
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237 | -fixed yes \ | |||
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238 | -DIRECTION Inout | |||
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239 | ||||
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240 | #================================ | |||
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241 | # REDUNDANT LINK | |||
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242 | #================================ | |||
|
243 | ||||
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244 | set_io SPW_RED_DIN \ | |||
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245 | -pinname U18 \ | |||
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246 | -fixed yes \ | |||
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247 | -DIRECTION Inout | |||
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248 | ||||
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249 | set_io SPW_RED_SIN \ | |||
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250 | -pinname T12 \ | |||
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251 | -fixed yes \ | |||
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252 | -DIRECTION Inout | |||
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253 | ||||
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254 | set_io SPW_RED_DOUT \ | |||
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255 | -pinname U10 \ | |||
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256 | -fixed yes \ | |||
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257 | -DIRECTION Inout | |||
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258 | ||||
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259 | set_io SPW_RED_SOUT \ | |||
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260 | -pinname P16 \ | |||
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261 | -fixed yes \ | |||
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262 | -DIRECTION Inout | |||
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263 | ||||
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264 | #==================================================================== | |||
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265 | # MINI LFR ADC INPUTS | |||
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266 | #==================================================================== | |||
|
267 | ||||
|
268 | set_io ADC_nCS \ | |||
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269 | -pinname K1 \ | |||
|
270 | -fixed yes \ | |||
|
271 | -DIRECTION Inout | |||
|
272 | ||||
|
273 | set_io ADC_CLK \ | |||
|
274 | -pinname T1 \ | |||
|
275 | -fixed yes \ | |||
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276 | -DIRECTION Inout | |||
|
277 | ||||
|
278 | ||||
|
279 | #================================ | |||
|
280 | # ADC DATA | |||
|
281 | #================================ | |||
|
282 | ||||
|
283 | set_io ADC_SDO\[0\] \ | |||
|
284 | -pinname V4 \ | |||
|
285 | -fixed yes \ | |||
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286 | -DIRECTION Inout | |||
|
287 | ||||
|
288 | set_io ADC_SDO\[1\] \ | |||
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289 | -pinname V3 \ | |||
|
290 | -fixed yes \ | |||
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291 | -DIRECTION Inout | |||
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292 | ||||
|
293 | set_io ADC_SDO\[2\] \ | |||
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294 | -pinname V2 \ | |||
|
295 | -fixed yes \ | |||
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296 | -DIRECTION Inout | |||
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297 | ||||
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298 | set_io ADC_SDO\[3\] \ | |||
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299 | -pinname U1 \ | |||
|
300 | -fixed yes \ | |||
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301 | -DIRECTION Inout | |||
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302 | ||||
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303 | set_io ADC_SDO\[4\] \ | |||
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304 | -pinname J1 \ | |||
|
305 | -fixed yes \ | |||
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306 | -DIRECTION Inout | |||
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307 | ||||
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308 | set_io ADC_SDO\[5\] \ | |||
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309 | -pinname H1 \ | |||
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310 | -fixed yes \ | |||
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311 | -DIRECTION Inout | |||
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312 | ||||
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313 | set_io ADC_SDO\[6\] \ | |||
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314 | -pinname F1 \ | |||
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315 | -fixed yes \ | |||
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316 | -DIRECTION Inout | |||
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317 | ||||
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318 | set_io ADC_SDO\[7\] \ | |||
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319 | -pinname E1 \ | |||
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320 | -fixed yes \ | |||
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321 | -DIRECTION Inout | |||
|
322 | ||||
|
323 | ||||
|
324 | #==================================================================== | |||
|
325 | # SRAM | |||
|
326 | #==================================================================== | |||
|
327 | ||||
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328 | #================================ | |||
|
329 | # SRAM CTRL | |||
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330 | #================================ | |||
|
331 | ||||
|
332 | set_io SRAM_nWE \ | |||
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333 | -pinname C13 \ | |||
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334 | -fixed yes \ | |||
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335 | -DIRECTION Inout | |||
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336 | ||||
|
337 | set_io SRAM_CE \ | |||
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338 | -pinname J14 \ | |||
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339 | -fixed yes \ | |||
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340 | -DIRECTION Inout | |||
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341 | ||||
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342 | set_io SRAM_nOE \ | |||
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343 | -pinname B9 \ | |||
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344 | -fixed yes \ | |||
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345 | -DIRECTION Inout | |||
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346 | ||||
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347 | set_io SRAM_nBE\[0\] \ | |||
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348 | -pinname H15 \ | |||
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349 | -fixed yes \ | |||
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350 | -DIRECTION Inout | |||
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351 | ||||
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352 | set_io SRAM_nBE\[1\] \ | |||
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353 | -pinname C12 \ | |||
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354 | -fixed yes \ | |||
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355 | -DIRECTION Inout | |||
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356 | ||||
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357 | set_io SRAM_nBE\[2\] \ | |||
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358 | -pinname A10 \ | |||
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359 | -fixed yes \ | |||
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360 | -DIRECTION Inout | |||
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361 | ||||
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362 | set_io SRAM_nBE\[3\] \ | |||
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363 | -pinname A9 \ | |||
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364 | -fixed yes \ | |||
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365 | -DIRECTION Inout | |||
|
366 | ||||
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367 | ||||
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368 | #================================ | |||
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369 | # SRAM ADDRESS | |||
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370 | #================================ | |||
|
371 | ||||
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372 | set_io SRAM_A\[0\] \ | |||
|
373 | -pinname C11 \ | |||
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374 | -fixed yes \ | |||
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375 | -DIRECTION Inout | |||
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376 | ||||
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377 | set_io SRAM_A\[1\] \ | |||
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378 | -pinname C10 \ | |||
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379 | -fixed yes \ | |||
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380 | -DIRECTION Inout | |||
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381 | ||||
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382 | set_io SRAM_A\[2\] \ | |||
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383 | -pinname C9 \ | |||
|
384 | -fixed yes \ | |||
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385 | -DIRECTION Inout | |||
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386 | ||||
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387 | set_io SRAM_A\[3\] \ | |||
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388 | -pinname C8 \ | |||
|
389 | -fixed yes \ | |||
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390 | -DIRECTION Inout | |||
|
391 | ||||
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392 | set_io SRAM_A\[4\] \ | |||
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393 | -pinname C7 \ | |||
|
394 | -fixed yes \ | |||
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395 | -DIRECTION Inout | |||
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396 | ||||
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397 | set_io SRAM_A\[5\] \ | |||
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398 | -pinname A5 \ | |||
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399 | -fixed yes \ | |||
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400 | -DIRECTION Inout | |||
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401 | ||||
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402 | set_io SRAM_A\[6\] \ | |||
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403 | -pinname A6 \ | |||
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404 | -fixed yes \ | |||
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405 | -DIRECTION Inout | |||
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406 | ||||
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407 | set_io SRAM_A\[7\] \ | |||
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408 | -pinname B6 \ | |||
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409 | -fixed yes \ | |||
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410 | -DIRECTION Inout | |||
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411 | ||||
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412 | set_io SRAM_A\[8\] \ | |||
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413 | -pinname B7 \ | |||
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414 | -fixed yes \ | |||
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415 | -DIRECTION Inout | |||
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416 | ||||
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417 | set_io SRAM_A\[9\] \ | |||
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418 | -pinname A8 \ | |||
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419 | -fixed yes \ | |||
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420 | -DIRECTION Inout | |||
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421 | ||||
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422 | set_io SRAM_A\[10\] \ | |||
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423 | -pinname B10 \ | |||
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424 | -fixed yes \ | |||
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425 | -DIRECTION Inout | |||
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426 | ||||
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427 | set_io SRAM_A\[11\] \ | |||
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428 | -pinname A11 \ | |||
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429 | -fixed yes \ | |||
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430 | -DIRECTION Inout | |||
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431 | ||||
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432 | set_io SRAM_A\[12\] \ | |||
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433 | -pinname B12 \ | |||
|
434 | -fixed yes \ | |||
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435 | -DIRECTION Inout | |||
|
436 | ||||
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437 | set_io SRAM_A\[13\] \ | |||
|
438 | -pinname A13 \ | |||
|
439 | -fixed yes \ | |||
|
440 | -DIRECTION Inout | |||
|
441 | ||||
|
442 | set_io SRAM_A\[14\] \ | |||
|
443 | -pinname B13 \ | |||
|
444 | -fixed yes \ | |||
|
445 | -DIRECTION Inout | |||
|
446 | ||||
|
447 | set_io SRAM_A\[15\] \ | |||
|
448 | -pinname C18 \ | |||
|
449 | -fixed yes \ | |||
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450 | -DIRECTION Inout | |||
|
451 | ||||
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452 | set_io SRAM_A\[16\] \ | |||
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453 | -pinname C17 \ | |||
|
454 | -fixed yes \ | |||
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455 | -DIRECTION Inout | |||
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456 | ||||
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457 | set_io SRAM_A\[17\] \ | |||
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458 | -pinname B18 \ | |||
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459 | -fixed yes \ | |||
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460 | -DIRECTION Inout | |||
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461 | ||||
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462 | set_io SRAM_A\[18\] \ | |||
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463 | -pinname C16 \ | |||
|
464 | -fixed yes \ | |||
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465 | -DIRECTION Inout | |||
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466 | ||||
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467 | set_io SRAM_A\[19\] \ | |||
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468 | -pinname D15 \ | |||
|
469 | -fixed yes \ | |||
|
470 | -DIRECTION Inout | |||
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471 | ||||
|
472 | ||||
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473 | #================================ | |||
|
474 | # SRAM DATA | |||
|
475 | #================================ | |||
|
476 | ||||
|
477 | set_io SRAM_DQ\[0\] \ | |||
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478 | -pinname D16 \ | |||
|
479 | -fixed yes \ | |||
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480 | -DIRECTION Inout | |||
|
481 | ||||
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482 | set_io SRAM_DQ\[1\] \ | |||
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483 | -pinname D18 \ | |||
|
484 | -fixed yes \ | |||
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485 | -DIRECTION Inout | |||
|
486 | ||||
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487 | set_io SRAM_DQ\[2\] \ | |||
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488 | -pinname E15 \ | |||
|
489 | -fixed yes \ | |||
|
490 | -DIRECTION Inout | |||
|
491 | ||||
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492 | set_io SRAM_DQ\[3\] \ | |||
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493 | -pinname E18 \ | |||
|
494 | -fixed yes \ | |||
|
495 | -DIRECTION Inout | |||
|
496 | ||||
|
497 | set_io SRAM_DQ\[4\] \ | |||
|
498 | -pinname F15 \ | |||
|
499 | -fixed yes \ | |||
|
500 | -DIRECTION Inout | |||
|
501 | ||||
|
502 | set_io SRAM_DQ\[5\] \ | |||
|
503 | -pinname F18 \ | |||
|
504 | -fixed yes \ | |||
|
505 | -DIRECTION Inout | |||
|
506 | ||||
|
507 | set_io SRAM_DQ\[6\] \ | |||
|
508 | -pinname G15 \ | |||
|
509 | -fixed yes \ | |||
|
510 | -DIRECTION Inout | |||
|
511 | ||||
|
512 | set_io SRAM_DQ\[7\] \ | |||
|
513 | -pinname G17 \ | |||
|
514 | -fixed yes \ | |||
|
515 | -DIRECTION Inout | |||
|
516 | ||||
|
517 | set_io SRAM_DQ\[8\] \ | |||
|
518 | -pinname K15 \ | |||
|
519 | -fixed yes \ | |||
|
520 | -DIRECTION Inout | |||
|
521 | ||||
|
522 | set_io SRAM_DQ\[9\] \ | |||
|
523 | -pinname J18 \ | |||
|
524 | -fixed yes \ | |||
|
525 | -DIRECTION Inout | |||
|
526 | ||||
|
527 | set_io SRAM_DQ\[10\] \ | |||
|
528 | -pinname J15 \ | |||
|
529 | -fixed yes \ | |||
|
530 | -DIRECTION Inout | |||
|
531 | ||||
|
532 | set_io SRAM_DQ\[11\] \ | |||
|
533 | -pinname H18 \ | |||
|
534 | -fixed yes \ | |||
|
535 | -DIRECTION Inout | |||
|
536 | ||||
|
537 | set_io SRAM_DQ\[12\] \ | |||
|
538 | -pinname C3 \ | |||
|
539 | -fixed yes \ | |||
|
540 | -DIRECTION Inout | |||
|
541 | ||||
|
542 | set_io SRAM_DQ\[13\] \ | |||
|
543 | -pinname D4 \ | |||
|
544 | -fixed yes \ | |||
|
545 | -DIRECTION Inout | |||
|
546 | ||||
|
547 | set_io SRAM_DQ\[14\] \ | |||
|
548 | -pinname D5 \ | |||
|
549 | -fixed yes \ | |||
|
550 | -DIRECTION Inout | |||
|
551 | ||||
|
552 | set_io SRAM_DQ\[15\] \ | |||
|
553 | -pinname C6 \ | |||
|
554 | -fixed yes \ | |||
|
555 | -DIRECTION Inout | |||
|
556 | ||||
|
557 | set_io SRAM_DQ\[16\] \ | |||
|
558 | -pinname D14 \ | |||
|
559 | -fixed yes \ | |||
|
560 | -DIRECTION Inout | |||
|
561 | ||||
|
562 | set_io SRAM_DQ\[17\] \ | |||
|
563 | -pinname A15 \ | |||
|
564 | -fixed yes \ | |||
|
565 | -DIRECTION Inout | |||
|
566 | ||||
|
567 | set_io SRAM_DQ\[18\] \ | |||
|
568 | -pinname C15 \ | |||
|
569 | -fixed yes \ | |||
|
570 | -DIRECTION Inout | |||
|
571 | ||||
|
572 | set_io SRAM_DQ\[19\] \ | |||
|
573 | -pinname B17 \ | |||
|
574 | -fixed yes \ | |||
|
575 | -DIRECTION Inout | |||
|
576 | ||||
|
577 | set_io SRAM_DQ\[20\] \ | |||
|
578 | -pinname A17 \ | |||
|
579 | -fixed yes \ | |||
|
580 | -DIRECTION Inout | |||
|
581 | ||||
|
582 | set_io SRAM_DQ\[21\] \ | |||
|
583 | -pinname B16 \ | |||
|
584 | -fixed yes \ | |||
|
585 | -DIRECTION Inout | |||
|
586 | ||||
|
587 | set_io SRAM_DQ\[22\] \ | |||
|
588 | -pinname A16 \ | |||
|
589 | -fixed yes \ | |||
|
590 | -DIRECTION Inout | |||
|
591 | ||||
|
592 | set_io SRAM_DQ\[23\] \ | |||
|
593 | -pinname A14 \ | |||
|
594 | -fixed yes \ | |||
|
595 | -DIRECTION Inout | |||
|
596 | ||||
|
597 | set_io SRAM_DQ\[24\] \ | |||
|
598 | -pinname A4 \ | |||
|
599 | -fixed yes \ | |||
|
600 | -DIRECTION Inout | |||
|
601 | ||||
|
602 | set_io SRAM_DQ\[25\] \ | |||
|
603 | -pinname A3 \ | |||
|
604 | -fixed yes \ | |||
|
605 | -DIRECTION Inout | |||
|
606 | ||||
|
607 | set_io SRAM_DQ\[26\] \ | |||
|
608 | -pinname A2 \ | |||
|
609 | -fixed yes \ | |||
|
610 | -DIRECTION Inout | |||
|
611 | ||||
|
612 | set_io SRAM_DQ\[27\] \ | |||
|
613 | -pinname B1 \ | |||
|
614 | -fixed yes \ | |||
|
615 | -DIRECTION Inout | |||
|
616 | ||||
|
617 | set_io SRAM_DQ\[28\] \ | |||
|
618 | -pinname C1 \ | |||
|
619 | -fixed yes \ | |||
|
620 | -DIRECTION Inout | |||
|
621 | ||||
|
622 | set_io SRAM_DQ\[29\] \ | |||
|
623 | -pinname B2 \ | |||
|
624 | -fixed yes \ | |||
|
625 | -DIRECTION Inout | |||
|
626 | ||||
|
627 | set_io SRAM_DQ\[30\] \ | |||
|
628 | -pinname B3 \ | |||
|
629 | -fixed yes \ | |||
|
630 | -DIRECTION Inout | |||
|
631 | ||||
|
632 | set_io SRAM_DQ\[31\] \ | |||
|
633 | -pinname C4 \ | |||
|
634 | -fixed yes \ | |||
|
635 | -DIRECTION Inout | |||
|
636 | ||||
|
637 | ||||
|
638 | ||||
|
639 | ||||
|
640 | ||||
|
641 | ||||
|
642 | ||||
|
643 | ||||
|
644 | ||||
|
645 | ||||
|
646 | ||||
|
647 | ||||
|
648 | ||||
|
649 | ||||
|
650 | ||||
|
651 | ||||
|
652 | ||||
|
653 | ||||
|
654 | ||||
|
655 | ||||
|
656 | ||||
|
657 | ||||
|
658 | ||||
|
659 | ||||
|
660 | ||||
|
661 | ||||
|
662 |
@@ -0,0 +1,59 | |||||
|
1 | # Synplicity, Inc. constraint file | |||
|
2 | # /home/jiri/ibm/vhdl/grlib/boards/actel-coremp7-1000/default.sdc | |||
|
3 | # Written on Wed Aug 1 19:29:24 2007 | |||
|
4 | # by Synplify Pro, Synplify Pro 8.8.0.4 Scope Editor | |||
|
5 | ||||
|
6 | # | |||
|
7 | # Collections | |||
|
8 | # | |||
|
9 | ||||
|
10 | # | |||
|
11 | # Clocks | |||
|
12 | # | |||
|
13 | define_clock {clk} -name {clk} -freq 60 -clockgroup default_clkgroup -route 5 | |||
|
14 | ||||
|
15 | # | |||
|
16 | # Clock to Clock | |||
|
17 | # | |||
|
18 | ||||
|
19 | # | |||
|
20 | # Inputs/Outputs | |||
|
21 | # | |||
|
22 | define_output_delay -disable -default 5.00 -improve 0.00 -route 0.00 -ref {clk:r} | |||
|
23 | define_input_delay -disable -default 5.00 -improve 0.00 -route 0.00 -ref {clk:r} | |||
|
24 | ||||
|
25 | ||||
|
26 | # | |||
|
27 | # Registers | |||
|
28 | # | |||
|
29 | ||||
|
30 | # | |||
|
31 | # Multicycle Path | |||
|
32 | # | |||
|
33 | ||||
|
34 | # | |||
|
35 | # False Path | |||
|
36 | # | |||
|
37 | ||||
|
38 | # | |||
|
39 | # Path Delay | |||
|
40 | # | |||
|
41 | ||||
|
42 | # | |||
|
43 | # Attributes | |||
|
44 | # | |||
|
45 | define_global_attribute syn_useioff {1} | |||
|
46 | define_global_attribute -disable syn_netlist_hierarchy {0} | |||
|
47 | define_attribute {etx_clk} syn_noclockbuf {1} | |||
|
48 | ||||
|
49 | # | |||
|
50 | # I/O standards | |||
|
51 | # | |||
|
52 | ||||
|
53 | # | |||
|
54 | # Compile Points | |||
|
55 | # | |||
|
56 | ||||
|
57 | # | |||
|
58 | # Other Constraints | |||
|
59 | # |
@@ -0,0 +1,288 | |||||
|
1 | # | |||
|
2 | # Automatically generated make config: don't edit | |||
|
3 | # | |||
|
4 | ||||
|
5 | # | |||
|
6 | # Synthesis | |||
|
7 | # | |||
|
8 | # CONFIG_SYN_INFERRED is not set | |||
|
9 | # CONFIG_SYN_STRATIX is not set | |||
|
10 | # CONFIG_SYN_STRATIXII is not set | |||
|
11 | # CONFIG_SYN_STRATIXIII is not set | |||
|
12 | # CONFIG_SYN_CYCLONEIII is not set | |||
|
13 | # CONFIG_SYN_ALTERA is not set | |||
|
14 | # CONFIG_SYN_AXCEL is not set | |||
|
15 | # CONFIG_SYN_PROASIC is not set | |||
|
16 | # CONFIG_SYN_PROASICPLUS is not set | |||
|
17 | CONFIG_SYN_PROASIC3=y | |||
|
18 | # CONFIG_SYN_UT025CRH is not set | |||
|
19 | # CONFIG_SYN_ATC18 is not set | |||
|
20 | # CONFIG_SYN_ATC18RHA is not set | |||
|
21 | # CONFIG_SYN_CUSTOM1 is not set | |||
|
22 | # CONFIG_SYN_EASIC90 is not set | |||
|
23 | # CONFIG_SYN_IHP25 is not set | |||
|
24 | # CONFIG_SYN_IHP25RH is not set | |||
|
25 | # CONFIG_SYN_LATTICE is not set | |||
|
26 | # CONFIG_SYN_ECLIPSE is not set | |||
|
27 | # CONFIG_SYN_PEREGRINE is not set | |||
|
28 | # CONFIG_SYN_RH_LIB18T is not set | |||
|
29 | # CONFIG_SYN_RHUMC is not set | |||
|
30 | # CONFIG_SYN_SMIC13 is not set | |||
|
31 | # CONFIG_SYN_SPARTAN2 is not set | |||
|
32 | # CONFIG_SYN_SPARTAN3 is not set | |||
|
33 | # CONFIG_SYN_SPARTAN3E is not set | |||
|
34 | # CONFIG_SYN_VIRTEX is not set | |||
|
35 | # CONFIG_SYN_VIRTEXE is not set | |||
|
36 | # CONFIG_SYN_VIRTEX2 is not set | |||
|
37 | # CONFIG_SYN_VIRTEX4 is not set | |||
|
38 | # CONFIG_SYN_VIRTEX5 is not set | |||
|
39 | # CONFIG_SYN_UMC is not set | |||
|
40 | # CONFIG_SYN_TSMC90 is not set | |||
|
41 | # CONFIG_SYN_INFER_RAM is not set | |||
|
42 | # CONFIG_SYN_INFER_PADS is not set | |||
|
43 | # CONFIG_SYN_NO_ASYNC is not set | |||
|
44 | # CONFIG_SYN_SCAN is not set | |||
|
45 | ||||
|
46 | # | |||
|
47 | # Clock generation | |||
|
48 | # | |||
|
49 | # CONFIG_CLK_INFERRED is not set | |||
|
50 | # CONFIG_CLK_HCLKBUF is not set | |||
|
51 | # CONFIG_CLK_ALTDLL is not set | |||
|
52 | # CONFIG_CLK_LATDLL is not set | |||
|
53 | CONFIG_CLK_PRO3PLL=y | |||
|
54 | # CONFIG_CLK_LIB18T is not set | |||
|
55 | # CONFIG_CLK_RHUMC is not set | |||
|
56 | # CONFIG_CLK_CLKDLL is not set | |||
|
57 | # CONFIG_CLK_DCM is not set | |||
|
58 | CONFIG_CLK_MUL=2 | |||
|
59 | CONFIG_CLK_DIV=8 | |||
|
60 | CONFIG_OCLK_DIV=2 | |||
|
61 | # CONFIG_PCI_SYSCLK is not set | |||
|
62 | CONFIG_LEON3=y | |||
|
63 | CONFIG_PROC_NUM=1 | |||
|
64 | ||||
|
65 | # | |||
|
66 | # Processor | |||
|
67 | # | |||
|
68 | ||||
|
69 | # | |||
|
70 | # Integer unit | |||
|
71 | # | |||
|
72 | CONFIG_IU_NWINDOWS=8 | |||
|
73 | # CONFIG_IU_V8MULDIV is not set | |||
|
74 | # CONFIG_IU_SVT is not set | |||
|
75 | CONFIG_IU_LDELAY=1 | |||
|
76 | CONFIG_IU_WATCHPOINTS=0 | |||
|
77 | # CONFIG_PWD is not set | |||
|
78 | CONFIG_IU_RSTADDR=00000 | |||
|
79 | ||||
|
80 | # | |||
|
81 | # Floating-point unit | |||
|
82 | # | |||
|
83 | # CONFIG_FPU_ENABLE is not set | |||
|
84 | ||||
|
85 | # | |||
|
86 | # Cache system | |||
|
87 | # | |||
|
88 | CONFIG_ICACHE_ENABLE=y | |||
|
89 | CONFIG_ICACHE_ASSO1=y | |||
|
90 | # CONFIG_ICACHE_ASSO2 is not set | |||
|
91 | # CONFIG_ICACHE_ASSO3 is not set | |||
|
92 | # CONFIG_ICACHE_ASSO4 is not set | |||
|
93 | # CONFIG_ICACHE_SZ1 is not set | |||
|
94 | # CONFIG_ICACHE_SZ2 is not set | |||
|
95 | CONFIG_ICACHE_SZ4=y | |||
|
96 | # CONFIG_ICACHE_SZ8 is not set | |||
|
97 | # CONFIG_ICACHE_SZ16 is not set | |||
|
98 | # CONFIG_ICACHE_SZ32 is not set | |||
|
99 | # CONFIG_ICACHE_SZ64 is not set | |||
|
100 | # CONFIG_ICACHE_SZ128 is not set | |||
|
101 | # CONFIG_ICACHE_SZ256 is not set | |||
|
102 | # CONFIG_ICACHE_LZ16 is not set | |||
|
103 | CONFIG_ICACHE_LZ32=y | |||
|
104 | CONFIG_DCACHE_ENABLE=y | |||
|
105 | CONFIG_DCACHE_ASSO1=y | |||
|
106 | # CONFIG_DCACHE_ASSO2 is not set | |||
|
107 | # CONFIG_DCACHE_ASSO3 is not set | |||
|
108 | # CONFIG_DCACHE_ASSO4 is not set | |||
|
109 | # CONFIG_DCACHE_SZ1 is not set | |||
|
110 | # CONFIG_DCACHE_SZ2 is not set | |||
|
111 | CONFIG_DCACHE_SZ4=y | |||
|
112 | # CONFIG_DCACHE_SZ8 is not set | |||
|
113 | # CONFIG_DCACHE_SZ16 is not set | |||
|
114 | # CONFIG_DCACHE_SZ32 is not set | |||
|
115 | # CONFIG_DCACHE_SZ64 is not set | |||
|
116 | # CONFIG_DCACHE_SZ128 is not set | |||
|
117 | # CONFIG_DCACHE_SZ256 is not set | |||
|
118 | # CONFIG_DCACHE_LZ16 is not set | |||
|
119 | CONFIG_DCACHE_LZ32=y | |||
|
120 | # CONFIG_DCACHE_SNOOP is not set | |||
|
121 | CONFIG_CACHE_FIXED=0 | |||
|
122 | ||||
|
123 | # | |||
|
124 | # MMU | |||
|
125 | # | |||
|
126 | CONFIG_MMU_ENABLE=y | |||
|
127 | # CONFIG_MMU_COMBINED is not set | |||
|
128 | CONFIG_MMU_SPLIT=y | |||
|
129 | # CONFIG_MMU_REPARRAY is not set | |||
|
130 | CONFIG_MMU_REPINCREMENT=y | |||
|
131 | # CONFIG_MMU_I2 is not set | |||
|
132 | # CONFIG_MMU_I4 is not set | |||
|
133 | CONFIG_MMU_I8=y | |||
|
134 | # CONFIG_MMU_I16 is not set | |||
|
135 | # CONFIG_MMU_I32 is not set | |||
|
136 | # CONFIG_MMU_D2 is not set | |||
|
137 | # CONFIG_MMU_D4 is not set | |||
|
138 | CONFIG_MMU_D8=y | |||
|
139 | # CONFIG_MMU_D16 is not set | |||
|
140 | # CONFIG_MMU_D32 is not set | |||
|
141 | CONFIG_MMU_FASTWB=y | |||
|
142 | CONFIG_MMU_PAGE_4K=y | |||
|
143 | # CONFIG_MMU_PAGE_8K is not set | |||
|
144 | # CONFIG_MMU_PAGE_16K is not set | |||
|
145 | # CONFIG_MMU_PAGE_32K is not set | |||
|
146 | # CONFIG_MMU_PAGE_PROG is not set | |||
|
147 | ||||
|
148 | # | |||
|
149 | # Debug Support Unit | |||
|
150 | # | |||
|
151 | # CONFIG_DSU_ENABLE is not set | |||
|
152 | ||||
|
153 | # | |||
|
154 | # Fault-tolerance | |||
|
155 | # | |||
|
156 | ||||
|
157 | # | |||
|
158 | # VHDL debug settings | |||
|
159 | # | |||
|
160 | # CONFIG_IU_DISAS is not set | |||
|
161 | # CONFIG_DEBUG_PC32 is not set | |||
|
162 | ||||
|
163 | # | |||
|
164 | # AMBA configuration | |||
|
165 | # | |||
|
166 | CONFIG_AHB_DEFMST=0 | |||
|
167 | CONFIG_AHB_RROBIN=y | |||
|
168 | # CONFIG_AHB_SPLIT is not set | |||
|
169 | CONFIG_AHB_IOADDR=FFF | |||
|
170 | CONFIG_APB_HADDR=800 | |||
|
171 | # CONFIG_AHB_MON is not set | |||
|
172 | ||||
|
173 | # | |||
|
174 | # Debug Link | |||
|
175 | # | |||
|
176 | CONFIG_DSU_UART=y | |||
|
177 | # CONFIG_DSU_JTAG is not set | |||
|
178 | ||||
|
179 | # | |||
|
180 | # Peripherals | |||
|
181 | # | |||
|
182 | ||||
|
183 | # | |||
|
184 | # Memory controllers | |||
|
185 | # | |||
|
186 | ||||
|
187 | # | |||
|
188 | # 8/32-bit PROM/SRAM controller | |||
|
189 | # | |||
|
190 | CONFIG_SRCTRL=y | |||
|
191 | # CONFIG_SRCTRL_8BIT is not set | |||
|
192 | CONFIG_SRCTRL_PROMWS=3 | |||
|
193 | CONFIG_SRCTRL_RAMWS=0 | |||
|
194 | CONFIG_SRCTRL_IOWS=0 | |||
|
195 | # CONFIG_SRCTRL_RMW is not set | |||
|
196 | CONFIG_SRCTRL_SRBANKS1=y | |||
|
197 | # CONFIG_SRCTRL_SRBANKS2 is not set | |||
|
198 | # CONFIG_SRCTRL_SRBANKS3 is not set | |||
|
199 | # CONFIG_SRCTRL_SRBANKS4 is not set | |||
|
200 | # CONFIG_SRCTRL_SRBANKS5 is not set | |||
|
201 | # CONFIG_SRCTRL_BANKSZ0 is not set | |||
|
202 | # CONFIG_SRCTRL_BANKSZ1 is not set | |||
|
203 | # CONFIG_SRCTRL_BANKSZ2 is not set | |||
|
204 | # CONFIG_SRCTRL_BANKSZ3 is not set | |||
|
205 | # CONFIG_SRCTRL_BANKSZ4 is not set | |||
|
206 | # CONFIG_SRCTRL_BANKSZ5 is not set | |||
|
207 | # CONFIG_SRCTRL_BANKSZ6 is not set | |||
|
208 | # CONFIG_SRCTRL_BANKSZ7 is not set | |||
|
209 | # CONFIG_SRCTRL_BANKSZ8 is not set | |||
|
210 | # CONFIG_SRCTRL_BANKSZ9 is not set | |||
|
211 | # CONFIG_SRCTRL_BANKSZ10 is not set | |||
|
212 | # CONFIG_SRCTRL_BANKSZ11 is not set | |||
|
213 | # CONFIG_SRCTRL_BANKSZ12 is not set | |||
|
214 | # CONFIG_SRCTRL_BANKSZ13 is not set | |||
|
215 | CONFIG_SRCTRL_ROMASEL=19 | |||
|
216 | ||||
|
217 | # | |||
|
218 | # Leon2 memory controller | |||
|
219 | # | |||
|
220 | CONFIG_MCTRL_LEON2=y | |||
|
221 | # CONFIG_MCTRL_8BIT is not set | |||
|
222 | # CONFIG_MCTRL_16BIT is not set | |||
|
223 | # CONFIG_MCTRL_5CS is not set | |||
|
224 | # CONFIG_MCTRL_SDRAM is not set | |||
|
225 | ||||
|
226 | # | |||
|
227 | # PC133 SDRAM controller | |||
|
228 | # | |||
|
229 | # CONFIG_SDCTRL is not set | |||
|
230 | ||||
|
231 | # | |||
|
232 | # On-chip RAM/ROM | |||
|
233 | # | |||
|
234 | # CONFIG_AHBROM_ENABLE is not set | |||
|
235 | # CONFIG_AHBRAM_ENABLE is not set | |||
|
236 | ||||
|
237 | # | |||
|
238 | # Ethernet | |||
|
239 | # | |||
|
240 | # CONFIG_GRETH_ENABLE is not set | |||
|
241 | ||||
|
242 | # | |||
|
243 | # CAN | |||
|
244 | # | |||
|
245 | # CONFIG_CAN_ENABLE is not set | |||
|
246 | ||||
|
247 | # | |||
|
248 | # PCI | |||
|
249 | # | |||
|
250 | # CONFIG_PCI_SIMPLE_TARGET is not set | |||
|
251 | # CONFIG_PCI_MASTER_TARGET is not set | |||
|
252 | # CONFIG_PCI_ARBITER is not set | |||
|
253 | # CONFIG_PCI_TRACE is not set | |||
|
254 | ||||
|
255 | # | |||
|
256 | # Spacewire | |||
|
257 | # | |||
|
258 | # CONFIG_SPW_ENABLE is not set | |||
|
259 | ||||
|
260 | # | |||
|
261 | # UARTs, timers and irq control | |||
|
262 | # | |||
|
263 | CONFIG_UART1_ENABLE=y | |||
|
264 | # CONFIG_UA1_FIFO1 is not set | |||
|
265 | # CONFIG_UA1_FIFO2 is not set | |||
|
266 | CONFIG_UA1_FIFO4=y | |||
|
267 | # CONFIG_UA1_FIFO8 is not set | |||
|
268 | # CONFIG_UA1_FIFO16 is not set | |||
|
269 | # CONFIG_UA1_FIFO32 is not set | |||
|
270 | # CONFIG_UART2_ENABLE is not set | |||
|
271 | CONFIG_IRQ3_ENABLE=y | |||
|
272 | # CONFIG_IRQ3_SEC is not set | |||
|
273 | CONFIG_GPT_ENABLE=y | |||
|
274 | CONFIG_GPT_NTIM=2 | |||
|
275 | CONFIG_GPT_SW=8 | |||
|
276 | CONFIG_GPT_TW=32 | |||
|
277 | CONFIG_GPT_IRQ=8 | |||
|
278 | CONFIG_GPT_SEPIRQ=y | |||
|
279 | CONFIG_GPT_WDOGEN=y | |||
|
280 | CONFIG_GPT_WDOG=FFFF | |||
|
281 | CONFIG_GRGPIO_ENABLE=y | |||
|
282 | CONFIG_GRGPIO_WIDTH=8 | |||
|
283 | CONFIG_GRGPIO_IMASK=0000 | |||
|
284 | ||||
|
285 | # | |||
|
286 | # VHDL Debugging | |||
|
287 | # | |||
|
288 | # CONFIG_DEBUG_UART is not set |
@@ -0,0 +1,271 | |||||
|
1 | ------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | ------------------------------------------------------------------------------- | |||
|
19 | -- Author : Jean-christophe Pellion | |||
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |||
|
21 | -- jean-christophe.pellion@easii-ic.com | |||
|
22 | ------------------------------------------------------------------------------- | |||
|
23 | LIBRARY IEEE; | |||
|
24 | USE IEEE.numeric_std.ALL; | |||
|
25 | USE IEEE.std_logic_1164.ALL; | |||
|
26 | LIBRARY grlib; | |||
|
27 | USE grlib.amba.ALL; | |||
|
28 | USE grlib.stdlib.ALL; | |||
|
29 | LIBRARY techmap; | |||
|
30 | USE techmap.gencomp.ALL; | |||
|
31 | LIBRARY gaisler; | |||
|
32 | USE gaisler.memctrl.ALL; | |||
|
33 | USE gaisler.leon3.ALL; | |||
|
34 | USE gaisler.uart.ALL; | |||
|
35 | USE gaisler.misc.ALL; | |||
|
36 | USE gaisler.spacewire.ALL; -- PLE | |||
|
37 | LIBRARY esa; | |||
|
38 | USE esa.memoryctrl.ALL; | |||
|
39 | ||||
|
40 | LIBRARY staging; | |||
|
41 | USE staging.SOC_LPP_JCP.ALL; | |||
|
42 | ||||
|
43 | ENTITY MINI_LFR_top IS | |||
|
44 | ||||
|
45 | PORT ( | |||
|
46 | clk_50 : IN STD_LOGIC; | |||
|
47 | clk_49 : IN STD_LOGIC; | |||
|
48 | reset : IN STD_LOGIC; | |||
|
49 | --BPs | |||
|
50 | BP0 : IN STD_LOGIC; | |||
|
51 | BP1 : IN STD_LOGIC; | |||
|
52 | --LEDs | |||
|
53 | LED0 : OUT STD_LOGIC; | |||
|
54 | LED1 : OUT STD_LOGIC; | |||
|
55 | LED2 : OUT STD_LOGIC; | |||
|
56 | --UARTs | |||
|
57 | TXD1 : IN STD_LOGIC; | |||
|
58 | RXD1 : OUT STD_LOGIC; | |||
|
59 | nCTS1 : OUT STD_LOGIC; | |||
|
60 | nRTS1 : IN STD_LOGIC; | |||
|
61 | ||||
|
62 | TXD2 : IN STD_LOGIC; | |||
|
63 | RXD2 : OUT STD_LOGIC; | |||
|
64 | nCTS2 : OUT STD_LOGIC; | |||
|
65 | nDTR2 : IN STD_LOGIC; | |||
|
66 | nRTS2 : IN STD_LOGIC; | |||
|
67 | nDCD2 : OUT STD_LOGIC; | |||
|
68 | ||||
|
69 | --EXT CONNECTOR | |||
|
70 | IO0 : INOUT STD_LOGIC; | |||
|
71 | IO1 : INOUT STD_LOGIC; | |||
|
72 | IO2 : INOUT STD_LOGIC; | |||
|
73 | IO3 : INOUT STD_LOGIC; | |||
|
74 | IO4 : INOUT STD_LOGIC; | |||
|
75 | IO5 : INOUT STD_LOGIC; | |||
|
76 | IO6 : INOUT STD_LOGIC; | |||
|
77 | IO7 : INOUT STD_LOGIC; | |||
|
78 | IO8 : INOUT STD_LOGIC; | |||
|
79 | IO9 : INOUT STD_LOGIC; | |||
|
80 | IO10 : INOUT STD_LOGIC; | |||
|
81 | IO11 : INOUT STD_LOGIC; | |||
|
82 | ||||
|
83 | --SPACE WIRE | |||
|
84 | SPW_EN : OUT STD_LOGIC; -- 0 => off | |||
|
85 | SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK | |||
|
86 | SPW_NOM_SIN : IN STD_LOGIC; | |||
|
87 | SPW_NOM_DOUT : OUT STD_LOGIC; | |||
|
88 | SPW_NOM_SOUT : OUT STD_LOGIC; | |||
|
89 | SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK | |||
|
90 | SPW_RED_SIN : IN STD_LOGIC; | |||
|
91 | SPW_RED_DOUT : OUT STD_LOGIC; | |||
|
92 | SPW_RED_SOUT : OUT STD_LOGIC; | |||
|
93 | -- MINI LFR ADC INPUTS | |||
|
94 | ADC_nCS : OUT STD_LOGIC; | |||
|
95 | ADC_CLK : OUT STD_LOGIC; | |||
|
96 | ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |||
|
97 | ||||
|
98 | -- SRAM | |||
|
99 | SRAM_nWE : OUT STD_LOGIC; | |||
|
100 | SRAM_CE : OUT STD_LOGIC; | |||
|
101 | SRAM_nOE : OUT STD_LOGIC; | |||
|
102 | SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
103 | SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); | |||
|
104 | SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |||
|
105 | ); | |||
|
106 | ||||
|
107 | END MINI_LFR_top; | |||
|
108 | ||||
|
109 | ||||
|
110 | ARCHITECTURE beh OF MINI_LFR_top IS | |||
|
111 | SIGNAL clk_50_s : STD_LOGIC := '0'; | |||
|
112 | SIGNAL clk_25 : STD_LOGIC := '0'; | |||
|
113 | ----------------------------------------------------------------------------- | |||
|
114 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
115 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); | |||
|
116 | -- | |||
|
117 | SIGNAL errorn : STD_LOGIC; | |||
|
118 | -- UART AHB --------------------------------------------------------------- | |||
|
119 | SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data | |||
|
120 | SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data | |||
|
121 | ||||
|
122 | -- UART APB --------------------------------------------------------------- | |||
|
123 | SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data | |||
|
124 | SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data | |||
|
125 | -- | |||
|
126 | SIGNAL I00_s : STD_LOGIC; | |||
|
127 | -- | |||
|
128 | CONSTANT NB_APB_SLAVE : INTEGER := 1; | |||
|
129 | CONSTANT NB_AHB_SLAVE : INTEGER := 1; | |||
|
130 | CONSTANT NB_AHB_MASTER : INTEGER := 1; | |||
|
131 | ||||
|
132 | SIGNAL apbi_ext : apb_slv_in_type; | |||
|
133 | SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5):= (OTHERS => apb_none); | |||
|
134 | SIGNAL ahbi_s_ext : ahb_slv_in_type; | |||
|
135 | SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3):= (OTHERS => ahbs_none); | |||
|
136 | SIGNAL ahbi_m_ext : AHB_Mst_In_Type; | |||
|
137 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1):= (OTHERS => ahbm_none); | |||
|
138 | ||||
|
139 | BEGIN -- beh | |||
|
140 | ||||
|
141 | ----------------------------------------------------------------------------- | |||
|
142 | -- CLK | |||
|
143 | ----------------------------------------------------------------------------- | |||
|
144 | ||||
|
145 | PROCESS(clk_50) | |||
|
146 | BEGIN | |||
|
147 | IF clk_50'EVENT AND clk_50 = '1' THEN | |||
|
148 | clk_50_s <= NOT clk_50_s; | |||
|
149 | END IF; | |||
|
150 | END PROCESS; | |||
|
151 | ||||
|
152 | PROCESS(clk_50_s) | |||
|
153 | BEGIN | |||
|
154 | IF clk_50_s'EVENT AND clk_50_s = '1' THEN | |||
|
155 | clk_25 <= NOT clk_25; | |||
|
156 | END IF; | |||
|
157 | END PROCESS; | |||
|
158 | ||||
|
159 | ----------------------------------------------------------------------------- | |||
|
160 | ||||
|
161 | PROCESS (clk_25, reset) | |||
|
162 | BEGIN -- PROCESS | |||
|
163 | IF reset = '0' THEN -- asynchronous reset (active low) | |||
|
164 | LED0 <= '0'; | |||
|
165 | LED1 <= '0'; | |||
|
166 | LED2 <= '0'; | |||
|
167 | IO1 <= '0'; | |||
|
168 | IO2 <= '1'; | |||
|
169 | IO3 <= '0'; | |||
|
170 | IO4 <= '0'; | |||
|
171 | IO5 <= '0'; | |||
|
172 | IO6 <= '0'; | |||
|
173 | IO7 <= '0'; | |||
|
174 | IO8 <= '0'; | |||
|
175 | IO9 <= '0'; | |||
|
176 | IO10 <= '0'; | |||
|
177 | IO11 <= '0'; | |||
|
178 | ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge | |||
|
179 | LED0 <= '0'; | |||
|
180 | LED1 <= '1'; | |||
|
181 | LED2 <= BP0; | |||
|
182 | IO1 <= '1'; | |||
|
183 | IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN; | |||
|
184 | IO3 <= ADC_SDO(0); | |||
|
185 | IO4 <= ADC_SDO(1); | |||
|
186 | IO5 <= ADC_SDO(2); | |||
|
187 | IO6 <= ADC_SDO(3); | |||
|
188 | IO7 <= ADC_SDO(4); | |||
|
189 | IO8 <= ADC_SDO(5); | |||
|
190 | IO9 <= ADC_SDO(6); | |||
|
191 | IO10 <= ADC_SDO(7); | |||
|
192 | IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1; | |||
|
193 | END IF; | |||
|
194 | END PROCESS; | |||
|
195 | ||||
|
196 | PROCESS (clk_49, reset) | |||
|
197 | BEGIN -- PROCESS | |||
|
198 | IF reset = '0' THEN -- asynchronous reset (active low) | |||
|
199 | I00_s <= '0'; | |||
|
200 | ELSIF clk_49'event AND clk_49 = '1' THEN -- rising clock edge | |||
|
201 | I00_s <= NOT I00_s; | |||
|
202 | END IF; | |||
|
203 | END PROCESS; | |||
|
204 | IO0 <= I00_s; | |||
|
205 | ||||
|
206 | --UARTs | |||
|
207 | nCTS1 <= '1'; | |||
|
208 | nCTS2 <= '1'; | |||
|
209 | nDCD2 <= '1'; | |||
|
210 | ||||
|
211 | --EXT CONNECTOR | |||
|
212 | ||||
|
213 | --SPACE WIRE | |||
|
214 | SPW_EN <= '0'; -- 0 => off | |||
|
215 | ||||
|
216 | SPW_NOM_DOUT <= '0'; | |||
|
217 | SPW_NOM_SOUT <= '0'; | |||
|
218 | SPW_RED_DOUT <= '0'; | |||
|
219 | SPW_RED_SOUT <= '0'; | |||
|
220 | ||||
|
221 | ADC_nCS <= '0'; | |||
|
222 | ADC_CLK <= '0'; | |||
|
223 | ||||
|
224 | ||||
|
225 | leon3_soc_1: leon3_soc_LPP_JCP | |||
|
226 | GENERIC MAP ( | |||
|
227 | fabtech => apa3e, | |||
|
228 | memtech => apa3e, | |||
|
229 | padtech => inferred, | |||
|
230 | clktech => inferred, | |||
|
231 | disas => 0, | |||
|
232 | dbguart => 0, | |||
|
233 | pclow => 2, | |||
|
234 | clk_freq => 25000, | |||
|
235 | NB_CPU => 1, | |||
|
236 | ENABLE_FPU => 0, | |||
|
237 | FPU_NETLIST => 0, | |||
|
238 | ENABLE_DSU => 1, | |||
|
239 | ENABLE_AHB_UART => 1, | |||
|
240 | ENABLE_APB_UART => 1, | |||
|
241 | ENABLE_IRQMP => 1, | |||
|
242 | ENABLE_GPT => 1, | |||
|
243 | NB_AHB_MASTER => NB_AHB_MASTER, | |||
|
244 | NB_AHB_SLAVE => NB_AHB_SLAVE, | |||
|
245 | NB_APB_SLAVE => NB_APB_SLAVE) | |||
|
246 | PORT MAP ( | |||
|
247 | clk => clk_25, | |||
|
248 | rstn => reset, | |||
|
249 | errorn => errorn, | |||
|
250 | ahbrxd => TXD1, | |||
|
251 | ahbtxd => RXD1, | |||
|
252 | urxd1 => TXD2, | |||
|
253 | utxd1 => RXD2, | |||
|
254 | address => SRAM_A, | |||
|
255 | data => SRAM_DQ, | |||
|
256 | nSRAM_BE0 => SRAM_nBE(0), | |||
|
257 | nSRAM_BE1 => SRAM_nBE(1), | |||
|
258 | nSRAM_BE2 => SRAM_nBE(2), | |||
|
259 | nSRAM_BE3 => SRAM_nBE(3), | |||
|
260 | nSRAM_WE => SRAM_nWE, | |||
|
261 | nSRAM_CE => SRAM_CE, | |||
|
262 | nSRAM_OE => SRAM_nOE, | |||
|
263 | ||||
|
264 | apbi_ext => apbi_ext, | |||
|
265 | apbo_ext => apbo_ext, | |||
|
266 | ahbi_s_ext => ahbi_s_ext, | |||
|
267 | ahbo_s_ext => ahbo_s_ext, | |||
|
268 | ahbi_m_ext => ahbi_m_ext, | |||
|
269 | ahbo_m_ext => ahbo_m_ext); | |||
|
270 | ||||
|
271 | END beh; |
@@ -0,0 +1,55 | |||||
|
1 | ##------------------------------------------------------------------------------ | |||
|
2 | ##-- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | ##-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
4 | ##-- | |||
|
5 | ##-- This program is free software; you can redistribute it and/or modify | |||
|
6 | ##-- it under the terms of the GNU General Public License as published by | |||
|
7 | ##-- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | ##-- (at your option) any later version. | |||
|
9 | ##-- | |||
|
10 | ##-- This program is distributed in the hope that it will be useful, | |||
|
11 | ##-- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | ##-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | ##-- GNU General Public License for more details. | |||
|
14 | ##-- | |||
|
15 | ##-- You should have received a copy of the GNU General Public License | |||
|
16 | ##-- along with this program; if not, write to the Free Software | |||
|
17 | ##-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | ##------------------------------------------------------------------------------- | |||
|
19 | ##-- Author : Jean-christophe Pellion | |||
|
20 | ##-- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |||
|
21 | ##-- jean-christophe.pellion@easii-ic.com | |||
|
22 | ##------------------------------------------------------------------------------- | |||
|
23 | VHDLIB=../.. | |||
|
24 | SCRIPTSDIR=$(VHDLIB)/scripts/ | |||
|
25 | GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) | |||
|
26 | TOP=MINI_LFR_top | |||
|
27 | BOARD=MINI-LFR | |||
|
28 | include $(VHDLIB)/boards/$(BOARD)/Makefile.inc | |||
|
29 | DEVICE=$(PART)-$(PACKAGE)$(SPEED) | |||
|
30 | UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf | |||
|
31 | QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf | |||
|
32 | EFFORT=high | |||
|
33 | XSTOPT= | |||
|
34 | SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" | |||
|
35 | VHDLSYNFILES= MINI_LFR_top.vhd | |||
|
36 | ||||
|
37 | PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc | |||
|
38 | BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut | |||
|
39 | CLEAN=soft-clean | |||
|
40 | ||||
|
41 | TECHLIBS = proasic3e | |||
|
42 | ||||
|
43 | LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ | |||
|
44 | tmtc openchip hynix ihp gleichmann micron usbhc | |||
|
45 | ||||
|
46 | DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ | |||
|
47 | pci grusbhc haps slink ascs pwm coremp7 spi ac97 | |||
|
48 | ||||
|
49 | FILESKIP = | |||
|
50 | ||||
|
51 | include $(GRLIB)/bin/Makefile | |||
|
52 | include $(GRLIB)/software/leon3/Makefile | |||
|
53 | ||||
|
54 | ################## project specific targets ########################## | |||
|
55 |
@@ -0,0 +1,1 | |||||
|
1 | ./LPP/JCP/SOC |
@@ -1,80 +1,79 | |||||
1 | SCRIPTSDIR=scripts/ |
|
1 | SCRIPTSDIR=scripts/ | |
2 | LIBDIR=lib/ |
|
2 | LIBDIR=lib/ | |
3 | BOARDSDIR=boards/ |
|
3 | BOARDSDIR=boards/ | |
4 | DESIGNSDIR=designs/ |
|
4 | DESIGNSDIR=designs/ | |
5 |
|
5 | |||
6 |
|
6 | |||
7 | .PHONY:doc |
|
7 | .PHONY:doc | |
8 |
|
8 | |||
9 |
|
9 | |||
10 | all: help |
|
10 | all: help | |
11 |
|
11 | |||
12 | help: |
|
12 | help: | |
13 | @echo |
|
13 | @echo | |
14 | @echo " batch targets:" |
|
14 | @echo " batch targets:" | |
15 | @echo |
|
15 | @echo | |
16 | @echo " make link : link lpp library to GRLIB at : $(GRLIB)" |
|
16 | @echo " make link : link lpp library to GRLIB at : $(GRLIB)" | |
17 | @echo " make Patch-GRLIB : install library into GRLIB at : $(GRLIB)" |
|
17 | @echo " make Patch-GRLIB : install library into GRLIB at : $(GRLIB)" | |
18 | @echo " make dist : create a tar file for using into an other computer" |
|
18 | @echo " make dist : create a tar file for using into an other computer" | |
19 | @echo " make Patched-dist : create a tar file for with a patched grlib for using" |
|
19 | @echo " make Patched-dist : create a tar file for with a patched grlib for using" | |
20 | @echo " into an other computer" |
|
20 | @echo " into an other computer" | |
21 | @echo " make allGPL : add a GPL HEADER in all vhdl Files" |
|
21 | @echo " make allGPL : add a GPL HEADER in all vhdl Files" | |
22 | @echo " make init : add a GPL HEADER in all vhdl Files, init all files" |
|
22 | @echo " make init : add a GPL HEADER in all vhdl Files, init all files" | |
23 | @echo " make doc : make documentation for VHDL IPs" |
|
23 | @echo " make doc : make documentation for VHDL IPs" | |
24 | @echo " make pdf : make pdf documentation for VHDL IPs" |
|
24 | @echo " make pdf : make pdf documentation for VHDL IPs" | |
25 | @echo " make C-libs : make C drivers for APB devices" |
|
25 | @echo " make C-libs : make C drivers for APB devices" | |
26 | @echo " binary files availiable on VHD_Lib/LPP_DRIVERS/lib ./includes" |
|
26 | @echo " binary files availiable on VHD_Lib/LPP_DRIVERS/lib ./includes" | |
27 | @echo |
|
27 | @echo | |
28 |
|
28 | |||
29 |
|
29 | |||
30 |
|
30 | |||
31 | allGPL: |
|
31 | allGPL: | |
32 | @echo "Scanning VHDL files ..." |
|
32 | @echo "Scanning VHDL files ..." | |
33 | sh $(SCRIPTSDIR)/GPL_Patcher.sh -R vhd lib |
|
33 | sh $(SCRIPTSDIR)/GPL_Patcher.sh -R vhd lib | |
34 | @echo "Scanning C files ..." |
|
34 | @echo "Scanning C files ..." | |
35 | sh $(SCRIPTSDIR)/GPL_Patcher.sh -R c LPP_drivers |
|
35 | sh $(SCRIPTSDIR)/GPL_Patcher.sh -R c LPP_drivers | |
36 | @echo "Scanning H files ..." |
|
36 | @echo "Scanning H files ..." | |
37 | sh $(SCRIPTSDIR)/GPL_Patcher.sh -R h LPP_drivers |
|
37 | sh $(SCRIPTSDIR)/GPL_Patcher.sh -R h LPP_drivers | |
38 |
|
38 | |||
39 | init: C-libs |
|
39 | init: C-libs | |
40 | sh $(SCRIPTSDIR)/vhdlsynPatcher.sh |
|
40 | sh $(SCRIPTSDIR)/vhdlsynPatcher.sh | |
41 | sh $(SCRIPTSDIR)/makeDirs.sh lib/lpp |
|
41 | sh $(SCRIPTSDIR)/makeDirs.sh lib/lpp | |
42 |
|
42 | |||
43 | C-libs:APB_devs |
|
43 | C-libs:APB_devs | |
44 | make -C LPP_drivers |
|
44 | make -C LPP_drivers | |
45 |
|
45 | |||
46 |
|
46 | |||
47 | APB_devs: |
|
47 | APB_devs: | |
48 | sh $(SCRIPTSDIR)/APB_DEV_UPDATER.sh |
|
48 | sh $(SCRIPTSDIR)/APB_DEV_UPDATER.sh | |
49 |
|
49 | |||
50 |
|
50 | |||
51 | Patch-GRLIB: init doc |
|
51 | Patch-GRLIB: init doc | |
52 | sh $(SCRIPTSDIR)/patch.sh $(GRLIB) |
|
52 | sh $(SCRIPTSDIR)/patch.sh $(GRLIB) | |
53 |
|
53 | |||
54 | link: |
|
54 | link: | |
55 | sh $(SCRIPTSDIR)/vhdlsynPatcher.sh |
|
|||
56 | sh $(SCRIPTSDIR)/linklibs.sh $(GRLIB) |
|
55 | sh $(SCRIPTSDIR)/linklibs.sh $(GRLIB) | |
57 |
|
56 | |||
58 | dist: init |
|
57 | dist: init | |
59 | tar -cvzf ./../lpp-lib.tgz ./../VHD_Lib/* |
|
58 | tar -cvzf ./../lpp-lib.tgz ./../VHD_Lib/* | |
60 |
|
59 | |||
61 |
|
60 | |||
62 | Patched-dist: Patch-GRLIB |
|
61 | Patched-dist: Patch-GRLIB | |
63 | tar -cvzf ./../lpp-patched-GRLIB.tgz $(GRLIB)/* |
|
62 | tar -cvzf ./../lpp-patched-GRLIB.tgz $(GRLIB)/* | |
64 |
|
63 | |||
65 |
|
64 | |||
66 | doc: |
|
65 | doc: | |
67 | mkdir -p doc/html |
|
66 | mkdir -p doc/html | |
68 | cp doc/ressources/*.jpg doc/html/ |
|
67 | cp doc/ressources/*.jpg doc/html/ | |
69 | cp doc/ressources/doxygen.css doc/html/ |
|
68 | cp doc/ressources/doxygen.css doc/html/ | |
70 | make -C lib/lpp doc |
|
69 | make -C lib/lpp doc | |
71 | make -C LPP_drivers doc |
|
70 | make -C LPP_drivers doc | |
72 |
|
71 | |||
73 |
|
72 | |||
74 | pdf: doc |
|
73 | pdf: doc | |
75 | sh $(SCRIPTSDIR)/doc.sh |
|
74 | sh $(SCRIPTSDIR)/doc.sh | |
76 |
|
75 | |||
77 |
|
76 | |||
78 |
|
77 | |||
79 |
|
78 | |||
80 |
|
79 |
@@ -1,75 +1,81 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2013, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2013, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 2 of the License, or |
|
7 | -- the Free Software Foundation; either version 2 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
19 | -- Author : Jean-christophe Pellion |
|
19 | -- Author : Jean-christophe Pellion | |
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
21 | -- jean-christophe.pellion@easii-ic.com |
|
21 | -- jean-christophe.pellion@easii-ic.com | |
22 | ---------------------------------------------------------------------------- |
|
22 | ------------------------------------------------------------------------------- | |
23 |
|
23 | |||
24 | LIBRARY ieee; |
|
24 | LIBRARY ieee; | |
25 | USE ieee.std_logic_1164.ALL; |
|
25 | USE ieee.std_logic_1164.ALL; | |
|
26 | LIBRARY grlib; | |||
|
27 | USE grlib.amba.ALL; | |||
26 |
|
28 | |||
27 |
PACKAGE SOC_ |
|
29 | PACKAGE SOC_LPP_JCP IS | |
28 |
|
30 | |||
29 | COMPONENT leon3_soc__LPP_JCP |
|
31 | type soc_ahb_mst_out_vector is array (natural range <>) of ahb_mst_out_type; | |
|
32 | type soc_ahb_slv_out_vector is array (natural range <>) of ahb_slv_out_type; | |||
|
33 | type soc_apb_slv_out_vector is array (natural range <>) of apb_slv_out_type; | |||
|
34 | ||||
|
35 | COMPONENT leon3_soc_LPP_JCP | |||
30 | GENERIC ( |
|
36 | GENERIC ( | |
31 | fabtech : INTEGER; |
|
37 | fabtech : INTEGER; | |
32 | memtech : INTEGER; |
|
38 | memtech : INTEGER; | |
33 | padtech : INTEGER; |
|
39 | padtech : INTEGER; | |
34 | clktech : INTEGER; |
|
40 | clktech : INTEGER; | |
35 | disas : INTEGER; |
|
41 | disas : INTEGER; | |
36 | dbguart : INTEGER; |
|
42 | dbguart : INTEGER; | |
37 | pclow : INTEGER; |
|
43 | pclow : INTEGER; | |
38 | clk_freq : INTEGER; |
|
44 | clk_freq : INTEGER; | |
39 | NB_CPU : INTEGER; |
|
45 | NB_CPU : INTEGER; | |
40 | ENABLE_FPU : INTEGER; |
|
46 | ENABLE_FPU : INTEGER; | |
41 | FPU_NETLIST : INTEGER; |
|
47 | FPU_NETLIST : INTEGER; | |
42 | ENABLE_DSU : INTEGER; |
|
48 | ENABLE_DSU : INTEGER; | |
43 | ENABLE_AHB_UART : INTEGER; |
|
49 | ENABLE_AHB_UART : INTEGER; | |
44 | ENABLE_APB_UART : INTEGER; |
|
50 | ENABLE_APB_UART : INTEGER; | |
45 | ENABLE_IRQMP : INTEGER; |
|
51 | ENABLE_IRQMP : INTEGER; | |
46 | ENABLE_GPT : INTEGER; |
|
52 | ENABLE_GPT : INTEGER; | |
47 | NB_AHB_MASTER : INTEGER; |
|
53 | NB_AHB_MASTER : INTEGER; | |
48 | NB_AHB_SLAVE : INTEGER; |
|
54 | NB_AHB_SLAVE : INTEGER; | |
49 | NB_APB_SLAVE : INTEGER); |
|
55 | NB_APB_SLAVE : INTEGER); | |
50 | PORT ( |
|
56 | PORT ( | |
51 | clk : IN STD_ULOGIC; |
|
57 | clk : IN STD_ULOGIC; | |
52 | rstn : IN STD_ULOGIC; |
|
58 | rstn : IN STD_ULOGIC; | |
53 | errorn : OUT STD_ULOGIC; |
|
59 | errorn : OUT STD_ULOGIC; | |
54 | ahbrxd : IN STD_ULOGIC; |
|
60 | ahbrxd : IN STD_ULOGIC; | |
55 | ahbtxd : OUT STD_ULOGIC; |
|
61 | ahbtxd : OUT STD_ULOGIC; | |
56 | urxd1 : IN STD_ULOGIC; |
|
62 | urxd1 : IN STD_ULOGIC; | |
57 | utxd1 : OUT STD_ULOGIC; |
|
63 | utxd1 : OUT STD_ULOGIC; | |
58 | address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); |
|
64 | address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); | |
59 | data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
65 | data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
60 | nSRAM_BE0 : OUT STD_LOGIC; |
|
66 | nSRAM_BE0 : OUT STD_LOGIC; | |
61 | nSRAM_BE1 : OUT STD_LOGIC; |
|
67 | nSRAM_BE1 : OUT STD_LOGIC; | |
62 | nSRAM_BE2 : OUT STD_LOGIC; |
|
68 | nSRAM_BE2 : OUT STD_LOGIC; | |
63 | nSRAM_BE3 : OUT STD_LOGIC; |
|
69 | nSRAM_BE3 : OUT STD_LOGIC; | |
64 | nSRAM_WE : OUT STD_LOGIC; |
|
70 | nSRAM_WE : OUT STD_LOGIC; | |
65 | nSRAM_CE : OUT STD_LOGIC; |
|
71 | nSRAM_CE : OUT STD_LOGIC; | |
66 | nSRAM_OE : OUT STD_LOGIC; |
|
72 | nSRAM_OE : OUT STD_LOGIC; | |
67 | apbi_ext : OUT apb_slv_in_type; |
|
73 | apbi_ext : OUT apb_slv_in_type; | |
68 | apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); |
|
74 | apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); | |
69 | ahbi_s_ext : OUT ahb_slv_in_type; |
|
75 | ahbi_s_ext : OUT ahb_slv_in_type; | |
70 | ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); |
|
76 | ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); | |
71 | ahbi_m_ext : OUT AHB_Mst_In_Type; |
|
77 | ahbi_m_ext : OUT AHB_Mst_In_Type; | |
72 | ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU)); |
|
78 | ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU)); | |
73 | END COMPONENT; |
|
79 | END COMPONENT; | |
74 |
|
80 | |||
75 | END; |
|
81 | END; |
@@ -1,421 +1,423 | |||||
1 | ----------------------------------------------------------------------------- |
|
1 | ----------------------------------------------------------------------------- | |
2 | -- LEON3 Demonstration design |
|
2 | -- LEON3 Demonstration design | |
3 | -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research |
|
3 | -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 2 of the License, or |
|
7 | -- the Free Software Foundation; either version 2 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------ |
|
18 | ------------------------------------------------------------------------------ | |
19 | -- Author : Jean-christophe Pellion |
|
19 | -- Author : Jean-christophe Pellion | |
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
21 | -- jean-christophe.pellion@easii-ic.com |
|
21 | -- jean-christophe.pellion@easii-ic.com | |
22 | ------------------------------------------------------------------------------- |
|
22 | ------------------------------------------------------------------------------- | |
23 |
|
23 | |||
24 | LIBRARY ieee; |
|
24 | LIBRARY ieee; | |
25 | USE ieee.std_logic_1164.ALL; |
|
25 | USE ieee.std_logic_1164.ALL; | |
26 | LIBRARY grlib; |
|
26 | LIBRARY grlib; | |
27 | USE grlib.amba.ALL; |
|
27 | USE grlib.amba.ALL; | |
28 | USE grlib.stdlib.ALL; |
|
28 | USE grlib.stdlib.ALL; | |
29 | LIBRARY techmap; |
|
29 | LIBRARY techmap; | |
30 | USE techmap.gencomp.ALL; |
|
30 | USE techmap.gencomp.ALL; | |
31 | LIBRARY gaisler; |
|
31 | LIBRARY gaisler; | |
32 | USE gaisler.memctrl.ALL; |
|
32 | USE gaisler.memctrl.ALL; | |
33 | USE gaisler.leon3.ALL; |
|
33 | USE gaisler.leon3.ALL; | |
34 | USE gaisler.uart.ALL; |
|
34 | USE gaisler.uart.ALL; | |
35 | USE gaisler.misc.ALL; |
|
35 | USE gaisler.misc.ALL; | |
36 | USE gaisler.spacewire.ALL; |
|
36 | USE gaisler.spacewire.ALL; | |
37 | LIBRARY esa; |
|
37 | LIBRARY esa; | |
38 | USE esa.memoryctrl.ALL; |
|
38 | USE esa.memoryctrl.ALL; | |
|
39 | LIBRARY staging; | |||
|
40 | USE staging.SOC_LPP_JCP.ALL; | |||
39 |
|
41 | |||
40 |
ENTITY leon3_soc_ |
|
42 | ENTITY leon3_soc_LPP_JCP IS | |
41 | GENERIC ( |
|
43 | GENERIC ( | |
42 | fabtech : INTEGER := apa3e; |
|
44 | fabtech : INTEGER := apa3e; | |
43 | memtech : INTEGER := apa3e; |
|
45 | memtech : INTEGER := apa3e; | |
44 | padtech : INTEGER := inferred; |
|
46 | padtech : INTEGER := inferred; | |
45 | clktech : INTEGER := inferred; |
|
47 | clktech : INTEGER := inferred; | |
46 | disas : INTEGER := 0; -- Enable disassembly to console |
|
48 | disas : INTEGER := 0; -- Enable disassembly to console | |
47 | dbguart : INTEGER := 0; -- Print UART on console |
|
49 | dbguart : INTEGER := 0; -- Print UART on console | |
48 | pclow : INTEGER := 2; |
|
50 | pclow : INTEGER := 2; | |
49 | -- |
|
51 | -- | |
50 | clk_freq : INTEGER := 25000; --kHz |
|
52 | clk_freq : INTEGER := 25000; --kHz | |
51 | -- |
|
53 | -- | |
52 | NB_CPU : INTEGER := 1; |
|
54 | NB_CPU : INTEGER := 1; | |
53 | ENABLE_FPU : INTEGER := 1; |
|
55 | ENABLE_FPU : INTEGER := 1; | |
54 | FPU_NETLIST : INTEGER := 1; |
|
56 | FPU_NETLIST : INTEGER := 1; | |
55 | ENABLE_DSU : INTEGER := 1; |
|
57 | ENABLE_DSU : INTEGER := 1; | |
56 | ENABLE_AHB_UART : INTEGER := 1; |
|
58 | ENABLE_AHB_UART : INTEGER := 1; | |
57 | ENABLE_APB_UART : INTEGER := 1; |
|
59 | ENABLE_APB_UART : INTEGER := 1; | |
58 | ENABLE_IRQMP : INTEGER := 1; |
|
60 | ENABLE_IRQMP : INTEGER := 1; | |
59 | ENABLE_GPT : INTEGER := 1; |
|
61 | ENABLE_GPT : INTEGER := 1; | |
60 | -- |
|
62 | -- | |
61 | NB_AHB_MASTER : INTEGER := 0; |
|
63 | NB_AHB_MASTER : INTEGER := 0; | |
62 | NB_AHB_SLAVE : INTEGER := 0; |
|
64 | NB_AHB_SLAVE : INTEGER := 0; | |
63 | NB_APB_SLAVE : INTEGER := 0 |
|
65 | NB_APB_SLAVE : INTEGER := 0 | |
64 | ); |
|
66 | ); | |
65 | PORT ( |
|
67 | PORT ( | |
66 | clk : IN STD_ULOGIC; |
|
68 | clk : IN STD_ULOGIC; | |
67 | rstn : IN STD_ULOGIC; |
|
69 | rstn : IN STD_ULOGIC; | |
68 |
|
70 | |||
69 | errorn : OUT STD_ULOGIC; |
|
71 | errorn : OUT STD_ULOGIC; | |
70 |
|
72 | |||
71 | -- UART AHB --------------------------------------------------------------- |
|
73 | -- UART AHB --------------------------------------------------------------- | |
72 | ahbrxd : IN STD_ULOGIC; -- DSU rx data |
|
74 | ahbrxd : IN STD_ULOGIC; -- DSU rx data | |
73 | ahbtxd : OUT STD_ULOGIC; -- DSU tx data |
|
75 | ahbtxd : OUT STD_ULOGIC; -- DSU tx data | |
74 |
|
76 | |||
75 | -- UART APB --------------------------------------------------------------- |
|
77 | -- UART APB --------------------------------------------------------------- | |
76 | urxd1 : IN STD_ULOGIC; -- UART1 rx data |
|
78 | urxd1 : IN STD_ULOGIC; -- UART1 rx data | |
77 | utxd1 : OUT STD_ULOGIC; -- UART1 tx data |
|
79 | utxd1 : OUT STD_ULOGIC; -- UART1 tx data | |
78 |
|
80 | |||
79 | -- RAM -------------------------------------------------------------------- |
|
81 | -- RAM -------------------------------------------------------------------- | |
80 | address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); |
|
82 | address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); | |
81 | data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
83 | data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
82 | nSRAM_BE0 : OUT STD_LOGIC; |
|
84 | nSRAM_BE0 : OUT STD_LOGIC; | |
83 | nSRAM_BE1 : OUT STD_LOGIC; |
|
85 | nSRAM_BE1 : OUT STD_LOGIC; | |
84 | nSRAM_BE2 : OUT STD_LOGIC; |
|
86 | nSRAM_BE2 : OUT STD_LOGIC; | |
85 | nSRAM_BE3 : OUT STD_LOGIC; |
|
87 | nSRAM_BE3 : OUT STD_LOGIC; | |
86 | nSRAM_WE : OUT STD_LOGIC; |
|
88 | nSRAM_WE : OUT STD_LOGIC; | |
87 | nSRAM_CE : OUT STD_LOGIC; |
|
89 | nSRAM_CE : OUT STD_LOGIC; | |
88 | nSRAM_OE : OUT STD_LOGIC; |
|
90 | nSRAM_OE : OUT STD_LOGIC; | |
89 |
|
91 | |||
90 | -- APB -------------------------------------------------------------------- |
|
92 | -- APB -------------------------------------------------------------------- | |
91 | apbi_ext : OUT apb_slv_in_type; |
|
93 | apbi_ext : OUT apb_slv_in_type; | |
92 | apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); |
|
94 | apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); | |
93 | -- AHB_Slave -------------------------------------------------------------- |
|
95 | -- AHB_Slave -------------------------------------------------------------- | |
94 | ahbi_s_ext : OUT ahb_slv_in_type; |
|
96 | ahbi_s_ext : OUT ahb_slv_in_type; | |
95 | ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); |
|
97 | ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); | |
96 | -- AHB_Master ------------------------------------------------------------- |
|
98 | -- AHB_Master ------------------------------------------------------------- | |
97 | ahbi_m_ext : OUT AHB_Mst_In_Type; |
|
99 | ahbi_m_ext : OUT AHB_Mst_In_Type; | |
98 | ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU) |
|
100 | ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU) | |
99 |
|
101 | |||
100 | ); |
|
102 | ); | |
101 | END; |
|
103 | END; | |
102 |
|
104 | |||
103 |
ARCHITECTURE Behavioral OF leon3_soc_ |
|
105 | ARCHITECTURE Behavioral OF leon3_soc_LPP_JCP IS | |
104 |
|
106 | |||
105 | ----------------------------------------------------------------------------- |
|
107 | ----------------------------------------------------------------------------- | |
106 | -- CONFIG ------------------------------------------------------------------- |
|
108 | -- CONFIG ------------------------------------------------------------------- | |
107 | ----------------------------------------------------------------------------- |
|
109 | ----------------------------------------------------------------------------- | |
108 |
|
110 | |||
109 | -- Clock generator |
|
111 | -- Clock generator | |
110 | CONSTANT CFG_CLKMUL : INTEGER := (1); |
|
112 | CONSTANT CFG_CLKMUL : INTEGER := (1); | |
111 | CONSTANT CFG_CLKDIV : INTEGER := (1); -- divide 50MHz by 2 to get 25MHz |
|
113 | CONSTANT CFG_CLKDIV : INTEGER := (1); -- divide 50MHz by 2 to get 25MHz | |
112 | CONSTANT CFG_OCLKDIV : INTEGER := (1); |
|
114 | CONSTANT CFG_OCLKDIV : INTEGER := (1); | |
113 | CONSTANT CFG_CLK_NOFB : INTEGER := 0; |
|
115 | CONSTANT CFG_CLK_NOFB : INTEGER := 0; | |
114 | -- LEON3 processor core |
|
116 | -- LEON3 processor core | |
115 | CONSTANT CFG_LEON3 : INTEGER := 1; |
|
117 | CONSTANT CFG_LEON3 : INTEGER := 1; | |
116 | CONSTANT CFG_NCPU : INTEGER := NB_CPU; |
|
118 | CONSTANT CFG_NCPU : INTEGER := NB_CPU; | |
117 | CONSTANT CFG_NWIN : INTEGER := (8); -- to be compatible with BCC and RCC |
|
119 | CONSTANT CFG_NWIN : INTEGER := (8); -- to be compatible with BCC and RCC | |
118 | CONSTANT CFG_V8 : INTEGER := 0; |
|
120 | CONSTANT CFG_V8 : INTEGER := 0; | |
119 | CONSTANT CFG_MAC : INTEGER := 0; |
|
121 | CONSTANT CFG_MAC : INTEGER := 0; | |
120 | CONSTANT CFG_SVT : INTEGER := 0; |
|
122 | CONSTANT CFG_SVT : INTEGER := 0; | |
121 | CONSTANT CFG_RSTADDR : INTEGER := 16#00000#; |
|
123 | CONSTANT CFG_RSTADDR : INTEGER := 16#00000#; | |
122 | CONSTANT CFG_LDDEL : INTEGER := (1); |
|
124 | CONSTANT CFG_LDDEL : INTEGER := (1); | |
123 | CONSTANT CFG_NWP : INTEGER := (0); |
|
125 | CONSTANT CFG_NWP : INTEGER := (0); | |
124 | CONSTANT CFG_PWD : INTEGER := 1*2; |
|
126 | CONSTANT CFG_PWD : INTEGER := 1*2; | |
125 | CONSTANT CFG_FPU : INTEGER := ENABLE_FPU *(8 + 16 * FPU_NETLIST); |
|
127 | CONSTANT CFG_FPU : INTEGER := ENABLE_FPU *(8 + 16 * FPU_NETLIST); | |
126 | -- 1*(8 + 16 * 0) => grfpu-light |
|
128 | -- 1*(8 + 16 * 0) => grfpu-light | |
127 | -- 1*(8 + 16 * 1) => netlist |
|
129 | -- 1*(8 + 16 * 1) => netlist | |
128 | -- 0*(8 + 16 * 0) => No FPU |
|
130 | -- 0*(8 + 16 * 0) => No FPU | |
129 | -- 0*(8 + 16 * 1) => No FPU; |
|
131 | -- 0*(8 + 16 * 1) => No FPU; | |
130 | CONSTANT CFG_ICEN : INTEGER := 1; |
|
132 | CONSTANT CFG_ICEN : INTEGER := 1; | |
131 | CONSTANT CFG_ISETS : INTEGER := 1; |
|
133 | CONSTANT CFG_ISETS : INTEGER := 1; | |
132 | CONSTANT CFG_ISETSZ : INTEGER := 4; |
|
134 | CONSTANT CFG_ISETSZ : INTEGER := 4; | |
133 | CONSTANT CFG_ILINE : INTEGER := 4; |
|
135 | CONSTANT CFG_ILINE : INTEGER := 4; | |
134 | CONSTANT CFG_IREPL : INTEGER := 0; |
|
136 | CONSTANT CFG_IREPL : INTEGER := 0; | |
135 | CONSTANT CFG_ILOCK : INTEGER := 0; |
|
137 | CONSTANT CFG_ILOCK : INTEGER := 0; | |
136 | CONSTANT CFG_ILRAMEN : INTEGER := 0; |
|
138 | CONSTANT CFG_ILRAMEN : INTEGER := 0; | |
137 | CONSTANT CFG_ILRAMADDR : INTEGER := 16#8E#; |
|
139 | CONSTANT CFG_ILRAMADDR : INTEGER := 16#8E#; | |
138 | CONSTANT CFG_ILRAMSZ : INTEGER := 1; |
|
140 | CONSTANT CFG_ILRAMSZ : INTEGER := 1; | |
139 | CONSTANT CFG_DCEN : INTEGER := 1; |
|
141 | CONSTANT CFG_DCEN : INTEGER := 1; | |
140 | CONSTANT CFG_DSETS : INTEGER := 1; |
|
142 | CONSTANT CFG_DSETS : INTEGER := 1; | |
141 | CONSTANT CFG_DSETSZ : INTEGER := 4; |
|
143 | CONSTANT CFG_DSETSZ : INTEGER := 4; | |
142 | CONSTANT CFG_DLINE : INTEGER := 4; |
|
144 | CONSTANT CFG_DLINE : INTEGER := 4; | |
143 | CONSTANT CFG_DREPL : INTEGER := 0; |
|
145 | CONSTANT CFG_DREPL : INTEGER := 0; | |
144 | CONSTANT CFG_DLOCK : INTEGER := 0; |
|
146 | CONSTANT CFG_DLOCK : INTEGER := 0; | |
145 | CONSTANT CFG_DSNOOP : INTEGER := 0 + 0 + 4*0; |
|
147 | CONSTANT CFG_DSNOOP : INTEGER := 0 + 0 + 4*0; | |
146 | CONSTANT CFG_DLRAMEN : INTEGER := 0; |
|
148 | CONSTANT CFG_DLRAMEN : INTEGER := 0; | |
147 | CONSTANT CFG_DLRAMADDR : INTEGER := 16#8F#; |
|
149 | CONSTANT CFG_DLRAMADDR : INTEGER := 16#8F#; | |
148 | CONSTANT CFG_DLRAMSZ : INTEGER := 1; |
|
150 | CONSTANT CFG_DLRAMSZ : INTEGER := 1; | |
149 | CONSTANT CFG_MMUEN : INTEGER := 0; |
|
151 | CONSTANT CFG_MMUEN : INTEGER := 0; | |
150 | CONSTANT CFG_ITLBNUM : INTEGER := 2; |
|
152 | CONSTANT CFG_ITLBNUM : INTEGER := 2; | |
151 | CONSTANT CFG_DTLBNUM : INTEGER := 2; |
|
153 | CONSTANT CFG_DTLBNUM : INTEGER := 2; | |
152 | CONSTANT CFG_TLB_TYPE : INTEGER := 1 + 0*2; |
|
154 | CONSTANT CFG_TLB_TYPE : INTEGER := 1 + 0*2; | |
153 | CONSTANT CFG_TLB_REP : INTEGER := 1; |
|
155 | CONSTANT CFG_TLB_REP : INTEGER := 1; | |
154 |
|
156 | |||
155 | CONSTANT CFG_DSU : INTEGER := ENABLE_DSU; |
|
157 | CONSTANT CFG_DSU : INTEGER := ENABLE_DSU; | |
156 | CONSTANT CFG_ITBSZ : INTEGER := 0; |
|
158 | CONSTANT CFG_ITBSZ : INTEGER := 0; | |
157 | CONSTANT CFG_ATBSZ : INTEGER := 0; |
|
159 | CONSTANT CFG_ATBSZ : INTEGER := 0; | |
158 |
|
160 | |||
159 | -- AMBA settings |
|
161 | -- AMBA settings | |
160 | CONSTANT CFG_DEFMST : INTEGER := (0); |
|
162 | CONSTANT CFG_DEFMST : INTEGER := (0); | |
161 | CONSTANT CFG_RROBIN : INTEGER := 1; |
|
163 | CONSTANT CFG_RROBIN : INTEGER := 1; | |
162 | CONSTANT CFG_SPLIT : INTEGER := 0; |
|
164 | CONSTANT CFG_SPLIT : INTEGER := 0; | |
163 | CONSTANT CFG_AHBIO : INTEGER := 16#FFF#; |
|
165 | CONSTANT CFG_AHBIO : INTEGER := 16#FFF#; | |
164 | CONSTANT CFG_APBADDR : INTEGER := 16#800#; |
|
166 | CONSTANT CFG_APBADDR : INTEGER := 16#800#; | |
165 |
|
167 | |||
166 | -- DSU UART |
|
168 | -- DSU UART | |
167 | CONSTANT CFG_AHB_UART : INTEGER := ENABLE_AHB_UART; |
|
169 | CONSTANT CFG_AHB_UART : INTEGER := ENABLE_AHB_UART; | |
168 |
|
170 | |||
169 | -- LEON2 memory controller |
|
171 | -- LEON2 memory controller | |
170 | CONSTANT CFG_MCTRL_SDEN : INTEGER := 0; |
|
172 | CONSTANT CFG_MCTRL_SDEN : INTEGER := 0; | |
171 |
|
173 | |||
172 | -- UART 1 |
|
174 | -- UART 1 | |
173 | CONSTANT CFG_UART1_ENABLE : INTEGER := ENABLE_APB_UART; |
|
175 | CONSTANT CFG_UART1_ENABLE : INTEGER := ENABLE_APB_UART; | |
174 | CONSTANT CFG_UART1_FIFO : INTEGER := 1; |
|
176 | CONSTANT CFG_UART1_FIFO : INTEGER := 1; | |
175 |
|
177 | |||
176 | -- LEON3 interrupt controller |
|
178 | -- LEON3 interrupt controller | |
177 | CONSTANT CFG_IRQ3_ENABLE : INTEGER := ENABLE_IRQMP; |
|
179 | CONSTANT CFG_IRQ3_ENABLE : INTEGER := ENABLE_IRQMP; | |
178 |
|
180 | |||
179 | -- Modular timer |
|
181 | -- Modular timer | |
180 | CONSTANT CFG_GPT_ENABLE : INTEGER := ENABLE_GPT; |
|
182 | CONSTANT CFG_GPT_ENABLE : INTEGER := ENABLE_GPT; | |
181 | CONSTANT CFG_GPT_NTIM : INTEGER := (2); |
|
183 | CONSTANT CFG_GPT_NTIM : INTEGER := (2); | |
182 | CONSTANT CFG_GPT_SW : INTEGER := (8); |
|
184 | CONSTANT CFG_GPT_SW : INTEGER := (8); | |
183 | CONSTANT CFG_GPT_TW : INTEGER := (32); |
|
185 | CONSTANT CFG_GPT_TW : INTEGER := (32); | |
184 | CONSTANT CFG_GPT_IRQ : INTEGER := (8); |
|
186 | CONSTANT CFG_GPT_IRQ : INTEGER := (8); | |
185 | CONSTANT CFG_GPT_SEPIRQ : INTEGER := 1; |
|
187 | CONSTANT CFG_GPT_SEPIRQ : INTEGER := 1; | |
186 | CONSTANT CFG_GPT_WDOGEN : INTEGER := 0; |
|
188 | CONSTANT CFG_GPT_WDOGEN : INTEGER := 0; | |
187 | CONSTANT CFG_GPT_WDOG : INTEGER := 16#0#; |
|
189 | CONSTANT CFG_GPT_WDOG : INTEGER := 16#0#; | |
188 | ----------------------------------------------------------------------------- |
|
190 | ----------------------------------------------------------------------------- | |
189 |
|
191 | |||
190 | ----------------------------------------------------------------------------- |
|
192 | ----------------------------------------------------------------------------- | |
191 | -- SIGNALs |
|
193 | -- SIGNALs | |
192 | ----------------------------------------------------------------------------- |
|
194 | ----------------------------------------------------------------------------- | |
193 | CONSTANT maxahbmsp : INTEGER := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER; |
|
195 | CONSTANT maxahbmsp : INTEGER := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER; | |
194 | -- CLK & RST -- |
|
196 | -- CLK & RST -- | |
195 | SIGNAL clk2x : STD_ULOGIC; |
|
197 | SIGNAL clk2x : STD_ULOGIC; | |
196 | SIGNAL clkmn : STD_ULOGIC; |
|
198 | SIGNAL clkmn : STD_ULOGIC; | |
197 | SIGNAL clkm : STD_ULOGIC; |
|
199 | SIGNAL clkm : STD_ULOGIC; | |
198 | SIGNAL rstn : STD_ULOGIC; |
|
200 | SIGNAL rstn_s : STD_ULOGIC; | |
199 | SIGNAL rstraw : STD_ULOGIC; |
|
201 | SIGNAL rstraw : STD_ULOGIC; | |
200 | SIGNAL pciclk : STD_ULOGIC; |
|
202 | SIGNAL pciclk : STD_ULOGIC; | |
201 | SIGNAL sdclkl : STD_ULOGIC; |
|
203 | SIGNAL sdclkl : STD_ULOGIC; | |
202 | SIGNAL cgi : clkgen_in_type; |
|
204 | SIGNAL cgi : clkgen_in_type; | |
203 | SIGNAL cgo : clkgen_out_type; |
|
205 | SIGNAL cgo : clkgen_out_type; | |
204 | --- AHB / APB |
|
206 | --- AHB / APB | |
205 | SIGNAL apbi : apb_slv_in_type; |
|
207 | SIGNAL apbi : apb_slv_in_type; | |
206 | SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none); |
|
208 | SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none); | |
207 | SIGNAL ahbsi : ahb_slv_in_type; |
|
209 | SIGNAL ahbsi : ahb_slv_in_type; | |
208 | SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none); |
|
210 | SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none); | |
209 | SIGNAL ahbmi : ahb_mst_in_type; |
|
211 | SIGNAL ahbmi : ahb_mst_in_type; | |
210 | SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); |
|
212 | SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); | |
211 | --UART |
|
213 | --UART | |
212 | SIGNAL ahbuarti : uart_in_type; |
|
214 | SIGNAL ahbuarti : uart_in_type; | |
213 | SIGNAL ahbuarto : uart_out_type; |
|
215 | SIGNAL ahbuarto : uart_out_type; | |
214 | SIGNAL apbuarti : uart_in_type; |
|
216 | SIGNAL apbuarti : uart_in_type; | |
215 | SIGNAL apbuarto : uart_out_type; |
|
217 | SIGNAL apbuarto : uart_out_type; | |
216 | --MEM CTRLR |
|
218 | --MEM CTRLR | |
217 | SIGNAL memi : memory_in_type; |
|
219 | SIGNAL memi : memory_in_type; | |
218 | SIGNAL memo : memory_out_type; |
|
220 | SIGNAL memo : memory_out_type; | |
219 | SIGNAL wpo : wprot_out_type; |
|
221 | SIGNAL wpo : wprot_out_type; | |
220 | SIGNAL sdo : sdram_out_type; |
|
222 | SIGNAL sdo : sdram_out_type; | |
221 | --IRQ |
|
223 | --IRQ | |
222 | SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1); |
|
224 | SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1); | |
223 | SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1); |
|
225 | SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1); | |
224 | --Timer |
|
226 | --Timer | |
225 | SIGNAL gpti : gptimer_in_type; |
|
227 | SIGNAL gpti : gptimer_in_type; | |
226 | SIGNAL gpto : gptimer_out_type; |
|
228 | SIGNAL gpto : gptimer_out_type; | |
227 | --DSU |
|
229 | --DSU | |
228 | SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1); |
|
230 | SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1); | |
229 | SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1); |
|
231 | SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1); | |
230 | SIGNAL dsui : dsu_in_type; |
|
232 | SIGNAL dsui : dsu_in_type; | |
231 | SIGNAL dsuo : dsu_out_type; |
|
233 | SIGNAL dsuo : dsu_out_type; | |
232 | ----------------------------------------------------------------------------- |
|
234 | ----------------------------------------------------------------------------- | |
233 |
|
235 | |||
234 | SIGNAL nSRAM_CE_s : STD_LOGIC; |
|
236 | SIGNAL nSRAM_CE_s : STD_LOGIC; | |
235 | BEGIN |
|
237 | BEGIN | |
236 |
|
238 | |||
237 |
|
239 | |||
238 | ---------------------------------------------------------------------- |
|
240 | ---------------------------------------------------------------------- | |
239 | --- Reset and Clock generation ------------------------------------- |
|
241 | --- Reset and Clock generation ------------------------------------- | |
240 | ---------------------------------------------------------------------- |
|
242 | ---------------------------------------------------------------------- | |
241 |
|
243 | |||
242 | cgi.pllctrl <= "00"; |
|
244 | cgi.pllctrl <= "00"; | |
243 | cgi.pllrst <= rstraw; |
|
245 | cgi.pllrst <= rstraw; | |
244 |
|
246 | |||
245 |
rst0 : rstgen PORT MAP (r |
|
247 | rst0 : rstgen PORT MAP (rstn, clkm, cgo.clklock, rstn_s, rstraw); | |
246 |
|
248 | |||
247 | clkgen0 : clkgen -- clock generator |
|
249 | clkgen0 : clkgen -- clock generator | |
248 | GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, |
|
250 | GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, | |
249 | CFG_CLK_NOFB, 0, 0, 0, clk_freq, 0, 0, CFG_OCLKDIV) |
|
251 | CFG_CLK_NOFB, 0, 0, 0, clk_freq, 0, 0, CFG_OCLKDIV) | |
250 | PORT MAP (clk, clk, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo); |
|
252 | PORT MAP (clk, clk, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo); | |
251 |
|
253 | |||
252 | ---------------------------------------------------------------------- |
|
254 | ---------------------------------------------------------------------- | |
253 | --- LEON3 processor / DSU / IRQ ------------------------------------ |
|
255 | --- LEON3 processor / DSU / IRQ ------------------------------------ | |
254 | ---------------------------------------------------------------------- |
|
256 | ---------------------------------------------------------------------- | |
255 |
|
257 | |||
256 | l3 : IF CFG_LEON3 = 1 GENERATE |
|
258 | l3 : IF CFG_LEON3 = 1 GENERATE | |
257 | cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE |
|
259 | cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE | |
258 | u0 : leon3s -- LEON3 processor |
|
260 | u0 : leon3s -- LEON3 processor | |
259 | GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, |
|
261 | GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, | |
260 | 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, |
|
262 | 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, | |
261 | CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, |
|
263 | CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, | |
262 | CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, |
|
264 | CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, | |
263 | CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, |
|
265 | CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, | |
264 | CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1) |
|
266 | CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1) | |
265 | PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, |
|
267 | PORT MAP (clkm, rstn_s, ahbmi, ahbmo(i), ahbsi, ahbso, | |
266 | irqi(i), irqo(i), dbgi(i), dbgo(i)); |
|
268 | irqi(i), irqo(i), dbgi(i), dbgo(i)); | |
267 | END GENERATE; |
|
269 | END GENERATE; | |
268 | errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error); |
|
270 | errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error); | |
269 |
|
271 | |||
270 | dsugen : IF CFG_DSU = 1 GENERATE |
|
272 | dsugen : IF CFG_DSU = 1 GENERATE | |
271 | dsu0 : dsu3 -- LEON3 Debug Support Unit |
|
273 | dsu0 : dsu3 -- LEON3 Debug Support Unit | |
272 | GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#, |
|
274 | GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#, | |
273 | ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) |
|
275 | ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) | |
274 | PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); |
|
276 | PORT MAP (rstn_s, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); | |
275 | dsui.enable <= '1'; |
|
277 | dsui.enable <= '1'; | |
276 | dsui.break <= '0'; |
|
278 | dsui.break <= '0'; | |
277 | END GENERATE; |
|
279 | END GENERATE; | |
278 | END GENERATE; |
|
280 | END GENERATE; | |
279 |
|
281 | |||
280 | nodsu : IF CFG_DSU = 0 GENERATE |
|
282 | nodsu : IF CFG_DSU = 0 GENERATE | |
281 | ahbso(2) <= ahbs_none; |
|
283 | ahbso(2) <= ahbs_none; | |
282 | dsuo.tstop <= '0'; |
|
284 | dsuo.tstop <= '0'; | |
283 | dsuo.active <= '0'; |
|
285 | dsuo.active <= '0'; | |
284 | END GENERATE; |
|
286 | END GENERATE; | |
285 |
|
287 | |||
286 | irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE |
|
288 | irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE | |
287 | irqctrl0 : irqmp -- interrupt controller |
|
289 | irqctrl0 : irqmp -- interrupt controller | |
288 | GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU) |
|
290 | GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU) | |
289 | PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi); |
|
291 | PORT MAP (rstn_s, clkm, apbi, apbo(2), irqo, irqi); | |
290 | END GENERATE; |
|
292 | END GENERATE; | |
291 | irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE |
|
293 | irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE | |
292 | x : FOR i IN 0 TO CFG_NCPU-1 GENERATE |
|
294 | x : FOR i IN 0 TO CFG_NCPU-1 GENERATE | |
293 | irqi(i).irl <= "0000"; |
|
295 | irqi(i).irl <= "0000"; | |
294 | END GENERATE; |
|
296 | END GENERATE; | |
295 | apbo(2) <= apb_none; |
|
297 | apbo(2) <= apb_none; | |
296 | END GENERATE; |
|
298 | END GENERATE; | |
297 |
|
299 | |||
298 | ---------------------------------------------------------------------- |
|
300 | ---------------------------------------------------------------------- | |
299 | --- Memory controllers --------------------------------------------- |
|
301 | --- Memory controllers --------------------------------------------- | |
300 | ---------------------------------------------------------------------- |
|
302 | ---------------------------------------------------------------------- | |
301 | memctrlr : mctrl GENERIC MAP ( |
|
303 | memctrlr : mctrl GENERIC MAP ( | |
302 | hindex => 0, |
|
304 | hindex => 0, | |
303 | pindex => 0, |
|
305 | pindex => 0, | |
304 | paddr => 0, |
|
306 | paddr => 0, | |
305 | srbanks => 1 |
|
307 | srbanks => 1 | |
306 | ) |
|
308 | ) | |
307 | PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); |
|
309 | PORT MAP (rstn_s, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); | |
308 |
|
310 | |||
309 | memi.brdyn <= '1'; |
|
311 | memi.brdyn <= '1'; | |
310 | memi.bexcn <= '1'; |
|
312 | memi.bexcn <= '1'; | |
311 | memi.writen <= '1'; |
|
313 | memi.writen <= '1'; | |
312 | memi.wrn <= "1111"; |
|
314 | memi.wrn <= "1111"; | |
313 | memi.bwidth <= "10"; |
|
315 | memi.bwidth <= "10"; | |
314 |
|
316 | |||
315 | bdr : FOR i IN 0 TO 3 GENERATE |
|
317 | bdr : FOR i IN 0 TO 3 GENERATE | |
316 | data_pad : iopadv GENERIC MAP (tech => padtech, width => 8) |
|
318 | data_pad : iopadv GENERIC MAP (tech => padtech, width => 8) | |
317 | PORT MAP ( |
|
319 | PORT MAP ( | |
318 | data(31-i*8 DOWNTO 24-i*8), |
|
320 | data(31-i*8 DOWNTO 24-i*8), | |
319 | memo.data(31-i*8 DOWNTO 24-i*8), |
|
321 | memo.data(31-i*8 DOWNTO 24-i*8), | |
320 | memo.bdrive(i), |
|
322 | memo.bdrive(i), | |
321 | memi.data(31-i*8 DOWNTO 24-i*8)); |
|
323 | memi.data(31-i*8 DOWNTO 24-i*8)); | |
322 | END GENERATE; |
|
324 | END GENERATE; | |
323 |
|
325 | |||
324 | addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech) |
|
326 | addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech) | |
325 | PORT MAP (address, memo.address(21 DOWNTO 2)); |
|
327 | PORT MAP (address, memo.address(21 DOWNTO 2)); | |
326 | nSRAM_CE_s <= NOT(memo.ramsn(0)); |
|
328 | nSRAM_CE_s <= NOT(memo.ramsn(0)); | |
327 | rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, nSRAM_CE_s); |
|
329 | rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, nSRAM_CE_s); | |
328 | oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0)); |
|
330 | oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0)); | |
329 | nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen); |
|
331 | nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen); | |
330 | nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3)); |
|
332 | nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3)); | |
331 | nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2)); |
|
333 | nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2)); | |
332 | nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1)); |
|
334 | nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1)); | |
333 | nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0)); |
|
335 | nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0)); | |
334 |
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336 | |||
335 | ---------------------------------------------------------------------- |
|
337 | ---------------------------------------------------------------------- | |
336 | --- AHB CONTROLLER ------------------------------------------------- |
|
338 | --- AHB CONTROLLER ------------------------------------------------- | |
337 | ---------------------------------------------------------------------- |
|
339 | ---------------------------------------------------------------------- | |
338 | ahb0 : ahbctrl -- AHB arbiter/multiplexer |
|
340 | ahb0 : ahbctrl -- AHB arbiter/multiplexer | |
339 | GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT, |
|
341 | GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT, | |
340 | rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, |
|
342 | rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, | |
341 | ioen => 0, nahbm => maxahbmsp, nahbs => 8) |
|
343 | ioen => 0, nahbm => maxahbmsp, nahbs => 8) | |
342 | PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); |
|
344 | PORT MAP (rstn_s, clkm, ahbmi, ahbmo, ahbsi, ahbso); | |
343 |
|
345 | |||
344 | ---------------------------------------------------------------------- |
|
346 | ---------------------------------------------------------------------- | |
345 | --- AHB UART ------------------------------------------------------- |
|
347 | --- AHB UART ------------------------------------------------------- | |
346 | ---------------------------------------------------------------------- |
|
348 | ---------------------------------------------------------------------- | |
347 | dcomgen : IF CFG_AHB_UART = 1 GENERATE |
|
349 | dcomgen : IF CFG_AHB_UART = 1 GENERATE | |
348 | dcom0 : ahbuart |
|
350 | dcom0 : ahbuart | |
349 | GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4) |
|
351 | GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4) | |
350 | PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1)); |
|
352 | PORT MAP (rstn_s, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1)); | |
351 | dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd); |
|
353 | dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd); | |
352 | dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd); |
|
354 | dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd); | |
353 | END GENERATE; |
|
355 | END GENERATE; | |
354 | nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE; |
|
356 | nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE; | |
355 |
|
357 | |||
356 | ---------------------------------------------------------------------- |
|
358 | ---------------------------------------------------------------------- | |
357 | --- APB Bridge ----------------------------------------------------- |
|
359 | --- APB Bridge ----------------------------------------------------- | |
358 | ---------------------------------------------------------------------- |
|
360 | ---------------------------------------------------------------------- | |
359 | apb0 : apbctrl -- AHB/APB bridge |
|
361 | apb0 : apbctrl -- AHB/APB bridge | |
360 | GENERIC MAP (hindex => 1, haddr => CFG_APBADDR) |
|
362 | GENERIC MAP (hindex => 1, haddr => CFG_APBADDR) | |
361 | PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo); |
|
363 | PORT MAP (rstn_s, clkm, ahbsi, ahbso(1), apbi, apbo); | |
362 |
|
364 | |||
363 | ---------------------------------------------------------------------- |
|
365 | ---------------------------------------------------------------------- | |
364 | --- GPT Timer ------------------------------------------------------ |
|
366 | --- GPT Timer ------------------------------------------------------ | |
365 | ---------------------------------------------------------------------- |
|
367 | ---------------------------------------------------------------------- | |
366 | gpt : IF CFG_GPT_ENABLE /= 0 GENERATE |
|
368 | gpt : IF CFG_GPT_ENABLE /= 0 GENERATE | |
367 | timer0 : gptimer -- timer unit |
|
369 | timer0 : gptimer -- timer unit | |
368 | GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, |
|
370 | GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, | |
369 | sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, |
|
371 | sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, | |
370 | nbits => CFG_GPT_TW) |
|
372 | nbits => CFG_GPT_TW) | |
371 | PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto); |
|
373 | PORT MAP (rstn_s, clkm, apbi, apbo(3), gpti, gpto); | |
372 | gpti.dhalt <= dsuo.tstop; |
|
374 | gpti.dhalt <= dsuo.tstop; | |
373 | gpti.extclk <= '0'; |
|
375 | gpti.extclk <= '0'; | |
374 | END GENERATE; |
|
376 | END GENERATE; | |
375 | notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE; |
|
377 | notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE; | |
376 |
|
378 | |||
377 |
|
379 | |||
378 | ---------------------------------------------------------------------- |
|
380 | ---------------------------------------------------------------------- | |
379 | --- APB UART ------------------------------------------------------- |
|
381 | --- APB UART ------------------------------------------------------- | |
380 | ---------------------------------------------------------------------- |
|
382 | ---------------------------------------------------------------------- | |
381 | ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE |
|
383 | ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE | |
382 | uart1 : apbuart -- UART 1 |
|
384 | uart1 : apbuart -- UART 1 | |
383 | GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart, |
|
385 | GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart, | |
384 | fifosize => CFG_UART1_FIFO) |
|
386 | fifosize => CFG_UART1_FIFO) | |
385 | PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto); |
|
387 | PORT MAP (rstn_s, clkm, apbi, apbo(1), apbuarti, apbuarto); | |
386 | apbuarti.rxd <= urxd1; |
|
388 | apbuarti.rxd <= urxd1; | |
387 | apbuarti.extclk <= '0'; |
|
389 | apbuarti.extclk <= '0'; | |
388 | utxd1 <= apbuarto.txd; |
|
390 | utxd1 <= apbuarto.txd; | |
389 | apbuarti.ctsn <= '0'; |
|
391 | apbuarti.ctsn <= '0'; | |
390 | END GENERATE; |
|
392 | END GENERATE; | |
391 | noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE; |
|
393 | noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE; | |
392 |
|
394 | |||
393 | ------------------------------------------------------------------------------- |
|
395 | ------------------------------------------------------------------------------- | |
394 | -- AMBA BUS ------------------------------------------------------------------- |
|
396 | -- AMBA BUS ------------------------------------------------------------------- | |
395 | ------------------------------------------------------------------------------- |
|
397 | ------------------------------------------------------------------------------- | |
396 |
|
398 | |||
397 | -- APB -------------------------------------------------------------------- |
|
399 | -- APB -------------------------------------------------------------------- | |
398 | apbi_ext <= apbi; |
|
400 | apbi_ext <= apbi; | |
399 | all_apb : FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE |
|
401 | all_apb : FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE | |
400 | max_16_apb : IF I + 5 < 16 GENERATE |
|
402 | max_16_apb : IF I + 5 < 16 GENERATE | |
401 | apbo(I+5) <= apbo_ext(I+5); |
|
403 | apbo(I+5) <= apbo_ext(I+5); | |
402 | END GENERATE max_16_apb; |
|
404 | END GENERATE max_16_apb; | |
403 | END GENERATE all_apb; |
|
405 | END GENERATE all_apb; | |
404 | -- AHB_Slave -------------------------------------------------------------- |
|
406 | -- AHB_Slave -------------------------------------------------------------- | |
405 | ahbi_s_ext <= ahbsi; |
|
407 | ahbi_s_ext <= ahbsi; | |
406 | all_ahbs : FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE |
|
408 | all_ahbs : FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE | |
407 | max_16_ahbs : IF I + 3 < 16 GENERATE |
|
409 | max_16_ahbs : IF I + 3 < 16 GENERATE | |
408 | ahbso(I+3) <= ahbo_s_ext(I+3); |
|
410 | ahbso(I+3) <= ahbo_s_ext(I+3); | |
409 | END GENERATE max_16_ahbs; |
|
411 | END GENERATE max_16_ahbs; | |
410 | END GENERATE all_ahbs; |
|
412 | END GENERATE all_ahbs; | |
411 | -- AHB_Master ------------------------------------------------------------- |
|
413 | -- AHB_Master ------------------------------------------------------------- | |
412 | ahbi_m_ext <= ahbmi; |
|
414 | ahbi_m_ext <= ahbmi; | |
413 | all_ahbm : FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE |
|
415 | all_ahbm : FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE | |
414 | max_16_ahbm : IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE |
|
416 | max_16_ahbm : IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE | |
415 | ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU); |
|
417 | ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU); | |
416 | END GENERATE max_16_ahbm; |
|
418 | END GENERATE max_16_ahbm; | |
417 | END GENERATE all_ahbm; |
|
419 | END GENERATE all_ahbm; | |
418 |
|
420 | |||
419 |
|
421 | |||
420 |
|
422 | |||
421 | END Behavioral; |
|
423 | END Behavioral; |
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