HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · boards/MINI-LFR/Makefile.inc

MINI-LFR : board and project with leon3_Soc

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             Makefile.inc
        
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      ##------------------------------------------------------------------------------

      ##--  This file is a part of the LPP VHDL IP LIBRARY

      ##--  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS

      ##--

      ##--  This program is free software; you can redistribute it and/or modify

      ##--  it under the terms of the GNU General Public License as published by

      ##--  the Free Software Foundation; either version 3 of the License, or

      ##--  (at your option) any later version.

      ##--

      ##--  This program is distributed in the hope that it will be useful,

      ##--  but WITHOUT ANY WARRANTY; without even the implied warranty of

      ##--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

      ##--  GNU General Public License for more details.

      ##--

      ##--  You should have received a copy of the GNU General Public License

      ##--  along with this program; if not, write to the Free Software

      ##--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 

      ##-------------------------------------------------------------------------------

      ##-- Author : Jean-christophe Pellion

      ##-- Mail   : jean-christophe.pellion@lpp.polytechnique.fr

      ##--          jean-christophe.pellion@easii-ic.com

      ##-------------------------------------------------------------------------------

      PACKAGE=\"\"

      SPEED=Std

      SYNFREQ=50

      TECHNOLOGY=ProASIC3E

      LIBERO_DIE=IT14X14M4

      PART=A3PE3000

      DESIGNER_VOLTAGE=COM

      DESIGNER_TEMP=COM

      DESIGNER_PACKAGE=FBGA

      DESIGNER_PINS=324

      MANUFACTURER=Actel

      MGCTECHNOLOGY=Proasic3

      MGCPART=$(PART)

      MGCPACKAGE= {$(DESIGNER_PINS) $(DESIGNER_PACKAGE)}

      LIBERO_PACKAGE=fg$(DESIGNER_PINS)

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				##------------------------------------------------------------------------------
				##-- This file is a part of the LPP VHDL IP LIBRARY
				##-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
				##--
				##-- This program is free software; you can redistribute it and/or modify
				##-- it under the terms of the GNU General Public License as published by
				##-- the Free Software Foundation; either version 3 of the License, or
				##-- (at your option) any later version.
				##--
				##-- This program is distributed in the hope that it will be useful,
				##-- but WITHOUT ANY WARRANTY; without even the implied warranty of
				##-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
				##-- GNU General Public License for more details.
				##--
				##-- You should have received a copy of the GNU General Public License
				##-- along with this program; if not, write to the Free Software
				##-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
				##-------------------------------------------------------------------------------
				##-- Author : Jean-christophe Pellion
				##-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
				##-- jean-christophe.pellion@easii-ic.com
				##-------------------------------------------------------------------------------

				PACKAGE=\"\"
				SPEED=Std
				SYNFREQ=50

				TECHNOLOGY=ProASIC3E
				LIBERO_DIE=IT14X14M4
				PART=A3PE3000

				DESIGNER_VOLTAGE=COM
				DESIGNER_TEMP=COM
				DESIGNER_PACKAGE=FBGA
				DESIGNER_PINS=324

				MANUFACTURER=Actel
				MGCTECHNOLOGY=Proasic3
				MGCPART=$(PART)
				MGCPACKAGE= {$(DESIGNER_PINS) $(DESIGNER_PACKAGE)}
				LIBERO_PACKAGE=fg$(DESIGNER_PINS)