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MINI-LFR : board and project with leon3_Soc
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1 ##------------------------------------------------------------------------------
2 ##-- This file is a part of the LPP VHDL IP LIBRARY
3 ##-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 ##--
5 ##-- This program is free software; you can redistribute it and/or modify
6 ##-- it under the terms of the GNU General Public License as published by
7 ##-- the Free Software Foundation; either version 3 of the License, or
8 ##-- (at your option) any later version.
9 ##--
10 ##-- This program is distributed in the hope that it will be useful,
11 ##-- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 ##-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 ##-- GNU General Public License for more details.
14 ##--
15 ##-- You should have received a copy of the GNU General Public License
16 ##-- along with this program; if not, write to the Free Software
17 ##-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ##-------------------------------------------------------------------------------
19 ##-- Author : Jean-christophe Pellion
20 ##-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 ##-- jean-christophe.pellion@easii-ic.com
22 ##-------------------------------------------------------------------------------
23
24 PACKAGE=\"\"
25 SPEED=Std
26 SYNFREQ=50
27
28 TECHNOLOGY=ProASIC3E
29 LIBERO_DIE=IT14X14M4
30 PART=A3PE3000
31
32 DESIGNER_VOLTAGE=COM
33 DESIGNER_TEMP=COM
34 DESIGNER_PACKAGE=FBGA
35 DESIGNER_PINS=324
36
37 MANUFACTURER=Actel
38 MGCTECHNOLOGY=Proasic3
39 MGCPART=$(PART)
40 MGCPACKAGE= {$(DESIGNER_PINS) $(DESIGNER_PACKAGE)}
41 LIBERO_PACKAGE=fg$(DESIGNER_PINS)
42
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1 ##------------------------------------------------------------------------------
2 ##-- This file is a part of the LPP VHDL IP LIBRARY
3 ##-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 ##--
5 ##-- This program is free software; you can redistribute it and/or modify
6 ##-- it under the terms of the GNU General Public License as published by
7 ##-- the Free Software Foundation; either version 3 of the License, or
8 ##-- (at your option) any later version.
9 ##--
10 ##-- This program is distributed in the hope that it will be useful,
11 ##-- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 ##-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 ##-- GNU General Public License for more details.
14 ##--
15 ##-- You should have received a copy of the GNU General Public License
16 ##-- along with this program; if not, write to the Free Software
17 ##-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ##-------------------------------------------------------------------------------
19 ##-- Author : Jean-christophe Pellion
20 ##-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 ##-- jean-christophe.pellion@easii-ic.com
22 ##-------------------------------------------------------------------------------
23
24 # Actel Physical design constraints file
25 # Generated file
26
27 # Version: 9.1 SP3 9.1.3.4
28 # Family: ProASIC3L , Die: A3PE3000L , Package: 324 FBGA
29 # Date generated: Tue Oct 18 08:21:45 2011
30
31
32 #
33 # IO banks setting
34 #
35
36
37 #
38 # I/O constraints
39 #
40
41 set_io clk_50 \
42 -pinname F7 \
43 -fixed yes \
44 -DIRECTION Inout
45
46 set_io clk_49 \
47 -pinname K14 \
48 -fixed yes \
49 -DIRECTION Inout
50
51 set_io reset \
52 -pinname T2 \
53 -fixed yes \
54 -DIRECTION Inout
55 #====================================================================
56 # BPs
57 #====================================================================
58 set_io BP0 \
59 -pinname L1 \
60 -fixed yes \
61 -DIRECTION Inout
62
63 set_io BP1 \
64 -pinname R1 \
65 -fixed yes \
66 -DIRECTION Inout
67
68 #====================================================================
69 # LEDs
70 #====================================================================
71
72 set_io LED0 \
73 -pinname V6 \
74 -fixed yes \
75 -DIRECTION Inout
76
77 set_io LED1 \
78 -pinname V5 \
79 -fixed yes \
80 -DIRECTION Inout
81
82 set_io LED2 \
83 -pinname T4 \
84 -fixed yes \
85 -DIRECTION Inout
86
87 #====================================================================
88 # UARTS
89 #====================================================================
90
91 set_io TXD1 \
92 -pinname N17 \
93 -fixed yes \
94 -DIRECTION Inout
95
96 set_io RXD1 \
97 -pinname N18 \
98 -fixed yes \
99 -DIRECTION Inout
100
101 set_io nCTS1 \
102 -pinname P18 \
103 -fixed yes \
104 -DIRECTION Inout
105
106 set_io nRTS1 \
107 -pinname P17 \
108 -fixed yes \
109 -DIRECTION Inout
110
111
112 set_io TXD2 \
113 -pinname P13 \
114 -fixed yes \
115 -DIRECTION Inout
116
117 set_io RXD2 \
118 -pinname T18 \
119 -fixed yes \
120 -DIRECTION Inout
121
122 set_io nCTS2 \
123 -pinname V17 \
124 -fixed yes \
125 -DIRECTION Inout
126
127 set_io nDTR2 \
128 -pinname L15 \
129 -fixed yes \
130 -DIRECTION Inout
131
132 set_io nRTS2 \
133 -pinname M15 \
134 -fixed yes \
135 -DIRECTION Inout
136
137 set_io nDCD2 \
138 -pinname N15 \
139 -fixed yes \
140 -DIRECTION Inout
141
142
143 #====================================================================
144 # EXT CONNECTOR
145 #====================================================================
146
147 set_io IO0 \
148 -pinname E4 \
149 -fixed yes \
150 -DIRECTION Inout
151
152 set_io IO1 \
153 -pinname D3 \
154 -fixed yes \
155 -DIRECTION Inout
156
157 set_io IO2 \
158 -pinname C2 \
159 -fixed yes \
160 -DIRECTION Inout
161
162 set_io IO3 \
163 -pinname D1 \
164 -fixed yes \
165 -DIRECTION Inout
166
167 set_io IO4 \
168 -pinname F2 \
169 -fixed yes \
170 -DIRECTION Inout
171
172 set_io IO5 \
173 -pinname F3 \
174 -fixed yes \
175 -DIRECTION Inout
176
177 set_io IO6 \
178 -pinname G2 \
179 -fixed yes \
180 -DIRECTION Inout
181
182 set_io IO7 \
183 -pinname H3 \
184 -fixed yes \
185 -DIRECTION Inout
186
187 set_io IO8 \
188 -pinname H4 \
189 -fixed yes \
190 -DIRECTION Inout
191
192 set_io IO9 \
193 -pinname J2 \
194 -fixed yes \
195 -DIRECTION Inout
196
197 set_io IO10 \
198 -pinname P1 \
199 -fixed yes \
200 -DIRECTION Inout
201
202 set_io IO11 \
203 -pinname N1 \
204 -fixed yes \
205 -DIRECTION Inout
206
207 #====================================================================
208 # SPACE WIRE
209 #====================================================================
210
211 set_io SPW_EN \
212 -pinname R12 \
213 -fixed yes \
214 -DIRECTION Inout
215
216 #================================
217 # NOMINAL LINK
218 #================================
219
220 set_io SPW_NOM_DIN \
221 -pinname R10 \
222 -fixed yes \
223 -DIRECTION Inout
224
225 set_io SPW_NOM_SIN \
226 -pinname R13 \
227 -fixed yes \
228 -DIRECTION Inout
229
230 set_io SPW_NOM_DOUT \
231 -pinname T13 \
232 -fixed yes \
233 -DIRECTION Inout
234
235 set_io SPW_NOM_SOUT \
236 -pinname T10 \
237 -fixed yes \
238 -DIRECTION Inout
239
240 #================================
241 # REDUNDANT LINK
242 #================================
243
244 set_io SPW_RED_DIN \
245 -pinname U18 \
246 -fixed yes \
247 -DIRECTION Inout
248
249 set_io SPW_RED_SIN \
250 -pinname T12 \
251 -fixed yes \
252 -DIRECTION Inout
253
254 set_io SPW_RED_DOUT \
255 -pinname U10 \
256 -fixed yes \
257 -DIRECTION Inout
258
259 set_io SPW_RED_SOUT \
260 -pinname P16 \
261 -fixed yes \
262 -DIRECTION Inout
263
264 #====================================================================
265 # MINI LFR ADC INPUTS
266 #====================================================================
267
268 set_io ADC_nCS \
269 -pinname K1 \
270 -fixed yes \
271 -DIRECTION Inout
272
273 set_io ADC_CLK \
274 -pinname T1 \
275 -fixed yes \
276 -DIRECTION Inout
277
278
279 #================================
280 # ADC DATA
281 #================================
282
283 set_io ADC_SDO\[0\] \
284 -pinname V4 \
285 -fixed yes \
286 -DIRECTION Inout
287
288 set_io ADC_SDO\[1\] \
289 -pinname V3 \
290 -fixed yes \
291 -DIRECTION Inout
292
293 set_io ADC_SDO\[2\] \
294 -pinname V2 \
295 -fixed yes \
296 -DIRECTION Inout
297
298 set_io ADC_SDO\[3\] \
299 -pinname U1 \
300 -fixed yes \
301 -DIRECTION Inout
302
303 set_io ADC_SDO\[4\] \
304 -pinname J1 \
305 -fixed yes \
306 -DIRECTION Inout
307
308 set_io ADC_SDO\[5\] \
309 -pinname H1 \
310 -fixed yes \
311 -DIRECTION Inout
312
313 set_io ADC_SDO\[6\] \
314 -pinname F1 \
315 -fixed yes \
316 -DIRECTION Inout
317
318 set_io ADC_SDO\[7\] \
319 -pinname E1 \
320 -fixed yes \
321 -DIRECTION Inout
322
323
324 #====================================================================
325 # SRAM
326 #====================================================================
327
328 #================================
329 # SRAM CTRL
330 #================================
331
332 set_io SRAM_nWE \
333 -pinname C13 \
334 -fixed yes \
335 -DIRECTION Inout
336
337 set_io SRAM_CE \
338 -pinname J14 \
339 -fixed yes \
340 -DIRECTION Inout
341
342 set_io SRAM_nOE \
343 -pinname B9 \
344 -fixed yes \
345 -DIRECTION Inout
346
347 set_io SRAM_nBE\[0\] \
348 -pinname H15 \
349 -fixed yes \
350 -DIRECTION Inout
351
352 set_io SRAM_nBE\[1\] \
353 -pinname C12 \
354 -fixed yes \
355 -DIRECTION Inout
356
357 set_io SRAM_nBE\[2\] \
358 -pinname A10 \
359 -fixed yes \
360 -DIRECTION Inout
361
362 set_io SRAM_nBE\[3\] \
363 -pinname A9 \
364 -fixed yes \
365 -DIRECTION Inout
366
367
368 #================================
369 # SRAM ADDRESS
370 #================================
371
372 set_io SRAM_A\[0\] \
373 -pinname C11 \
374 -fixed yes \
375 -DIRECTION Inout
376
377 set_io SRAM_A\[1\] \
378 -pinname C10 \
379 -fixed yes \
380 -DIRECTION Inout
381
382 set_io SRAM_A\[2\] \
383 -pinname C9 \
384 -fixed yes \
385 -DIRECTION Inout
386
387 set_io SRAM_A\[3\] \
388 -pinname C8 \
389 -fixed yes \
390 -DIRECTION Inout
391
392 set_io SRAM_A\[4\] \
393 -pinname C7 \
394 -fixed yes \
395 -DIRECTION Inout
396
397 set_io SRAM_A\[5\] \
398 -pinname A5 \
399 -fixed yes \
400 -DIRECTION Inout
401
402 set_io SRAM_A\[6\] \
403 -pinname A6 \
404 -fixed yes \
405 -DIRECTION Inout
406
407 set_io SRAM_A\[7\] \
408 -pinname B6 \
409 -fixed yes \
410 -DIRECTION Inout
411
412 set_io SRAM_A\[8\] \
413 -pinname B7 \
414 -fixed yes \
415 -DIRECTION Inout
416
417 set_io SRAM_A\[9\] \
418 -pinname A8 \
419 -fixed yes \
420 -DIRECTION Inout
421
422 set_io SRAM_A\[10\] \
423 -pinname B10 \
424 -fixed yes \
425 -DIRECTION Inout
426
427 set_io SRAM_A\[11\] \
428 -pinname A11 \
429 -fixed yes \
430 -DIRECTION Inout
431
432 set_io SRAM_A\[12\] \
433 -pinname B12 \
434 -fixed yes \
435 -DIRECTION Inout
436
437 set_io SRAM_A\[13\] \
438 -pinname A13 \
439 -fixed yes \
440 -DIRECTION Inout
441
442 set_io SRAM_A\[14\] \
443 -pinname B13 \
444 -fixed yes \
445 -DIRECTION Inout
446
447 set_io SRAM_A\[15\] \
448 -pinname C18 \
449 -fixed yes \
450 -DIRECTION Inout
451
452 set_io SRAM_A\[16\] \
453 -pinname C17 \
454 -fixed yes \
455 -DIRECTION Inout
456
457 set_io SRAM_A\[17\] \
458 -pinname B18 \
459 -fixed yes \
460 -DIRECTION Inout
461
462 set_io SRAM_A\[18\] \
463 -pinname C16 \
464 -fixed yes \
465 -DIRECTION Inout
466
467 set_io SRAM_A\[19\] \
468 -pinname D15 \
469 -fixed yes \
470 -DIRECTION Inout
471
472
473 #================================
474 # SRAM DATA
475 #================================
476
477 set_io SRAM_DQ\[0\] \
478 -pinname D16 \
479 -fixed yes \
480 -DIRECTION Inout
481
482 set_io SRAM_DQ\[1\] \
483 -pinname D18 \
484 -fixed yes \
485 -DIRECTION Inout
486
487 set_io SRAM_DQ\[2\] \
488 -pinname E15 \
489 -fixed yes \
490 -DIRECTION Inout
491
492 set_io SRAM_DQ\[3\] \
493 -pinname E18 \
494 -fixed yes \
495 -DIRECTION Inout
496
497 set_io SRAM_DQ\[4\] \
498 -pinname F15 \
499 -fixed yes \
500 -DIRECTION Inout
501
502 set_io SRAM_DQ\[5\] \
503 -pinname F18 \
504 -fixed yes \
505 -DIRECTION Inout
506
507 set_io SRAM_DQ\[6\] \
508 -pinname G15 \
509 -fixed yes \
510 -DIRECTION Inout
511
512 set_io SRAM_DQ\[7\] \
513 -pinname G17 \
514 -fixed yes \
515 -DIRECTION Inout
516
517 set_io SRAM_DQ\[8\] \
518 -pinname K15 \
519 -fixed yes \
520 -DIRECTION Inout
521
522 set_io SRAM_DQ\[9\] \
523 -pinname J18 \
524 -fixed yes \
525 -DIRECTION Inout
526
527 set_io SRAM_DQ\[10\] \
528 -pinname J15 \
529 -fixed yes \
530 -DIRECTION Inout
531
532 set_io SRAM_DQ\[11\] \
533 -pinname H18 \
534 -fixed yes \
535 -DIRECTION Inout
536
537 set_io SRAM_DQ\[12\] \
538 -pinname C3 \
539 -fixed yes \
540 -DIRECTION Inout
541
542 set_io SRAM_DQ\[13\] \
543 -pinname D4 \
544 -fixed yes \
545 -DIRECTION Inout
546
547 set_io SRAM_DQ\[14\] \
548 -pinname D5 \
549 -fixed yes \
550 -DIRECTION Inout
551
552 set_io SRAM_DQ\[15\] \
553 -pinname C6 \
554 -fixed yes \
555 -DIRECTION Inout
556
557 set_io SRAM_DQ\[16\] \
558 -pinname D14 \
559 -fixed yes \
560 -DIRECTION Inout
561
562 set_io SRAM_DQ\[17\] \
563 -pinname A15 \
564 -fixed yes \
565 -DIRECTION Inout
566
567 set_io SRAM_DQ\[18\] \
568 -pinname C15 \
569 -fixed yes \
570 -DIRECTION Inout
571
572 set_io SRAM_DQ\[19\] \
573 -pinname B17 \
574 -fixed yes \
575 -DIRECTION Inout
576
577 set_io SRAM_DQ\[20\] \
578 -pinname A17 \
579 -fixed yes \
580 -DIRECTION Inout
581
582 set_io SRAM_DQ\[21\] \
583 -pinname B16 \
584 -fixed yes \
585 -DIRECTION Inout
586
587 set_io SRAM_DQ\[22\] \
588 -pinname A16 \
589 -fixed yes \
590 -DIRECTION Inout
591
592 set_io SRAM_DQ\[23\] \
593 -pinname A14 \
594 -fixed yes \
595 -DIRECTION Inout
596
597 set_io SRAM_DQ\[24\] \
598 -pinname A4 \
599 -fixed yes \
600 -DIRECTION Inout
601
602 set_io SRAM_DQ\[25\] \
603 -pinname A3 \
604 -fixed yes \
605 -DIRECTION Inout
606
607 set_io SRAM_DQ\[26\] \
608 -pinname A2 \
609 -fixed yes \
610 -DIRECTION Inout
611
612 set_io SRAM_DQ\[27\] \
613 -pinname B1 \
614 -fixed yes \
615 -DIRECTION Inout
616
617 set_io SRAM_DQ\[28\] \
618 -pinname C1 \
619 -fixed yes \
620 -DIRECTION Inout
621
622 set_io SRAM_DQ\[29\] \
623 -pinname B2 \
624 -fixed yes \
625 -DIRECTION Inout
626
627 set_io SRAM_DQ\[30\] \
628 -pinname B3 \
629 -fixed yes \
630 -DIRECTION Inout
631
632 set_io SRAM_DQ\[31\] \
633 -pinname C4 \
634 -fixed yes \
635 -DIRECTION Inout
636
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643
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1 # Synplicity, Inc. constraint file
2 # /home/jiri/ibm/vhdl/grlib/boards/actel-coremp7-1000/default.sdc
3 # Written on Wed Aug 1 19:29:24 2007
4 # by Synplify Pro, Synplify Pro 8.8.0.4 Scope Editor
5
6 #
7 # Collections
8 #
9
10 #
11 # Clocks
12 #
13 define_clock {clk} -name {clk} -freq 60 -clockgroup default_clkgroup -route 5
14
15 #
16 # Clock to Clock
17 #
18
19 #
20 # Inputs/Outputs
21 #
22 define_output_delay -disable -default 5.00 -improve 0.00 -route 0.00 -ref {clk:r}
23 define_input_delay -disable -default 5.00 -improve 0.00 -route 0.00 -ref {clk:r}
24
25
26 #
27 # Registers
28 #
29
30 #
31 # Multicycle Path
32 #
33
34 #
35 # False Path
36 #
37
38 #
39 # Path Delay
40 #
41
42 #
43 # Attributes
44 #
45 define_global_attribute syn_useioff {1}
46 define_global_attribute -disable syn_netlist_hierarchy {0}
47 define_attribute {etx_clk} syn_noclockbuf {1}
48
49 #
50 # I/O standards
51 #
52
53 #
54 # Compile Points
55 #
56
57 #
58 # Other Constraints
59 #
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1 #
2 # Automatically generated make config: don't edit
3 #
4
5 #
6 # Synthesis
7 #
8 # CONFIG_SYN_INFERRED is not set
9 # CONFIG_SYN_STRATIX is not set
10 # CONFIG_SYN_STRATIXII is not set
11 # CONFIG_SYN_STRATIXIII is not set
12 # CONFIG_SYN_CYCLONEIII is not set
13 # CONFIG_SYN_ALTERA is not set
14 # CONFIG_SYN_AXCEL is not set
15 # CONFIG_SYN_PROASIC is not set
16 # CONFIG_SYN_PROASICPLUS is not set
17 CONFIG_SYN_PROASIC3=y
18 # CONFIG_SYN_UT025CRH is not set
19 # CONFIG_SYN_ATC18 is not set
20 # CONFIG_SYN_ATC18RHA is not set
21 # CONFIG_SYN_CUSTOM1 is not set
22 # CONFIG_SYN_EASIC90 is not set
23 # CONFIG_SYN_IHP25 is not set
24 # CONFIG_SYN_IHP25RH is not set
25 # CONFIG_SYN_LATTICE is not set
26 # CONFIG_SYN_ECLIPSE is not set
27 # CONFIG_SYN_PEREGRINE is not set
28 # CONFIG_SYN_RH_LIB18T is not set
29 # CONFIG_SYN_RHUMC is not set
30 # CONFIG_SYN_SMIC13 is not set
31 # CONFIG_SYN_SPARTAN2 is not set
32 # CONFIG_SYN_SPARTAN3 is not set
33 # CONFIG_SYN_SPARTAN3E is not set
34 # CONFIG_SYN_VIRTEX is not set
35 # CONFIG_SYN_VIRTEXE is not set
36 # CONFIG_SYN_VIRTEX2 is not set
37 # CONFIG_SYN_VIRTEX4 is not set
38 # CONFIG_SYN_VIRTEX5 is not set
39 # CONFIG_SYN_UMC is not set
40 # CONFIG_SYN_TSMC90 is not set
41 # CONFIG_SYN_INFER_RAM is not set
42 # CONFIG_SYN_INFER_PADS is not set
43 # CONFIG_SYN_NO_ASYNC is not set
44 # CONFIG_SYN_SCAN is not set
45
46 #
47 # Clock generation
48 #
49 # CONFIG_CLK_INFERRED is not set
50 # CONFIG_CLK_HCLKBUF is not set
51 # CONFIG_CLK_ALTDLL is not set
52 # CONFIG_CLK_LATDLL is not set
53 CONFIG_CLK_PRO3PLL=y
54 # CONFIG_CLK_LIB18T is not set
55 # CONFIG_CLK_RHUMC is not set
56 # CONFIG_CLK_CLKDLL is not set
57 # CONFIG_CLK_DCM is not set
58 CONFIG_CLK_MUL=2
59 CONFIG_CLK_DIV=8
60 CONFIG_OCLK_DIV=2
61 # CONFIG_PCI_SYSCLK is not set
62 CONFIG_LEON3=y
63 CONFIG_PROC_NUM=1
64
65 #
66 # Processor
67 #
68
69 #
70 # Integer unit
71 #
72 CONFIG_IU_NWINDOWS=8
73 # CONFIG_IU_V8MULDIV is not set
74 # CONFIG_IU_SVT is not set
75 CONFIG_IU_LDELAY=1
76 CONFIG_IU_WATCHPOINTS=0
77 # CONFIG_PWD is not set
78 CONFIG_IU_RSTADDR=00000
79
80 #
81 # Floating-point unit
82 #
83 # CONFIG_FPU_ENABLE is not set
84
85 #
86 # Cache system
87 #
88 CONFIG_ICACHE_ENABLE=y
89 CONFIG_ICACHE_ASSO1=y
90 # CONFIG_ICACHE_ASSO2 is not set
91 # CONFIG_ICACHE_ASSO3 is not set
92 # CONFIG_ICACHE_ASSO4 is not set
93 # CONFIG_ICACHE_SZ1 is not set
94 # CONFIG_ICACHE_SZ2 is not set
95 CONFIG_ICACHE_SZ4=y
96 # CONFIG_ICACHE_SZ8 is not set
97 # CONFIG_ICACHE_SZ16 is not set
98 # CONFIG_ICACHE_SZ32 is not set
99 # CONFIG_ICACHE_SZ64 is not set
100 # CONFIG_ICACHE_SZ128 is not set
101 # CONFIG_ICACHE_SZ256 is not set
102 # CONFIG_ICACHE_LZ16 is not set
103 CONFIG_ICACHE_LZ32=y
104 CONFIG_DCACHE_ENABLE=y
105 CONFIG_DCACHE_ASSO1=y
106 # CONFIG_DCACHE_ASSO2 is not set
107 # CONFIG_DCACHE_ASSO3 is not set
108 # CONFIG_DCACHE_ASSO4 is not set
109 # CONFIG_DCACHE_SZ1 is not set
110 # CONFIG_DCACHE_SZ2 is not set
111 CONFIG_DCACHE_SZ4=y
112 # CONFIG_DCACHE_SZ8 is not set
113 # CONFIG_DCACHE_SZ16 is not set
114 # CONFIG_DCACHE_SZ32 is not set
115 # CONFIG_DCACHE_SZ64 is not set
116 # CONFIG_DCACHE_SZ128 is not set
117 # CONFIG_DCACHE_SZ256 is not set
118 # CONFIG_DCACHE_LZ16 is not set
119 CONFIG_DCACHE_LZ32=y
120 # CONFIG_DCACHE_SNOOP is not set
121 CONFIG_CACHE_FIXED=0
122
123 #
124 # MMU
125 #
126 CONFIG_MMU_ENABLE=y
127 # CONFIG_MMU_COMBINED is not set
128 CONFIG_MMU_SPLIT=y
129 # CONFIG_MMU_REPARRAY is not set
130 CONFIG_MMU_REPINCREMENT=y
131 # CONFIG_MMU_I2 is not set
132 # CONFIG_MMU_I4 is not set
133 CONFIG_MMU_I8=y
134 # CONFIG_MMU_I16 is not set
135 # CONFIG_MMU_I32 is not set
136 # CONFIG_MMU_D2 is not set
137 # CONFIG_MMU_D4 is not set
138 CONFIG_MMU_D8=y
139 # CONFIG_MMU_D16 is not set
140 # CONFIG_MMU_D32 is not set
141 CONFIG_MMU_FASTWB=y
142 CONFIG_MMU_PAGE_4K=y
143 # CONFIG_MMU_PAGE_8K is not set
144 # CONFIG_MMU_PAGE_16K is not set
145 # CONFIG_MMU_PAGE_32K is not set
146 # CONFIG_MMU_PAGE_PROG is not set
147
148 #
149 # Debug Support Unit
150 #
151 # CONFIG_DSU_ENABLE is not set
152
153 #
154 # Fault-tolerance
155 #
156
157 #
158 # VHDL debug settings
159 #
160 # CONFIG_IU_DISAS is not set
161 # CONFIG_DEBUG_PC32 is not set
162
163 #
164 # AMBA configuration
165 #
166 CONFIG_AHB_DEFMST=0
167 CONFIG_AHB_RROBIN=y
168 # CONFIG_AHB_SPLIT is not set
169 CONFIG_AHB_IOADDR=FFF
170 CONFIG_APB_HADDR=800
171 # CONFIG_AHB_MON is not set
172
173 #
174 # Debug Link
175 #
176 CONFIG_DSU_UART=y
177 # CONFIG_DSU_JTAG is not set
178
179 #
180 # Peripherals
181 #
182
183 #
184 # Memory controllers
185 #
186
187 #
188 # 8/32-bit PROM/SRAM controller
189 #
190 CONFIG_SRCTRL=y
191 # CONFIG_SRCTRL_8BIT is not set
192 CONFIG_SRCTRL_PROMWS=3
193 CONFIG_SRCTRL_RAMWS=0
194 CONFIG_SRCTRL_IOWS=0
195 # CONFIG_SRCTRL_RMW is not set
196 CONFIG_SRCTRL_SRBANKS1=y
197 # CONFIG_SRCTRL_SRBANKS2 is not set
198 # CONFIG_SRCTRL_SRBANKS3 is not set
199 # CONFIG_SRCTRL_SRBANKS4 is not set
200 # CONFIG_SRCTRL_SRBANKS5 is not set
201 # CONFIG_SRCTRL_BANKSZ0 is not set
202 # CONFIG_SRCTRL_BANKSZ1 is not set
203 # CONFIG_SRCTRL_BANKSZ2 is not set
204 # CONFIG_SRCTRL_BANKSZ3 is not set
205 # CONFIG_SRCTRL_BANKSZ4 is not set
206 # CONFIG_SRCTRL_BANKSZ5 is not set
207 # CONFIG_SRCTRL_BANKSZ6 is not set
208 # CONFIG_SRCTRL_BANKSZ7 is not set
209 # CONFIG_SRCTRL_BANKSZ8 is not set
210 # CONFIG_SRCTRL_BANKSZ9 is not set
211 # CONFIG_SRCTRL_BANKSZ10 is not set
212 # CONFIG_SRCTRL_BANKSZ11 is not set
213 # CONFIG_SRCTRL_BANKSZ12 is not set
214 # CONFIG_SRCTRL_BANKSZ13 is not set
215 CONFIG_SRCTRL_ROMASEL=19
216
217 #
218 # Leon2 memory controller
219 #
220 CONFIG_MCTRL_LEON2=y
221 # CONFIG_MCTRL_8BIT is not set
222 # CONFIG_MCTRL_16BIT is not set
223 # CONFIG_MCTRL_5CS is not set
224 # CONFIG_MCTRL_SDRAM is not set
225
226 #
227 # PC133 SDRAM controller
228 #
229 # CONFIG_SDCTRL is not set
230
231 #
232 # On-chip RAM/ROM
233 #
234 # CONFIG_AHBROM_ENABLE is not set
235 # CONFIG_AHBRAM_ENABLE is not set
236
237 #
238 # Ethernet
239 #
240 # CONFIG_GRETH_ENABLE is not set
241
242 #
243 # CAN
244 #
245 # CONFIG_CAN_ENABLE is not set
246
247 #
248 # PCI
249 #
250 # CONFIG_PCI_SIMPLE_TARGET is not set
251 # CONFIG_PCI_MASTER_TARGET is not set
252 # CONFIG_PCI_ARBITER is not set
253 # CONFIG_PCI_TRACE is not set
254
255 #
256 # Spacewire
257 #
258 # CONFIG_SPW_ENABLE is not set
259
260 #
261 # UARTs, timers and irq control
262 #
263 CONFIG_UART1_ENABLE=y
264 # CONFIG_UA1_FIFO1 is not set
265 # CONFIG_UA1_FIFO2 is not set
266 CONFIG_UA1_FIFO4=y
267 # CONFIG_UA1_FIFO8 is not set
268 # CONFIG_UA1_FIFO16 is not set
269 # CONFIG_UA1_FIFO32 is not set
270 # CONFIG_UART2_ENABLE is not set
271 CONFIG_IRQ3_ENABLE=y
272 # CONFIG_IRQ3_SEC is not set
273 CONFIG_GPT_ENABLE=y
274 CONFIG_GPT_NTIM=2
275 CONFIG_GPT_SW=8
276 CONFIG_GPT_TW=32
277 CONFIG_GPT_IRQ=8
278 CONFIG_GPT_SEPIRQ=y
279 CONFIG_GPT_WDOGEN=y
280 CONFIG_GPT_WDOG=FFFF
281 CONFIG_GRGPIO_ENABLE=y
282 CONFIG_GRGPIO_WIDTH=8
283 CONFIG_GRGPIO_IMASK=0000
284
285 #
286 # VHDL Debugging
287 #
288 # CONFIG_DEBUG_UART is not set
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@@ -0,0 +1,271
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
23 LIBRARY IEEE;
24 USE IEEE.numeric_std.ALL;
25 USE IEEE.std_logic_1164.ALL;
26 LIBRARY grlib;
27 USE grlib.amba.ALL;
28 USE grlib.stdlib.ALL;
29 LIBRARY techmap;
30 USE techmap.gencomp.ALL;
31 LIBRARY gaisler;
32 USE gaisler.memctrl.ALL;
33 USE gaisler.leon3.ALL;
34 USE gaisler.uart.ALL;
35 USE gaisler.misc.ALL;
36 USE gaisler.spacewire.ALL; -- PLE
37 LIBRARY esa;
38 USE esa.memoryctrl.ALL;
39
40 LIBRARY staging;
41 USE staging.SOC_LPP_JCP.ALL;
42
43 ENTITY MINI_LFR_top IS
44
45 PORT (
46 clk_50 : IN STD_LOGIC;
47 clk_49 : IN STD_LOGIC;
48 reset : IN STD_LOGIC;
49 --BPs
50 BP0 : IN STD_LOGIC;
51 BP1 : IN STD_LOGIC;
52 --LEDs
53 LED0 : OUT STD_LOGIC;
54 LED1 : OUT STD_LOGIC;
55 LED2 : OUT STD_LOGIC;
56 --UARTs
57 TXD1 : IN STD_LOGIC;
58 RXD1 : OUT STD_LOGIC;
59 nCTS1 : OUT STD_LOGIC;
60 nRTS1 : IN STD_LOGIC;
61
62 TXD2 : IN STD_LOGIC;
63 RXD2 : OUT STD_LOGIC;
64 nCTS2 : OUT STD_LOGIC;
65 nDTR2 : IN STD_LOGIC;
66 nRTS2 : IN STD_LOGIC;
67 nDCD2 : OUT STD_LOGIC;
68
69 --EXT CONNECTOR
70 IO0 : INOUT STD_LOGIC;
71 IO1 : INOUT STD_LOGIC;
72 IO2 : INOUT STD_LOGIC;
73 IO3 : INOUT STD_LOGIC;
74 IO4 : INOUT STD_LOGIC;
75 IO5 : INOUT STD_LOGIC;
76 IO6 : INOUT STD_LOGIC;
77 IO7 : INOUT STD_LOGIC;
78 IO8 : INOUT STD_LOGIC;
79 IO9 : INOUT STD_LOGIC;
80 IO10 : INOUT STD_LOGIC;
81 IO11 : INOUT STD_LOGIC;
82
83 --SPACE WIRE
84 SPW_EN : OUT STD_LOGIC; -- 0 => off
85 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
86 SPW_NOM_SIN : IN STD_LOGIC;
87 SPW_NOM_DOUT : OUT STD_LOGIC;
88 SPW_NOM_SOUT : OUT STD_LOGIC;
89 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
90 SPW_RED_SIN : IN STD_LOGIC;
91 SPW_RED_DOUT : OUT STD_LOGIC;
92 SPW_RED_SOUT : OUT STD_LOGIC;
93 -- MINI LFR ADC INPUTS
94 ADC_nCS : OUT STD_LOGIC;
95 ADC_CLK : OUT STD_LOGIC;
96 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
97
98 -- SRAM
99 SRAM_nWE : OUT STD_LOGIC;
100 SRAM_CE : OUT STD_LOGIC;
101 SRAM_nOE : OUT STD_LOGIC;
102 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
103 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
104 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
105 );
106
107 END MINI_LFR_top;
108
109
110 ARCHITECTURE beh OF MINI_LFR_top IS
111 SIGNAL clk_50_s : STD_LOGIC := '0';
112 SIGNAL clk_25 : STD_LOGIC := '0';
113 -----------------------------------------------------------------------------
114 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
115 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
116 --
117 SIGNAL errorn : STD_LOGIC;
118 -- UART AHB ---------------------------------------------------------------
119 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
120 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
121
122 -- UART APB ---------------------------------------------------------------
123 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
124 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
125 --
126 SIGNAL I00_s : STD_LOGIC;
127 --
128 CONSTANT NB_APB_SLAVE : INTEGER := 1;
129 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
130 CONSTANT NB_AHB_MASTER : INTEGER := 1;
131
132 SIGNAL apbi_ext : apb_slv_in_type;
133 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5):= (OTHERS => apb_none);
134 SIGNAL ahbi_s_ext : ahb_slv_in_type;
135 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3):= (OTHERS => ahbs_none);
136 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
137 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1):= (OTHERS => ahbm_none);
138
139 BEGIN -- beh
140
141 -----------------------------------------------------------------------------
142 -- CLK
143 -----------------------------------------------------------------------------
144
145 PROCESS(clk_50)
146 BEGIN
147 IF clk_50'EVENT AND clk_50 = '1' THEN
148 clk_50_s <= NOT clk_50_s;
149 END IF;
150 END PROCESS;
151
152 PROCESS(clk_50_s)
153 BEGIN
154 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
155 clk_25 <= NOT clk_25;
156 END IF;
157 END PROCESS;
158
159 -----------------------------------------------------------------------------
160
161 PROCESS (clk_25, reset)
162 BEGIN -- PROCESS
163 IF reset = '0' THEN -- asynchronous reset (active low)
164 LED0 <= '0';
165 LED1 <= '0';
166 LED2 <= '0';
167 IO1 <= '0';
168 IO2 <= '1';
169 IO3 <= '0';
170 IO4 <= '0';
171 IO5 <= '0';
172 IO6 <= '0';
173 IO7 <= '0';
174 IO8 <= '0';
175 IO9 <= '0';
176 IO10 <= '0';
177 IO11 <= '0';
178 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
179 LED0 <= '0';
180 LED1 <= '1';
181 LED2 <= BP0;
182 IO1 <= '1';
183 IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
184 IO3 <= ADC_SDO(0);
185 IO4 <= ADC_SDO(1);
186 IO5 <= ADC_SDO(2);
187 IO6 <= ADC_SDO(3);
188 IO7 <= ADC_SDO(4);
189 IO8 <= ADC_SDO(5);
190 IO9 <= ADC_SDO(6);
191 IO10 <= ADC_SDO(7);
192 IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
193 END IF;
194 END PROCESS;
195
196 PROCESS (clk_49, reset)
197 BEGIN -- PROCESS
198 IF reset = '0' THEN -- asynchronous reset (active low)
199 I00_s <= '0';
200 ELSIF clk_49'event AND clk_49 = '1' THEN -- rising clock edge
201 I00_s <= NOT I00_s;
202 END IF;
203 END PROCESS;
204 IO0 <= I00_s;
205
206 --UARTs
207 nCTS1 <= '1';
208 nCTS2 <= '1';
209 nDCD2 <= '1';
210
211 --EXT CONNECTOR
212
213 --SPACE WIRE
214 SPW_EN <= '0'; -- 0 => off
215
216 SPW_NOM_DOUT <= '0';
217 SPW_NOM_SOUT <= '0';
218 SPW_RED_DOUT <= '0';
219 SPW_RED_SOUT <= '0';
220
221 ADC_nCS <= '0';
222 ADC_CLK <= '0';
223
224
225 leon3_soc_1: leon3_soc_LPP_JCP
226 GENERIC MAP (
227 fabtech => apa3e,
228 memtech => apa3e,
229 padtech => inferred,
230 clktech => inferred,
231 disas => 0,
232 dbguart => 0,
233 pclow => 2,
234 clk_freq => 25000,
235 NB_CPU => 1,
236 ENABLE_FPU => 0,
237 FPU_NETLIST => 0,
238 ENABLE_DSU => 1,
239 ENABLE_AHB_UART => 1,
240 ENABLE_APB_UART => 1,
241 ENABLE_IRQMP => 1,
242 ENABLE_GPT => 1,
243 NB_AHB_MASTER => NB_AHB_MASTER,
244 NB_AHB_SLAVE => NB_AHB_SLAVE,
245 NB_APB_SLAVE => NB_APB_SLAVE)
246 PORT MAP (
247 clk => clk_25,
248 rstn => reset,
249 errorn => errorn,
250 ahbrxd => TXD1,
251 ahbtxd => RXD1,
252 urxd1 => TXD2,
253 utxd1 => RXD2,
254 address => SRAM_A,
255 data => SRAM_DQ,
256 nSRAM_BE0 => SRAM_nBE(0),
257 nSRAM_BE1 => SRAM_nBE(1),
258 nSRAM_BE2 => SRAM_nBE(2),
259 nSRAM_BE3 => SRAM_nBE(3),
260 nSRAM_WE => SRAM_nWE,
261 nSRAM_CE => SRAM_CE,
262 nSRAM_OE => SRAM_nOE,
263
264 apbi_ext => apbi_ext,
265 apbo_ext => apbo_ext,
266 ahbi_s_ext => ahbi_s_ext,
267 ahbo_s_ext => ahbo_s_ext,
268 ahbi_m_ext => ahbi_m_ext,
269 ahbo_m_ext => ahbo_m_ext);
270
271 END beh;
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@@ -0,0 +1,55
1 ##------------------------------------------------------------------------------
2 ##-- This file is a part of the LPP VHDL IP LIBRARY
3 ##-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 ##--
5 ##-- This program is free software; you can redistribute it and/or modify
6 ##-- it under the terms of the GNU General Public License as published by
7 ##-- the Free Software Foundation; either version 3 of the License, or
8 ##-- (at your option) any later version.
9 ##--
10 ##-- This program is distributed in the hope that it will be useful,
11 ##-- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 ##-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 ##-- GNU General Public License for more details.
14 ##--
15 ##-- You should have received a copy of the GNU General Public License
16 ##-- along with this program; if not, write to the Free Software
17 ##-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ##-------------------------------------------------------------------------------
19 ##-- Author : Jean-christophe Pellion
20 ##-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 ##-- jean-christophe.pellion@easii-ic.com
22 ##-------------------------------------------------------------------------------
23 VHDLIB=../..
24 SCRIPTSDIR=$(VHDLIB)/scripts/
25 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
26 TOP=MINI_LFR_top
27 BOARD=MINI-LFR
28 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
29 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
30 UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf
31 QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf
32 EFFORT=high
33 XSTOPT=
34 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
35 VHDLSYNFILES= MINI_LFR_top.vhd
36
37 PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc
38 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
39 CLEAN=soft-clean
40
41 TECHLIBS = proasic3e
42
43 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
44 tmtc openchip hynix ihp gleichmann micron usbhc
45
46 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
47 pci grusbhc haps slink ascs pwm coremp7 spi ac97
48
49 FILESKIP =
50
51 include $(GRLIB)/bin/Makefile
52 include $(GRLIB)/software/leon3/Makefile
53
54 ################## project specific targets ##########################
55
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@@ -0,0 +1,1
1 ./LPP/JCP/SOC
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@@ -52,7 +52,6 Patch-GRLIB: init doc
52 sh $(SCRIPTSDIR)/patch.sh $(GRLIB)
52 sh $(SCRIPTSDIR)/patch.sh $(GRLIB)
53
53
54 link:
54 link:
55 sh $(SCRIPTSDIR)/vhdlsynPatcher.sh
56 sh $(SCRIPTSDIR)/linklibs.sh $(GRLIB)
55 sh $(SCRIPTSDIR)/linklibs.sh $(GRLIB)
57
56
58 dist: init
57 dist: init
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@@ -19,14 +19,20
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
22 -------------------------------------------------------------------------------
23
23
24 LIBRARY ieee;
24 LIBRARY ieee;
25 USE ieee.std_logic_1164.ALL;
25 USE ieee.std_logic_1164.ALL;
26 LIBRARY grlib;
27 USE grlib.amba.ALL;
26
28
27 PACKAGE SOC__LPP_JCP IS
29 PACKAGE SOC_LPP_JCP IS
28
30
29 COMPONENT leon3_soc__LPP_JCP
31 type soc_ahb_mst_out_vector is array (natural range <>) of ahb_mst_out_type;
32 type soc_ahb_slv_out_vector is array (natural range <>) of ahb_slv_out_type;
33 type soc_apb_slv_out_vector is array (natural range <>) of apb_slv_out_type;
34
35 COMPONENT leon3_soc_LPP_JCP
30 GENERIC (
36 GENERIC (
31 fabtech : INTEGER;
37 fabtech : INTEGER;
32 memtech : INTEGER;
38 memtech : INTEGER;
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@@ -36,8 +36,10 USE gaisler.misc.ALL;
36 USE gaisler.spacewire.ALL;
36 USE gaisler.spacewire.ALL;
37 LIBRARY esa;
37 LIBRARY esa;
38 USE esa.memoryctrl.ALL;
38 USE esa.memoryctrl.ALL;
39 LIBRARY staging;
40 USE staging.SOC_LPP_JCP.ALL;
39
41
40 ENTITY leon3_soc__LPP_JCP IS
42 ENTITY leon3_soc_LPP_JCP IS
41 GENERIC (
43 GENERIC (
42 fabtech : INTEGER := apa3e;
44 fabtech : INTEGER := apa3e;
43 memtech : INTEGER := apa3e;
45 memtech : INTEGER := apa3e;
@@ -100,7 +102,7 ENTITY leon3_soc__LPP_JCP IS
100 );
102 );
101 END;
103 END;
102
104
103 ARCHITECTURE Behavioral OF leon3_soc__LPP_JCP IS
105 ARCHITECTURE Behavioral OF leon3_soc_LPP_JCP IS
104
106
105 -----------------------------------------------------------------------------
107 -----------------------------------------------------------------------------
106 -- CONFIG -------------------------------------------------------------------
108 -- CONFIG -------------------------------------------------------------------
@@ -195,7 +197,7 ARCHITECTURE Behavioral OF leon3_soc__LP
195 SIGNAL clk2x : STD_ULOGIC;
197 SIGNAL clk2x : STD_ULOGIC;
196 SIGNAL clkmn : STD_ULOGIC;
198 SIGNAL clkmn : STD_ULOGIC;
197 SIGNAL clkm : STD_ULOGIC;
199 SIGNAL clkm : STD_ULOGIC;
198 SIGNAL rstn : STD_ULOGIC;
200 SIGNAL rstn_s : STD_ULOGIC;
199 SIGNAL rstraw : STD_ULOGIC;
201 SIGNAL rstraw : STD_ULOGIC;
200 SIGNAL pciclk : STD_ULOGIC;
202 SIGNAL pciclk : STD_ULOGIC;
201 SIGNAL sdclkl : STD_ULOGIC;
203 SIGNAL sdclkl : STD_ULOGIC;
@@ -242,7 +244,7 BEGIN
242 cgi.pllctrl <= "00";
244 cgi.pllctrl <= "00";
243 cgi.pllrst <= rstraw;
245 cgi.pllrst <= rstraw;
244
246
245 rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
247 rst0 : rstgen PORT MAP (rstn, clkm, cgo.clklock, rstn_s, rstraw);
246
248
247 clkgen0 : clkgen -- clock generator
249 clkgen0 : clkgen -- clock generator
248 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
250 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
@@ -262,7 +264,7 BEGIN
262 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
264 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
263 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
265 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
264 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
266 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
265 PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
267 PORT MAP (clkm, rstn_s, ahbmi, ahbmo(i), ahbsi, ahbso,
266 irqi(i), irqo(i), dbgi(i), dbgo(i));
268 irqi(i), irqo(i), dbgi(i), dbgo(i));
267 END GENERATE;
269 END GENERATE;
268 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
270 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
@@ -271,7 +273,7 BEGIN
271 dsu0 : dsu3 -- LEON3 Debug Support Unit
273 dsu0 : dsu3 -- LEON3 Debug Support Unit
272 GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
274 GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
273 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
275 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
274 PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
276 PORT MAP (rstn_s, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
275 dsui.enable <= '1';
277 dsui.enable <= '1';
276 dsui.break <= '0';
278 dsui.break <= '0';
277 END GENERATE;
279 END GENERATE;
@@ -286,7 +288,7 BEGIN
286 irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
288 irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
287 irqctrl0 : irqmp -- interrupt controller
289 irqctrl0 : irqmp -- interrupt controller
288 GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
290 GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
289 PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
291 PORT MAP (rstn_s, clkm, apbi, apbo(2), irqo, irqi);
290 END GENERATE;
292 END GENERATE;
291 irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
293 irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
292 x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
294 x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
@@ -304,7 +306,7 BEGIN
304 paddr => 0,
306 paddr => 0,
305 srbanks => 1
307 srbanks => 1
306 )
308 )
307 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
309 PORT MAP (rstn_s, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
308
310
309 memi.brdyn <= '1';
311 memi.brdyn <= '1';
310 memi.bexcn <= '1';
312 memi.bexcn <= '1';
@@ -339,7 +341,7 BEGIN
339 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
341 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
340 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
342 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
341 ioen => 0, nahbm => maxahbmsp, nahbs => 8)
343 ioen => 0, nahbm => maxahbmsp, nahbs => 8)
342 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
344 PORT MAP (rstn_s, clkm, ahbmi, ahbmo, ahbsi, ahbso);
343
345
344 ----------------------------------------------------------------------
346 ----------------------------------------------------------------------
345 --- AHB UART -------------------------------------------------------
347 --- AHB UART -------------------------------------------------------
@@ -347,7 +349,7 BEGIN
347 dcomgen : IF CFG_AHB_UART = 1 GENERATE
349 dcomgen : IF CFG_AHB_UART = 1 GENERATE
348 dcom0 : ahbuart
350 dcom0 : ahbuart
349 GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4)
351 GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4)
350 PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1));
352 PORT MAP (rstn_s, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1));
351 dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
353 dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
352 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
354 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
353 END GENERATE;
355 END GENERATE;
@@ -358,7 +360,7 BEGIN
358 ----------------------------------------------------------------------
360 ----------------------------------------------------------------------
359 apb0 : apbctrl -- AHB/APB bridge
361 apb0 : apbctrl -- AHB/APB bridge
360 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
362 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
361 PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
363 PORT MAP (rstn_s, clkm, ahbsi, ahbso(1), apbi, apbo);
362
364
363 ----------------------------------------------------------------------
365 ----------------------------------------------------------------------
364 --- GPT Timer ------------------------------------------------------
366 --- GPT Timer ------------------------------------------------------
@@ -368,7 +370,7 BEGIN
368 GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
370 GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
369 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
371 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
370 nbits => CFG_GPT_TW)
372 nbits => CFG_GPT_TW)
371 PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
373 PORT MAP (rstn_s, clkm, apbi, apbo(3), gpti, gpto);
372 gpti.dhalt <= dsuo.tstop;
374 gpti.dhalt <= dsuo.tstop;
373 gpti.extclk <= '0';
375 gpti.extclk <= '0';
374 END GENERATE;
376 END GENERATE;
@@ -382,7 +384,7 BEGIN
382 uart1 : apbuart -- UART 1
384 uart1 : apbuart -- UART 1
383 GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
385 GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
384 fifosize => CFG_UART1_FIFO)
386 fifosize => CFG_UART1_FIFO)
385 PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
387 PORT MAP (rstn_s, clkm, apbi, apbo(1), apbuarti, apbuarto);
386 apbuarti.rxd <= urxd1;
388 apbuarti.rxd <= urxd1;
387 apbuarti.extclk <= '0';
389 apbuarti.extclk <= '0';
388 utxd1 <= apbuarto.txd;
390 utxd1 <= apbuarto.txd;
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