# HG changeset patch # User pellion # Date 2014-02-26 13:37:11 # Node ID 1414644b2cfcde7ce14d7031fd6fc7de2bef9aa3 # Parent ce43eaf761dd863779a368d55121e4c2d75196e4 MINI-LFR : board and project with leon3_Soc diff --git a/Makefile b/Makefile --- a/Makefile +++ b/Makefile @@ -52,7 +52,6 @@ Patch-GRLIB: init doc sh $(SCRIPTSDIR)/patch.sh $(GRLIB) link: - sh $(SCRIPTSDIR)/vhdlsynPatcher.sh sh $(SCRIPTSDIR)/linklibs.sh $(GRLIB) dist: init diff --git a/boards/MINI-LFR/Makefile.inc b/boards/MINI-LFR/Makefile.inc new file mode 100644 --- /dev/null +++ b/boards/MINI-LFR/Makefile.inc @@ -0,0 +1,42 @@ +##------------------------------------------------------------------------------ +##-- This file is a part of the LPP VHDL IP LIBRARY +##-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +##-- +##-- This program is free software; you can redistribute it and/or modify +##-- it under the terms of the GNU General Public License as published by +##-- the Free Software Foundation; either version 3 of the License, or +##-- (at your option) any later version. +##-- +##-- This program is distributed in the hope that it will be useful, +##-- but WITHOUT ANY WARRANTY; without even the implied warranty of +##-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +##-- GNU General Public License for more details. +##-- +##-- You should have received a copy of the GNU General Public License +##-- along with this program; if not, write to the Free Software +##-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +##------------------------------------------------------------------------------- +##-- Author : Jean-christophe Pellion +##-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +##-- jean-christophe.pellion@easii-ic.com +##------------------------------------------------------------------------------- + +PACKAGE=\"\" +SPEED=Std +SYNFREQ=50 + +TECHNOLOGY=ProASIC3E +LIBERO_DIE=IT14X14M4 +PART=A3PE3000 + +DESIGNER_VOLTAGE=COM +DESIGNER_TEMP=COM +DESIGNER_PACKAGE=FBGA +DESIGNER_PINS=324 + +MANUFACTURER=Actel +MGCTECHNOLOGY=Proasic3 +MGCPART=$(PART) +MGCPACKAGE= {$(DESIGNER_PINS) $(DESIGNER_PACKAGE)} +LIBERO_PACKAGE=fg$(DESIGNER_PINS) + diff --git a/boards/MINI-LFR/default.pdc b/boards/MINI-LFR/default.pdc new file mode 100644 --- /dev/null +++ b/boards/MINI-LFR/default.pdc @@ -0,0 +1,662 @@ +##------------------------------------------------------------------------------ +##-- This file is a part of the LPP VHDL IP LIBRARY +##-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +##-- +##-- This program is free software; you can redistribute it and/or modify +##-- it under the terms of the GNU General Public License as published by +##-- the Free Software Foundation; either version 3 of the License, or +##-- (at your option) any later version. +##-- +##-- This program is distributed in the hope that it will be useful, +##-- but WITHOUT ANY WARRANTY; without even the implied warranty of +##-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +##-- GNU General Public License for more details. +##-- +##-- You should have received a copy of the GNU General Public License +##-- along with this program; if not, write to the Free Software +##-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +##------------------------------------------------------------------------------- +##-- Author : Jean-christophe Pellion +##-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +##-- jean-christophe.pellion@easii-ic.com +##------------------------------------------------------------------------------- + +# Actel Physical design constraints file +# Generated file + +# Version: 9.1 SP3 9.1.3.4 +# Family: ProASIC3L , Die: A3PE3000L , Package: 324 FBGA +# Date generated: Tue Oct 18 08:21:45 2011 + + +# +# IO banks setting +# + + +# +# I/O constraints +# + +set_io clk_50 \ + -pinname F7 \ + -fixed yes \ + -DIRECTION Inout + +set_io clk_49 \ + -pinname K14 \ + -fixed yes \ + -DIRECTION Inout + +set_io reset \ + -pinname T2 \ + -fixed yes \ + -DIRECTION Inout +#==================================================================== +# BPs +#==================================================================== +set_io BP0 \ + -pinname L1 \ + -fixed yes \ + -DIRECTION Inout + +set_io BP1 \ + -pinname R1 \ + -fixed yes \ + -DIRECTION Inout + +#==================================================================== +# LEDs +#==================================================================== + +set_io LED0 \ + -pinname V6 \ + -fixed yes \ + -DIRECTION Inout + +set_io LED1 \ + -pinname V5 \ + -fixed yes \ + -DIRECTION Inout + +set_io LED2 \ + -pinname T4 \ + -fixed yes \ + -DIRECTION Inout + +#==================================================================== +# UARTS +#==================================================================== + +set_io TXD1 \ + -pinname N17 \ + -fixed yes \ + -DIRECTION Inout + +set_io RXD1 \ + -pinname N18 \ + -fixed yes \ + -DIRECTION Inout + +set_io nCTS1 \ + -pinname P18 \ + -fixed yes \ + -DIRECTION Inout + +set_io nRTS1 \ + -pinname P17 \ + -fixed yes \ + -DIRECTION Inout + + +set_io TXD2 \ + -pinname P13 \ + -fixed yes \ + -DIRECTION Inout + +set_io RXD2 \ + -pinname T18 \ + -fixed yes \ + -DIRECTION Inout + +set_io nCTS2 \ + -pinname V17 \ + -fixed yes \ + -DIRECTION Inout + +set_io nDTR2 \ + -pinname L15 \ + -fixed yes \ + -DIRECTION Inout + +set_io nRTS2 \ + -pinname M15 \ + -fixed yes \ + -DIRECTION Inout + +set_io nDCD2 \ + -pinname N15 \ + -fixed yes \ + -DIRECTION Inout + + +#==================================================================== +# EXT CONNECTOR +#==================================================================== + +set_io IO0 \ + -pinname E4 \ + -fixed yes \ + -DIRECTION Inout + +set_io IO1 \ + -pinname D3 \ + -fixed yes \ + -DIRECTION Inout + +set_io IO2 \ + -pinname C2 \ + -fixed yes \ + -DIRECTION Inout + +set_io IO3 \ + -pinname D1 \ + -fixed yes \ + -DIRECTION Inout + +set_io IO4 \ + -pinname F2 \ + -fixed yes \ + -DIRECTION Inout + +set_io IO5 \ + -pinname F3 \ + -fixed yes \ + -DIRECTION Inout + +set_io IO6 \ + -pinname G2 \ + -fixed yes \ + -DIRECTION Inout + +set_io IO7 \ + -pinname H3 \ + -fixed yes \ + -DIRECTION Inout + +set_io IO8 \ + -pinname H4 \ + -fixed yes \ + -DIRECTION Inout + +set_io IO9 \ + -pinname J2 \ + -fixed yes \ + -DIRECTION Inout + +set_io IO10 \ + -pinname P1 \ + -fixed yes \ + -DIRECTION Inout + +set_io IO11 \ + -pinname N1 \ + -fixed yes \ + -DIRECTION Inout + +#==================================================================== +# SPACE WIRE +#==================================================================== + +set_io SPW_EN \ + -pinname R12 \ + -fixed yes \ + -DIRECTION Inout + + #================================ + # NOMINAL LINK + #================================ + +set_io SPW_NOM_DIN \ + -pinname R10 \ + -fixed yes \ + -DIRECTION Inout + +set_io SPW_NOM_SIN \ + -pinname R13 \ + -fixed yes \ + -DIRECTION Inout + +set_io SPW_NOM_DOUT \ + -pinname T13 \ + -fixed yes \ + -DIRECTION Inout + +set_io SPW_NOM_SOUT \ + -pinname T10 \ + -fixed yes \ + -DIRECTION Inout + + #================================ + # REDUNDANT LINK + #================================ + +set_io SPW_RED_DIN \ + -pinname U18 \ + -fixed yes \ + -DIRECTION Inout + +set_io SPW_RED_SIN \ + -pinname T12 \ + -fixed yes \ + -DIRECTION Inout + +set_io SPW_RED_DOUT \ + -pinname U10 \ + -fixed yes \ + -DIRECTION Inout + +set_io SPW_RED_SOUT \ + -pinname P16 \ + -fixed yes \ + -DIRECTION Inout + +#==================================================================== +# MINI LFR ADC INPUTS +#==================================================================== + +set_io ADC_nCS \ + -pinname K1 \ + -fixed yes \ + -DIRECTION Inout + +set_io ADC_CLK \ + -pinname T1 \ + -fixed yes \ + -DIRECTION Inout + + + #================================ + # ADC DATA + #================================ + +set_io ADC_SDO\[0\] \ + -pinname V4 \ + -fixed yes \ + -DIRECTION Inout + +set_io ADC_SDO\[1\] \ + -pinname V3 \ + -fixed yes \ + -DIRECTION Inout + +set_io ADC_SDO\[2\] \ + -pinname V2 \ + -fixed yes \ + -DIRECTION Inout + +set_io ADC_SDO\[3\] \ + -pinname U1 \ + -fixed yes \ + -DIRECTION Inout + +set_io ADC_SDO\[4\] \ + -pinname J1 \ + -fixed yes \ + -DIRECTION Inout + +set_io ADC_SDO\[5\] \ + -pinname H1 \ + -fixed yes \ + -DIRECTION Inout + +set_io ADC_SDO\[6\] \ + -pinname F1 \ + -fixed yes \ + -DIRECTION Inout + +set_io ADC_SDO\[7\] \ + -pinname E1 \ + -fixed yes \ + -DIRECTION Inout + + +#==================================================================== +# SRAM +#==================================================================== + + #================================ + # SRAM CTRL + #================================ + +set_io SRAM_nWE \ + -pinname C13 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_CE \ + -pinname J14 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_nOE \ + -pinname B9 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_nBE\[0\] \ + -pinname H15 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_nBE\[1\] \ + -pinname C12 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_nBE\[2\] \ + -pinname A10 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_nBE\[3\] \ + -pinname A9 \ + -fixed yes \ + -DIRECTION Inout + + + #================================ + # SRAM ADDRESS + #================================ + +set_io SRAM_A\[0\] \ + -pinname C11 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_A\[1\] \ + -pinname C10 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_A\[2\] \ + -pinname C9 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_A\[3\] \ + -pinname C8 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_A\[4\] \ + -pinname C7 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_A\[5\] \ + -pinname A5 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_A\[6\] \ + -pinname A6 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_A\[7\] \ + -pinname B6 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_A\[8\] \ + -pinname B7 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_A\[9\] \ + -pinname A8 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_A\[10\] \ + -pinname B10 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_A\[11\] \ + -pinname A11 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_A\[12\] \ + -pinname B12 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_A\[13\] \ + -pinname A13 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_A\[14\] \ + -pinname B13 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_A\[15\] \ + -pinname C18 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_A\[16\] \ + -pinname C17 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_A\[17\] \ + -pinname B18 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_A\[18\] \ + -pinname C16 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_A\[19\] \ + -pinname D15 \ + -fixed yes \ + -DIRECTION Inout + + + #================================ + # SRAM DATA + #================================ + +set_io SRAM_DQ\[0\] \ + -pinname D16 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[1\] \ + -pinname D18 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[2\] \ + -pinname E15 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[3\] \ + -pinname E18 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[4\] \ + -pinname F15 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[5\] \ + -pinname F18 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[6\] \ + -pinname G15 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[7\] \ + -pinname G17 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[8\] \ + -pinname K15 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[9\] \ + -pinname J18 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[10\] \ + -pinname J15 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[11\] \ + -pinname H18 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[12\] \ + -pinname C3 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[13\] \ + -pinname D4 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[14\] \ + -pinname D5 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[15\] \ + -pinname C6 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[16\] \ + -pinname D14 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[17\] \ + -pinname A15 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[18\] \ + -pinname C15 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[19\] \ + -pinname B17 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[20\] \ + -pinname A17 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[21\] \ + -pinname B16 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[22\] \ + -pinname A16 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[23\] \ + -pinname A14 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[24\] \ + -pinname A4 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[25\] \ + -pinname A3 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[26\] \ + -pinname A2 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[27\] \ + -pinname B1 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[28\] \ + -pinname C1 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[29\] \ + -pinname B2 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[30\] \ + -pinname B3 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[31\] \ + -pinname C4 \ + -fixed yes \ + -DIRECTION Inout + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/MINI-LFR/default.sdc b/boards/MINI-LFR/default.sdc new file mode 100644 --- /dev/null +++ b/boards/MINI-LFR/default.sdc @@ -0,0 +1,59 @@ +# Synplicity, Inc. constraint file +# /home/jiri/ibm/vhdl/grlib/boards/actel-coremp7-1000/default.sdc +# Written on Wed Aug 1 19:29:24 2007 +# by Synplify Pro, Synplify Pro 8.8.0.4 Scope Editor + +# +# Collections +# + +# +# Clocks +# +define_clock {clk} -name {clk} -freq 60 -clockgroup default_clkgroup -route 5 + +# +# Clock to Clock +# + +# +# Inputs/Outputs +# +define_output_delay -disable -default 5.00 -improve 0.00 -route 0.00 -ref {clk:r} +define_input_delay -disable -default 5.00 -improve 0.00 -route 0.00 -ref {clk:r} + + +# +# Registers +# + +# +# Multicycle Path +# + +# +# False Path +# + +# +# Path Delay +# + +# +# Attributes +# +define_global_attribute syn_useioff {1} +define_global_attribute -disable syn_netlist_hierarchy {0} +define_attribute {etx_clk} syn_noclockbuf {1} + +# +# I/O standards +# + +# +# Compile Points +# + +# +# Other Constraints +# diff --git a/designs/MINI-LFR/.config b/designs/MINI-LFR/.config new file mode 100644 --- /dev/null +++ b/designs/MINI-LFR/.config @@ -0,0 +1,288 @@ +# +# Automatically generated make config: don't edit +# + +# +# Synthesis +# +# CONFIG_SYN_INFERRED is not set +# CONFIG_SYN_STRATIX is not set +# CONFIG_SYN_STRATIXII is not set +# CONFIG_SYN_STRATIXIII is not set +# CONFIG_SYN_CYCLONEIII is not set +# CONFIG_SYN_ALTERA is not set +# CONFIG_SYN_AXCEL is not set +# CONFIG_SYN_PROASIC is not set +# CONFIG_SYN_PROASICPLUS is not set +CONFIG_SYN_PROASIC3=y +# CONFIG_SYN_UT025CRH is not set +# CONFIG_SYN_ATC18 is not set +# CONFIG_SYN_ATC18RHA is not set +# CONFIG_SYN_CUSTOM1 is not set +# CONFIG_SYN_EASIC90 is not set +# CONFIG_SYN_IHP25 is not set +# CONFIG_SYN_IHP25RH is not set +# CONFIG_SYN_LATTICE is not set +# CONFIG_SYN_ECLIPSE is not set +# CONFIG_SYN_PEREGRINE is not set +# CONFIG_SYN_RH_LIB18T is not set +# CONFIG_SYN_RHUMC is not set +# CONFIG_SYN_SMIC13 is not set +# CONFIG_SYN_SPARTAN2 is not set +# CONFIG_SYN_SPARTAN3 is not set +# CONFIG_SYN_SPARTAN3E is not set +# CONFIG_SYN_VIRTEX is not set +# CONFIG_SYN_VIRTEXE is not set +# CONFIG_SYN_VIRTEX2 is not set +# CONFIG_SYN_VIRTEX4 is not set +# CONFIG_SYN_VIRTEX5 is not set +# CONFIG_SYN_UMC is not set +# CONFIG_SYN_TSMC90 is not set +# CONFIG_SYN_INFER_RAM is not set +# CONFIG_SYN_INFER_PADS is not set +# CONFIG_SYN_NO_ASYNC is not set +# CONFIG_SYN_SCAN is not set + +# +# Clock generation +# +# CONFIG_CLK_INFERRED is not set +# CONFIG_CLK_HCLKBUF is not set +# CONFIG_CLK_ALTDLL is not set +# CONFIG_CLK_LATDLL is not set +CONFIG_CLK_PRO3PLL=y +# CONFIG_CLK_LIB18T is not set +# CONFIG_CLK_RHUMC is not set +# CONFIG_CLK_CLKDLL is not set +# CONFIG_CLK_DCM is not set +CONFIG_CLK_MUL=2 +CONFIG_CLK_DIV=8 +CONFIG_OCLK_DIV=2 +# CONFIG_PCI_SYSCLK is not set +CONFIG_LEON3=y +CONFIG_PROC_NUM=1 + +# +# Processor +# + +# +# Integer unit +# +CONFIG_IU_NWINDOWS=8 +# CONFIG_IU_V8MULDIV is not set +# CONFIG_IU_SVT is not set +CONFIG_IU_LDELAY=1 +CONFIG_IU_WATCHPOINTS=0 +# CONFIG_PWD is not set +CONFIG_IU_RSTADDR=00000 + +# +# Floating-point unit +# +# CONFIG_FPU_ENABLE is not set + +# +# Cache system +# +CONFIG_ICACHE_ENABLE=y +CONFIG_ICACHE_ASSO1=y +# CONFIG_ICACHE_ASSO2 is not set +# CONFIG_ICACHE_ASSO3 is not set +# CONFIG_ICACHE_ASSO4 is not set +# CONFIG_ICACHE_SZ1 is not set +# CONFIG_ICACHE_SZ2 is not set +CONFIG_ICACHE_SZ4=y +# CONFIG_ICACHE_SZ8 is not set +# CONFIG_ICACHE_SZ16 is not set +# CONFIG_ICACHE_SZ32 is not set +# CONFIG_ICACHE_SZ64 is not set +# CONFIG_ICACHE_SZ128 is not set +# CONFIG_ICACHE_SZ256 is not set +# CONFIG_ICACHE_LZ16 is not set +CONFIG_ICACHE_LZ32=y +CONFIG_DCACHE_ENABLE=y +CONFIG_DCACHE_ASSO1=y +# CONFIG_DCACHE_ASSO2 is not set +# CONFIG_DCACHE_ASSO3 is not set +# CONFIG_DCACHE_ASSO4 is not set +# CONFIG_DCACHE_SZ1 is not set +# CONFIG_DCACHE_SZ2 is not set +CONFIG_DCACHE_SZ4=y +# CONFIG_DCACHE_SZ8 is not set +# CONFIG_DCACHE_SZ16 is not set +# CONFIG_DCACHE_SZ32 is not set +# CONFIG_DCACHE_SZ64 is not set +# CONFIG_DCACHE_SZ128 is not set +# CONFIG_DCACHE_SZ256 is not set +# CONFIG_DCACHE_LZ16 is not set +CONFIG_DCACHE_LZ32=y +# CONFIG_DCACHE_SNOOP is not set +CONFIG_CACHE_FIXED=0 + +# +# MMU +# +CONFIG_MMU_ENABLE=y +# CONFIG_MMU_COMBINED is not set +CONFIG_MMU_SPLIT=y +# CONFIG_MMU_REPARRAY is not set +CONFIG_MMU_REPINCREMENT=y +# CONFIG_MMU_I2 is not set +# CONFIG_MMU_I4 is not set +CONFIG_MMU_I8=y +# CONFIG_MMU_I16 is not set +# CONFIG_MMU_I32 is not set +# CONFIG_MMU_D2 is not set +# CONFIG_MMU_D4 is not set +CONFIG_MMU_D8=y +# CONFIG_MMU_D16 is not set +# CONFIG_MMU_D32 is not set +CONFIG_MMU_FASTWB=y +CONFIG_MMU_PAGE_4K=y +# CONFIG_MMU_PAGE_8K is not set +# CONFIG_MMU_PAGE_16K is not set +# CONFIG_MMU_PAGE_32K is not set +# CONFIG_MMU_PAGE_PROG is not set + +# +# Debug Support Unit +# +# CONFIG_DSU_ENABLE is not set + +# +# Fault-tolerance +# + +# +# VHDL debug settings +# +# CONFIG_IU_DISAS is not set +# CONFIG_DEBUG_PC32 is not set + +# +# AMBA configuration +# +CONFIG_AHB_DEFMST=0 +CONFIG_AHB_RROBIN=y +# CONFIG_AHB_SPLIT is not set +CONFIG_AHB_IOADDR=FFF +CONFIG_APB_HADDR=800 +# CONFIG_AHB_MON is not set + +# +# Debug Link +# +CONFIG_DSU_UART=y +# CONFIG_DSU_JTAG is not set + +# +# Peripherals +# + +# +# Memory controllers +# + +# +# 8/32-bit PROM/SRAM controller +# +CONFIG_SRCTRL=y +# CONFIG_SRCTRL_8BIT is not set +CONFIG_SRCTRL_PROMWS=3 +CONFIG_SRCTRL_RAMWS=0 +CONFIG_SRCTRL_IOWS=0 +# CONFIG_SRCTRL_RMW is not set +CONFIG_SRCTRL_SRBANKS1=y +# CONFIG_SRCTRL_SRBANKS2 is not set +# CONFIG_SRCTRL_SRBANKS3 is not set +# CONFIG_SRCTRL_SRBANKS4 is not set +# CONFIG_SRCTRL_SRBANKS5 is not set +# CONFIG_SRCTRL_BANKSZ0 is not set +# CONFIG_SRCTRL_BANKSZ1 is not set +# CONFIG_SRCTRL_BANKSZ2 is not set +# CONFIG_SRCTRL_BANKSZ3 is not set +# CONFIG_SRCTRL_BANKSZ4 is not set +# CONFIG_SRCTRL_BANKSZ5 is not set +# CONFIG_SRCTRL_BANKSZ6 is not set +# CONFIG_SRCTRL_BANKSZ7 is not set +# CONFIG_SRCTRL_BANKSZ8 is not set +# CONFIG_SRCTRL_BANKSZ9 is not set +# CONFIG_SRCTRL_BANKSZ10 is not set +# CONFIG_SRCTRL_BANKSZ11 is not set +# CONFIG_SRCTRL_BANKSZ12 is not set +# CONFIG_SRCTRL_BANKSZ13 is not set +CONFIG_SRCTRL_ROMASEL=19 + +# +# Leon2 memory controller +# +CONFIG_MCTRL_LEON2=y +# CONFIG_MCTRL_8BIT is not set +# CONFIG_MCTRL_16BIT is not set +# CONFIG_MCTRL_5CS is not set +# CONFIG_MCTRL_SDRAM is not set + +# +# PC133 SDRAM controller +# +# CONFIG_SDCTRL is not set + +# +# On-chip RAM/ROM +# +# CONFIG_AHBROM_ENABLE is not set +# CONFIG_AHBRAM_ENABLE is not set + +# +# Ethernet +# +# CONFIG_GRETH_ENABLE is not set + +# +# CAN +# +# CONFIG_CAN_ENABLE is not set + +# +# PCI +# +# CONFIG_PCI_SIMPLE_TARGET is not set +# CONFIG_PCI_MASTER_TARGET is not set +# CONFIG_PCI_ARBITER is not set +# CONFIG_PCI_TRACE is not set + +# +# Spacewire +# +# CONFIG_SPW_ENABLE is not set + +# +# UARTs, timers and irq control +# +CONFIG_UART1_ENABLE=y +# CONFIG_UA1_FIFO1 is not set +# CONFIG_UA1_FIFO2 is not set +CONFIG_UA1_FIFO4=y +# CONFIG_UA1_FIFO8 is not set +# CONFIG_UA1_FIFO16 is not set +# CONFIG_UA1_FIFO32 is not set +# CONFIG_UART2_ENABLE is not set +CONFIG_IRQ3_ENABLE=y +# CONFIG_IRQ3_SEC is not set +CONFIG_GPT_ENABLE=y +CONFIG_GPT_NTIM=2 +CONFIG_GPT_SW=8 +CONFIG_GPT_TW=32 +CONFIG_GPT_IRQ=8 +CONFIG_GPT_SEPIRQ=y +CONFIG_GPT_WDOGEN=y +CONFIG_GPT_WDOG=FFFF +CONFIG_GRGPIO_ENABLE=y +CONFIG_GRGPIO_WIDTH=8 +CONFIG_GRGPIO_IMASK=0000 + +# +# VHDL Debugging +# +# CONFIG_DEBUG_UART is not set diff --git a/designs/MINI-LFR/MINI_LFR_top.vhd b/designs/MINI-LFR/MINI_LFR_top.vhd new file mode 100644 --- /dev/null +++ b/designs/MINI-LFR/MINI_LFR_top.vhd @@ -0,0 +1,271 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +-- jean-christophe.pellion@easii-ic.com +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_1164.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +LIBRARY techmap; +USE techmap.gencomp.ALL; +LIBRARY gaisler; +USE gaisler.memctrl.ALL; +USE gaisler.leon3.ALL; +USE gaisler.uart.ALL; +USE gaisler.misc.ALL; +USE gaisler.spacewire.ALL; -- PLE +LIBRARY esa; +USE esa.memoryctrl.ALL; + +LIBRARY staging; +USE staging.SOC_LPP_JCP.ALL; + +ENTITY MINI_LFR_top IS + + PORT ( + clk_50 : IN STD_LOGIC; + clk_49 : IN STD_LOGIC; + reset : IN STD_LOGIC; + --BPs + BP0 : IN STD_LOGIC; + BP1 : IN STD_LOGIC; + --LEDs + LED0 : OUT STD_LOGIC; + LED1 : OUT STD_LOGIC; + LED2 : OUT STD_LOGIC; + --UARTs + TXD1 : IN STD_LOGIC; + RXD1 : OUT STD_LOGIC; + nCTS1 : OUT STD_LOGIC; + nRTS1 : IN STD_LOGIC; + + TXD2 : IN STD_LOGIC; + RXD2 : OUT STD_LOGIC; + nCTS2 : OUT STD_LOGIC; + nDTR2 : IN STD_LOGIC; + nRTS2 : IN STD_LOGIC; + nDCD2 : OUT STD_LOGIC; + + --EXT CONNECTOR + IO0 : INOUT STD_LOGIC; + IO1 : INOUT STD_LOGIC; + IO2 : INOUT STD_LOGIC; + IO3 : INOUT STD_LOGIC; + IO4 : INOUT STD_LOGIC; + IO5 : INOUT STD_LOGIC; + IO6 : INOUT STD_LOGIC; + IO7 : INOUT STD_LOGIC; + IO8 : INOUT STD_LOGIC; + IO9 : INOUT STD_LOGIC; + IO10 : INOUT STD_LOGIC; + IO11 : INOUT STD_LOGIC; + + --SPACE WIRE + SPW_EN : OUT STD_LOGIC; -- 0 => off + SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK + SPW_NOM_SIN : IN STD_LOGIC; + SPW_NOM_DOUT : OUT STD_LOGIC; + SPW_NOM_SOUT : OUT STD_LOGIC; + SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK + SPW_RED_SIN : IN STD_LOGIC; + SPW_RED_DOUT : OUT STD_LOGIC; + SPW_RED_SOUT : OUT STD_LOGIC; + -- MINI LFR ADC INPUTS + ADC_nCS : OUT STD_LOGIC; + ADC_CLK : OUT STD_LOGIC; + ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + + -- SRAM + SRAM_nWE : OUT STD_LOGIC; + SRAM_CE : OUT STD_LOGIC; + SRAM_nOE : OUT STD_LOGIC; + SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); + SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); + +END MINI_LFR_top; + + +ARCHITECTURE beh OF MINI_LFR_top IS + SIGNAL clk_50_s : STD_LOGIC := '0'; + SIGNAL clk_25 : STD_LOGIC := '0'; + ----------------------------------------------------------------------------- + SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); + -- + SIGNAL errorn : STD_LOGIC; + -- UART AHB --------------------------------------------------------------- + SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data + SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data + + -- UART APB --------------------------------------------------------------- + SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data + SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data + -- + SIGNAL I00_s : STD_LOGIC; + -- + CONSTANT NB_APB_SLAVE : INTEGER := 1; + CONSTANT NB_AHB_SLAVE : INTEGER := 1; + CONSTANT NB_AHB_MASTER : INTEGER := 1; + + SIGNAL apbi_ext : apb_slv_in_type; + SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5):= (OTHERS => apb_none); + SIGNAL ahbi_s_ext : ahb_slv_in_type; + SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3):= (OTHERS => ahbs_none); + SIGNAL ahbi_m_ext : AHB_Mst_In_Type; + SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1):= (OTHERS => ahbm_none); + +BEGIN -- beh + + ----------------------------------------------------------------------------- + -- CLK + ----------------------------------------------------------------------------- + + PROCESS(clk_50) + BEGIN + IF clk_50'EVENT AND clk_50 = '1' THEN + clk_50_s <= NOT clk_50_s; + END IF; + END PROCESS; + + PROCESS(clk_50_s) + BEGIN + IF clk_50_s'EVENT AND clk_50_s = '1' THEN + clk_25 <= NOT clk_25; + END IF; + END PROCESS; + + ----------------------------------------------------------------------------- + + PROCESS (clk_25, reset) + BEGIN -- PROCESS + IF reset = '0' THEN -- asynchronous reset (active low) + LED0 <= '0'; + LED1 <= '0'; + LED2 <= '0'; + IO1 <= '0'; + IO2 <= '1'; + IO3 <= '0'; + IO4 <= '0'; + IO5 <= '0'; + IO6 <= '0'; + IO7 <= '0'; + IO8 <= '0'; + IO9 <= '0'; + IO10 <= '0'; + IO11 <= '0'; + ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge + LED0 <= '0'; + LED1 <= '1'; + LED2 <= BP0; + IO1 <= '1'; + IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN; + IO3 <= ADC_SDO(0); + IO4 <= ADC_SDO(1); + IO5 <= ADC_SDO(2); + IO6 <= ADC_SDO(3); + IO7 <= ADC_SDO(4); + IO8 <= ADC_SDO(5); + IO9 <= ADC_SDO(6); + IO10 <= ADC_SDO(7); + IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1; + END IF; + END PROCESS; + + PROCESS (clk_49, reset) + BEGIN -- PROCESS + IF reset = '0' THEN -- asynchronous reset (active low) + I00_s <= '0'; + ELSIF clk_49'event AND clk_49 = '1' THEN -- rising clock edge + I00_s <= NOT I00_s; + END IF; + END PROCESS; + IO0 <= I00_s; + + --UARTs + nCTS1 <= '1'; + nCTS2 <= '1'; + nDCD2 <= '1'; + + --EXT CONNECTOR + + --SPACE WIRE + SPW_EN <= '0'; -- 0 => off + + SPW_NOM_DOUT <= '0'; + SPW_NOM_SOUT <= '0'; + SPW_RED_DOUT <= '0'; + SPW_RED_SOUT <= '0'; + + ADC_nCS <= '0'; + ADC_CLK <= '0'; + + + leon3_soc_1: leon3_soc_LPP_JCP + GENERIC MAP ( + fabtech => apa3e, + memtech => apa3e, + padtech => inferred, + clktech => inferred, + disas => 0, + dbguart => 0, + pclow => 2, + clk_freq => 25000, + NB_CPU => 1, + ENABLE_FPU => 0, + FPU_NETLIST => 0, + ENABLE_DSU => 1, + ENABLE_AHB_UART => 1, + ENABLE_APB_UART => 1, + ENABLE_IRQMP => 1, + ENABLE_GPT => 1, + NB_AHB_MASTER => NB_AHB_MASTER, + NB_AHB_SLAVE => NB_AHB_SLAVE, + NB_APB_SLAVE => NB_APB_SLAVE) + PORT MAP ( + clk => clk_25, + rstn => reset, + errorn => errorn, + ahbrxd => TXD1, + ahbtxd => RXD1, + urxd1 => TXD2, + utxd1 => RXD2, + address => SRAM_A, + data => SRAM_DQ, + nSRAM_BE0 => SRAM_nBE(0), + nSRAM_BE1 => SRAM_nBE(1), + nSRAM_BE2 => SRAM_nBE(2), + nSRAM_BE3 => SRAM_nBE(3), + nSRAM_WE => SRAM_nWE, + nSRAM_CE => SRAM_CE, + nSRAM_OE => SRAM_nOE, + + apbi_ext => apbi_ext, + apbo_ext => apbo_ext, + ahbi_s_ext => ahbi_s_ext, + ahbo_s_ext => ahbo_s_ext, + ahbi_m_ext => ahbi_m_ext, + ahbo_m_ext => ahbo_m_ext); + +END beh; diff --git a/designs/MINI-LFR/Makefile b/designs/MINI-LFR/Makefile new file mode 100644 --- /dev/null +++ b/designs/MINI-LFR/Makefile @@ -0,0 +1,55 @@ +##------------------------------------------------------------------------------ +##-- This file is a part of the LPP VHDL IP LIBRARY +##-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +##-- +##-- This program is free software; you can redistribute it and/or modify +##-- it under the terms of the GNU General Public License as published by +##-- the Free Software Foundation; either version 3 of the License, or +##-- (at your option) any later version. +##-- +##-- This program is distributed in the hope that it will be useful, +##-- but WITHOUT ANY WARRANTY; without even the implied warranty of +##-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +##-- GNU General Public License for more details. +##-- +##-- You should have received a copy of the GNU General Public License +##-- along with this program; if not, write to the Free Software +##-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +##------------------------------------------------------------------------------- +##-- Author : Jean-christophe Pellion +##-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +##-- jean-christophe.pellion@easii-ic.com +##------------------------------------------------------------------------------- +VHDLIB=../.. +SCRIPTSDIR=$(VHDLIB)/scripts/ +GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) +TOP=MINI_LFR_top +BOARD=MINI-LFR +include $(VHDLIB)/boards/$(BOARD)/Makefile.inc +DEVICE=$(PART)-$(PACKAGE)$(SPEED) +UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf +QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf +EFFORT=high +XSTOPT= +SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" +VHDLSYNFILES= MINI_LFR_top.vhd + +PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc +BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut +CLEAN=soft-clean + +TECHLIBS = proasic3e + +LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ + tmtc openchip hynix ihp gleichmann micron usbhc + +DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ + pci grusbhc haps slink ascs pwm coremp7 spi ac97 + +FILESKIP = + +include $(GRLIB)/bin/Makefile +include $(GRLIB)/software/leon3/Makefile + +################## project specific targets ########################## + diff --git a/lib/staging/LPP/JCP/SOC/SOC.vhd b/lib/staging/LPP/JCP/SOC/SOC.vhd --- a/lib/staging/LPP/JCP/SOC/SOC.vhd +++ b/lib/staging/LPP/JCP/SOC/SOC.vhd @@ -19,14 +19,20 @@ -- Author : Jean-christophe Pellion -- Mail : jean-christophe.pellion@lpp.polytechnique.fr -- jean-christophe.pellion@easii-ic.com ----------------------------------------------------------------------------- +------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; -PACKAGE SOC__LPP_JCP IS +PACKAGE SOC_LPP_JCP IS - COMPONENT leon3_soc__LPP_JCP + type soc_ahb_mst_out_vector is array (natural range <>) of ahb_mst_out_type; + type soc_ahb_slv_out_vector is array (natural range <>) of ahb_slv_out_type; + type soc_apb_slv_out_vector is array (natural range <>) of apb_slv_out_type; + + COMPONENT leon3_soc_LPP_JCP GENERIC ( fabtech : INTEGER; memtech : INTEGER; diff --git a/lib/staging/LPP/JCP/SOC/leon3_soc.vhd b/lib/staging/LPP/JCP/SOC/leon3_soc.vhd --- a/lib/staging/LPP/JCP/SOC/leon3_soc.vhd +++ b/lib/staging/LPP/JCP/SOC/leon3_soc.vhd @@ -36,8 +36,10 @@ USE gaisler.misc.ALL; USE gaisler.spacewire.ALL; LIBRARY esa; USE esa.memoryctrl.ALL; +LIBRARY staging; +USE staging.SOC_LPP_JCP.ALL; -ENTITY leon3_soc__LPP_JCP IS +ENTITY leon3_soc_LPP_JCP IS GENERIC ( fabtech : INTEGER := apa3e; memtech : INTEGER := apa3e; @@ -100,7 +102,7 @@ ENTITY leon3_soc__LPP_JCP IS ); END; -ARCHITECTURE Behavioral OF leon3_soc__LPP_JCP IS +ARCHITECTURE Behavioral OF leon3_soc_LPP_JCP IS ----------------------------------------------------------------------------- -- CONFIG ------------------------------------------------------------------- @@ -195,7 +197,7 @@ ARCHITECTURE Behavioral OF leon3_soc__LP SIGNAL clk2x : STD_ULOGIC; SIGNAL clkmn : STD_ULOGIC; SIGNAL clkm : STD_ULOGIC; - SIGNAL rstn : STD_ULOGIC; + SIGNAL rstn_s : STD_ULOGIC; SIGNAL rstraw : STD_ULOGIC; SIGNAL pciclk : STD_ULOGIC; SIGNAL sdclkl : STD_ULOGIC; @@ -242,7 +244,7 @@ BEGIN cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; - rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw); + rst0 : rstgen PORT MAP (rstn, clkm, cgo.clklock, rstn_s, rstraw); clkgen0 : clkgen -- clock generator GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, @@ -262,7 +264,7 @@ BEGIN CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1) - PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, + PORT MAP (clkm, rstn_s, ahbmi, ahbmo(i), ahbsi, ahbso, irqi(i), irqo(i), dbgi(i), dbgo(i)); END GENERATE; errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error); @@ -271,7 +273,7 @@ BEGIN dsu0 : dsu3 -- LEON3 Debug Support Unit GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#, ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) - PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); + PORT MAP (rstn_s, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); dsui.enable <= '1'; dsui.break <= '0'; END GENERATE; @@ -286,7 +288,7 @@ BEGIN irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE irqctrl0 : irqmp -- interrupt controller GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU) - PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi); + PORT MAP (rstn_s, clkm, apbi, apbo(2), irqo, irqi); END GENERATE; irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE x : FOR i IN 0 TO CFG_NCPU-1 GENERATE @@ -304,7 +306,7 @@ BEGIN paddr => 0, srbanks => 1 ) - PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); + PORT MAP (rstn_s, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); memi.brdyn <= '1'; memi.bexcn <= '1'; @@ -339,7 +341,7 @@ BEGIN GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT, rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 0, nahbm => maxahbmsp, nahbs => 8) - PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); + PORT MAP (rstn_s, clkm, ahbmi, ahbmo, ahbsi, ahbso); ---------------------------------------------------------------------- --- AHB UART ------------------------------------------------------- @@ -347,7 +349,7 @@ BEGIN dcomgen : IF CFG_AHB_UART = 1 GENERATE dcom0 : ahbuart GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4) - PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1)); + PORT MAP (rstn_s, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1)); dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd); dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd); END GENERATE; @@ -358,7 +360,7 @@ BEGIN ---------------------------------------------------------------------- apb0 : apbctrl -- AHB/APB bridge GENERIC MAP (hindex => 1, haddr => CFG_APBADDR) - PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo); + PORT MAP (rstn_s, clkm, ahbsi, ahbso(1), apbi, apbo); ---------------------------------------------------------------------- --- GPT Timer ------------------------------------------------------ @@ -368,7 +370,7 @@ BEGIN GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, nbits => CFG_GPT_TW) - PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto); + PORT MAP (rstn_s, clkm, apbi, apbo(3), gpti, gpto); gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0'; END GENERATE; @@ -382,7 +384,7 @@ BEGIN uart1 : apbuart -- UART 1 GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart, fifosize => CFG_UART1_FIFO) - PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto); + PORT MAP (rstn_s, clkm, apbi, apbo(1), apbuarti, apbuarto); apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd; diff --git a/lib/staging/dirs.txt b/lib/staging/dirs.txt new file mode 100644 --- /dev/null +++ b/lib/staging/dirs.txt @@ -0,0 +1,1 @@ +./LPP/JCP/SOC