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1 | ||||
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2 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/general_purpose.vhd | |||
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3 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/SYNC_FF.vhd | |||
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4 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MUXN.vhd | |||
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5 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MUX2.vhd | |||
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6 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/REG.vhd | |||
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7 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC.vhd | |||
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8 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_CONTROLER.vhd | |||
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9 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_REG.vhd | |||
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10 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_MUX.vhd | |||
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11 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_MUX2.vhd | |||
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12 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/Shifter.vhd | |||
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13 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MULTIPLIER.vhd | |||
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14 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ADDER.vhd | |||
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15 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ALU.vhd | |||
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16 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ADDRcntr.vhd | |||
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17 | ||||
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18 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/iir_filter.vhd | |||
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19 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/FILTERcfg.vhd | |||
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20 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CEL.vhd | |||
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21 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CEL_N.vhd | |||
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22 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR2.vhd | |||
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23 | #vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR.vhd | |||
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24 | ||||
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25 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd | |||
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26 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd | |||
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27 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd | |||
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28 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd | |||
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29 | ||||
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30 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lpp_memory.vhd | |||
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31 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lpp_FIFO.vhd | |||
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32 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lppFIFOxN.vhd | |||
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33 | ||||
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34 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/lpp_downsampling/Downsampling.vhd | |||
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35 | ||||
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36 | vcom -quiet -93 -work lpp e:/opt/tortoiseHG_vhdlib/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd | |||
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37 | vcom -quiet -93 -work lpp e:/opt/tortoiseHG_vhdlib/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd | |||
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38 | ||||
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39 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/lpp_ad_conv.vhd | |||
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40 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/AD7688_drvr.vhd | |||
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41 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/TestModule_ADS7886.vhd | |||
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42 | ||||
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43 | ||||
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44 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd | |||
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45 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_apbreg.vhd | |||
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46 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_lfr_wf_picker_ip.vhd | |||
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47 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_lfr_wf_picker.vhd | |||
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48 | #vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_acq.vhd | |||
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49 | #vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_lfr.vhd | |||
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50 | ||||
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51 | vcom -quiet -93 -work lpp ../../lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd | |||
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52 | vcom -quiet -93 -work lpp ../../lib/lpp/lfr_time_management/apb_lfr_time_management.vhd | |||
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53 | vcom -quiet -93 -work lpp ../../lib/lpp/lfr_time_management/lfr_time_management.vhd | |||
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54 | ||||
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55 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/lpp_dma_pkg.vhd | |||
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56 | ||||
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57 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd | |||
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58 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform.vhd | |||
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59 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_snapshot_controler.vhd | |||
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60 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_snapshot.vhd | |||
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61 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_burst.vhd | |||
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62 | ||||
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63 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter.vhd | |||
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64 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_fifo_ctrl.vhd | |||
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65 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_fifo.vhd | |||
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66 | ||||
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67 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_dma.vhd | |||
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68 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/lpp_dma_pkg.vhd | |||
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69 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/lpp_dma_send_1word.vhd | |||
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70 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/lpp_dma_send_16word.vhd | |||
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71 | #vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_dma_send_Nword.vhd | |||
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72 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_dma_selectaddress.vhd | |||
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73 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_dma_genvalid.vhd | |||
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74 | ||||
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75 | vcom -quiet -93 -work work Top_Data_Acquisition.vhd | |||
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76 | ||||
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77 | vcom -quiet -93 -work work TB_Data_Acquisition.vhd | |||
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78 | ||||
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79 | vsim work.TB_Data_Acquisition | |||
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80 | ||||
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81 | log -r * | |||
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82 | do wave_waveform_picker.do | |||
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83 | run 5 ms | |||
| @@ -0,0 +1,364 | |||||
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1 | onerror {resume} | |||
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2 | quietly WaveActivateNextPane {} 0 | |||
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3 | add wave -noupdate /tb_data_acquisition/sample_f0_wen | |||
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4 | add wave -noupdate /tb_data_acquisition/sample_f0_wdata | |||
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5 | add wave -noupdate /tb_data_acquisition/sample_f1_wen | |||
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6 | add wave -noupdate /tb_data_acquisition/sample_f1_wdata | |||
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7 | add wave -noupdate /tb_data_acquisition/sample_f2_wen | |||
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8 | add wave -noupdate /tb_data_acquisition/sample_f2_wdata | |||
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9 | add wave -noupdate /tb_data_acquisition/sample_f3_wen | |||
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10 | add wave -noupdate /tb_data_acquisition/sample_f3_wdata | |||
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11 | add wave -noupdate -group TOP /tb_data_acquisition/ahb_master_in | |||
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12 | add wave -noupdate -group TOP /tb_data_acquisition/ahb_master_out | |||
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13 | add wave -noupdate -group TOP /tb_data_acquisition/coarse_time_0 | |||
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14 | add wave -noupdate -group TOP /tb_data_acquisition/coarse_time_0_t | |||
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15 | add wave -noupdate -group TOP /tb_data_acquisition/coarse_time_0_t2 | |||
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16 | add wave -noupdate -group TOP /tb_data_acquisition/delta_snapshot | |||
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17 | add wave -noupdate -group TOP /tb_data_acquisition/delta_f2_f1 | |||
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18 | add wave -noupdate -group TOP /tb_data_acquisition/delta_f2_f0 | |||
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19 | add wave -noupdate -group TOP /tb_data_acquisition/enable_f0 | |||
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20 | add wave -noupdate -group TOP /tb_data_acquisition/enable_f1 | |||
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21 | add wave -noupdate -group TOP /tb_data_acquisition/enable_f2 | |||
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22 | add wave -noupdate -group TOP /tb_data_acquisition/enable_f3 | |||
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23 | add wave -noupdate -group TOP /tb_data_acquisition/burst_f0 | |||
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24 | add wave -noupdate -group TOP /tb_data_acquisition/burst_f1 | |||
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25 | add wave -noupdate -group TOP /tb_data_acquisition/burst_f2 | |||
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26 | add wave -noupdate -group TOP /tb_data_acquisition/nb_snapshot_param | |||
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27 | add wave -noupdate -group TOP /tb_data_acquisition/status_full | |||
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28 | add wave -noupdate -group TOP /tb_data_acquisition/status_full_ack | |||
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29 | add wave -noupdate -group TOP /tb_data_acquisition/status_full_err | |||
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30 | add wave -noupdate -group TOP /tb_data_acquisition/status_new_err | |||
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31 | add wave -noupdate -group TOP /tb_data_acquisition/addr_data_f0 | |||
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32 | add wave -noupdate -group TOP /tb_data_acquisition/addr_data_f1 | |||
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33 | add wave -noupdate -group TOP /tb_data_acquisition/addr_data_f2 | |||
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34 | add wave -noupdate -group TOP /tb_data_acquisition/addr_data_f3 | |||
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35 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_size | |||
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36 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/nb_snapshot_param_size | |||
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37 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/delta_snapshot_size | |||
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38 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/delta_f2_f0_size | |||
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39 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/delta_f2_f1_size | |||
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40 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/clk | |||
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41 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/rstn | |||
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42 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/ahb_master_in | |||
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43 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/ahb_master_out | |||
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44 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/coarse_time_0 | |||
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45 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/delta_snapshot | |||
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46 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/delta_f2_f1 | |||
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47 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/delta_f2_f0 | |||
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48 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/enable_f0 | |||
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49 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/enable_f1 | |||
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50 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/enable_f2 | |||
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51 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/enable_f3 | |||
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52 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/burst_f0 | |||
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53 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/burst_f1 | |||
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54 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/burst_f2 | |||
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55 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/nb_snapshot_param | |||
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56 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/status_full | |||
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57 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/status_full_ack | |||
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58 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/status_full_err | |||
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59 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/status_new_err | |||
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60 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/addr_data_f0 | |||
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61 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/addr_data_f1 | |||
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62 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/addr_data_f2 | |||
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63 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/addr_data_f3 | |||
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64 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f0_in | |||
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65 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f1_in | |||
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66 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f2_in | |||
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67 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f3_in | |||
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68 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f0_in_valid | |||
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69 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f1_in_valid | |||
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70 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f2_in_valid | |||
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71 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f3_in_valid | |||
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72 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/start_snapshot_f0 | |||
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73 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/start_snapshot_f1 | |||
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74 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/start_snapshot_f2 | |||
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75 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f0_out | |||
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76 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f1_out | |||
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77 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f2_out | |||
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78 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f3_out | |||
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79 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f0_out_valid | |||
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80 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f1_out_valid | |||
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81 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f2_out_valid | |||
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82 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f3_out_valid | |||
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83 | add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/clk | |||
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84 | add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/rstn | |||
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85 | add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/delta_snapshot | |||
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86 | add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/delta_f2_f1 | |||
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87 | add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/delta_f2_f0 | |||
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88 | add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/coarse_time_0 | |||
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89 | add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/data_f2_in_valid | |||
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90 | add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/start_snapshot_f0 | |||
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91 | add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/start_snapshot_f1 | |||
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92 | add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/start_snapshot_f2 | |||
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93 | add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/counter_delta_snapshot | |||
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94 | add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/coarse_time_0_r | |||
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95 | add wave -noupdate -group waveform_snapshot_f0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f0/clk | |||
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96 | add wave -noupdate -group waveform_snapshot_f0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f0/rstn | |||
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97 | add wave -noupdate -group waveform_snapshot_f0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f0/enable | |||
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98 | add wave -noupdate -group waveform_snapshot_f0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f0/burst_enable | |||
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99 | add wave -noupdate -group waveform_snapshot_f0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f0/nb_snapshot_param | |||
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100 | add wave -noupdate -group waveform_snapshot_f0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f0/start_snapshot | |||
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101 | add wave -noupdate -group waveform_snapshot_f0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f0/data_in | |||
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102 | add wave -noupdate -group waveform_snapshot_f0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f0/data_in_valid | |||
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103 | add wave -noupdate -group waveform_snapshot_f0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f0/data_out | |||
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104 | add wave -noupdate -group waveform_snapshot_f0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f0/data_out_valid | |||
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105 | add wave -noupdate -group waveform_snapshot_f0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f0/counter_points_snapshot | |||
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106 | add wave -noupdate -group waveform_snapshot_f1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f1/clk | |||
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107 | add wave -noupdate -group waveform_snapshot_f1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f1/rstn | |||
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108 | add wave -noupdate -group waveform_snapshot_f1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f1/enable | |||
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109 | add wave -noupdate -group waveform_snapshot_f1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f1/burst_enable | |||
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110 | add wave -noupdate -group waveform_snapshot_f1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f1/nb_snapshot_param | |||
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111 | add wave -noupdate -group waveform_snapshot_f1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f1/start_snapshot | |||
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112 | add wave -noupdate -group waveform_snapshot_f1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f1/data_in | |||
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113 | add wave -noupdate -group waveform_snapshot_f1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f1/data_in_valid | |||
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114 | add wave -noupdate -group waveform_snapshot_f1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f1/data_out | |||
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115 | add wave -noupdate -group waveform_snapshot_f1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f1/data_out_valid | |||
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116 | add wave -noupdate -group waveform_snapshot_f1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f1/counter_points_snapshot | |||
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117 | add wave -noupdate -group waveform_snapshot_f2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f2/clk | |||
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118 | add wave -noupdate -group waveform_snapshot_f2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f2/rstn | |||
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119 | add wave -noupdate -group waveform_snapshot_f2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f2/enable | |||
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120 | add wave -noupdate -group waveform_snapshot_f2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f2/burst_enable | |||
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121 | add wave -noupdate -group waveform_snapshot_f2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f2/nb_snapshot_param | |||
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122 | add wave -noupdate -group waveform_snapshot_f2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f2/start_snapshot | |||
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123 | add wave -noupdate -group waveform_snapshot_f2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f2/data_in | |||
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124 | add wave -noupdate -group waveform_snapshot_f2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f2/data_in_valid | |||
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125 | add wave -noupdate -group waveform_snapshot_f2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f2/data_out | |||
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126 | add wave -noupdate -group waveform_snapshot_f2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f2/data_out_valid | |||
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127 | add wave -noupdate -group waveform_snapshot_f2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f2/counter_points_snapshot | |||
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128 | add wave -noupdate -group waveform_burst____f3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_burst_f3/clk | |||
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129 | add wave -noupdate -group waveform_burst____f3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_burst_f3/rstn | |||
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130 | add wave -noupdate -group waveform_burst____f3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_burst_f3/enable | |||
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131 | add wave -noupdate -group waveform_burst____f3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_burst_f3/data_in | |||
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132 | add wave -noupdate -group waveform_burst____f3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_burst_f3/data_in_valid | |||
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133 | add wave -noupdate -group waveform_burst____f3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_burst_f3/data_out | |||
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134 | add wave -noupdate -group waveform_burst____f3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_burst_f3/data_out_valid | |||
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135 | add wave -noupdate -group GEN_VALID_F0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(0)/lpp_waveform_dma_gen_valid_i/hclk | |||
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136 | add wave -noupdate -group GEN_VALID_F0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(0)/lpp_waveform_dma_gen_valid_i/hresetn | |||
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137 | add wave -noupdate -group GEN_VALID_F0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(0)/lpp_waveform_dma_gen_valid_i/valid_in | |||
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138 | add wave -noupdate -group GEN_VALID_F0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(0)/lpp_waveform_dma_gen_valid_i/ack_in | |||
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139 | add wave -noupdate -group GEN_VALID_F0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(0)/lpp_waveform_dma_gen_valid_i/valid_out | |||
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140 | add wave -noupdate -group GEN_VALID_F0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(0)/lpp_waveform_dma_gen_valid_i/error | |||
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141 | add wave -noupdate -group GEN_VALID_F1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(1)/lpp_waveform_dma_gen_valid_i/hclk | |||
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142 | add wave -noupdate -group GEN_VALID_F1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(1)/lpp_waveform_dma_gen_valid_i/hresetn | |||
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143 | add wave -noupdate -group GEN_VALID_F1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(1)/lpp_waveform_dma_gen_valid_i/valid_in | |||
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144 | add wave -noupdate -group GEN_VALID_F1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(1)/lpp_waveform_dma_gen_valid_i/ack_in | |||
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145 | add wave -noupdate -group GEN_VALID_F1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(1)/lpp_waveform_dma_gen_valid_i/valid_out | |||
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146 | add wave -noupdate -group GEN_VALID_F1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(1)/lpp_waveform_dma_gen_valid_i/error | |||
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147 | add wave -noupdate -group GEN_VALID_F1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(1)/lpp_waveform_dma_gen_valid_i/state | |||
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148 | add wave -noupdate -group GEN_VALID_F2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(2)/lpp_waveform_dma_gen_valid_i/hclk | |||
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149 | add wave -noupdate -group GEN_VALID_F2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(2)/lpp_waveform_dma_gen_valid_i/hresetn | |||
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150 | add wave -noupdate -group GEN_VALID_F2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(2)/lpp_waveform_dma_gen_valid_i/valid_in | |||
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151 | add wave -noupdate -group GEN_VALID_F2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(2)/lpp_waveform_dma_gen_valid_i/ack_in | |||
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152 | add wave -noupdate -group GEN_VALID_F2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(2)/lpp_waveform_dma_gen_valid_i/valid_out | |||
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153 | add wave -noupdate -group GEN_VALID_F2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(2)/lpp_waveform_dma_gen_valid_i/error | |||
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154 | add wave -noupdate -group GEN_VALID_F2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(2)/lpp_waveform_dma_gen_valid_i/state | |||
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155 | add wave -noupdate -group GEN_VALID_F3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(3)/lpp_waveform_dma_gen_valid_i/hclk | |||
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156 | add wave -noupdate -group GEN_VALID_F3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(3)/lpp_waveform_dma_gen_valid_i/hresetn | |||
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157 | add wave -noupdate -group GEN_VALID_F3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(3)/lpp_waveform_dma_gen_valid_i/valid_in | |||
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158 | add wave -noupdate -group GEN_VALID_F3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(3)/lpp_waveform_dma_gen_valid_i/ack_in | |||
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159 | add wave -noupdate -group GEN_VALID_F3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(3)/lpp_waveform_dma_gen_valid_i/valid_out | |||
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160 | add wave -noupdate -group GEN_VALID_F3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(3)/lpp_waveform_dma_gen_valid_i/error | |||
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161 | add wave -noupdate -group GEN_VALID_F3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(3)/lpp_waveform_dma_gen_valid_i/state | |||
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162 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/valid_in | |||
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163 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/valid_out | |||
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164 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/valid_ack | |||
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165 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/status_new_err | |||
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166 | add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/clk | |||
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167 | add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/rstn | |||
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168 | add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/state | |||
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169 | add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_f0_valid | |||
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170 | add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_f1_valid | |||
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171 | add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_f2_valid | |||
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172 | add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_f3_valid | |||
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173 | add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_valid_ack | |||
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174 | add wave -noupdate -group FIFO_ARB -radix hexadecimal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_f0 | |||
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175 | add wave -noupdate -group FIFO_ARB -radix hexadecimal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_f1 | |||
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176 | add wave -noupdate -group FIFO_ARB -radix hexadecimal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_f2 | |||
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177 | add wave -noupdate -group FIFO_ARB -radix hexadecimal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_f3 | |||
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178 | add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/ready | |||
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179 | add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/time_wen | |||
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180 | add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_wen | |||
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181 | add wave -noupdate -group FIFO_ARB -radix hexadecimal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data | |||
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182 | add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_valid_and_ready | |||
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183 | add wave -noupdate -group FIFO_ARB -radix hexadecimal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_selected | |||
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184 | add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_valid_selected | |||
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185 | add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_ready_to_go | |||
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186 | add wave -noupdate -group FIFO_ARB -radix hexadecimal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_temp | |||
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187 | add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/time_en_temp | |||
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188 | add wave -noupdate -expand -group FIFO -expand -group {IN - OUT} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/rstn | |||
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189 | add wave -noupdate -expand -group FIFO -expand -group {IN - OUT} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/ready | |||
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190 | add wave -noupdate -expand -group FIFO -expand -group {IN - OUT} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/time_ren | |||
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191 | add wave -noupdate -expand -group FIFO -expand -group {IN - OUT} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/data_ren | |||
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|
192 | add wave -noupdate -expand -group FIFO -expand -group {IN - OUT} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/rdata | |||
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193 | add wave -noupdate -expand -group FIFO -expand -group {IN - OUT} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/time_wen | |||
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194 | add wave -noupdate -expand -group FIFO -expand -group {IN - OUT} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/data_wen | |||
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195 | add wave -noupdate -expand -group FIFO -expand -group {IN - OUT} -radix hexadecimal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/wdata | |||
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196 | add wave -noupdate -expand -group FIFO -expand -group read -radix hexadecimal -subitemconfig {/tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/time_mem_addr_r(3) {-radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/time_mem_addr_r(2) {-radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/time_mem_addr_r(1) {-radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/time_mem_addr_r(0) {-radix hexadecimal}} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/time_mem_addr_r | |||
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197 | add wave -noupdate -expand -group FIFO -expand -group read /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/data_mem_addr_r | |||
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198 | add wave -noupdate -expand -group FIFO -expand -group read /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/time_mem_ren | |||
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199 | add wave -noupdate -expand -group FIFO -expand -group read /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/data_mem_ren | |||
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200 | add wave -noupdate -expand -group FIFO -expand -group read /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/data_addr_r | |||
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201 | add wave -noupdate -expand -group FIFO -expand -group read /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/ren | |||
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202 | add wave -noupdate -expand -group FIFO -group write /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/data_mem_addr_w | |||
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203 | add wave -noupdate -expand -group FIFO -group write /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/time_mem_addr_w | |||
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204 | add wave -noupdate -expand -group FIFO -group write /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/data_mem_wen | |||
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205 | add wave -noupdate -expand -group FIFO -group write /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/time_mem_wen | |||
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206 | add wave -noupdate -expand -group FIFO -group write -radix unsigned /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/data_addr_w | |||
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207 | add wave -noupdate -expand -group FIFO -group write /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/wen | |||
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|
208 | add wave -noupdate -radix hexadecimal -subitemconfig {/tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(0) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(1) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(2) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(3) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(4) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(5) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(6) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(7) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(8) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(9) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(10) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(11) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(12) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(13) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(14) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(15) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(16) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(17) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(18) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(19) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(20) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(21) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(22) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(23) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(24) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(25) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(26) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(27) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(28) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(29) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(30) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(31) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(32) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(33) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(34) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(35) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(36) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(37) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(38) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(39) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(40) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(41) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(42) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(43) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(44) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(45) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(46) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(47) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(48) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(49) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(50) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(51) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(52) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(53) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(54) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(55) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(56) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(57) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(58) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(59) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(60) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(61) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(62) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(63) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(64) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(65) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(66) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(67) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(68) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(69) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(70) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(71) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(72) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(73) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(74) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(75) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(76) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(77) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(78) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(79) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(80) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(81) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(82) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(83) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(84) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(85) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(86) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(87) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(88) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(89) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(90) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(91) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(92) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(93) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(94) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(95) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(96) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(97) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(98) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(99) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(100) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(101) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(102) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(103) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(104) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(105) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(106) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(107) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(108) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(109) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(110) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(111) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(112) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(113) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(114) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(115) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(116) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(117) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(118) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(119) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(120) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(121) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(122) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(123) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(124) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(125) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(126) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(127) {-height 15 -radix hexadecimal}} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd | |||
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209 | add wave -noupdate -expand -group DMA -expand -group INOUT /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/hclk | |||
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210 | add wave -noupdate -expand -group DMA -expand -group INOUT /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/hresetn | |||
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211 | add wave -noupdate -expand -group DMA -expand -group INOUT /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/ahb_master_in | |||
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212 | add wave -noupdate -expand -group DMA -expand -group INOUT -subitemconfig {/tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/ahb_master_out.haddr {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/ahb_master_out.hwdata {-height 15 -radix hexadecimal}} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/ahb_master_out | |||
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213 | add wave -noupdate -expand -group DMA -expand -group INOUT -expand -group FIFO_interface /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/data_ready | |||
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214 | add wave -noupdate -expand -group DMA -expand -group INOUT -expand -group FIFO_interface /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/data | |||
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215 | add wave -noupdate -expand -group DMA -expand -group INOUT -expand -group FIFO_interface /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/data_data_ren | |||
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216 | add wave -noupdate -expand -group DMA -expand -group INOUT -expand -group FIFO_interface /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/data_time_ren | |||
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217 | add wave -noupdate -expand -group DMA -expand -group INOUT -expand -group REG_CONFIG -radix unsigned /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/nb_burst_available | |||
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218 | add wave -noupdate -expand -group DMA -expand -group INOUT -expand -group REG_CONFIG /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/addr_data_f0 | |||
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219 | add wave -noupdate -expand -group DMA -expand -group INOUT -expand -group REG_CONFIG /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/addr_data_f1 | |||
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220 | add wave -noupdate -expand -group DMA -expand -group INOUT -expand -group REG_CONFIG /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/addr_data_f2 | |||
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221 | add wave -noupdate -expand -group DMA -expand -group INOUT -expand -group REG_CONFIG /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/addr_data_f3 | |||
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222 | add wave -noupdate -expand -group DMA -expand -group INOUT /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/status_full | |||
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223 | add wave -noupdate -expand -group DMA -expand -group INOUT /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/status_full_ack | |||
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224 | add wave -noupdate -expand -group DMA -expand -group INOUT /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/status_full_err | |||
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225 | add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/dmain | |||
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226 | add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/dmaout | |||
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227 | add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/state | |||
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228 | add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/sel_data_s | |||
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229 | add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/sel_data | |||
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230 | add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/update | |||
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231 | add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/time_select | |||
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232 | add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/time_write | |||
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233 | add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/time_already_send | |||
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234 | add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/time_already_send_s | |||
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235 | add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/time_dmai | |||
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236 | add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/time_send | |||
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237 | add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/time_send_ok | |||
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238 | add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/time_send_ko | |||
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239 | add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/time_fifo_ren | |||
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240 | add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/time_ren | |||
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241 | add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/data_dmai | |||
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242 | add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/data_send | |||
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243 | add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/data_send_ok | |||
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244 | add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/data_send_ko | |||
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245 | add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/data_fifo_ren | |||
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246 | add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/data_ren | |||
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247 | add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/data_address | |||
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248 | add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/update_and_sel | |||
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249 | add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/addr_data_reg_vector | |||
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250 | add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/addr_data_vector | |||
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251 | add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/send_16_3_time | |||
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252 | add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/count_send_time | |||
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253 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/ren | |||
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254 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/wen | |||
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255 | add wave -noupdate -group fifo_ctrl_time_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(3)/lpp_waveform_fifo_ctrl_time/clk | |||
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256 | add wave -noupdate -group fifo_ctrl_time_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(3)/lpp_waveform_fifo_ctrl_time/rstn | |||
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257 | add wave -noupdate -group fifo_ctrl_time_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(3)/lpp_waveform_fifo_ctrl_time/ren | |||
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258 | add wave -noupdate -group fifo_ctrl_time_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(3)/lpp_waveform_fifo_ctrl_time/wen | |||
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259 | add wave -noupdate -group fifo_ctrl_time_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(3)/lpp_waveform_fifo_ctrl_time/mem_re | |||
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260 | add wave -noupdate -group fifo_ctrl_time_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(3)/lpp_waveform_fifo_ctrl_time/mem_we | |||
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261 | add wave -noupdate -group fifo_ctrl_time_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(3)/lpp_waveform_fifo_ctrl_time/mem_addr_ren | |||
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262 | add wave -noupdate -group fifo_ctrl_time_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(3)/lpp_waveform_fifo_ctrl_time/mem_addr_wen | |||
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263 | add wave -noupdate -group fifo_ctrl_time_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(3)/lpp_waveform_fifo_ctrl_time/ready | |||
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264 | add wave -noupdate -expand -group fifo_ctrl_time_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(2)/lpp_waveform_fifo_ctrl_time/clk | |||
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265 | add wave -noupdate -expand -group fifo_ctrl_time_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(2)/lpp_waveform_fifo_ctrl_time/rstn | |||
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266 | add wave -noupdate -expand -group fifo_ctrl_time_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(2)/lpp_waveform_fifo_ctrl_time/ren | |||
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267 | add wave -noupdate -expand -group fifo_ctrl_time_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(2)/lpp_waveform_fifo_ctrl_time/wen | |||
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268 | add wave -noupdate -expand -group fifo_ctrl_time_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(2)/lpp_waveform_fifo_ctrl_time/mem_re | |||
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269 | add wave -noupdate -expand -group fifo_ctrl_time_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(2)/lpp_waveform_fifo_ctrl_time/mem_we | |||
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270 | add wave -noupdate -expand -group fifo_ctrl_time_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(2)/lpp_waveform_fifo_ctrl_time/mem_addr_ren | |||
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271 | add wave -noupdate -expand -group fifo_ctrl_time_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(2)/lpp_waveform_fifo_ctrl_time/mem_addr_wen | |||
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272 | add wave -noupdate -expand -group fifo_ctrl_time_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(2)/lpp_waveform_fifo_ctrl_time/ready | |||
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273 | add wave -noupdate -expand -group fifo_ctrl_time_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(1)/lpp_waveform_fifo_ctrl_time/clk | |||
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274 | add wave -noupdate -expand -group fifo_ctrl_time_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(1)/lpp_waveform_fifo_ctrl_time/rstn | |||
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275 | add wave -noupdate -expand -group fifo_ctrl_time_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(1)/lpp_waveform_fifo_ctrl_time/ren | |||
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276 | add wave -noupdate -expand -group fifo_ctrl_time_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(1)/lpp_waveform_fifo_ctrl_time/wen | |||
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277 | add wave -noupdate -expand -group fifo_ctrl_time_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(1)/lpp_waveform_fifo_ctrl_time/mem_re | |||
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278 | add wave -noupdate -expand -group fifo_ctrl_time_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(1)/lpp_waveform_fifo_ctrl_time/mem_we | |||
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279 | add wave -noupdate -expand -group fifo_ctrl_time_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(1)/lpp_waveform_fifo_ctrl_time/mem_addr_ren | |||
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280 | add wave -noupdate -expand -group fifo_ctrl_time_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(1)/lpp_waveform_fifo_ctrl_time/mem_addr_wen | |||
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281 | add wave -noupdate -expand -group fifo_ctrl_time_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(1)/lpp_waveform_fifo_ctrl_time/ready | |||
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282 | add wave -noupdate -group fifo_ctrl_time_0 -group IN /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/clk | |||
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283 | add wave -noupdate -group fifo_ctrl_time_0 -group IN /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/rstn | |||
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284 | add wave -noupdate -group fifo_ctrl_time_0 -group IN /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/ren | |||
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285 | add wave -noupdate -group fifo_ctrl_time_0 -group IN /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/wen | |||
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286 | add wave -noupdate -group fifo_ctrl_time_0 -group OUT /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/mem_re | |||
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287 | add wave -noupdate -group fifo_ctrl_time_0 -group OUT /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/mem_we | |||
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288 | add wave -noupdate -group fifo_ctrl_time_0 -group OUT /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/mem_addr_ren | |||
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289 | add wave -noupdate -group fifo_ctrl_time_0 -group OUT /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/mem_addr_wen | |||
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290 | add wave -noupdate -group fifo_ctrl_time_0 -group OUT /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/ready | |||
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291 | add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/sfull | |||
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292 | add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/sfull_s | |||
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293 | add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/sempty_s | |||
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294 | add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/sempty | |||
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295 | add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/sren | |||
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296 | add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/swen | |||
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297 | add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/sre | |||
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298 | add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/swe | |||
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299 | add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/waddr_vect | |||
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300 | add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/raddr_vect | |||
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301 | add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/waddr_vect_s | |||
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302 | add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/raddr_vect_s | |||
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303 | add wave -noupdate -group fifo_ctrl_time_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/clk | |||
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304 | add wave -noupdate -group fifo_ctrl_time_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/rstn | |||
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305 | add wave -noupdate -group fifo_ctrl_time_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/ren | |||
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306 | add wave -noupdate -group fifo_ctrl_time_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/wen | |||
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307 | add wave -noupdate -group fifo_ctrl_time_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/mem_re | |||
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308 | add wave -noupdate -group fifo_ctrl_time_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/mem_we | |||
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309 | add wave -noupdate -group fifo_ctrl_time_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/mem_addr_ren | |||
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310 | add wave -noupdate -group fifo_ctrl_time_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/mem_addr_wen | |||
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311 | add wave -noupdate -group fifo_ctrl_time_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/ready | |||
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312 | add wave -noupdate -group fifo_ctrl_data_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(3)/lpp_waveform_fifo_ctrl_data/clk | |||
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|
313 | add wave -noupdate -group fifo_ctrl_data_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(3)/lpp_waveform_fifo_ctrl_data/rstn | |||
|
|
314 | add wave -noupdate -group fifo_ctrl_data_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(3)/lpp_waveform_fifo_ctrl_data/ren | |||
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|
315 | add wave -noupdate -group fifo_ctrl_data_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(3)/lpp_waveform_fifo_ctrl_data/wen | |||
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|
316 | add wave -noupdate -group fifo_ctrl_data_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(3)/lpp_waveform_fifo_ctrl_data/mem_re | |||
|
|
317 | add wave -noupdate -group fifo_ctrl_data_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(3)/lpp_waveform_fifo_ctrl_data/mem_we | |||
|
|
318 | add wave -noupdate -group fifo_ctrl_data_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(3)/lpp_waveform_fifo_ctrl_data/mem_addr_ren | |||
|
|
319 | add wave -noupdate -group fifo_ctrl_data_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(3)/lpp_waveform_fifo_ctrl_data/mem_addr_wen | |||
|
|
320 | add wave -noupdate -group fifo_ctrl_data_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(3)/lpp_waveform_fifo_ctrl_data/ready | |||
|
|
321 | add wave -noupdate -expand -group fifo_ctrl_data_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(2)/lpp_waveform_fifo_ctrl_data/clk | |||
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|
322 | add wave -noupdate -expand -group fifo_ctrl_data_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(2)/lpp_waveform_fifo_ctrl_data/rstn | |||
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323 | add wave -noupdate -expand -group fifo_ctrl_data_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(2)/lpp_waveform_fifo_ctrl_data/ren | |||
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|
324 | add wave -noupdate -expand -group fifo_ctrl_data_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(2)/lpp_waveform_fifo_ctrl_data/wen | |||
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|
325 | add wave -noupdate -expand -group fifo_ctrl_data_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(2)/lpp_waveform_fifo_ctrl_data/mem_re | |||
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326 | add wave -noupdate -expand -group fifo_ctrl_data_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(2)/lpp_waveform_fifo_ctrl_data/mem_we | |||
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327 | add wave -noupdate -expand -group fifo_ctrl_data_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(2)/lpp_waveform_fifo_ctrl_data/mem_addr_ren | |||
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328 | add wave -noupdate -expand -group fifo_ctrl_data_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(2)/lpp_waveform_fifo_ctrl_data/mem_addr_wen | |||
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329 | add wave -noupdate -expand -group fifo_ctrl_data_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(2)/lpp_waveform_fifo_ctrl_data/ready | |||
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330 | add wave -noupdate -group fifo_ctrl_data_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(1)/lpp_waveform_fifo_ctrl_data/clk | |||
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331 | add wave -noupdate -group fifo_ctrl_data_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(1)/lpp_waveform_fifo_ctrl_data/rstn | |||
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332 | add wave -noupdate -group fifo_ctrl_data_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(1)/lpp_waveform_fifo_ctrl_data/ren | |||
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333 | add wave -noupdate -group fifo_ctrl_data_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(1)/lpp_waveform_fifo_ctrl_data/wen | |||
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334 | add wave -noupdate -group fifo_ctrl_data_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(1)/lpp_waveform_fifo_ctrl_data/mem_re | |||
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335 | add wave -noupdate -group fifo_ctrl_data_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(1)/lpp_waveform_fifo_ctrl_data/mem_we | |||
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336 | add wave -noupdate -group fifo_ctrl_data_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(1)/lpp_waveform_fifo_ctrl_data/mem_addr_ren | |||
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337 | add wave -noupdate -group fifo_ctrl_data_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(1)/lpp_waveform_fifo_ctrl_data/mem_addr_wen | |||
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338 | add wave -noupdate -group fifo_ctrl_data_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(1)/lpp_waveform_fifo_ctrl_data/ready | |||
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339 | add wave -noupdate -group fifo_ctrl_data_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(0)/lpp_waveform_fifo_ctrl_data/clk | |||
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340 | add wave -noupdate -group fifo_ctrl_data_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(0)/lpp_waveform_fifo_ctrl_data/rstn | |||
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341 | add wave -noupdate -group fifo_ctrl_data_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(0)/lpp_waveform_fifo_ctrl_data/ren | |||
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342 | add wave -noupdate -group fifo_ctrl_data_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(0)/lpp_waveform_fifo_ctrl_data/wen | |||
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343 | add wave -noupdate -group fifo_ctrl_data_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(0)/lpp_waveform_fifo_ctrl_data/mem_re | |||
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344 | add wave -noupdate -group fifo_ctrl_data_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(0)/lpp_waveform_fifo_ctrl_data/mem_we | |||
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345 | add wave -noupdate -group fifo_ctrl_data_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(0)/lpp_waveform_fifo_ctrl_data/mem_addr_ren | |||
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346 | add wave -noupdate -group fifo_ctrl_data_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(0)/lpp_waveform_fifo_ctrl_data/mem_addr_wen | |||
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347 | add wave -noupdate -group fifo_ctrl_data_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(0)/lpp_waveform_fifo_ctrl_data/ready | |||
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348 | TreeUpdate [SetDefaultTree] | |||
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349 | WaveRestoreCursors {{Cursor 1} {70458134452 ps} 0} | |||
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350 | configure wave -namecolwidth 842 | |||
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351 | configure wave -valuecolwidth 100 | |||
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352 | configure wave -justifyvalue left | |||
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353 | configure wave -signalnamewidth 0 | |||
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354 | configure wave -snapdistance 10 | |||
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355 | configure wave -datasetprefix 0 | |||
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356 | configure wave -rowmargin 4 | |||
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357 | configure wave -childrowmargin 2 | |||
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358 | configure wave -gridoffset 0 | |||
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359 | configure wave -gridperiod 1 | |||
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360 | configure wave -griddelta 40 | |||
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361 | configure wave -timeline 0 | |||
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362 | configure wave -timelineunits ns | |||
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363 | update | |||
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|
364 | WaveRestoreZoom {70455153866 ps} {70464281299 ps} | |||
| @@ -0,0 +1,41 | |||||
|
|
1 | ||||
|
|
2 | --================================================================================= | |||
|
|
3 | --THIS FILE IS GENERATED BY A SCRIPT, DON'T TRY TO EDIT | |||
|
|
4 | -- | |||
|
|
5 | --TAKE A LOOK AT VHD_LIB/APB_DEVICES FOLDER TO ADD A DEVICE ID OR VENDOR ID | |||
|
|
6 | --================================================================================= | |||
|
|
7 | ||||
|
|
8 | ||||
|
|
9 | library ieee; | |||
|
|
10 | use ieee.std_logic_1164.all; | |||
|
|
11 | library grlib; | |||
|
|
12 | use grlib.amba.all; | |||
|
|
13 | use std.textio.all; | |||
|
|
14 | ||||
|
|
15 | ||||
|
|
16 | package apb_devices_list is | |||
|
|
17 | ||||
|
|
18 | ||||
|
|
19 | constant VENDOR_LPP : amba_vendor_type := 16#19#; | |||
|
|
20 | ||||
|
|
21 | constant ROCKET_TM : amba_device_type := 16#1#; | |||
|
|
22 | constant otherCore : amba_device_type := 16#2#; | |||
|
|
23 | constant LPP_SIMPLE_DIODE : amba_device_type := 16#3#; | |||
|
|
24 | constant LPP_MULTI_DIODE : amba_device_type := 16#4#; | |||
|
|
25 | constant LPP_LCD_CTRLR : amba_device_type := 16#5#; | |||
|
|
26 | constant LPP_UART : amba_device_type := 16#6#; | |||
|
|
27 | constant LPP_CNA : amba_device_type := 16#7#; | |||
|
|
28 | constant LPP_APB_ADC : amba_device_type := 16#8#; | |||
|
|
29 | constant LPP_CHENILLARD : amba_device_type := 16#9#; | |||
|
|
30 | constant LPP_IIR_CEL_FILTER : amba_device_type := 16#10#; | |||
|
|
31 | constant LPP_FIFO_PID : amba_device_type := 16#11#; | |||
|
|
32 | constant LPP_FFT : amba_device_type := 16#12#; | |||
|
|
33 | constant LPP_MATRIX : amba_device_type := 16#13#; | |||
|
|
34 | constant LPP_BALISE : amba_device_type := 16#14#; | |||
|
|
35 | constant LPP_USB : amba_device_type := 16#15#; | |||
|
|
36 | constant LPP_DELAY : amba_device_type := 16#16#; | |||
|
|
37 | constant LPP_DMA_TYPE : amba_device_type := 16#17#; | |||
|
|
38 | constant LPP_BOOTLOADER_TYPE : amba_device_type := 16#18#; | |||
|
|
39 | ||||
|
|
40 | ||||
|
|
41 | end; | |||
| @@ -0,0 +1,80 | |||||
|
|
1 | ------------------------------------------------------------------------------ | |||
|
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
|
4 | -- | |||
|
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
|
8 | -- (at your option) any later version. | |||
|
|
9 | -- | |||
|
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
|
13 | -- GNU General Public License for more details. | |||
|
|
14 | -- | |||
|
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
|
16 | -- along with this program; if not, write to the Free Software | |||
|
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
|
18 | ------------------------------------------------------------------------------- | |||
|
|
19 | -- Author : Martin Morlot | |||
|
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |||
|
|
21 | ------------------------------------------------------------------------------- | |||
|
|
22 | library IEEE; | |||
|
|
23 | use IEEE.numeric_std.all; | |||
|
|
24 | use IEEE.std_logic_1164.all; | |||
|
|
25 | ||||
|
|
26 | entity ReUse_CTRLR is | |||
|
|
27 | port( | |||
|
|
28 | clk : in std_logic; | |||
|
|
29 | reset : in std_logic; | |||
|
|
30 | ||||
|
|
31 | SetReUse : in std_logic_vector(4 downto 0); | |||
|
|
32 | Statu : in std_logic_vector(3 downto 0); | |||
|
|
33 | ||||
|
|
34 | ReUse : out std_logic_vector(4 downto 0) | |||
|
|
35 | ); | |||
|
|
36 | end entity; | |||
|
|
37 | ||||
|
|
38 | ||||
|
|
39 | architecture ar_ReUse_CTRLR of ReUse_CTRLR is | |||
|
|
40 | ||||
|
|
41 | signal ResetReUse : std_logic_vector(4 downto 0); | |||
|
|
42 | signal MatrixParam : integer; | |||
|
|
43 | signal MatrixParam_Reg : integer; | |||
|
|
44 | ||||
|
|
45 | begin | |||
|
|
46 | ||||
|
|
47 | ||||
|
|
48 | ||||
|
|
49 | process (clk,reset) | |||
|
|
50 | -- variable MatrixParam : integer; | |||
|
|
51 | begin | |||
|
|
52 | -- MatrixParam := to_integer(unsigned(Statu)); | |||
|
|
53 | ||||
|
|
54 | if(reset='0')then | |||
|
|
55 | ResetReUse <= (others => '1'); | |||
|
|
56 | MatrixParam_Reg <= 0; | |||
|
|
57 | ||||
|
|
58 | ||||
|
|
59 | elsif(clk' event and clk='1')then | |||
|
|
60 | MatrixParam_Reg <= MatrixParam; | |||
|
|
61 | ||||
|
|
62 | if(MatrixParam_Reg = 7 and MatrixParam = 8)then -- On videra FIFO(B1) a sa derni�re utilisation PARAM = 11 | |||
|
|
63 | ResetReUse(0) <= '0'; | |||
|
|
64 | elsif(MatrixParam_Reg = 8 and MatrixParam = 9)then -- On videra FIFO(B2) a sa derni�re utilisation PARAM = 12 | |||
|
|
65 | ResetReUse(1) <= '0'; | |||
|
|
66 | elsif(MatrixParam_Reg = 9 and MatrixParam = 10)then -- On videra FIFO(B3) a sa derni�re utilisation PARAM = 13 | |||
|
|
67 | ResetReUse(2) <= '0'; | |||
|
|
68 | elsif(MatrixParam_Reg = 10 and MatrixParam = 11)then -- On videra FIFO(E1) a sa derni�re utilisation PARAM = 14 | |||
|
|
69 | ResetReUse(3) <= '0'; | |||
|
|
70 | elsif(MatrixParam_Reg = 14 and MatrixParam = 15)then -- On videra FIFO(E2) a sa derni�re utilisation PARAM = 15 | |||
|
|
71 | ResetReUse(4) <= '0'; | |||
|
|
72 | end if; | |||
|
|
73 | ||||
|
|
74 | end if; | |||
|
|
75 | end process; | |||
|
|
76 | ||||
|
|
77 | MatrixParam <= to_integer(unsigned(Statu)); | |||
|
|
78 | ReUse <= SetReUse and ResetReUse; | |||
|
|
79 | ||||
|
|
80 | end architecture; No newline at end of file | |||
| @@ -0,0 +1,243 | |||||
|
|
1 | LIBRARY ieee; | |||
|
|
2 | USE ieee.std_logic_1164.ALL; | |||
|
|
3 | USE ieee.numeric_std.ALL; | |||
|
|
4 | ||||
|
|
5 | LIBRARY lpp; | |||
|
|
6 | USE lpp.lpp_ad_conv.ALL; | |||
|
|
7 | USE lpp.iir_filter.ALL; | |||
|
|
8 | USE lpp.FILTERcfg.ALL; | |||
|
|
9 | USE lpp.lpp_memory.ALL; | |||
|
|
10 | USE lpp.lpp_waveform_pkg.ALL; | |||
|
|
11 | USE lpp.lpp_top_lfr_pkg.ALL; | |||
|
|
12 | ||||
|
|
13 | LIBRARY techmap; | |||
|
|
14 | USE techmap.gencomp.ALL; | |||
|
|
15 | ||||
|
|
16 | LIBRARY grlib; | |||
|
|
17 | USE grlib.amba.ALL; | |||
|
|
18 | USE grlib.stdlib.ALL; | |||
|
|
19 | USE grlib.devices.ALL; | |||
|
|
20 | USE GRLIB.DMA2AHB_Package.ALL; | |||
|
|
21 | ||||
|
|
22 | ENTITY lpp_top_lfr_wf_picker IS | |||
|
|
23 | GENERIC ( | |||
|
|
24 | hindex : INTEGER := 2; | |||
|
|
25 | pindex : INTEGER := 4; | |||
|
|
26 | paddr : INTEGER := 4; | |||
|
|
27 | pmask : INTEGER := 16#fff#; | |||
|
|
28 | pirq : INTEGER := 0; | |||
|
|
29 | tech : INTEGER := 0; | |||
|
|
30 | nb_burst_available_size : INTEGER := 11; | |||
|
|
31 | nb_snapshot_param_size : INTEGER := 11; | |||
|
|
32 | delta_snapshot_size : INTEGER := 16; | |||
|
|
33 | delta_f2_f0_size : INTEGER := 10; | |||
|
|
34 | delta_f2_f1_size : INTEGER := 10 | |||
|
|
35 | ); | |||
|
|
36 | PORT ( | |||
|
|
37 | -- ADS7886 | |||
|
|
38 | cnv_run : IN STD_LOGIC; | |||
|
|
39 | cnv : OUT STD_LOGIC; | |||
|
|
40 | sck : OUT STD_LOGIC; | |||
|
|
41 | sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |||
|
|
42 | -- | |||
|
|
43 | cnv_clk : IN STD_LOGIC; | |||
|
|
44 | cnv_rstn : IN STD_LOGIC; | |||
|
|
45 | ||||
|
|
46 | -- AMBA AHB system signals | |||
|
|
47 | HCLK : IN STD_ULOGIC; | |||
|
|
48 | HRESETn : IN STD_ULOGIC; | |||
|
|
49 | ||||
|
|
50 | -- AMBA APB Slave Interface | |||
|
|
51 | apbi : IN apb_slv_in_type; | |||
|
|
52 | apbo : OUT apb_slv_out_type; | |||
|
|
53 | ||||
|
|
54 | -- AMBA AHB Master Interface | |||
|
|
55 | AHB_Master_In : IN AHB_Mst_In_Type; | |||
|
|
56 | AHB_Master_Out : OUT AHB_Mst_Out_Type; | |||
|
|
57 | ||||
|
|
58 | -- | |||
|
|
59 | coarse_time_0 : IN STD_LOGIC; | |||
|
|
60 | ||||
|
|
61 | -- | |||
|
|
62 | data_shaping_BW : OUT STD_LOGIC | |||
|
|
63 | ); | |||
|
|
64 | END lpp_top_lfr_wf_picker; | |||
|
|
65 | ||||
|
|
66 | ARCHITECTURE tb OF lpp_top_lfr_wf_picker IS | |||
|
|
67 | ||||
|
|
68 | SIGNAL ready_matrix_f0_0 : STD_LOGIC; | |||
|
|
69 | SIGNAL ready_matrix_f0_1 : STD_LOGIC; | |||
|
|
70 | SIGNAL ready_matrix_f1 : STD_LOGIC; | |||
|
|
71 | SIGNAL ready_matrix_f2 : STD_LOGIC; | |||
|
|
72 | SIGNAL error_anticipating_empty_fifo : STD_LOGIC; | |||
|
|
73 | SIGNAL error_bad_component_error : STD_LOGIC; | |||
|
|
74 | SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
75 | SIGNAL status_ready_matrix_f0_0 : STD_LOGIC; | |||
|
|
76 | SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; | |||
|
|
77 | SIGNAL status_ready_matrix_f1 : STD_LOGIC; | |||
|
|
78 | SIGNAL status_ready_matrix_f2 : STD_LOGIC; | |||
|
|
79 | SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC; | |||
|
|
80 | SIGNAL status_error_bad_component_error : STD_LOGIC; | |||
|
|
81 | SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC; | |||
|
|
82 | SIGNAL config_active_interruption_onError : STD_LOGIC; | |||
|
|
83 | SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
84 | SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
85 | SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
86 | SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
87 | ||||
|
|
88 | SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
89 | SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
90 | SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
91 | SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
92 | SIGNAL data_shaping_SP0 : STD_LOGIC; | |||
|
|
93 | SIGNAL data_shaping_SP1 : STD_LOGIC; | |||
|
|
94 | SIGNAL data_shaping_R0 : STD_LOGIC; | |||
|
|
95 | SIGNAL data_shaping_R1 : STD_LOGIC; | |||
|
|
96 | SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); | |||
|
|
97 | SIGNAL delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); | |||
|
|
98 | SIGNAL delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); | |||
|
|
99 | SIGNAL nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); | |||
|
|
100 | SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |||
|
|
101 | SIGNAL enable_f0 : STD_LOGIC; | |||
|
|
102 | SIGNAL enable_f1 : STD_LOGIC; | |||
|
|
103 | SIGNAL enable_f2 : STD_LOGIC; | |||
|
|
104 | SIGNAL enable_f3 : STD_LOGIC; | |||
|
|
105 | SIGNAL burst_f0 : STD_LOGIC; | |||
|
|
106 | SIGNAL burst_f1 : STD_LOGIC; | |||
|
|
107 | SIGNAL burst_f2 : STD_LOGIC; | |||
|
|
108 | SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
109 | SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
110 | SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
111 | SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
112 | ||||
|
|
113 | SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); | |||
|
|
114 | SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |||
|
|
115 | SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); | |||
|
|
116 | SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |||
|
|
117 | SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); | |||
|
|
118 | SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |||
|
|
119 | SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); | |||
|
|
120 | SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |||
|
|
121 | ||||
|
|
122 | ||||
|
|
123 | BEGIN | |||
|
|
124 | ||||
|
|
125 | lpp_top_apbreg_1: lpp_top_apbreg | |||
|
|
126 | GENERIC MAP ( | |||
|
|
127 | nb_burst_available_size => nb_burst_available_size, | |||
|
|
128 | nb_snapshot_param_size => nb_snapshot_param_size, | |||
|
|
129 | delta_snapshot_size => delta_snapshot_size, | |||
|
|
130 | delta_f2_f0_size => delta_f2_f0_size, | |||
|
|
131 | delta_f2_f1_size => delta_f2_f1_size, | |||
|
|
132 | pindex => pindex, | |||
|
|
133 | paddr => paddr, | |||
|
|
134 | pmask => pmask, | |||
|
|
135 | pirq => pirq) | |||
|
|
136 | PORT MAP ( | |||
|
|
137 | HCLK => HCLK, | |||
|
|
138 | HRESETn => HRESETn, | |||
|
|
139 | apbi => apbi, | |||
|
|
140 | apbo => apbo, | |||
|
|
141 | ||||
|
|
142 | ready_matrix_f0_0 => ready_matrix_f0_0, | |||
|
|
143 | ready_matrix_f0_1 => ready_matrix_f0_1, | |||
|
|
144 | ready_matrix_f1 => ready_matrix_f1, | |||
|
|
145 | ready_matrix_f2 => ready_matrix_f2, | |||
|
|
146 | error_anticipating_empty_fifo => error_anticipating_empty_fifo, | |||
|
|
147 | error_bad_component_error => error_bad_component_error, | |||
|
|
148 | debug_reg => debug_reg, | |||
|
|
149 | status_ready_matrix_f0_0 => status_ready_matrix_f0_0, | |||
|
|
150 | status_ready_matrix_f0_1 => status_ready_matrix_f0_1, | |||
|
|
151 | status_ready_matrix_f1 => status_ready_matrix_f1, | |||
|
|
152 | status_ready_matrix_f2 => status_ready_matrix_f2, | |||
|
|
153 | status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, | |||
|
|
154 | status_error_bad_component_error => status_error_bad_component_error, | |||
|
|
155 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, | |||
|
|
156 | config_active_interruption_onError => config_active_interruption_onError, | |||
|
|
157 | addr_matrix_f0_0 => addr_matrix_f0_0, | |||
|
|
158 | addr_matrix_f0_1 => addr_matrix_f0_1, | |||
|
|
159 | addr_matrix_f1 => addr_matrix_f1, | |||
|
|
160 | addr_matrix_f2 => addr_matrix_f2, | |||
|
|
161 | ||||
|
|
162 | status_full => status_full, | |||
|
|
163 | status_full_ack => status_full_ack, | |||
|
|
164 | status_full_err => status_full_err, | |||
|
|
165 | status_new_err => status_new_err, | |||
|
|
166 | data_shaping_BW => data_shaping_BW, | |||
|
|
167 | data_shaping_SP0 => data_shaping_SP0, | |||
|
|
168 | data_shaping_SP1 => data_shaping_SP1, | |||
|
|
169 | data_shaping_R0 => data_shaping_R0, | |||
|
|
170 | data_shaping_R1 => data_shaping_R1, | |||
|
|
171 | delta_snapshot => delta_snapshot, | |||
|
|
172 | delta_f2_f1 => delta_f2_f1, | |||
|
|
173 | delta_f2_f0 => delta_f2_f0, | |||
|
|
174 | nb_burst_available => nb_burst_available, | |||
|
|
175 | nb_snapshot_param => nb_snapshot_param, | |||
|
|
176 | enable_f0 => enable_f0, | |||
|
|
177 | enable_f1 => enable_f1, | |||
|
|
178 | enable_f2 => enable_f2, | |||
|
|
179 | enable_f3 => enable_f3, | |||
|
|
180 | burst_f0 => burst_f0, | |||
|
|
181 | burst_f1 => burst_f1, | |||
|
|
182 | burst_f2 => burst_f2, | |||
|
|
183 | addr_data_f0 => addr_data_f0, | |||
|
|
184 | addr_data_f1 => addr_data_f1, | |||
|
|
185 | addr_data_f2 => addr_data_f2, | |||
|
|
186 | addr_data_f3 => addr_data_f3); | |||
|
|
187 | ||||
|
|
188 | lpp_top_lfr_wf_picker_ip_1: lpp_top_lfr_wf_picker_ip | |||
|
|
189 | GENERIC MAP ( | |||
|
|
190 | hindex => hindex, | |||
|
|
191 | nb_burst_available_size => nb_burst_available_size, | |||
|
|
192 | nb_snapshot_param_size => nb_snapshot_param_size, | |||
|
|
193 | delta_snapshot_size => delta_snapshot_size, | |||
|
|
194 | delta_f2_f0_size => delta_f2_f0_size, | |||
|
|
195 | delta_f2_f1_size => delta_f2_f1_size, | |||
|
|
196 | tech => tech) | |||
|
|
197 | PORT MAP ( | |||
|
|
198 | cnv_run => cnv_run, | |||
|
|
199 | cnv => cnv, | |||
|
|
200 | sck => sck, | |||
|
|
201 | sdo => sdo, | |||
|
|
202 | cnv_clk => cnv_clk, | |||
|
|
203 | cnv_rstn => cnv_rstn, | |||
|
|
204 | ||||
|
|
205 | clk => HCLK, | |||
|
|
206 | rstn => HRESETn, | |||
|
|
207 | ||||
|
|
208 | sample_f0_wen => sample_f0_wen, | |||
|
|
209 | sample_f0_wdata => sample_f0_wdata, | |||
|
|
210 | sample_f1_wen => sample_f1_wen, | |||
|
|
211 | sample_f1_wdata => sample_f1_wdata, | |||
|
|
212 | sample_f2_wen => sample_f2_wen, | |||
|
|
213 | sample_f2_wdata => sample_f2_wdata, | |||
|
|
214 | sample_f3_wen => sample_f3_wen, | |||
|
|
215 | sample_f3_wdata => sample_f3_wdata, | |||
|
|
216 | AHB_Master_In => AHB_Master_In, | |||
|
|
217 | AHB_Master_Out => AHB_Master_Out, | |||
|
|
218 | coarse_time_0 => coarse_time_0, | |||
|
|
219 | data_shaping_SP0 => data_shaping_SP0, | |||
|
|
220 | data_shaping_SP1 => data_shaping_SP1, | |||
|
|
221 | data_shaping_R0 => data_shaping_R0, | |||
|
|
222 | data_shaping_R1 => data_shaping_R1, | |||
|
|
223 | delta_snapshot => delta_snapshot, | |||
|
|
224 | delta_f2_f1 => delta_f2_f1, | |||
|
|
225 | delta_f2_f0 => delta_f2_f0, | |||
|
|
226 | enable_f0 => enable_f0, | |||
|
|
227 | enable_f1 => enable_f1, | |||
|
|
228 | enable_f2 => enable_f2, | |||
|
|
229 | enable_f3 => enable_f3, | |||
|
|
230 | burst_f0 => burst_f0, | |||
|
|
231 | burst_f1 => burst_f1, | |||
|
|
232 | burst_f2 => burst_f2, | |||
|
|
233 | nb_burst_available => nb_burst_available, | |||
|
|
234 | nb_snapshot_param => nb_snapshot_param, | |||
|
|
235 | status_full => status_full, | |||
|
|
236 | status_full_ack => status_full_ack, | |||
|
|
237 | status_full_err => status_full_err, | |||
|
|
238 | status_new_err => status_new_err, | |||
|
|
239 | addr_data_f0 => addr_data_f0, | |||
|
|
240 | addr_data_f1 => addr_data_f1, | |||
|
|
241 | addr_data_f2 => addr_data_f2, | |||
|
|
242 | addr_data_f3 => addr_data_f3); | |||
|
|
243 | END tb; | |||
| @@ -0,0 +1,498 | |||||
|
|
1 | LIBRARY ieee; | |||
|
|
2 | USE ieee.std_logic_1164.ALL; | |||
|
|
3 | USE ieee.numeric_std.ALL; | |||
|
|
4 | ||||
|
|
5 | LIBRARY lpp; | |||
|
|
6 | USE lpp.lpp_ad_conv.ALL; | |||
|
|
7 | USE lpp.iir_filter.ALL; | |||
|
|
8 | USE lpp.FILTERcfg.ALL; | |||
|
|
9 | USE lpp.lpp_memory.ALL; | |||
|
|
10 | USE lpp.lpp_waveform_pkg.ALL; | |||
|
|
11 | ||||
|
|
12 | LIBRARY techmap; | |||
|
|
13 | USE techmap.gencomp.ALL; | |||
|
|
14 | ||||
|
|
15 | LIBRARY grlib; | |||
|
|
16 | USE grlib.amba.ALL; | |||
|
|
17 | USE grlib.stdlib.ALL; | |||
|
|
18 | USE grlib.devices.ALL; | |||
|
|
19 | USE GRLIB.DMA2AHB_Package.ALL; | |||
|
|
20 | ||||
|
|
21 | ENTITY lpp_top_lfr_wf_picker_ip IS | |||
|
|
22 | GENERIC( | |||
|
|
23 | hindex : INTEGER := 2; | |||
|
|
24 | nb_burst_available_size : INTEGER := 11; | |||
|
|
25 | nb_snapshot_param_size : INTEGER := 11; | |||
|
|
26 | delta_snapshot_size : INTEGER := 16; | |||
|
|
27 | delta_f2_f0_size : INTEGER := 10; | |||
|
|
28 | delta_f2_f1_size : INTEGER := 10; | |||
|
|
29 | tech : INTEGER := 0 | |||
|
|
30 | ); | |||
|
|
31 | PORT ( | |||
|
|
32 | -- ADS7886 | |||
|
|
33 | cnv_run : IN STD_LOGIC; | |||
|
|
34 | cnv : OUT STD_LOGIC; | |||
|
|
35 | sck : OUT STD_LOGIC; | |||
|
|
36 | sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |||
|
|
37 | -- | |||
|
|
38 | cnv_clk : IN STD_LOGIC; | |||
|
|
39 | cnv_rstn : IN STD_LOGIC; | |||
|
|
40 | -- | |||
|
|
41 | clk : IN STD_LOGIC; | |||
|
|
42 | rstn : IN STD_LOGIC; | |||
|
|
43 | -- | |||
|
|
44 | sample_f0_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); | |||
|
|
45 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |||
|
|
46 | -- | |||
|
|
47 | sample_f1_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); | |||
|
|
48 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |||
|
|
49 | -- | |||
|
|
50 | sample_f2_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); | |||
|
|
51 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |||
|
|
52 | -- | |||
|
|
53 | sample_f3_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); | |||
|
|
54 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |||
|
|
55 | ||||
|
|
56 | -- AMBA AHB Master Interface | |||
|
|
57 | AHB_Master_In : IN AHB_Mst_In_Type; | |||
|
|
58 | AHB_Master_Out : OUT AHB_Mst_Out_Type; | |||
|
|
59 | ||||
|
|
60 | coarse_time_0 : IN STD_LOGIC; | |||
|
|
61 | ||||
|
|
62 | --config | |||
|
|
63 | data_shaping_SP0 : IN STD_LOGIC; | |||
|
|
64 | data_shaping_SP1 : IN STD_LOGIC; | |||
|
|
65 | data_shaping_R0 : IN STD_LOGIC; | |||
|
|
66 | data_shaping_R1 : IN STD_LOGIC; | |||
|
|
67 | ||||
|
|
68 | delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); | |||
|
|
69 | delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); | |||
|
|
70 | delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); | |||
|
|
71 | ||||
|
|
72 | enable_f0 : IN STD_LOGIC; | |||
|
|
73 | enable_f1 : IN STD_LOGIC; | |||
|
|
74 | enable_f2 : IN STD_LOGIC; | |||
|
|
75 | enable_f3 : IN STD_LOGIC; | |||
|
|
76 | ||||
|
|
77 | burst_f0 : IN STD_LOGIC; | |||
|
|
78 | burst_f1 : IN STD_LOGIC; | |||
|
|
79 | burst_f2 : IN STD_LOGIC; | |||
|
|
80 | ||||
|
|
81 | nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); | |||
|
|
82 | nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |||
|
|
83 | status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
84 | status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
85 | status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
86 | status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma | |||
|
|
87 | ||||
|
|
88 | addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
89 | addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
90 | addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
91 | addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) | |||
|
|
92 | ); | |||
|
|
93 | END lpp_top_lfr_wf_picker_ip; | |||
|
|
94 | ||||
|
|
95 | ARCHITECTURE tb OF lpp_top_lfr_wf_picker_ip IS | |||
|
|
96 | ||||
|
|
97 | COMPONENT Downsampling | |||
|
|
98 | GENERIC ( | |||
|
|
99 | ChanelCount : INTEGER; | |||
|
|
100 | SampleSize : INTEGER; | |||
|
|
101 | DivideParam : INTEGER); | |||
|
|
102 | PORT ( | |||
|
|
103 | clk : IN STD_LOGIC; | |||
|
|
104 | rstn : IN STD_LOGIC; | |||
|
|
105 | sample_in_val : IN STD_LOGIC; | |||
|
|
106 | sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0); | |||
|
|
107 | sample_out_val : OUT STD_LOGIC; | |||
|
|
108 | sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0)); | |||
|
|
109 | END COMPONENT; | |||
|
|
110 | ||||
|
|
111 | ----------------------------------------------------------------------------- | |||
|
|
112 | CONSTANT ChanelCount : INTEGER := 8; | |||
|
|
113 | CONSTANT ncycle_cnv_high : INTEGER := 79; | |||
|
|
114 | CONSTANT ncycle_cnv : INTEGER := 500; | |||
|
|
115 | ||||
|
|
116 | ----------------------------------------------------------------------------- | |||
|
|
117 | SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0); | |||
|
|
118 | SIGNAL sample_val : STD_LOGIC; | |||
|
|
119 | SIGNAL sample_val_delay : STD_LOGIC; | |||
|
|
120 | ----------------------------------------------------------------------------- | |||
|
|
121 | CONSTANT Coef_SZ : INTEGER := 9; | |||
|
|
122 | CONSTANT CoefCntPerCel : INTEGER := 6; | |||
|
|
123 | CONSTANT CoefPerCel : INTEGER := 5; | |||
|
|
124 | CONSTANT Cels_count : INTEGER := 5; | |||
|
|
125 | ||||
|
|
126 | SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0); | |||
|
|
127 | SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0); | |||
|
|
128 | SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |||
|
|
129 | SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |||
|
|
130 | -- | |||
|
|
131 | SIGNAL sample_filter_v2_out_val : STD_LOGIC; | |||
|
|
132 | SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |||
|
|
133 | ----------------------------------------------------------------------------- | |||
|
|
134 | SIGNAL sample_data_shaping_out_val : STD_LOGIC; | |||
|
|
135 | SIGNAL sample_data_shaping_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |||
|
|
136 | SIGNAL sample_data_shaping_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0); | |||
|
|
137 | SIGNAL sample_data_shaping_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0); | |||
|
|
138 | SIGNAL sample_data_shaping_f2_s : STD_LOGIC_VECTOR(17 DOWNTO 0); | |||
|
|
139 | SIGNAL sample_data_shaping_f1_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0); | |||
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140 | SIGNAL sample_data_shaping_f2_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0); | |||
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141 | ----------------------------------------------------------------------------- | |||
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142 | SIGNAL sample_filter_v2_out_val_s : STD_LOGIC; | |||
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143 | SIGNAL sample_filter_v2_out_s : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0); | |||
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144 | ----------------------------------------------------------------------------- | |||
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145 | SIGNAL sample_f0_val : STD_LOGIC; | |||
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146 | SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0); | |||
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147 | SIGNAL sample_f0_s : samplT(5 DOWNTO 0, 15 DOWNTO 0); | |||
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148 | -- | |||
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149 | SIGNAL sample_f1_val : STD_LOGIC; | |||
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150 | SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0); | |||
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151 | SIGNAL sample_f1_s : samplT(5 DOWNTO 0, 15 DOWNTO 0); | |||
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152 | -- | |||
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153 | SIGNAL sample_f2_val : STD_LOGIC; | |||
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154 | SIGNAL sample_f2 : samplT(5 DOWNTO 0, 15 DOWNTO 0); | |||
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155 | -- | |||
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156 | SIGNAL sample_f3_val : STD_LOGIC; | |||
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157 | SIGNAL sample_f3 : samplT(5 DOWNTO 0, 15 DOWNTO 0); | |||
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158 | ||||
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159 | ----------------------------------------------------------------------------- | |||
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160 | SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); | |||
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161 | SIGNAL data_f1_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); | |||
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162 | SIGNAL data_f2_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); | |||
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163 | SIGNAL data_f3_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); | |||
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164 | ----------------------------------------------------------------------------- | |||
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165 | ||||
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166 | SIGNAL sample_f0_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |||
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167 | SIGNAL sample_f1_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |||
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168 | SIGNAL sample_f2_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |||
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169 | SIGNAL sample_f3_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |||
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170 | BEGIN | |||
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171 | ||||
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172 | -- component instantiation | |||
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173 | ----------------------------------------------------------------------------- | |||
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174 | DIGITAL_acquisition : AD7688_drvr | |||
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175 | GENERIC MAP ( | |||
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176 | ChanelCount => ChanelCount, | |||
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177 | ncycle_cnv_high => ncycle_cnv_high, | |||
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178 | ncycle_cnv => ncycle_cnv) | |||
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179 | PORT MAP ( | |||
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180 | cnv_clk => cnv_clk, -- | |||
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181 | cnv_rstn => cnv_rstn, -- | |||
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182 | cnv_run => cnv_run, -- | |||
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183 | cnv => cnv, -- | |||
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184 | clk => clk, -- | |||
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185 | rstn => rstn, -- | |||
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186 | sck => sck, -- | |||
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187 | sdo => sdo(ChanelCount-1 DOWNTO 0), -- | |||
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188 | sample => sample, | |||
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189 | sample_val => sample_val); | |||
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190 | ||||
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191 | ----------------------------------------------------------------------------- | |||
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192 | ||||
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193 | PROCESS (clk, rstn) | |||
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194 | BEGIN -- PROCESS | |||
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195 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
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196 | sample_val_delay <= '0'; | |||
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197 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |||
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198 | sample_val_delay <= sample_val; | |||
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199 | END IF; | |||
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200 | END PROCESS; | |||
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201 | ||||
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202 | ----------------------------------------------------------------------------- | |||
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203 | ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE | |||
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204 | SampleLoop : FOR j IN 0 TO 15 GENERATE | |||
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205 | sample_filter_in(i, j) <= sample(i)(j); | |||
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206 | END GENERATE; | |||
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207 | ||||
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208 | sample_filter_in(i, 16) <= sample(i)(15); | |||
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209 | sample_filter_in(i, 17) <= sample(i)(15); | |||
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210 | END GENERATE; | |||
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211 | ||||
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212 | coefs_v2 <= CoefsInitValCst_v2; | |||
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213 | ||||
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214 | IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 | |||
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215 | GENERIC MAP ( | |||
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216 | tech => 0, | |||
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217 | Mem_use => use_CEL, -- use_RAM | |||
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218 | Sample_SZ => 18, | |||
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219 | Coef_SZ => Coef_SZ, | |||
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220 | Coef_Nb => 25, | |||
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221 | Coef_sel_SZ => 5, | |||
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222 | Cels_count => Cels_count, | |||
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223 | ChanelsCount => ChanelCount) | |||
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224 | PORT MAP ( | |||
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225 | rstn => rstn, | |||
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226 | clk => clk, | |||
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227 | virg_pos => 7, | |||
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228 | coefs => coefs_v2, | |||
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229 | sample_in_val => sample_val_delay, | |||
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230 | sample_in => sample_filter_in, | |||
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231 | sample_out_val => sample_filter_v2_out_val, | |||
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232 | sample_out => sample_filter_v2_out); | |||
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233 | ||||
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234 | ----------------------------------------------------------------------------- | |||
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235 | -- DATA_SHAPING | |||
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236 | ----------------------------------------------------------------------------- | |||
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237 | all_data_shaping_in_loop: FOR I IN 17 DOWNTO 0 GENERATE | |||
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238 | sample_data_shaping_f0_s(I) <= sample_filter_v2_out(0,I); | |||
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239 | sample_data_shaping_f1_s(I) <= sample_filter_v2_out(1,I); | |||
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240 | sample_data_shaping_f2_s(I) <= sample_filter_v2_out(2,I); | |||
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241 | END GENERATE all_data_shaping_in_loop; | |||
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242 | ||||
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243 | sample_data_shaping_f1_f0_s <= sample_data_shaping_f1_s - sample_data_shaping_f0_s; | |||
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244 | sample_data_shaping_f2_f1_s <= sample_data_shaping_f2_s - sample_data_shaping_f1_s; | |||
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245 | ||||
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246 | PROCESS (clk, rstn) | |||
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247 | BEGIN -- PROCESS | |||
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248 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
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249 | sample_data_shaping_out_val <= '0'; | |||
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250 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |||
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251 | sample_data_shaping_out_val <= sample_filter_v2_out_val; | |||
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252 | END IF; | |||
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253 | END PROCESS; | |||
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254 | ||||
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255 | SampleLoop_data_shaping: FOR j IN 0 TO 17 GENERATE | |||
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256 | PROCESS (clk, rstn) | |||
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257 | BEGIN | |||
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258 | IF rstn = '0' THEN | |||
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259 | sample_data_shaping_out(0,j) <= '0'; | |||
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260 | sample_data_shaping_out(1,j) <= '0'; | |||
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261 | sample_data_shaping_out(2,j) <= '0'; | |||
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262 | sample_data_shaping_out(3,j) <= '0'; | |||
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263 | sample_data_shaping_out(4,j) <= '0'; | |||
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264 | sample_data_shaping_out(5,j) <= '0'; | |||
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265 | sample_data_shaping_out(6,j) <= '0'; | |||
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266 | sample_data_shaping_out(7,j) <= '0'; | |||
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267 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |||
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268 | sample_data_shaping_out(0,j) <= sample_filter_v2_out(0,j); | |||
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269 | IF data_shaping_SP0 = '1' THEN | |||
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270 | sample_data_shaping_out(1,j) <= sample_data_shaping_f1_f0_s(j); | |||
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271 | ELSE | |||
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272 | sample_data_shaping_out(1,j) <= sample_filter_v2_out(1,j); | |||
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273 | END IF; | |||
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274 | IF data_shaping_SP1 = '1' THEN | |||
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275 | sample_data_shaping_out(2,j) <= sample_data_shaping_f2_f1_s(j); | |||
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276 | ELSE | |||
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277 | sample_data_shaping_out(2,j) <= sample_filter_v2_out(2,j); | |||
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278 | END IF; | |||
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279 | sample_data_shaping_out(4,j) <= sample_filter_v2_out(4,j); | |||
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280 | sample_data_shaping_out(5,j) <= sample_filter_v2_out(5,j); | |||
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281 | sample_data_shaping_out(6,j) <= sample_filter_v2_out(6,j); | |||
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282 | sample_data_shaping_out(7,j) <= sample_filter_v2_out(7,j); | |||
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283 | END IF; | |||
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284 | END PROCESS; | |||
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285 | END GENERATE; | |||
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286 | ||||
|
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287 | sample_filter_v2_out_val_s <= sample_data_shaping_out_val; | |||
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288 | ChanelLoopOut : FOR i IN 0 TO 7 GENERATE | |||
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289 | SampleLoopOut : FOR j IN 0 TO 15 GENERATE | |||
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290 | sample_filter_v2_out_s(i,j) <= sample_data_shaping_out(i,j); | |||
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291 | END GENERATE; | |||
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292 | END GENERATE; | |||
|
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293 | ----------------------------------------------------------------------------- | |||
|
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294 | -- F0 -- @24.576 kHz | |||
|
|
295 | ----------------------------------------------------------------------------- | |||
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296 | Downsampling_f0 : Downsampling | |||
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297 | GENERIC MAP ( | |||
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298 | ChanelCount => 8, | |||
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299 | SampleSize => 16, | |||
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300 | DivideParam => 4) | |||
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301 | PORT MAP ( | |||
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302 | clk => clk, | |||
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303 | rstn => rstn, | |||
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304 | sample_in_val => sample_filter_v2_out_val_s, | |||
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305 | sample_in => sample_filter_v2_out_s, | |||
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306 | sample_out_val => sample_f0_val, | |||
|
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307 | sample_out => sample_f0); | |||
|
|
308 | ||||
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309 | all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE | |||
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310 | sample_f0_wdata_s(I) <= sample_f0(0, I); -- V | |||
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311 | sample_f0_wdata_s(16*1+I) <= sample_f0(1, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(3, I); -- E1 | |||
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312 | sample_f0_wdata_s(16*2+I) <= sample_f0(2, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(4, I); -- E2 | |||
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313 | sample_f0_wdata_s(16*3+I) <= sample_f0(5, I); -- B1 | |||
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314 | sample_f0_wdata_s(16*4+I) <= sample_f0(6, I); -- B2 | |||
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315 | sample_f0_wdata_s(16*5+I) <= sample_f0(7, I); -- B3 | |||
|
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316 | END GENERATE all_bit_sample_f0; | |||
|
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317 | ||||
|
|
318 | sample_f0_wen <= NOT(sample_f0_val) & | |||
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319 | NOT(sample_f0_val) & | |||
|
|
320 | NOT(sample_f0_val) & | |||
|
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321 | NOT(sample_f0_val) & | |||
|
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322 | NOT(sample_f0_val) & | |||
|
|
323 | NOT(sample_f0_val); | |||
|
|
324 | ||||
|
|
325 | ----------------------------------------------------------------------------- | |||
|
|
326 | -- F1 -- @4096 Hz | |||
|
|
327 | ----------------------------------------------------------------------------- | |||
|
|
328 | Downsampling_f1 : Downsampling | |||
|
|
329 | GENERIC MAP ( | |||
|
|
330 | ChanelCount => 8, | |||
|
|
331 | SampleSize => 16, | |||
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|
332 | DivideParam => 6) | |||
|
|
333 | PORT MAP ( | |||
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|
334 | clk => clk, | |||
|
|
335 | rstn => rstn, | |||
|
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336 | sample_in_val => sample_f0_val , | |||
|
|
337 | sample_in => sample_f0, | |||
|
|
338 | sample_out_val => sample_f1_val, | |||
|
|
339 | sample_out => sample_f1); | |||
|
|
340 | ||||
|
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341 | all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE | |||
|
|
342 | sample_f1_wdata_s(I) <= sample_f1(0, I); -- V | |||
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|
343 | sample_f1_wdata_s(16*1+I) <= sample_f1(1, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(3, I); -- E1 | |||
|
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344 | sample_f1_wdata_s(16*2+I) <= sample_f1(2, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(4, I); -- E2 | |||
|
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345 | sample_f1_wdata_s(16*3+I) <= sample_f1(5, I); -- B1 | |||
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346 | sample_f1_wdata_s(16*4+I) <= sample_f1(6, I); -- B2 | |||
|
|
347 | sample_f1_wdata_s(16*5+I) <= sample_f1(7, I); -- B3 | |||
|
|
348 | END GENERATE all_bit_sample_f1; | |||
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|
349 | ||||
|
|
350 | sample_f1_wen <= NOT(sample_f1_val) & | |||
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|
351 | NOT(sample_f1_val) & | |||
|
|
352 | NOT(sample_f1_val) & | |||
|
|
353 | NOT(sample_f1_val) & | |||
|
|
354 | NOT(sample_f1_val) & | |||
|
|
355 | NOT(sample_f1_val); | |||
|
|
356 | ||||
|
|
357 | ----------------------------------------------------------------------------- | |||
|
|
358 | -- F2 -- @256 Hz | |||
|
|
359 | ----------------------------------------------------------------------------- | |||
|
|
360 | all_bit_sample_f0_s : FOR I IN 15 DOWNTO 0 GENERATE | |||
|
|
361 | sample_f0_s(0, I) <= sample_f0(0, I); -- V | |||
|
|
362 | sample_f0_s(1, I) <= sample_f0(1, I); -- E1 | |||
|
|
363 | sample_f0_s(2, I) <= sample_f0(2, I); -- E2 | |||
|
|
364 | sample_f0_s(3, I) <= sample_f0(5, I); -- B1 | |||
|
|
365 | sample_f0_s(4, I) <= sample_f0(6, I); -- B2 | |||
|
|
366 | sample_f0_s(5, I) <= sample_f0(7, I); -- B3 | |||
|
|
367 | END GENERATE all_bit_sample_f0_s; | |||
|
|
368 | ||||
|
|
369 | Downsampling_f2 : Downsampling | |||
|
|
370 | GENERIC MAP ( | |||
|
|
371 | ChanelCount => 6, | |||
|
|
372 | SampleSize => 16, | |||
|
|
373 | DivideParam => 96) | |||
|
|
374 | PORT MAP ( | |||
|
|
375 | clk => clk, | |||
|
|
376 | rstn => rstn, | |||
|
|
377 | sample_in_val => sample_f0_val , | |||
|
|
378 | sample_in => sample_f0_s, | |||
|
|
379 | sample_out_val => sample_f2_val, | |||
|
|
380 | sample_out => sample_f2); | |||
|
|
381 | ||||
|
|
382 | sample_f2_wen <= NOT(sample_f2_val) & | |||
|
|
383 | NOT(sample_f2_val) & | |||
|
|
384 | NOT(sample_f2_val) & | |||
|
|
385 | NOT(sample_f2_val) & | |||
|
|
386 | NOT(sample_f2_val) & | |||
|
|
387 | NOT(sample_f2_val); | |||
|
|
388 | ||||
|
|
389 | all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE | |||
|
|
390 | sample_f2_wdata_s(I) <= sample_f2(0, I); | |||
|
|
391 | sample_f2_wdata_s(16*1+I) <= sample_f2(1, I); | |||
|
|
392 | sample_f2_wdata_s(16*2+I) <= sample_f2(2, I); | |||
|
|
393 | sample_f2_wdata_s(16*3+I) <= sample_f2(3, I); | |||
|
|
394 | sample_f2_wdata_s(16*4+I) <= sample_f2(4, I); | |||
|
|
395 | sample_f2_wdata_s(16*5+I) <= sample_f2(5, I); | |||
|
|
396 | END GENERATE all_bit_sample_f2; | |||
|
|
397 | ||||
|
|
398 | ----------------------------------------------------------------------------- | |||
|
|
399 | -- F3 -- @16 Hz | |||
|
|
400 | ----------------------------------------------------------------------------- | |||
|
|
401 | all_bit_sample_f1_s : FOR I IN 15 DOWNTO 0 GENERATE | |||
|
|
402 | sample_f1_s(0, I) <= sample_f1(0, I); -- V | |||
|
|
403 | sample_f1_s(1, I) <= sample_f1(1, I); -- E1 | |||
|
|
404 | sample_f1_s(2, I) <= sample_f1(2, I); -- E2 | |||
|
|
405 | sample_f1_s(3, I) <= sample_f1(5, I); -- B1 | |||
|
|
406 | sample_f1_s(4, I) <= sample_f1(6, I); -- B2 | |||
|
|
407 | sample_f1_s(5, I) <= sample_f1(7, I); -- B3 | |||
|
|
408 | END GENERATE all_bit_sample_f1_s; | |||
|
|
409 | ||||
|
|
410 | Downsampling_f3 : Downsampling | |||
|
|
411 | GENERIC MAP ( | |||
|
|
412 | ChanelCount => 6, | |||
|
|
413 | SampleSize => 16, | |||
|
|
414 | DivideParam => 256) | |||
|
|
415 | PORT MAP ( | |||
|
|
416 | clk => clk, | |||
|
|
417 | rstn => rstn, | |||
|
|
418 | sample_in_val => sample_f1_val , | |||
|
|
419 | sample_in => sample_f1_s, | |||
|
|
420 | sample_out_val => sample_f3_val, | |||
|
|
421 | sample_out => sample_f3); | |||
|
|
422 | ||||
|
|
423 | sample_f3_wen <= (NOT sample_f3_val) & | |||
|
|
424 | (NOT sample_f3_val) & | |||
|
|
425 | (NOT sample_f3_val) & | |||
|
|
426 | (NOT sample_f3_val) & | |||
|
|
427 | (NOT sample_f3_val) & | |||
|
|
428 | (NOT sample_f3_val); | |||
|
|
429 | ||||
|
|
430 | all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE | |||
|
|
431 | sample_f3_wdata_s(I) <= sample_f3(0, I); | |||
|
|
432 | sample_f3_wdata_s(16*1+I) <= sample_f3(1, I); | |||
|
|
433 | sample_f3_wdata_s(16*2+I) <= sample_f3(2, I); | |||
|
|
434 | sample_f3_wdata_s(16*3+I) <= sample_f3(3, I); | |||
|
|
435 | sample_f3_wdata_s(16*4+I) <= sample_f3(4, I); | |||
|
|
436 | sample_f3_wdata_s(16*5+I) <= sample_f3(5, I); | |||
|
|
437 | END GENERATE all_bit_sample_f3; | |||
|
|
438 | ||||
|
|
439 | lpp_waveform_1 : lpp_waveform | |||
|
|
440 | GENERIC MAP ( | |||
|
|
441 | hindex => hindex, | |||
|
|
442 | tech => tech, | |||
|
|
443 | data_size => 160, | |||
|
|
444 | nb_burst_available_size => nb_burst_available_size, | |||
|
|
445 | nb_snapshot_param_size => nb_snapshot_param_size, | |||
|
|
446 | delta_snapshot_size => delta_snapshot_size, | |||
|
|
447 | delta_f2_f0_size => delta_f2_f0_size, | |||
|
|
448 | delta_f2_f1_size => delta_f2_f1_size) | |||
|
|
449 | PORT MAP ( | |||
|
|
450 | clk => clk, | |||
|
|
451 | rstn => rstn, | |||
|
|
452 | ||||
|
|
453 | AHB_Master_In => AHB_Master_In, | |||
|
|
454 | AHB_Master_Out => AHB_Master_Out, | |||
|
|
455 | ||||
|
|
456 | coarse_time_0 => coarse_time_0, -- IN | |||
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457 | delta_snapshot => delta_snapshot, -- IN | |||
|
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458 | delta_f2_f1 => delta_f2_f1, -- IN | |||
|
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459 | delta_f2_f0 => delta_f2_f0, -- IN | |||
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460 | enable_f0 => enable_f0, -- IN | |||
|
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461 | enable_f1 => enable_f1, -- IN | |||
|
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462 | enable_f2 => enable_f2, -- IN | |||
|
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463 | enable_f3 => enable_f3, -- IN | |||
|
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464 | burst_f0 => burst_f0, -- IN | |||
|
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465 | burst_f1 => burst_f1, -- IN | |||
|
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466 | burst_f2 => burst_f2, -- IN | |||
|
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467 | nb_burst_available => nb_burst_available, | |||
|
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468 | nb_snapshot_param => nb_snapshot_param, | |||
|
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469 | status_full => status_full, | |||
|
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470 | status_full_ack => status_full_ack, -- IN | |||
|
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471 | status_full_err => status_full_err, | |||
|
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472 | status_new_err => status_new_err, | |||
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473 | ||||
|
|
474 | addr_data_f0 => addr_data_f0, -- IN | |||
|
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475 | addr_data_f1 => addr_data_f1, -- IN | |||
|
|
476 | addr_data_f2 => addr_data_f2, -- IN | |||
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477 | addr_data_f3 => addr_data_f3, -- IN | |||
|
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478 | ||||
|
|
479 | data_f0_in => data_f0_in_valid, | |||
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480 | data_f1_in => data_f1_in_valid, | |||
|
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481 | data_f2_in => data_f2_in_valid, | |||
|
|
482 | data_f3_in => data_f3_in_valid, | |||
|
|
483 | data_f0_in_valid => sample_f0_val, | |||
|
|
484 | data_f1_in_valid => sample_f1_val, | |||
|
|
485 | data_f2_in_valid => sample_f2_val, | |||
|
|
486 | data_f3_in_valid => sample_f3_val); | |||
|
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487 | ||||
|
|
488 | data_f0_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f0_wdata_s; | |||
|
|
489 | data_f1_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f1_wdata_s; | |||
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490 | data_f2_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f2_wdata_s; | |||
|
|
491 | data_f3_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f3_wdata_s; | |||
|
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492 | ||||
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|
493 | sample_f0_wdata <= sample_f0_wdata_s; | |||
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494 | sample_f1_wdata <= sample_f1_wdata_s; | |||
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495 | sample_f2_wdata <= sample_f2_wdata_s; | |||
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496 | sample_f3_wdata <= sample_f3_wdata_s; | |||
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497 | ||||
|
|
498 | END tb; | |||
| @@ -0,0 +1,277 | |||||
|
|
1 | LIBRARY IEEE; | |||
|
|
2 | USE IEEE.STD_LOGIC_1164.ALL; | |||
|
|
3 | USE ieee.numeric_std.ALL; | |||
|
|
4 | ||||
|
|
5 | LIBRARY grlib; | |||
|
|
6 | USE grlib.amba.ALL; | |||
|
|
7 | USE grlib.stdlib.ALL; | |||
|
|
8 | USE grlib.devices.ALL; | |||
|
|
9 | USE GRLIB.DMA2AHB_Package.ALL; | |||
|
|
10 | ||||
|
|
11 | LIBRARY lpp; | |||
|
|
12 | USE lpp.lpp_waveform_pkg.ALL; | |||
|
|
13 | ||||
|
|
14 | LIBRARY techmap; | |||
|
|
15 | USE techmap.gencomp.ALL; | |||
|
|
16 | ||||
|
|
17 | ENTITY lpp_waveform IS | |||
|
|
18 | ||||
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19 | GENERIC ( | |||
|
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20 | hindex : INTEGER := 2; | |||
|
|
21 | tech : INTEGER := inferred; | |||
|
|
22 | data_size : INTEGER := 160; | |||
|
|
23 | nb_burst_available_size : INTEGER := 11; | |||
|
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24 | nb_snapshot_param_size : INTEGER := 11; | |||
|
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25 | delta_snapshot_size : INTEGER := 16; | |||
|
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26 | delta_f2_f0_size : INTEGER := 10; | |||
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27 | delta_f2_f1_size : INTEGER := 10); | |||
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28 | ||||
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29 | PORT ( | |||
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30 | clk : IN STD_LOGIC; | |||
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31 | rstn : IN STD_LOGIC; | |||
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32 | ||||
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33 | -- AMBA AHB Master Interface | |||
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34 | AHB_Master_In : IN AHB_Mst_In_Type; | |||
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35 | AHB_Master_Out : OUT AHB_Mst_Out_Type; | |||
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36 | ||||
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37 | coarse_time_0 : IN STD_LOGIC; | |||
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38 | ||||
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39 | --config | |||
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40 | delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); | |||
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41 | delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); | |||
|
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42 | delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); | |||
|
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43 | ||||
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44 | enable_f0 : IN STD_LOGIC; | |||
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45 | enable_f1 : IN STD_LOGIC; | |||
|
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46 | enable_f2 : IN STD_LOGIC; | |||
|
|
47 | enable_f3 : IN STD_LOGIC; | |||
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48 | ||||
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49 | burst_f0 : IN STD_LOGIC; | |||
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50 | burst_f1 : IN STD_LOGIC; | |||
|
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51 | burst_f2 : IN STD_LOGIC; | |||
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52 | ||||
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53 | nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); | |||
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|
54 | nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |||
|
|
55 | status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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56 | status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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57 | status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
58 | status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma | |||
|
|
59 | addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
60 | addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
61 | addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
62 | addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
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63 | ||||
|
|
64 | data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
|
|
65 | data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
|
|
66 | data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
|
|
67 | data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
|
|
68 | ||||
|
|
69 | data_f0_in_valid : IN STD_LOGIC; | |||
|
|
70 | data_f1_in_valid : IN STD_LOGIC; | |||
|
|
71 | data_f2_in_valid : IN STD_LOGIC; | |||
|
|
72 | data_f3_in_valid : IN STD_LOGIC | |||
|
|
73 | ); | |||
|
|
74 | ||||
|
|
75 | END lpp_waveform; | |||
|
|
76 | ||||
|
|
77 | ARCHITECTURE beh OF lpp_waveform IS | |||
|
|
78 | SIGNAL start_snapshot_f0 : STD_LOGIC; | |||
|
|
79 | SIGNAL start_snapshot_f1 : STD_LOGIC; | |||
|
|
80 | SIGNAL start_snapshot_f2 : STD_LOGIC; | |||
|
|
81 | ||||
|
|
82 | SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
|
|
83 | SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
|
|
84 | SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
|
|
85 | SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
|
|
86 | ||||
|
|
87 | SIGNAL data_f0_out_valid : STD_LOGIC; | |||
|
|
88 | SIGNAL data_f1_out_valid : STD_LOGIC; | |||
|
|
89 | SIGNAL data_f2_out_valid : STD_LOGIC; | |||
|
|
90 | SIGNAL data_f3_out_valid : STD_LOGIC; | |||
|
|
91 | SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0); | |||
|
|
92 | ||||
|
|
93 | -- | |||
|
|
94 | SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
95 | SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
96 | SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
97 | SIGNAL ready : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
98 | SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
99 | SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
100 | SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
101 | SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
102 | -- | |||
|
|
103 | SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
104 | SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
105 | SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
106 | ||||
|
|
107 | BEGIN -- beh | |||
|
|
108 | ||||
|
|
109 | lpp_waveform_snapshot_controler_1: lpp_waveform_snapshot_controler | |||
|
|
110 | GENERIC MAP ( | |||
|
|
111 | delta_snapshot_size => delta_snapshot_size, | |||
|
|
112 | delta_f2_f0_size => delta_f2_f0_size, | |||
|
|
113 | delta_f2_f1_size => delta_f2_f1_size) | |||
|
|
114 | PORT MAP ( | |||
|
|
115 | clk => clk, | |||
|
|
116 | rstn => rstn, | |||
|
|
117 | delta_snapshot => delta_snapshot, | |||
|
|
118 | delta_f2_f1 => delta_f2_f1, | |||
|
|
119 | delta_f2_f0 => delta_f2_f0, | |||
|
|
120 | coarse_time_0 => coarse_time_0, | |||
|
|
121 | data_f0_in_valid => data_f0_in_valid, | |||
|
|
122 | data_f2_in_valid => data_f2_in_valid, | |||
|
|
123 | start_snapshot_f0 => start_snapshot_f0, | |||
|
|
124 | start_snapshot_f1 => start_snapshot_f1, | |||
|
|
125 | start_snapshot_f2 => start_snapshot_f2); | |||
|
|
126 | ||||
|
|
127 | lpp_waveform_snapshot_f0 : lpp_waveform_snapshot | |||
|
|
128 | GENERIC MAP ( | |||
|
|
129 | data_size => data_size, | |||
|
|
130 | nb_snapshot_param_size => nb_snapshot_param_size) | |||
|
|
131 | PORT MAP ( | |||
|
|
132 | clk => clk, | |||
|
|
133 | rstn => rstn, | |||
|
|
134 | enable => enable_f0, | |||
|
|
135 | burst_enable => burst_f0, | |||
|
|
136 | nb_snapshot_param => nb_snapshot_param, | |||
|
|
137 | start_snapshot => start_snapshot_f0, | |||
|
|
138 | data_in => data_f0_in, | |||
|
|
139 | data_in_valid => data_f0_in_valid, | |||
|
|
140 | data_out => data_f0_out, | |||
|
|
141 | data_out_valid => data_f0_out_valid); | |||
|
|
142 | ||||
|
|
143 | nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) + 1; | |||
|
|
144 | ||||
|
|
145 | lpp_waveform_snapshot_f1 : lpp_waveform_snapshot | |||
|
|
146 | GENERIC MAP ( | |||
|
|
147 | data_size => data_size, | |||
|
|
148 | nb_snapshot_param_size => nb_snapshot_param_size+1) | |||
|
|
149 | PORT MAP ( | |||
|
|
150 | clk => clk, | |||
|
|
151 | rstn => rstn, | |||
|
|
152 | enable => enable_f1, | |||
|
|
153 | burst_enable => burst_f1, | |||
|
|
154 | nb_snapshot_param => nb_snapshot_param_more_one, | |||
|
|
155 | start_snapshot => start_snapshot_f1, | |||
|
|
156 | data_in => data_f1_in, | |||
|
|
157 | data_in_valid => data_f1_in_valid, | |||
|
|
158 | data_out => data_f1_out, | |||
|
|
159 | data_out_valid => data_f1_out_valid); | |||
|
|
160 | ||||
|
|
161 | lpp_waveform_snapshot_f2 : lpp_waveform_snapshot | |||
|
|
162 | GENERIC MAP ( | |||
|
|
163 | data_size => data_size, | |||
|
|
164 | nb_snapshot_param_size => nb_snapshot_param_size+1) | |||
|
|
165 | PORT MAP ( | |||
|
|
166 | clk => clk, | |||
|
|
167 | rstn => rstn, | |||
|
|
168 | enable => enable_f2, | |||
|
|
169 | burst_enable => burst_f2, | |||
|
|
170 | nb_snapshot_param => nb_snapshot_param_more_one, | |||
|
|
171 | start_snapshot => start_snapshot_f2, | |||
|
|
172 | data_in => data_f2_in, | |||
|
|
173 | data_in_valid => data_f2_in_valid, | |||
|
|
174 | data_out => data_f2_out, | |||
|
|
175 | data_out_valid => data_f2_out_valid); | |||
|
|
176 | ||||
|
|
177 | lpp_waveform_burst_f3: lpp_waveform_burst | |||
|
|
178 | GENERIC MAP ( | |||
|
|
179 | data_size => data_size) | |||
|
|
180 | PORT MAP ( | |||
|
|
181 | clk => clk, | |||
|
|
182 | rstn => rstn, | |||
|
|
183 | enable => enable_f3, | |||
|
|
184 | data_in => data_f3_in, | |||
|
|
185 | data_in_valid => data_f3_in_valid, | |||
|
|
186 | data_out => data_f3_out, | |||
|
|
187 | data_out_valid => data_f3_out_valid); | |||
|
|
188 | ||||
|
|
189 | ||||
|
|
190 | valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid; | |||
|
|
191 | ||||
|
|
192 | all_input_valid: FOR i IN 3 DOWNTO 0 GENERATE | |||
|
|
193 | lpp_waveform_dma_gen_valid_I: lpp_waveform_dma_gen_valid | |||
|
|
194 | PORT MAP ( | |||
|
|
195 | HCLK => clk, | |||
|
|
196 | HRESETn => rstn, | |||
|
|
197 | valid_in => valid_in(I), | |||
|
|
198 | ack_in => valid_ack(I), | |||
|
|
199 | valid_out => valid_out(I), | |||
|
|
200 | error => status_new_err(I)); | |||
|
|
201 | END GENERATE all_input_valid; | |||
|
|
202 | ||||
|
|
203 | lpp_waveform_fifo_arbiter_1: lpp_waveform_fifo_arbiter | |||
|
|
204 | GENERIC MAP (tech => tech) | |||
|
|
205 | PORT MAP ( | |||
|
|
206 | clk => clk, | |||
|
|
207 | rstn => rstn, | |||
|
|
208 | data_f0_valid => valid_out(0), | |||
|
|
209 | data_f1_valid => valid_out(1), | |||
|
|
210 | data_f2_valid => valid_out(2), | |||
|
|
211 | data_f3_valid => valid_out(3), | |||
|
|
212 | ||||
|
|
213 | data_valid_ack => valid_ack, | |||
|
|
214 | ||||
|
|
215 | data_f0 => data_f0_out, | |||
|
|
216 | data_f1 => data_f1_out, | |||
|
|
217 | data_f2 => data_f2_out, | |||
|
|
218 | data_f3 => data_f3_out, | |||
|
|
219 | ||||
|
|
220 | ready => ready_arb, | |||
|
|
221 | time_wen => time_wen, | |||
|
|
222 | data_wen => data_wen, | |||
|
|
223 | data => wdata); | |||
|
|
224 | ||||
|
|
225 | ready_arb <= NOT ready; | |||
|
|
226 | ||||
|
|
227 | lpp_waveform_fifo_1: lpp_waveform_fifo | |||
|
|
228 | GENERIC MAP (tech => tech) | |||
|
|
229 | PORT MAP ( | |||
|
|
230 | clk => clk, | |||
|
|
231 | rstn => rstn, | |||
|
|
232 | ready => ready, | |||
|
|
233 | time_ren => time_ren, -- todo | |||
|
|
234 | data_ren => data_ren, -- todo | |||
|
|
235 | rdata => rdata, -- todo | |||
|
|
236 | ||||
|
|
237 | time_wen => time_wen, | |||
|
|
238 | data_wen => data_wen, | |||
|
|
239 | wdata => wdata); | |||
|
|
240 | ||||
|
|
241 | --time_ren <= (OTHERS => '1'); | |||
|
|
242 | --data_ren <= (OTHERS => '1'); | |||
|
|
243 | ||||
|
|
244 | pp_waveform_dma_1: lpp_waveform_dma | |||
|
|
245 | GENERIC MAP ( | |||
|
|
246 | data_size => data_size, | |||
|
|
247 | tech => tech, | |||
|
|
248 | hindex => hindex, | |||
|
|
249 | nb_burst_available_size => nb_burst_available_size) | |||
|
|
250 | PORT MAP ( | |||
|
|
251 | HCLK => clk, | |||
|
|
252 | HRESETn => rstn, | |||
|
|
253 | AHB_Master_In => AHB_Master_In, | |||
|
|
254 | AHB_Master_Out => AHB_Master_Out, | |||
|
|
255 | data_ready => ready, | |||
|
|
256 | data => rdata, | |||
|
|
257 | data_data_ren => data_ren, | |||
|
|
258 | data_time_ren => time_ren, | |||
|
|
259 | --data_f0_in => data_f0_out, | |||
|
|
260 | --data_f1_in => data_f1_out, | |||
|
|
261 | --data_f2_in => data_f2_out, | |||
|
|
262 | --data_f3_in => data_f3_out, | |||
|
|
263 | --data_f0_in_valid => data_f0_out_valid, | |||
|
|
264 | --data_f1_in_valid => data_f1_out_valid, | |||
|
|
265 | --data_f2_in_valid => data_f2_out_valid, | |||
|
|
266 | --data_f3_in_valid => data_f3_out_valid, | |||
|
|
267 | nb_burst_available => nb_burst_available, | |||
|
|
268 | status_full => status_full, | |||
|
|
269 | status_full_ack => status_full_ack, | |||
|
|
270 | status_full_err => status_full_err, | |||
|
|
271 | -- status_new_err => status_new_err, | |||
|
|
272 | addr_data_f0 => addr_data_f0, | |||
|
|
273 | addr_data_f1 => addr_data_f1, | |||
|
|
274 | addr_data_f2 => addr_data_f2, | |||
|
|
275 | addr_data_f3 => addr_data_f3); | |||
|
|
276 | ||||
|
|
277 | END beh; | |||
| @@ -0,0 +1,42 | |||||
|
|
1 | LIBRARY IEEE; | |||
|
|
2 | USE IEEE.STD_LOGIC_1164.ALL; | |||
|
|
3 | ||||
|
|
4 | ENTITY lpp_waveform_burst IS | |||
|
|
5 | ||||
|
|
6 | GENERIC ( | |||
|
|
7 | data_size : INTEGER := 16); | |||
|
|
8 | ||||
|
|
9 | PORT ( | |||
|
|
10 | clk : IN STD_LOGIC; | |||
|
|
11 | rstn : IN STD_LOGIC; | |||
|
|
12 | ||||
|
|
13 | enable : IN STD_LOGIC; | |||
|
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14 | ||||
|
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15 | data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
|
|
16 | data_in_valid : IN STD_LOGIC; | |||
|
|
17 | ||||
|
|
18 | data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
|
|
19 | data_out_valid : OUT STD_LOGIC | |||
|
|
20 | ); | |||
|
|
21 | ||||
|
|
22 | END lpp_waveform_burst; | |||
|
|
23 | ||||
|
|
24 | ARCHITECTURE beh OF lpp_waveform_burst IS | |||
|
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25 | BEGIN -- beh | |||
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|
26 | ||||
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27 | PROCESS (clk, rstn) | |||
|
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28 | BEGIN | |||
|
|
29 | IF rstn = '0' THEN | |||
|
|
30 | data_out <= (OTHERS => '0'); | |||
|
|
31 | data_out_valid <= '0'; | |||
|
|
32 | ELSIF clk'EVENT AND clk = '1' THEN | |||
|
|
33 | data_out <= data_in; | |||
|
|
34 | IF enable = '0' THEN | |||
|
|
35 | data_out_valid <= '0'; | |||
|
|
36 | ELSE | |||
|
|
37 | data_out_valid <= data_in_valid; | |||
|
|
38 | END IF; | |||
|
|
39 | END IF; | |||
|
|
40 | END PROCESS; | |||
|
|
41 | ||||
|
|
42 | END beh; | |||
| @@ -0,0 +1,363 | |||||
|
|
1 | ||||
|
|
2 | ------------------------------------------------------------------------------ | |||
|
|
3 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
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4 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
|
5 | -- | |||
|
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6 | -- This program is free software; you can redistribute it and/or modify | |||
|
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7 | -- it under the terms of the GNU General Public License as published by | |||
|
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8 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
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9 | -- (at your option) any later version. | |||
|
|
10 | -- | |||
|
|
11 | -- This program is distributed in the hope that it will be useful, | |||
|
|
12 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
|
13 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
|
14 | -- GNU General Public License for more details. | |||
|
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15 | -- | |||
|
|
16 | -- You should have received a copy of the GNU General Public License | |||
|
|
17 | -- along with this program; if not, write to the Free Software | |||
|
|
18 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
|
19 | ------------------------------------------------------------------------------- | |||
|
|
20 | -- Author : Jean-christophe Pellion | |||
|
|
21 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |||
|
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22 | -- jean-christophe.pellion@easii-ic.com | |||
|
|
23 | ------------------------------------------------------------------------------- | |||
|
|
24 | -- 1.0 - initial version | |||
|
|
25 | -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS) | |||
|
|
26 | ------------------------------------------------------------------------------- | |||
|
|
27 | LIBRARY ieee; | |||
|
|
28 | USE ieee.std_logic_1164.ALL; | |||
|
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29 | USE ieee.numeric_std.ALL; | |||
|
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30 | LIBRARY grlib; | |||
|
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31 | USE grlib.amba.ALL; | |||
|
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32 | USE grlib.stdlib.ALL; | |||
|
|
33 | USE grlib.devices.ALL; | |||
|
|
34 | USE GRLIB.DMA2AHB_Package.ALL; | |||
|
|
35 | LIBRARY lpp; | |||
|
|
36 | USE lpp.lpp_amba.ALL; | |||
|
|
37 | USE lpp.apb_devices_list.ALL; | |||
|
|
38 | USE lpp.lpp_memory.ALL; | |||
|
|
39 | USE lpp.lpp_dma_pkg.ALL; | |||
|
|
40 | USE lpp.lpp_waveform_pkg.ALL; | |||
|
|
41 | LIBRARY techmap; | |||
|
|
42 | USE techmap.gencomp.ALL; | |||
|
|
43 | ||||
|
|
44 | ||||
|
|
45 | ENTITY lpp_waveform_dma IS | |||
|
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46 | GENERIC ( | |||
|
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47 | data_size : INTEGER := 160; | |||
|
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48 | tech : INTEGER := inferred; | |||
|
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49 | hindex : INTEGER := 2; | |||
|
|
50 | nb_burst_available_size : INTEGER := 11 | |||
|
|
51 | ); | |||
|
|
52 | PORT ( | |||
|
|
53 | -- AMBA AHB system signals | |||
|
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54 | HCLK : IN STD_ULOGIC; | |||
|
|
55 | HRESETn : IN STD_ULOGIC; | |||
|
|
56 | -- AMBA AHB Master Interface | |||
|
|
57 | AHB_Master_In : IN AHB_Mst_In_Type; | |||
|
|
58 | AHB_Master_Out : OUT AHB_Mst_Out_Type; | |||
|
|
59 | -- | |||
|
|
60 | data_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo | |||
|
|
61 | data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo | |||
|
|
62 | data_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo | |||
|
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63 | data_time_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo | |||
|
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64 | -- Reg | |||
|
|
65 | nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); | |||
|
|
66 | status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
67 | status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
68 | status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
69 | -- status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma | |||
|
|
70 | addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
71 | addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
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72 | addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
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73 | addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) | |||
|
|
74 | ); | |||
|
|
75 | END; | |||
|
|
76 | ||||
|
|
77 | ARCHITECTURE Behavioral OF lpp_waveform_dma IS | |||
|
|
78 | ----------------------------------------------------------------------------- | |||
|
|
79 | SIGNAL DMAIn : DMA_In_Type; | |||
|
|
80 | SIGNAL DMAOut : DMA_OUt_Type; | |||
|
|
81 | ----------------------------------------------------------------------------- | |||
|
|
82 | TYPE state_DMAWriteBurst IS (IDLE, | |||
|
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83 | SEND_TIME_0, WAIT_TIME_0, | |||
|
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84 | SEND_TIME_1, WAIT_TIME_1, | |||
|
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85 | SEND_5_TIME, | |||
|
|
86 | SEND_DATA, WAIT_DATA); | |||
|
|
87 | SIGNAL state : state_DMAWriteBurst := IDLE; | |||
|
|
88 | ----------------------------------------------------------------------------- | |||
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89 | -- CONTROL | |||
|
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90 | SIGNAL sel_data_s : STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
|
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91 | SIGNAL sel_data : STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
|
|
92 | SIGNAL update : STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
|
|
93 | SIGNAL time_select : STD_LOGIC; | |||
|
|
94 | SIGNAL time_write : STD_LOGIC; | |||
|
|
95 | SIGNAL time_already_send : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
96 | SIGNAL time_already_send_s : STD_LOGIC; | |||
|
|
97 | ----------------------------------------------------------------------------- | |||
|
|
98 | -- SEND TIME MODULE | |||
|
|
99 | SIGNAL time_dmai : DMA_In_Type; | |||
|
|
100 | SIGNAL time_send : STD_LOGIC; | |||
|
|
101 | SIGNAL time_send_ok : STD_LOGIC; | |||
|
|
102 | SIGNAL time_send_ko : STD_LOGIC; | |||
|
|
103 | SIGNAL time_fifo_ren : STD_LOGIC; | |||
|
|
104 | SIGNAL time_ren : STD_LOGIC; | |||
|
|
105 | ----------------------------------------------------------------------------- | |||
|
|
106 | -- SEND DATA MODULE | |||
|
|
107 | SIGNAL data_dmai : DMA_In_Type; | |||
|
|
108 | SIGNAL data_send : STD_LOGIC; | |||
|
|
109 | SIGNAL data_send_ok : STD_LOGIC; | |||
|
|
110 | SIGNAL data_send_ko : STD_LOGIC; | |||
|
|
111 | SIGNAL data_fifo_ren : STD_LOGIC; | |||
|
|
112 | SIGNAL data_ren : STD_LOGIC; | |||
|
|
113 | ----------------------------------------------------------------------------- | |||
|
|
114 | -- SELECT ADDRESS | |||
|
|
115 | SIGNAL data_address : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
116 | SIGNAL update_and_sel : STD_LOGIC_VECTOR(7 DOWNTO 0); | |||
|
|
117 | SIGNAL addr_data_reg_vector : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); | |||
|
|
118 | SIGNAL addr_data_vector : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); | |||
|
|
119 | ----------------------------------------------------------------------------- | |||
|
|
120 | SIGNAL send_16_3_time : STD_LOGIC_VECTOR(2 DOWNTO 0); | |||
|
|
121 | SIGNAL count_send_time : INTEGER; | |||
|
|
122 | BEGIN | |||
|
|
123 | ||||
|
|
124 | ----------------------------------------------------------------------------- | |||
|
|
125 | -- DMA to AHB interface | |||
|
|
126 | DMA2AHB_1 : DMA2AHB | |||
|
|
127 | GENERIC MAP ( | |||
|
|
128 | hindex => hindex, | |||
|
|
129 | vendorid => VENDOR_LPP, | |||
|
|
130 | deviceid => 0, | |||
|
|
131 | version => 0, | |||
|
|
132 | syncrst => 1, | |||
|
|
133 | boundary => 1) -- FIX 11/01/2013 | |||
|
|
134 | PORT MAP ( | |||
|
|
135 | HCLK => HCLK, | |||
|
|
136 | HRESETn => HRESETn, | |||
|
|
137 | DMAIn => DMAIn, | |||
|
|
138 | DMAOut => DMAOut, | |||
|
|
139 | AHBIn => AHB_Master_In, | |||
|
|
140 | AHBOut => AHB_Master_Out); | |||
|
|
141 | ----------------------------------------------------------------------------- | |||
|
|
142 | ||||
|
|
143 | ----------------------------------------------------------------------------- | |||
|
|
144 | -- This module memorises when the Times info are write. When FSM send | |||
|
|
145 | -- the Times info, the "reg" is set and when a full_ack is received the "reg" is reset. | |||
|
|
146 | all_time_write: FOR I IN 3 DOWNTO 0 GENERATE | |||
|
|
147 | PROCESS (HCLK, HRESETn) | |||
|
|
148 | BEGIN -- PROCESS | |||
|
|
149 | IF HRESETn = '0' THEN -- asynchronous reset (active low) | |||
|
|
150 | time_already_send(I) <= '0'; | |||
|
|
151 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge | |||
|
|
152 | IF time_write = '1' AND UNSIGNED(sel_data) = I THEN | |||
|
|
153 | time_already_send(I) <= '1'; | |||
|
|
154 | ELSIF status_full_ack(I) = '1' THEN | |||
|
|
155 | time_already_send(I) <= '0'; | |||
|
|
156 | END IF; | |||
|
|
157 | END IF; | |||
|
|
158 | END PROCESS; | |||
|
|
159 | END GENERATE all_time_write; | |||
|
|
160 | ||||
|
|
161 | ----------------------------------------------------------------------------- | |||
|
|
162 | sel_data_s <= "00" WHEN data_ready(0) = '1' ELSE | |||
|
|
163 | "01" WHEN data_ready(1) = '1' ELSE | |||
|
|
164 | "10" WHEN data_ready(2) = '1' ELSE | |||
|
|
165 | "11"; | |||
|
|
166 | ||||
|
|
167 | time_already_send_s <= time_already_send(0) WHEN data_ready(0) = '1' ELSE | |||
|
|
168 | time_already_send(1) WHEN data_ready(1) = '1' ELSE | |||
|
|
169 | time_already_send(2) WHEN data_ready(2) = '1' ELSE | |||
|
|
170 | time_already_send(3); | |||
|
|
171 | ||||
|
|
172 | -- DMA control | |||
|
|
173 | DMAWriteFSM_p : PROCESS (HCLK, HRESETn) | |||
|
|
174 | BEGIN -- PROCESS DMAWriteBurst_p | |||
|
|
175 | IF HRESETn = '0' THEN | |||
|
|
176 | state <= IDLE; | |||
|
|
177 | ||||
|
|
178 | sel_data <= "00"; | |||
|
|
179 | update <= "00"; | |||
|
|
180 | time_select <= '0'; | |||
|
|
181 | time_fifo_ren <= '1'; | |||
|
|
182 | data_send <= '0'; | |||
|
|
183 | time_send <= '0'; | |||
|
|
184 | time_write <= '0'; | |||
|
|
185 | send_16_3_time <= "001"; | |||
|
|
186 | ||||
|
|
187 | ELSIF HCLK'EVENT AND HCLK = '1' THEN | |||
|
|
188 | ||||
|
|
189 | CASE state IS | |||
|
|
190 | WHEN IDLE => | |||
|
|
191 | count_send_time <= 0; | |||
|
|
192 | sel_data <= "00"; | |||
|
|
193 | update <= "00"; | |||
|
|
194 | time_select <= '0'; | |||
|
|
195 | time_fifo_ren <= '1'; | |||
|
|
196 | data_send <= '0'; | |||
|
|
197 | time_send <= '0'; | |||
|
|
198 | time_write <= '0'; | |||
|
|
199 | ||||
|
|
200 | IF data_ready = "0000" THEN | |||
|
|
201 | state <= IDLE; | |||
|
|
202 | ELSE | |||
|
|
203 | sel_data <= sel_data_s; | |||
|
|
204 | send_16_3_time <= send_16_3_time(1 DOWNTO 0) & send_16_3_time(2); | |||
|
|
205 | IF send_16_3_time(0) = '1' THEN | |||
|
|
206 | state <= SEND_TIME_0; | |||
|
|
207 | ELSE | |||
|
|
208 | state <= SEND_5_TIME; | |||
|
|
209 | END IF; | |||
|
|
210 | END IF; | |||
|
|
211 | ||||
|
|
212 | WHEN SEND_TIME_0 => | |||
|
|
213 | time_select <= '1'; | |||
|
|
214 | IF time_already_send_s = '0' THEN | |||
|
|
215 | time_send <= '1'; | |||
|
|
216 | state <= WAIT_TIME_0; | |||
|
|
217 | ELSE | |||
|
|
218 | time_send <= '0'; | |||
|
|
219 | state <= SEND_TIME_1; | |||
|
|
220 | END IF; | |||
|
|
221 | time_fifo_ren <= '0'; | |||
|
|
222 | ||||
|
|
223 | WHEN WAIT_TIME_0 => | |||
|
|
224 | time_fifo_ren <= '1'; | |||
|
|
225 | update <= "00"; | |||
|
|
226 | time_send <= '0'; | |||
|
|
227 | IF time_send_ok = '1' OR time_send_ko = '1' THEN | |||
|
|
228 | update <= "01"; | |||
|
|
229 | state <= SEND_TIME_1; | |||
|
|
230 | END IF; | |||
|
|
231 | ||||
|
|
232 | WHEN SEND_TIME_1 => | |||
|
|
233 | time_select <= '1'; | |||
|
|
234 | IF time_already_send_s = '0' THEN | |||
|
|
235 | time_send <= '1'; | |||
|
|
236 | state <= WAIT_TIME_1; | |||
|
|
237 | ELSE | |||
|
|
238 | time_send <= '0'; | |||
|
|
239 | state <= SEND_5_TIME; | |||
|
|
240 | END IF; | |||
|
|
241 | time_fifo_ren <= '0'; | |||
|
|
242 | ||||
|
|
243 | WHEN WAIT_TIME_1 => | |||
|
|
244 | time_fifo_ren <= '1'; | |||
|
|
245 | update <= "00"; | |||
|
|
246 | time_send <= '0'; | |||
|
|
247 | IF time_send_ok = '1' OR time_send_ko = '1' THEN | |||
|
|
248 | time_write <= '1'; | |||
|
|
249 | update <= "01"; | |||
|
|
250 | state <= SEND_5_TIME; | |||
|
|
251 | END IF; | |||
|
|
252 | ||||
|
|
253 | WHEN SEND_5_TIME => | |||
|
|
254 | update <= "00"; | |||
|
|
255 | time_select <= '1'; | |||
|
|
256 | time_fifo_ren <= '0'; | |||
|
|
257 | count_send_time <= count_send_time + 1; | |||
|
|
258 | IF count_send_time = 10 THEN | |||
|
|
259 | state <= SEND_DATA; | |||
|
|
260 | END IF; | |||
|
|
261 | ||||
|
|
262 | WHEN SEND_DATA => | |||
|
|
263 | time_fifo_ren <= '1'; | |||
|
|
264 | time_write <= '0'; | |||
|
|
265 | time_send <= '0'; | |||
|
|
266 | ||||
|
|
267 | time_select <= '0'; | |||
|
|
268 | data_send <= '1'; | |||
|
|
269 | update <= "00"; | |||
|
|
270 | state <= WAIT_DATA; | |||
|
|
271 | ||||
|
|
272 | WHEN WAIT_DATA => | |||
|
|
273 | data_send <= '0'; | |||
|
|
274 | ||||
|
|
275 | IF data_send_ok = '1' OR data_send_ko = '1' THEN | |||
|
|
276 | state <= IDLE; | |||
|
|
277 | update <= "10"; | |||
|
|
278 | END IF; | |||
|
|
279 | ||||
|
|
280 | WHEN OTHERS => NULL; | |||
|
|
281 | END CASE; | |||
|
|
282 | ||||
|
|
283 | END IF; | |||
|
|
284 | END PROCESS DMAWriteFSM_p; | |||
|
|
285 | ----------------------------------------------------------------------------- | |||
|
|
286 | ||||
|
|
287 | ||||
|
|
288 | ||||
|
|
289 | ----------------------------------------------------------------------------- | |||
|
|
290 | -- SEND 1 word by DMA | |||
|
|
291 | ----------------------------------------------------------------------------- | |||
|
|
292 | lpp_dma_send_1word_1 : lpp_dma_send_1word | |||
|
|
293 | PORT MAP ( | |||
|
|
294 | HCLK => HCLK, | |||
|
|
295 | HRESETn => HRESETn, | |||
|
|
296 | DMAIn => time_dmai, | |||
|
|
297 | DMAOut => DMAOut, | |||
|
|
298 | ||||
|
|
299 | send => time_send, | |||
|
|
300 | address => data_address, | |||
|
|
301 | data => data, | |||
|
|
302 | send_ok => time_send_ok, | |||
|
|
303 | send_ko => time_send_ko | |||
|
|
304 | ); | |||
|
|
305 | ||||
|
|
306 | ----------------------------------------------------------------------------- | |||
|
|
307 | -- SEND 16 word by DMA (in burst mode) | |||
|
|
308 | ----------------------------------------------------------------------------- | |||
|
|
309 | lpp_dma_send_16word_1 : lpp_dma_send_16word | |||
|
|
310 | PORT MAP ( | |||
|
|
311 | HCLK => HCLK, | |||
|
|
312 | HRESETn => HRESETn, | |||
|
|
313 | DMAIn => data_dmai, | |||
|
|
314 | DMAOut => DMAOut, | |||
|
|
315 | ||||
|
|
316 | send => data_send, | |||
|
|
317 | address => data_address, | |||
|
|
318 | data => data, | |||
|
|
319 | ren => data_fifo_ren, | |||
|
|
320 | send_ok => data_send_ok, | |||
|
|
321 | send_ko => data_send_ko); | |||
|
|
322 | ||||
|
|
323 | DMAIn <= time_dmai WHEN time_select = '1' ELSE data_dmai; | |||
|
|
324 | data_ren <= '1' WHEN time_select = '1' ELSE data_fifo_ren; | |||
|
|
325 | time_ren <= time_fifo_ren WHEN time_select = '1' ELSE '1'; | |||
|
|
326 | ||||
|
|
327 | all_data_ren : FOR I IN 3 DOWNTO 0 GENERATE | |||
|
|
328 | data_data_ren(I) <= data_ren WHEN UNSIGNED(sel_data) = I ELSE '1'; | |||
|
|
329 | data_time_ren(I) <= time_ren WHEN UNSIGNED(sel_data) = I ELSE '1'; | |||
|
|
330 | END GENERATE all_data_ren; | |||
|
|
331 | ||||
|
|
332 | ----------------------------------------------------------------------------- | |||
|
|
333 | -- SELECT ADDRESS | |||
|
|
334 | addr_data_reg_vector <= addr_data_f3 & addr_data_f2 & addr_data_f1 & addr_data_f0; | |||
|
|
335 | ||||
|
|
336 | gen_select_address : FOR I IN 3 DOWNTO 0 GENERATE | |||
|
|
337 | ||||
|
|
338 | update_and_sel((2*I)+1 DOWNTO 2*I) <= update WHEN UNSIGNED(sel_data) = I ELSE "00"; | |||
|
|
339 | ||||
|
|
340 | lpp_waveform_dma_selectaddress_I : lpp_waveform_dma_selectaddress | |||
|
|
341 | GENERIC MAP ( | |||
|
|
342 | nb_burst_available_size => nb_burst_available_size) | |||
|
|
343 | PORT MAP ( | |||
|
|
344 | HCLK => HCLK, | |||
|
|
345 | HRESETn => HRESETn, | |||
|
|
346 | update => update_and_sel((2*I)+1 DOWNTO 2*I), | |||
|
|
347 | nb_burst_available => nb_burst_available, | |||
|
|
348 | addr_data_reg => addr_data_reg_vector(32*I+31 DOWNTO 32*I), | |||
|
|
349 | addr_data => addr_data_vector(32*I+31 DOWNTO 32*I), | |||
|
|
350 | status_full => status_full(I), | |||
|
|
351 | status_full_ack => status_full_ack(I), | |||
|
|
352 | status_full_err => status_full_err(I)); | |||
|
|
353 | ||||
|
|
354 | END GENERATE gen_select_address; | |||
|
|
355 | ||||
|
|
356 | data_address <= addr_data_vector(31 DOWNTO 0) WHEN UNSIGNED(sel_data) = 0 ELSE | |||
|
|
357 | addr_data_vector(32*1+31 DOWNTO 32*1) WHEN UNSIGNED(sel_data) = 1 ELSE | |||
|
|
358 | addr_data_vector(32*2+31 DOWNTO 32*2) WHEN UNSIGNED(sel_data) = 2 ELSE | |||
|
|
359 | addr_data_vector(32*3+31 DOWNTO 32*3); | |||
|
|
360 | ----------------------------------------------------------------------------- | |||
|
|
361 | ||||
|
|
362 | ||||
|
|
363 | END Behavioral; | |||
| @@ -0,0 +1,88 | |||||
|
|
1 | ||||
|
|
2 | ------------------------------------------------------------------------------ | |||
|
|
3 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
|
4 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
|
5 | -- | |||
|
|
6 | -- This program is free software; you can redistribute it and/or modify | |||
|
|
7 | -- it under the terms of the GNU General Public License as published by | |||
|
|
8 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
|
9 | -- (at your option) any later version. | |||
|
|
10 | -- | |||
|
|
11 | -- This program is distributed in the hope that it will be useful, | |||
|
|
12 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
|
13 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
|
14 | -- GNU General Public License for more details. | |||
|
|
15 | -- | |||
|
|
16 | -- You should have received a copy of the GNU General Public License | |||
|
|
17 | -- along with this program; if not, write to the Free Software | |||
|
|
18 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
|
19 | ------------------------------------------------------------------------------- | |||
|
|
20 | -- Author : Jean-christophe Pellion | |||
|
|
21 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |||
|
|
22 | -- jean-christophe.pellion@easii-ic.com | |||
|
|
23 | ------------------------------------------------------------------------------- | |||
|
|
24 | -- 1.0 - initial version | |||
|
|
25 | ------------------------------------------------------------------------------- | |||
|
|
26 | ||||
|
|
27 | LIBRARY ieee; | |||
|
|
28 | USE ieee.std_logic_1164.ALL; | |||
|
|
29 | USE ieee.numeric_std.ALL; | |||
|
|
30 | ||||
|
|
31 | ||||
|
|
32 | ENTITY lpp_waveform_dma_gen_valid IS | |||
|
|
33 | PORT ( | |||
|
|
34 | HCLK : IN STD_LOGIC; | |||
|
|
35 | HRESETn : IN STD_LOGIC; | |||
|
|
36 | ||||
|
|
37 | valid_in : IN STD_LOGIC; | |||
|
|
38 | ack_in : IN STD_LOGIC; | |||
|
|
39 | ||||
|
|
40 | valid_out : OUT STD_LOGIC; | |||
|
|
41 | error : OUT STD_LOGIC | |||
|
|
42 | ); | |||
|
|
43 | END; | |||
|
|
44 | ||||
|
|
45 | ARCHITECTURE Behavioral OF lpp_waveform_dma_gen_valid IS | |||
|
|
46 | TYPE state_fsm IS (IDLE, VALID); | |||
|
|
47 | SIGNAL state : state_fsm; | |||
|
|
48 | BEGIN | |||
|
|
49 | ||||
|
|
50 | FSM_SELECT_ADDRESS : PROCESS (HCLK, HRESETn) | |||
|
|
51 | BEGIN | |||
|
|
52 | IF HRESETn = '0' THEN | |||
|
|
53 | state <= IDLE; | |||
|
|
54 | valid_out <= '0'; | |||
|
|
55 | error <= '0'; | |||
|
|
56 | ELSIF HCLK'EVENT AND HCLK = '1' THEN | |||
|
|
57 | CASE state IS | |||
|
|
58 | WHEN IDLE => | |||
|
|
59 | valid_out <= '0'; | |||
|
|
60 | error <= '0'; | |||
|
|
61 | IF valid_in = '1' THEN | |||
|
|
62 | state <= VALID; | |||
|
|
63 | valid_out <= '1'; | |||
|
|
64 | END IF; | |||
|
|
65 | ||||
|
|
66 | WHEN VALID => | |||
|
|
67 | valid_out <= '1'; | |||
|
|
68 | error <= '0'; | |||
|
|
69 | IF valid_in = '1' THEN | |||
|
|
70 | IF ack_in = '1' THEN | |||
|
|
71 | state <= VALID; | |||
|
|
72 | valid_out <= '1'; | |||
|
|
73 | ELSE | |||
|
|
74 | state <= IDLE; | |||
|
|
75 | error <= '1'; | |||
|
|
76 | valid_out <= '0'; | |||
|
|
77 | END IF; | |||
|
|
78 | ELSIF ack_in = '1' THEN | |||
|
|
79 | state <= IDLE; | |||
|
|
80 | valid_out <= '0'; | |||
|
|
81 | END IF; | |||
|
|
82 | ||||
|
|
83 | WHEN OTHERS => NULL; | |||
|
|
84 | END CASE; | |||
|
|
85 | END IF; | |||
|
|
86 | END PROCESS FSM_SELECT_ADDRESS; | |||
|
|
87 | ||||
|
|
88 | END Behavioral; | |||
| @@ -0,0 +1,132 | |||||
|
|
1 | ||||
|
|
2 | ------------------------------------------------------------------------------ | |||
|
|
3 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
|
4 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
|
5 | -- | |||
|
|
6 | -- This program is free software; you can redistribute it and/or modify | |||
|
|
7 | -- it under the terms of the GNU General Public License as published by | |||
|
|
8 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
|
9 | -- (at your option) any later version. | |||
|
|
10 | -- | |||
|
|
11 | -- This program is distributed in the hope that it will be useful, | |||
|
|
12 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
|
13 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
|
14 | -- GNU General Public License for more details. | |||
|
|
15 | -- | |||
|
|
16 | -- You should have received a copy of the GNU General Public License | |||
|
|
17 | -- along with this program; if not, write to the Free Software | |||
|
|
18 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
|
19 | ------------------------------------------------------------------------------- | |||
|
|
20 | -- Author : Jean-christophe Pellion | |||
|
|
21 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |||
|
|
22 | -- jean-christophe.pellion@easii-ic.com | |||
|
|
23 | ------------------------------------------------------------------------------- | |||
|
|
24 | -- 1.0 - initial version | |||
|
|
25 | ------------------------------------------------------------------------------- | |||
|
|
26 | ||||
|
|
27 | LIBRARY ieee; | |||
|
|
28 | USE ieee.std_logic_1164.ALL; | |||
|
|
29 | USE ieee.numeric_std.ALL; | |||
|
|
30 | ||||
|
|
31 | ||||
|
|
32 | ENTITY lpp_waveform_dma_selectaddress IS | |||
|
|
33 | GENERIC ( | |||
|
|
34 | nb_burst_available_size : INTEGER := 11 | |||
|
|
35 | ); | |||
|
|
36 | PORT ( | |||
|
|
37 | HCLK : IN STD_ULOGIC; | |||
|
|
38 | HRESETn : IN STD_ULOGIC; | |||
|
|
39 | ||||
|
|
40 | update : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
|
|
41 | ||||
|
|
42 | nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); | |||
|
|
43 | addr_data_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
44 | ||||
|
|
45 | addr_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
46 | ||||
|
|
47 | status_full : OUT STD_LOGIC; | |||
|
|
48 | status_full_ack : IN STD_LOGIC; | |||
|
|
49 | status_full_err : OUT STD_LOGIC | |||
|
|
50 | ); | |||
|
|
51 | END; | |||
|
|
52 | ||||
|
|
53 | ARCHITECTURE Behavioral OF lpp_waveform_dma_selectaddress IS | |||
|
|
54 | TYPE state_fsm_select_data IS (IDLE, ADD, FULL, ERR, UPDATED); | |||
|
|
55 | SIGNAL state : state_fsm_select_data; | |||
|
|
56 | ||||
|
|
57 | SIGNAL address : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
58 | SIGNAL nb_send : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); | |||
|
|
59 | SIGNAL nb_send_next : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); | |||
|
|
60 | ||||
|
|
61 | SIGNAL update_s : STD_LOGIC; | |||
|
|
62 | SIGNAL update_r : STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
|
|
63 | BEGIN | |||
|
|
64 | ||||
|
|
65 | update_s <= update(0) OR update(1); | |||
|
|
66 | ||||
|
|
67 | addr_data <= address; | |||
|
|
68 | nb_send_next <= STD_LOGIC_VECTOR(UNSIGNED(nb_send) + 1); | |||
|
|
69 | ||||
|
|
70 | FSM_SELECT_ADDRESS : PROCESS (HCLK, HRESETn) | |||
|
|
71 | BEGIN | |||
|
|
72 | IF HRESETn = '0' THEN | |||
|
|
73 | state <= IDLE; | |||
|
|
74 | address <= (OTHERS => '0'); | |||
|
|
75 | nb_send <= (OTHERS => '0'); | |||
|
|
76 | status_full <= '0'; | |||
|
|
77 | status_full_err <= '0'; | |||
|
|
78 | update_r <= "00"; | |||
|
|
79 | ELSIF HCLK'EVENT AND HCLK = '1' THEN | |||
|
|
80 | update_r <= update; | |||
|
|
81 | CASE state IS | |||
|
|
82 | WHEN IDLE => | |||
|
|
83 | IF update_s = '1' THEN | |||
|
|
84 | state <= ADD; | |||
|
|
85 | END IF; | |||
|
|
86 | ||||
|
|
87 | WHEN ADD => | |||
|
|
88 | IF UNSIGNED(nb_send_next) < UNSIGNED(nb_burst_available) THEN | |||
|
|
89 | state <= IDLE; | |||
|
|
90 | IF update_r = "10" THEN | |||
|
|
91 | address <= STD_LOGIC_VECTOR(UNSIGNED(address) + 64); | |||
|
|
92 | nb_send <= nb_send_next; | |||
|
|
93 | ELSIF update_r = "01" THEN | |||
|
|
94 | address <= STD_LOGIC_VECTOR(UNSIGNED(address) + 4); | |||
|
|
95 | END IF; | |||
|
|
96 | ELSE | |||
|
|
97 | state <= FULL; | |||
|
|
98 | nb_send <= (OTHERS => '0'); | |||
|
|
99 | status_full <= '1'; | |||
|
|
100 | END IF; | |||
|
|
101 | ||||
|
|
102 | WHEN FULL => | |||
|
|
103 | status_full <= '0'; | |||
|
|
104 | IF status_full_ack = '1' THEN | |||
|
|
105 | IF update_s = '1' THEN | |||
|
|
106 | status_full_err <= '1'; | |||
|
|
107 | END IF; | |||
|
|
108 | state <= UPDATED; | |||
|
|
109 | ELSE | |||
|
|
110 | IF update_s = '1' THEN | |||
|
|
111 | status_full_err <= '1'; | |||
|
|
112 | state <= ERR; | |||
|
|
113 | END IF; | |||
|
|
114 | END IF; | |||
|
|
115 | ||||
|
|
116 | WHEN ERR => | |||
|
|
117 | status_full_err <= '0'; | |||
|
|
118 | IF status_full_ack = '1' THEN | |||
|
|
119 | state <= UPDATED; | |||
|
|
120 | END IF; | |||
|
|
121 | ||||
|
|
122 | WHEN UPDATED => | |||
|
|
123 | status_full_err <= '0'; | |||
|
|
124 | state <= IDLE; | |||
|
|
125 | address <= addr_data_reg; | |||
|
|
126 | ||||
|
|
127 | WHEN OTHERS => NULL; | |||
|
|
128 | END CASE; | |||
|
|
129 | END IF; | |||
|
|
130 | END PROCESS FSM_SELECT_ADDRESS; | |||
|
|
131 | ||||
|
|
132 | END Behavioral; | |||
| @@ -0,0 +1,173 | |||||
|
|
1 | ------------------------------------------------------------------------------ | |||
|
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
|
4 | -- | |||
|
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
|
8 | -- (at your option) any later version. | |||
|
|
9 | -- | |||
|
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
|
13 | -- GNU General Public License for more details. | |||
|
|
14 | -- | |||
|
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
|
16 | -- along with this program; if not, write to the Free Software | |||
|
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
|
18 | ------------------------------------------------------------------------------- | |||
|
|
19 | -- Author : Jean-christophe Pellion | |||
|
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |||
|
|
21 | -- jean-christophe.pellion@easii-ic.com | |||
|
|
22 | ---------------------------------------------------------------------------- | |||
|
|
23 | ||||
|
|
24 | LIBRARY ieee; | |||
|
|
25 | USE ieee.std_logic_1164.ALL; | |||
|
|
26 | USE ieee.numeric_std.ALL; | |||
|
|
27 | LIBRARY grlib; | |||
|
|
28 | USE grlib.amba.ALL; | |||
|
|
29 | USE grlib.stdlib.ALL; | |||
|
|
30 | USE grlib.devices.ALL; | |||
|
|
31 | USE GRLIB.DMA2AHB_Package.ALL; | |||
|
|
32 | LIBRARY lpp; | |||
|
|
33 | USE lpp.lpp_amba.ALL; | |||
|
|
34 | USE lpp.apb_devices_list.ALL; | |||
|
|
35 | USE lpp.lpp_memory.ALL; | |||
|
|
36 | LIBRARY techmap; | |||
|
|
37 | USE techmap.gencomp.ALL; | |||
|
|
38 | ||||
|
|
39 | ENTITY lpp_waveform_dma_send_Nword IS | |||
|
|
40 | PORT ( | |||
|
|
41 | -- AMBA AHB system signals | |||
|
|
42 | HCLK : IN STD_ULOGIC; | |||
|
|
43 | HRESETn : IN STD_ULOGIC; | |||
|
|
44 | ||||
|
|
45 | -- DMA | |||
|
|
46 | DMAIn : OUT DMA_In_Type; | |||
|
|
47 | DMAOut : IN DMA_OUt_Type; | |||
|
|
48 | ||||
|
|
49 | -- | |||
|
|
50 | Nb_word_less1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
51 | -- | |||
|
|
52 | send : IN STD_LOGIC; | |||
|
|
53 | address : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
54 | data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
55 | ren : OUT STD_LOGIC; | |||
|
|
56 | -- | |||
|
|
57 | send_ok : OUT STD_LOGIC; | |||
|
|
58 | send_ko : OUT STD_LOGIC | |||
|
|
59 | ); | |||
|
|
60 | END lpp_waveform_dma_send_Nword; | |||
|
|
61 | ||||
|
|
62 | ARCHITECTURE beh OF lpp_waveform_dma_send_Nword IS | |||
|
|
63 | ||||
|
|
64 | TYPE state_fsm_send_Nword IS (IDLE, REQUEST_BUS, SEND_DATA, ERROR0, ERROR1, WAIT_LAST_READY); | |||
|
|
65 | SIGNAL state : state_fsm_send_Nword; | |||
|
|
66 | ||||
|
|
67 | SIGNAL data_counter : INTEGER; | |||
|
|
68 | SIGNAL grant_counter : INTEGER; | |||
|
|
69 | ||||
|
|
70 | BEGIN -- beh | |||
|
|
71 | ||||
|
|
72 | DMAIn.Beat <= HINCR16; | |||
|
|
73 | DMAIn.Size <= HSIZE32; | |||
|
|
74 | ||||
|
|
75 | PROCESS (HCLK, HRESETn) | |||
|
|
76 | BEGIN -- PROCESS | |||
|
|
77 | IF HRESETn = '0' THEN -- asynchronous reset (active low) | |||
|
|
78 | state <= IDLE; | |||
|
|
79 | send_ok <= '0'; | |||
|
|
80 | send_ko <= '0'; | |||
|
|
81 | ||||
|
|
82 | DMAIn.Reset <= '0'; | |||
|
|
83 | DMAIn.Address <= (OTHERS => '0'); | |||
|
|
84 | DMAIn.Request <= '0'; | |||
|
|
85 | DMAIn.Store <= '0'; | |||
|
|
86 | DMAIn.Burst <= '1'; | |||
|
|
87 | DMAIn.Lock <= '0'; | |||
|
|
88 | data_counter <= 0; | |||
|
|
89 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge | |||
|
|
90 | ||||
|
|
91 | CASE state IS | |||
|
|
92 | WHEN IDLE => | |||
|
|
93 | DMAIn.Store <= '1'; | |||
|
|
94 | DMAIn.Request <= '0'; | |||
|
|
95 | send_ok <= '0'; | |||
|
|
96 | send_ko <= '0'; | |||
|
|
97 | DMAIn.Address <= address; | |||
|
|
98 | data_counter <= 0; | |||
|
|
99 | DMAIn.Lock <= '0'; -- FIX test | |||
|
|
100 | IF send = '1' THEN | |||
|
|
101 | state <= REQUEST_BUS; | |||
|
|
102 | DMAIn.Request <= '1'; | |||
|
|
103 | DMAIn.Lock <= '1'; -- FIX test | |||
|
|
104 | DMAIn.Store <= '1'; | |||
|
|
105 | END IF; | |||
|
|
106 | WHEN REQUEST_BUS => | |||
|
|
107 | IF DMAOut.Grant = '1' THEN | |||
|
|
108 | data_counter <= 1; | |||
|
|
109 | grant_counter <= 1; | |||
|
|
110 | state <= SEND_DATA; | |||
|
|
111 | END IF; | |||
|
|
112 | WHEN SEND_DATA => | |||
|
|
113 | ||||
|
|
114 | IF DMAOut.Fault = '1' THEN | |||
|
|
115 | DMAIn.Reset <= '0'; | |||
|
|
116 | DMAIn.Address <= (OTHERS => '0'); | |||
|
|
117 | DMAIn.Request <= '0'; | |||
|
|
118 | DMAIn.Store <= '0'; | |||
|
|
119 | DMAIn.Burst <= '0'; | |||
|
|
120 | state <= ERROR0; | |||
|
|
121 | ELSE | |||
|
|
122 | ||||
|
|
123 | IF DMAOut.Grant = '1' THEN | |||
|
|
124 | IF grant_counter = UNSIGNED(Nb_word_less1) THEN -- | |||
|
|
125 | DMAIn.Reset <= '0'; | |||
|
|
126 | DMAIn.Request <= '0'; | |||
|
|
127 | DMAIn.Store <= '0'; | |||
|
|
128 | DMAIn.Burst <= '0'; | |||
|
|
129 | ELSE | |||
|
|
130 | grant_counter <= grant_counter+1; | |||
|
|
131 | END IF; | |||
|
|
132 | END IF; | |||
|
|
133 | ||||
|
|
134 | IF DMAOut.OKAY = '1' THEN | |||
|
|
135 | IF data_counter = UNSIGNED(Nb_word_less1) THEN | |||
|
|
136 | DMAIn.Address <= (OTHERS => '0'); | |||
|
|
137 | state <= WAIT_LAST_READY; | |||
|
|
138 | ELSE | |||
|
|
139 | data_counter <= data_counter + 1; | |||
|
|
140 | END IF; | |||
|
|
141 | END IF; | |||
|
|
142 | END IF; | |||
|
|
143 | ||||
|
|
144 | ||||
|
|
145 | WHEN WAIT_LAST_READY => | |||
|
|
146 | IF DMAOut.Ready = '1' THEN | |||
|
|
147 | IF grant_counter = UNSIGNED(Nb_word_less1) THEN | |||
|
|
148 | state <= IDLE; | |||
|
|
149 | send_ok <= '1'; | |||
|
|
150 | send_ko <= '0'; | |||
|
|
151 | ELSE | |||
|
|
152 | state <= ERROR0; | |||
|
|
153 | END IF; | |||
|
|
154 | END IF; | |||
|
|
155 | ||||
|
|
156 | WHEN ERROR0 => | |||
|
|
157 | state <= ERROR1; | |||
|
|
158 | WHEN ERROR1 => | |||
|
|
159 | send_ok <= '0'; | |||
|
|
160 | send_ko <= '1'; | |||
|
|
161 | state <= IDLE; | |||
|
|
162 | WHEN OTHERS => NULL; | |||
|
|
163 | END CASE; | |||
|
|
164 | END IF; | |||
|
|
165 | END PROCESS; | |||
|
|
166 | ||||
|
|
167 | DMAIn.Data <= data; | |||
|
|
168 | ||||
|
|
169 | ren <= '0' WHEN DMAOut.OKAY = '1' AND state = SEND_DATA ELSE | |||
|
|
170 | '0' WHEN state = REQUEST_BUS AND DMAOut.Grant = '1' ELSE | |||
|
|
171 | '1'; | |||
|
|
172 | ||||
|
|
173 | END beh; | |||
| @@ -0,0 +1,176 | |||||
|
|
1 | ------------------------------------------------------------------------------ | |||
|
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
|
3 | -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS | |||
|
|
4 | -- | |||
|
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
|
8 | -- (at your option) any later version. | |||
|
|
9 | -- | |||
|
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
|
13 | -- GNU General Public License for more details. | |||
|
|
14 | -- | |||
|
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
|
16 | -- along with this program; if not, write to the Free Software | |||
|
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
|
18 | ------------------------------------------------------------------------------ | |||
|
|
19 | -- Author : Jean-christophe PELLION | |||
|
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |||
|
|
21 | ------------------------------------------------------------------------------ | |||
|
|
22 | LIBRARY IEEE; | |||
|
|
23 | USE IEEE.std_logic_1164.ALL; | |||
|
|
24 | USE IEEE.numeric_std.ALL; | |||
|
|
25 | LIBRARY lpp; | |||
|
|
26 | USE lpp.lpp_memory.ALL; | |||
|
|
27 | USE lpp.iir_filter.ALL; | |||
|
|
28 | USE lpp.lpp_waveform_pkg.ALL; | |||
|
|
29 | ||||
|
|
30 | LIBRARY techmap; | |||
|
|
31 | USE techmap.gencomp.ALL; | |||
|
|
32 | ||||
|
|
33 | ENTITY lpp_waveform_fifo IS | |||
|
|
34 | GENERIC( | |||
|
|
35 | tech : INTEGER := 0 | |||
|
|
36 | ); | |||
|
|
37 | PORT( | |||
|
|
38 | clk : IN STD_LOGIC; | |||
|
|
39 | rstn : IN STD_LOGIC; | |||
|
|
40 | ||||
|
|
41 | --------------------------------------------------------------------------- | |||
|
|
42 | ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- FIFO_DATA occupancy is greater than 16 * 32b | |||
|
|
43 | ||||
|
|
44 | --------------------------------------------------------------------------- | |||
|
|
45 | time_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
46 | data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
47 | ||||
|
|
48 | rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
49 | ||||
|
|
50 | --------------------------------------------------------------------------- | |||
|
|
51 | time_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
52 | data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
53 | ||||
|
|
54 | wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0) | |||
|
|
55 | ); | |||
|
|
56 | END ENTITY; | |||
|
|
57 | ||||
|
|
58 | ||||
|
|
59 | ARCHITECTURE ar_lpp_waveform_fifo OF lpp_waveform_fifo IS | |||
|
|
60 | ||||
|
|
61 | ||||
|
|
62 | SIGNAL time_mem_addr_r : LPP_TYPE_ADDR_FIFO_WAVEFORM(3 DOWNTO 0); | |||
|
|
63 | SIGNAL time_mem_addr_w : LPP_TYPE_ADDR_FIFO_WAVEFORM(3 DOWNTO 0); | |||
|
|
64 | SIGNAL time_mem_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
65 | SIGNAL time_mem_wen : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
66 | ||||
|
|
67 | SIGNAL data_mem_addr_r : LPP_TYPE_ADDR_FIFO_WAVEFORM(3 DOWNTO 0); | |||
|
|
68 | SIGNAL data_mem_addr_w : LPP_TYPE_ADDR_FIFO_WAVEFORM(3 DOWNTO 0); | |||
|
|
69 | SIGNAL data_mem_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
70 | SIGNAL data_mem_wen : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
71 | ||||
|
|
72 | SIGNAL data_addr_r : STD_LOGIC_VECTOR(6 DOWNTO 0); | |||
|
|
73 | SIGNAL data_addr_w : STD_LOGIC_VECTOR(6 DOWNTO 0); | |||
|
|
74 | SIGNAL ren : STD_LOGIC; | |||
|
|
75 | SIGNAL wen : STD_LOGIC; | |||
|
|
76 | ||||
|
|
77 | BEGIN | |||
|
|
78 | ||||
|
|
79 | SRAM : syncram_2p | |||
|
|
80 | GENERIC MAP(tech, 7, 32) | |||
|
|
81 | PORT MAP(clk, ren, data_addr_r, rdata, | |||
|
|
82 | clk, wen, data_addr_w, wdata); | |||
|
|
83 | ||||
|
|
84 | ||||
|
|
85 | ren <= time_mem_ren(3) OR data_mem_ren(3) OR | |||
|
|
86 | time_mem_ren(2) OR data_mem_ren(2) OR | |||
|
|
87 | time_mem_ren(1) OR data_mem_ren(1) OR | |||
|
|
88 | time_mem_ren(0) OR data_mem_ren(0); | |||
|
|
89 | ||||
|
|
90 | wen <= time_mem_wen(3) OR data_mem_wen(3) OR | |||
|
|
91 | time_mem_wen(2) OR data_mem_wen(2) OR | |||
|
|
92 | time_mem_wen(1) OR data_mem_wen(1) OR | |||
|
|
93 | time_mem_wen(0) OR data_mem_wen(0); | |||
|
|
94 | ||||
|
|
95 | data_addr_r <= time_mem_addr_r(0) WHEN time_mem_ren(0) = '1' ELSE | |||
|
|
96 | time_mem_addr_r(1) WHEN time_mem_ren(1) = '1' ELSE | |||
|
|
97 | time_mem_addr_r(2) WHEN time_mem_ren(2) = '1' ELSE | |||
|
|
98 | time_mem_addr_r(3) WHEN time_mem_ren(3) = '1' ELSE | |||
|
|
99 | data_mem_addr_r(0) WHEN data_mem_ren(0) = '1' ELSE | |||
|
|
100 | data_mem_addr_r(1) WHEN data_mem_ren(1) = '1' ELSE | |||
|
|
101 | data_mem_addr_r(2) WHEN data_mem_ren(2) = '1' ELSE | |||
|
|
102 | data_mem_addr_r(3); | |||
|
|
103 | ||||
|
|
104 | data_addr_w <= time_mem_addr_w(0) WHEN time_mem_wen(0) = '1' ELSE | |||
|
|
105 | time_mem_addr_w(1) WHEN time_mem_wen(1) = '1' ELSE | |||
|
|
106 | time_mem_addr_w(2) WHEN time_mem_wen(2) = '1' ELSE | |||
|
|
107 | time_mem_addr_w(3) WHEN time_mem_wen(3) = '1' ELSE | |||
|
|
108 | data_mem_addr_w(0) WHEN data_mem_wen(0) = '1' ELSE | |||
|
|
109 | data_mem_addr_w(1) WHEN data_mem_wen(1) = '1' ELSE | |||
|
|
110 | data_mem_addr_w(2) WHEN data_mem_wen(2) = '1' ELSE | |||
|
|
111 | data_mem_addr_w(3); | |||
|
|
112 | ||||
|
|
113 | gen_fifo_ctrl_time: FOR I IN 3 DOWNTO 0 GENERATE | |||
|
|
114 | lpp_waveform_fifo_ctrl_time: lpp_waveform_fifo_ctrl | |||
|
|
115 | GENERIC MAP ( | |||
|
|
116 | offset => 32*I + 20, | |||
|
|
117 | length => 10, | |||
|
|
118 | enable_ready => '0') | |||
|
|
119 | PORT MAP ( | |||
|
|
120 | clk => clk, | |||
|
|
121 | rstn => rstn, | |||
|
|
122 | ren => time_ren(I), | |||
|
|
123 | wen => time_wen(I), | |||
|
|
124 | mem_re => time_mem_ren(I), | |||
|
|
125 | mem_we => time_mem_wen(I), | |||
|
|
126 | mem_addr_ren => time_mem_addr_r(I), | |||
|
|
127 | mem_addr_wen => time_mem_addr_w(I), | |||
|
|
128 | ready => OPEN); | |||
|
|
129 | END GENERATE gen_fifo_ctrl_time; | |||
|
|
130 | ||||
|
|
131 | gen_fifo_ctrl_data: FOR I IN 3 DOWNTO 0 GENERATE | |||
|
|
132 | lpp_waveform_fifo_ctrl_data: lpp_waveform_fifo_ctrl | |||
|
|
133 | GENERIC MAP ( | |||
|
|
134 | offset => 32*I, | |||
|
|
135 | length => 20, | |||
|
|
136 | enable_ready => '1') | |||
|
|
137 | PORT MAP ( | |||
|
|
138 | clk => clk, | |||
|
|
139 | rstn => rstn, | |||
|
|
140 | ren => data_ren(I), | |||
|
|
141 | wen => data_wen(I), | |||
|
|
142 | mem_re => data_mem_ren(I), | |||
|
|
143 | mem_we => data_mem_wen(I), | |||
|
|
144 | mem_addr_ren => data_mem_addr_r(I), | |||
|
|
145 | mem_addr_wen => data_mem_addr_w(I), | |||
|
|
146 | ready => ready(I)); | |||
|
|
147 | END GENERATE gen_fifo_ctrl_data; | |||
|
|
148 | ||||
|
|
149 | ||||
|
|
150 | END ARCHITECTURE; | |||
|
|
151 | ||||
|
|
152 | ||||
|
|
153 | ||||
|
|
154 | ||||
|
|
155 | ||||
|
|
156 | ||||
|
|
157 | ||||
|
|
158 | ||||
|
|
159 | ||||
|
|
160 | ||||
|
|
161 | ||||
|
|
162 | ||||
|
|
163 | ||||
|
|
164 | ||||
|
|
165 | ||||
|
|
166 | ||||
|
|
167 | ||||
|
|
168 | ||||
|
|
169 | ||||
|
|
170 | ||||
|
|
171 | ||||
|
|
172 | ||||
|
|
173 | ||||
|
|
174 | ||||
|
|
175 | ||||
|
|
176 | ||||
| @@ -0,0 +1,177 | |||||
|
|
1 | ------------------------------------------------------------------------------ | |||
|
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
|
3 | -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS | |||
|
|
4 | -- | |||
|
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
|
8 | -- (at your option) any later version. | |||
|
|
9 | -- | |||
|
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
|
13 | -- GNU General Public License for more details. | |||
|
|
14 | -- | |||
|
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
|
16 | -- along with this program; if not, write to the Free Software | |||
|
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
|
18 | ------------------------------------------------------------------------------ | |||
|
|
19 | -- Author : Jean-christophe PELLION | |||
|
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |||
|
|
21 | ------------------------------------------------------------------------------ | |||
|
|
22 | LIBRARY IEEE; | |||
|
|
23 | USE IEEE.std_logic_1164.ALL; | |||
|
|
24 | USE IEEE.numeric_std.ALL; | |||
|
|
25 | ||||
|
|
26 | LIBRARY lpp; | |||
|
|
27 | USE lpp.lpp_waveform_pkg.ALL; | |||
|
|
28 | ||||
|
|
29 | ENTITY lpp_waveform_fifo_arbiter IS | |||
|
|
30 | GENERIC( | |||
|
|
31 | tech : INTEGER := 0 | |||
|
|
32 | ); | |||
|
|
33 | PORT( | |||
|
|
34 | clk : IN STD_LOGIC; | |||
|
|
35 | rstn : IN STD_LOGIC; | |||
|
|
36 | ||||
|
|
37 | --------------------------------------------------------------------------- | |||
|
|
38 | data_f0_valid : IN STD_LOGIC; | |||
|
|
39 | data_f1_valid : IN STD_LOGIC; | |||
|
|
40 | data_f2_valid : IN STD_LOGIC; | |||
|
|
41 | data_f3_valid : IN STD_LOGIC; | |||
|
|
42 | ||||
|
|
43 | data_valid_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
44 | ||||
|
|
45 | data_f0 : IN STD_LOGIC_VECTOR(159 DOWNTO 0); | |||
|
|
46 | data_f1 : IN STD_LOGIC_VECTOR(159 DOWNTO 0); | |||
|
|
47 | data_f2 : IN STD_LOGIC_VECTOR(159 DOWNTO 0); | |||
|
|
48 | data_f3 : IN STD_LOGIC_VECTOR(159 DOWNTO 0); | |||
|
|
49 | ||||
|
|
50 | --------------------------------------------------------------------------- | |||
|
|
51 | ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
52 | ||||
|
|
53 | --------------------------------------------------------------------------- | |||
|
|
54 | time_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
55 | data_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
56 | data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |||
|
|
57 | ||||
|
|
58 | ); | |||
|
|
59 | END ENTITY; | |||
|
|
60 | ||||
|
|
61 | ||||
|
|
62 | ARCHITECTURE ar_lpp_waveform_fifo_arbiter OF lpp_waveform_fifo_arbiter IS | |||
|
|
63 | TYPE state_fsm IS (IDLE, T1, T2, D1, D2); | |||
|
|
64 | SIGNAL state : state_fsm; | |||
|
|
65 | ||||
|
|
66 | SIGNAL data_valid_and_ready : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
67 | SIGNAL data_selected : STD_LOGIC_VECTOR(159 DOWNTO 0); | |||
|
|
68 | SIGNAL data_valid_selected : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
69 | SIGNAL data_ready_to_go : STD_LOGIC; | |||
|
|
70 | ||||
|
|
71 | SIGNAL data_temp : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); | |||
|
|
72 | SIGNAL time_en_temp : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
73 | BEGIN | |||
|
|
74 | ||||
|
|
75 | data_valid_and_ready(0) <= ready(0) AND data_f0_valid; | |||
|
|
76 | data_valid_and_ready(1) <= ready(1) AND data_f1_valid; | |||
|
|
77 | data_valid_and_ready(2) <= ready(2) AND data_f2_valid; | |||
|
|
78 | data_valid_and_ready(3) <= ready(3) AND data_f3_valid; | |||
|
|
79 | ||||
|
|
80 | data_selected <= data_f0 WHEN data_valid_and_ready(0) = '1' ELSE | |||
|
|
81 | data_f1 WHEN data_valid_and_ready(1) = '1' ELSE | |||
|
|
82 | data_f2 WHEN data_valid_and_ready(2) = '1' ELSE | |||
|
|
83 | data_f3; | |||
|
|
84 | ||||
|
|
85 | data_valid_selected <= "0001" WHEN data_valid_and_ready(0) = '1' ELSE | |||
|
|
86 | "0010" WHEN data_valid_and_ready(1) = '1' ELSE | |||
|
|
87 | "0100" WHEN data_valid_and_ready(2) = '1' ELSE | |||
|
|
88 | "1000" WHEN data_valid_and_ready(3) = '1' ELSE | |||
|
|
89 | "0000"; | |||
|
|
90 | ||||
|
|
91 | data_ready_to_go <= data_valid_and_ready(0) OR | |||
|
|
92 | data_valid_and_ready(1) OR | |||
|
|
93 | data_valid_and_ready(2) OR | |||
|
|
94 | data_valid_and_ready(3); | |||
|
|
95 | ||||
|
|
96 | PROCESS (clk, rstn) | |||
|
|
97 | BEGIN | |||
|
|
98 | IF rstn = '0' THEN | |||
|
|
99 | state <= IDLE; | |||
|
|
100 | data_valid_ack <= (OTHERS => '0'); | |||
|
|
101 | data_wen <= (OTHERS => '1'); | |||
|
|
102 | time_wen <= (OTHERS => '1'); | |||
|
|
103 | data <= (OTHERS => '0'); | |||
|
|
104 | data_temp <= (OTHERS => '0'); | |||
|
|
105 | time_en_temp <= (OTHERS => '0'); | |||
|
|
106 | ELSIF clk'EVENT AND clk = '1' THEN | |||
|
|
107 | CASE state IS | |||
|
|
108 | WHEN IDLE => | |||
|
|
109 | data_valid_ack <= (OTHERS => '0'); | |||
|
|
110 | time_wen <= (OTHERS => '1'); | |||
|
|
111 | data_wen <= (OTHERS => '1'); | |||
|
|
112 | data <= (OTHERS => '0'); | |||
|
|
113 | data_temp <= (OTHERS => '0'); | |||
|
|
114 | IF data_ready_to_go = '1' THEN | |||
|
|
115 | state <= T1; | |||
|
|
116 | data_valid_ack <= data_valid_selected; | |||
|
|
117 | time_wen <= NOT data_valid_selected; | |||
|
|
118 | time_en_temp <= NOT data_valid_selected; | |||
|
|
119 | data <= data_selected(31 DOWNTO 0); | |||
|
|
120 | data_temp <= data_selected(159 DOWNTO 32); | |||
|
|
121 | END IF; | |||
|
|
122 | WHEN T1 => | |||
|
|
123 | state <= T2; | |||
|
|
124 | data_valid_ack <= (OTHERS => '0'); | |||
|
|
125 | data <= data_temp(31 DOWNTO 0); | |||
|
|
126 | data_temp(32*3-1 DOWNTO 0) <= data_temp(32*4-1 DOWNTO 32); | |||
|
|
127 | ||||
|
|
128 | WHEN T2 => | |||
|
|
129 | state <= D1; | |||
|
|
130 | time_wen <= (OTHERS => '1'); | |||
|
|
131 | data_wen <= time_en_temp; | |||
|
|
132 | data <= data_temp(31 DOWNTO 0); | |||
|
|
133 | data_temp(32*3-1 DOWNTO 0) <= data_temp(32*4-1 DOWNTO 32); | |||
|
|
134 | ||||
|
|
135 | WHEN D1 => | |||
|
|
136 | state <= D2; | |||
|
|
137 | data <= data_temp(31 DOWNTO 0); | |||
|
|
138 | data_temp(32*3-1 DOWNTO 0) <= data_temp(32*4-1 DOWNTO 32); | |||
|
|
139 | ||||
|
|
140 | WHEN D2 => | |||
|
|
141 | state <= IDLE; | |||
|
|
142 | data <= data_temp(31 DOWNTO 0); | |||
|
|
143 | data_temp(32*3-1 DOWNTO 0) <= data_temp(32*4-1 DOWNTO 32); | |||
|
|
144 | ||||
|
|
145 | WHEN OTHERS => NULL; | |||
|
|
146 | END CASE; | |||
|
|
147 | ||||
|
|
148 | END IF; | |||
|
|
149 | END PROCESS; | |||
|
|
150 | ||||
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151 | END ARCHITECTURE; | |||
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152 | ||||
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153 | ||||
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154 | ||||
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155 | ||||
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156 | ||||
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169 | ||||
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174 | ||||
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176 | ||||
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177 | ||||
| @@ -0,0 +1,171 | |||||
|
|
1 | ------------------------------------------------------------------------------ | |||
|
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
|
3 | -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS | |||
|
|
4 | -- | |||
|
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
|
8 | -- (at your option) any later version. | |||
|
|
9 | -- | |||
|
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
|
13 | -- GNU General Public License for more details. | |||
|
|
14 | -- | |||
|
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
|
16 | -- along with this program; if not, write to the Free Software | |||
|
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
|
18 | ------------------------------------------------------------------------------ | |||
|
|
19 | -- Author : Jean-christophe PELLION | |||
|
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |||
|
|
21 | ------------------------------------------------------------------------------ | |||
|
|
22 | LIBRARY IEEE; | |||
|
|
23 | USE IEEE.std_logic_1164.ALL; | |||
|
|
24 | USE IEEE.numeric_std.ALL; | |||
|
|
25 | LIBRARY lpp; | |||
|
|
26 | USE lpp.lpp_memory.ALL; | |||
|
|
27 | USE lpp.iir_filter.ALL; | |||
|
|
28 | USE lpp.lpp_waveform_pkg.ALL; | |||
|
|
29 | ||||
|
|
30 | LIBRARY techmap; | |||
|
|
31 | USE techmap.gencomp.ALL; | |||
|
|
32 | ||||
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33 | ENTITY lpp_waveform_fifo_ctrl IS | |||
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34 | generic( | |||
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35 | offset : INTEGER := 0; | |||
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|
36 | length : INTEGER := 20; | |||
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37 | enable_ready : STD_LOGIC := '1' | |||
|
|
38 | ); | |||
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39 | PORT( | |||
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|
40 | clk : IN STD_LOGIC; | |||
|
|
41 | rstn : IN STD_LOGIC; | |||
|
|
42 | ||||
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43 | ren : IN STD_LOGIC; | |||
|
|
44 | wen : IN STD_LOGIC; | |||
|
|
45 | ||||
|
|
46 | mem_re : OUT STD_LOGIC; | |||
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47 | mem_we : OUT STD_LOGIC; | |||
|
|
48 | ||||
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49 | mem_addr_ren : out STD_LOGIC_VECTOR(6 DOWNTO 0); | |||
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50 | mem_addr_wen : out STD_LOGIC_VECTOR(6 DOWNTO 0); | |||
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51 | ||||
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52 | ready : OUT STD_LOGIC | |||
|
|
53 | ); | |||
|
|
54 | END ENTITY; | |||
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55 | ||||
|
|
56 | ||||
|
|
57 | ARCHITECTURE ar_lpp_waveform_fifo_ctrl OF lpp_waveform_fifo_ctrl IS | |||
|
|
58 | ||||
|
|
59 | SIGNAL sFull : STD_LOGIC; | |||
|
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60 | SIGNAL sFull_s : STD_LOGIC; | |||
|
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61 | SIGNAL sEmpty_s : STD_LOGIC; | |||
|
|
62 | ||||
|
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63 | SIGNAL sEmpty : STD_LOGIC; | |||
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64 | SIGNAL sREN : STD_LOGIC; | |||
|
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65 | SIGNAL sWEN : STD_LOGIC; | |||
|
|
66 | SIGNAL sRE : STD_LOGIC; | |||
|
|
67 | SIGNAL sWE : STD_LOGIC; | |||
|
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68 | ||||
|
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69 | SIGNAL Waddr_vect : INTEGER RANGE 0 TO length := 0; | |||
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70 | SIGNAL Raddr_vect : INTEGER RANGE 0 TO length := 0; | |||
|
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71 | SIGNAL Waddr_vect_s : INTEGER RANGE 0 TO length := 0; | |||
|
|
72 | SIGNAL Raddr_vect_s : INTEGER RANGE 0 TO length := 0; | |||
|
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73 | ||||
|
|
74 | BEGIN | |||
|
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75 | mem_re <= sRE; | |||
|
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76 | mem_we <= sWE; | |||
|
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77 | --============================= | |||
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78 | -- Read section | |||
|
|
79 | --============================= | |||
|
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80 | sREN <= REN OR sEmpty; | |||
|
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81 | sRE <= NOT sREN; | |||
|
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82 | ||||
|
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83 | sEmpty_s <= '1' WHEN sEmpty = '1' AND Wen = '1' ELSE | |||
|
|
84 | '1' WHEN sEmpty = '0' AND (Wen = '1' AND Ren = '0' AND Raddr_vect_s = Waddr_vect) ELSE | |||
|
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85 | '0'; | |||
|
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86 | ||||
|
|
87 | Raddr_vect_s <= Raddr_vect +1 WHEN Raddr_vect < length -1 ELSE 0 ; | |||
|
|
88 | ||||
|
|
89 | PROCESS (clk, rstn) | |||
|
|
90 | BEGIN | |||
|
|
91 | IF(rstn = '0')then | |||
|
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92 | Raddr_vect <= 0; | |||
|
|
93 | sempty <= '1'; | |||
|
|
94 | ELSIF(clk'EVENT AND clk = '1')then | |||
|
|
95 | sEmpty <= sempty_s; | |||
|
|
96 | ||||
|
|
97 | IF(sREN = '0' and sempty = '0')then | |||
|
|
98 | Raddr_vect <= Raddr_vect_s; | |||
|
|
99 | END IF; | |||
|
|
100 | ||||
|
|
101 | END IF; | |||
|
|
102 | END PROCESS; | |||
|
|
103 | ||||
|
|
104 | --============================= | |||
|
|
105 | -- Write section | |||
|
|
106 | --============================= | |||
|
|
107 | sWEN <= WEN OR sFull; | |||
|
|
108 | sWE <= NOT sWEN; | |||
|
|
109 | ||||
|
|
110 | sFull_s <= '1' WHEN Waddr_vect_s = Raddr_vect AND REN = '1' AND WEN = '0' ELSE | |||
|
|
111 | '1' WHEN sFull = '1' AND REN = '1' ELSE | |||
|
|
112 | '0'; | |||
|
|
113 | ||||
|
|
114 | Waddr_vect_s <= Waddr_vect +1 WHEN Waddr_vect < length -1 ELSE 0 ; | |||
|
|
115 | ||||
|
|
116 | PROCESS (clk, rstn) | |||
|
|
117 | BEGIN | |||
|
|
118 | IF(rstn = '0')then | |||
|
|
119 | Waddr_vect <= 0; | |||
|
|
120 | sfull <= '0'; | |||
|
|
121 | ELSIF(clk'EVENT AND clk = '1')then | |||
|
|
122 | sfull <= sfull_s; | |||
|
|
123 | ||||
|
|
124 | IF(sWEN = '0' and sfull = '0')THEN | |||
|
|
125 | Waddr_vect <= Waddr_vect_s; | |||
|
|
126 | END IF; | |||
|
|
127 | ||||
|
|
128 | END IF; | |||
|
|
129 | END PROCESS; | |||
|
|
130 | ||||
|
|
131 | ||||
|
|
132 | mem_addr_wen <= std_logic_vector(to_unsigned((Waddr_vect + offset), mem_addr_wen'length)); | |||
|
|
133 | mem_addr_ren <= std_logic_vector(to_unsigned((Raddr_vect + offset), mem_addr_ren'length)); | |||
|
|
134 | ||||
|
|
135 | ready_gen: IF enable_ready = '1' GENERATE | |||
|
|
136 | ready <= '1' WHEN Waddr_vect > Raddr_vect AND (Waddr_vect - Raddr_vect) > 15 ELSE | |||
|
|
137 | '1' WHEN Waddr_vect < Raddr_vect AND (length + Waddr_vect - Raddr_vect) > 15 ELSE | |||
|
|
138 | '0'; | |||
|
|
139 | END GENERATE ready_gen; | |||
|
|
140 | ||||
|
|
141 | ready_not_gen: IF enable_ready = '0' GENERATE | |||
|
|
142 | ready <= '0'; | |||
|
|
143 | END GENERATE ready_not_gen; | |||
|
|
144 | ||||
|
|
145 | END ARCHITECTURE; | |||
|
|
146 | ||||
|
|
147 | ||||
|
|
148 | ||||
|
|
149 | ||||
|
|
150 | ||||
|
|
151 | ||||
|
|
152 | ||||
|
|
153 | ||||
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|
154 | ||||
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|
155 | ||||
|
|
156 | ||||
|
|
157 | ||||
|
|
158 | ||||
|
|
159 | ||||
|
|
160 | ||||
|
|
161 | ||||
|
|
162 | ||||
|
|
163 | ||||
|
|
164 | ||||
|
|
165 | ||||
|
|
166 | ||||
|
|
167 | ||||
|
|
168 | ||||
|
|
169 | ||||
|
|
170 | ||||
|
|
171 | ||||
| @@ -0,0 +1,243 | |||||
|
|
1 | LIBRARY IEEE; | |||
|
|
2 | USE IEEE.STD_LOGIC_1164.ALL; | |||
|
|
3 | ||||
|
|
4 | LIBRARY grlib; | |||
|
|
5 | USE grlib.amba.ALL; | |||
|
|
6 | USE grlib.stdlib.ALL; | |||
|
|
7 | USE grlib.devices.ALL; | |||
|
|
8 | USE GRLIB.DMA2AHB_Package.ALL; | |||
|
|
9 | ||||
|
|
10 | LIBRARY techmap; | |||
|
|
11 | USE techmap.gencomp.ALL; | |||
|
|
12 | ||||
|
|
13 | PACKAGE lpp_waveform_pkg IS | |||
|
|
14 | ||||
|
|
15 | TYPE LPP_TYPE_ADDR_FIFO_WAVEFORM IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(6 DOWNTO 0); | |||
|
|
16 | ||||
|
|
17 | COMPONENT lpp_waveform_snapshot | |||
|
|
18 | GENERIC ( | |||
|
|
19 | data_size : INTEGER; | |||
|
|
20 | nb_snapshot_param_size : INTEGER); | |||
|
|
21 | PORT ( | |||
|
|
22 | clk : IN STD_LOGIC; | |||
|
|
23 | rstn : IN STD_LOGIC; | |||
|
|
24 | enable : IN STD_LOGIC; | |||
|
|
25 | burst_enable : IN STD_LOGIC; | |||
|
|
26 | nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |||
|
|
27 | start_snapshot : IN STD_LOGIC; | |||
|
|
28 | data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
|
|
29 | data_in_valid : IN STD_LOGIC; | |||
|
|
30 | data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
|
|
31 | data_out_valid : OUT STD_LOGIC); | |||
|
|
32 | END COMPONENT; | |||
|
|
33 | ||||
|
|
34 | COMPONENT lpp_waveform_burst | |||
|
|
35 | GENERIC ( | |||
|
|
36 | data_size : INTEGER); | |||
|
|
37 | PORT ( | |||
|
|
38 | clk : IN STD_LOGIC; | |||
|
|
39 | rstn : IN STD_LOGIC; | |||
|
|
40 | enable : IN STD_LOGIC; | |||
|
|
41 | data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
|
|
42 | data_in_valid : IN STD_LOGIC; | |||
|
|
43 | data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
|
|
44 | data_out_valid : OUT STD_LOGIC); | |||
|
|
45 | END COMPONENT; | |||
|
|
46 | ||||
|
|
47 | COMPONENT lpp_waveform_snapshot_controler | |||
|
|
48 | GENERIC ( | |||
|
|
49 | delta_snapshot_size : INTEGER; | |||
|
|
50 | delta_f2_f0_size : INTEGER; | |||
|
|
51 | delta_f2_f1_size : INTEGER); | |||
|
|
52 | PORT ( | |||
|
|
53 | clk : IN STD_LOGIC; | |||
|
|
54 | rstn : IN STD_LOGIC; | |||
|
|
55 | delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); | |||
|
|
56 | delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); | |||
|
|
57 | delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); | |||
|
|
58 | coarse_time_0 : IN STD_LOGIC; | |||
|
|
59 | data_f0_in_valid : IN STD_LOGIC; | |||
|
|
60 | data_f2_in_valid : IN STD_LOGIC; | |||
|
|
61 | start_snapshot_f0 : OUT STD_LOGIC; | |||
|
|
62 | start_snapshot_f1 : OUT STD_LOGIC; | |||
|
|
63 | start_snapshot_f2 : OUT STD_LOGIC); | |||
|
|
64 | END COMPONENT; | |||
|
|
65 | ||||
|
|
66 | ||||
|
|
67 | ||||
|
|
68 | COMPONENT lpp_waveform | |||
|
|
69 | GENERIC ( | |||
|
|
70 | hindex : INTEGER; | |||
|
|
71 | tech : INTEGER; | |||
|
|
72 | data_size : INTEGER; | |||
|
|
73 | nb_burst_available_size : INTEGER; | |||
|
|
74 | nb_snapshot_param_size : INTEGER; | |||
|
|
75 | delta_snapshot_size : INTEGER; | |||
|
|
76 | delta_f2_f0_size : INTEGER; | |||
|
|
77 | delta_f2_f1_size : INTEGER); | |||
|
|
78 | PORT ( | |||
|
|
79 | clk : IN STD_LOGIC; | |||
|
|
80 | rstn : IN STD_LOGIC; | |||
|
|
81 | AHB_Master_In : IN AHB_Mst_In_Type; | |||
|
|
82 | AHB_Master_Out : OUT AHB_Mst_Out_Type; | |||
|
|
83 | coarse_time_0 : IN STD_LOGIC; | |||
|
|
84 | delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); | |||
|
|
85 | delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); | |||
|
|
86 | delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); | |||
|
|
87 | enable_f0 : IN STD_LOGIC; | |||
|
|
88 | enable_f1 : IN STD_LOGIC; | |||
|
|
89 | enable_f2 : IN STD_LOGIC; | |||
|
|
90 | enable_f3 : IN STD_LOGIC; | |||
|
|
91 | burst_f0 : IN STD_LOGIC; | |||
|
|
92 | burst_f1 : IN STD_LOGIC; | |||
|
|
93 | burst_f2 : IN STD_LOGIC; | |||
|
|
94 | nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); | |||
|
|
95 | nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |||
|
|
96 | status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
97 | status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
98 | status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
99 | status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
100 | addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
101 | addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
102 | addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
103 | addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
104 | data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
|
|
105 | data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
|
|
106 | data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
|
|
107 | data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
|
|
108 | data_f0_in_valid : IN STD_LOGIC; | |||
|
|
109 | data_f1_in_valid : IN STD_LOGIC; | |||
|
|
110 | data_f2_in_valid : IN STD_LOGIC; | |||
|
|
111 | data_f3_in_valid : IN STD_LOGIC); | |||
|
|
112 | END COMPONENT; | |||
|
|
113 | ||||
|
|
114 | COMPONENT lpp_waveform_dma_send_Nword | |||
|
|
115 | PORT ( | |||
|
|
116 | HCLK : IN STD_ULOGIC; | |||
|
|
117 | HRESETn : IN STD_ULOGIC; | |||
|
|
118 | DMAIn : OUT DMA_In_Type; | |||
|
|
119 | DMAOut : IN DMA_OUt_Type; | |||
|
|
120 | Nb_word_less1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
121 | send : IN STD_LOGIC; | |||
|
|
122 | address : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
123 | data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
124 | ren : OUT STD_LOGIC; | |||
|
|
125 | send_ok : OUT STD_LOGIC; | |||
|
|
126 | send_ko : OUT STD_LOGIC); | |||
|
|
127 | END COMPONENT; | |||
|
|
128 | ||||
|
|
129 | COMPONENT lpp_waveform_dma_selectaddress | |||
|
|
130 | GENERIC ( | |||
|
|
131 | nb_burst_available_size : INTEGER); | |||
|
|
132 | PORT ( | |||
|
|
133 | HCLK : IN STD_ULOGIC; | |||
|
|
134 | HRESETn : IN STD_ULOGIC; | |||
|
|
135 | update : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
|
|
136 | nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); | |||
|
|
137 | addr_data_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
138 | addr_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
139 | status_full : OUT STD_LOGIC; | |||
|
|
140 | status_full_ack : IN STD_LOGIC; | |||
|
|
141 | status_full_err : OUT STD_LOGIC); | |||
|
|
142 | END COMPONENT; | |||
|
|
143 | ||||
|
|
144 | COMPONENT lpp_waveform_dma_gen_valid | |||
|
|
145 | PORT ( | |||
|
|
146 | HCLK : IN STD_LOGIC; | |||
|
|
147 | HRESETn : IN STD_LOGIC; | |||
|
|
148 | valid_in : IN STD_LOGIC; | |||
|
|
149 | ack_in : IN STD_LOGIC; | |||
|
|
150 | valid_out : OUT STD_LOGIC; | |||
|
|
151 | error : OUT STD_LOGIC); | |||
|
|
152 | END COMPONENT; | |||
|
|
153 | ||||
|
|
154 | COMPONENT lpp_waveform_dma | |||
|
|
155 | GENERIC ( | |||
|
|
156 | data_size : INTEGER; | |||
|
|
157 | tech : INTEGER; | |||
|
|
158 | hindex : INTEGER; | |||
|
|
159 | nb_burst_available_size : INTEGER); | |||
|
|
160 | PORT ( | |||
|
|
161 | HCLK : IN STD_ULOGIC; | |||
|
|
162 | HRESETn : IN STD_ULOGIC; | |||
|
|
163 | AHB_Master_In : IN AHB_Mst_In_Type; | |||
|
|
164 | AHB_Master_Out : OUT AHB_Mst_Out_Type; | |||
|
|
165 | data_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
166 | data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
167 | data_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
168 | data_time_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
169 | --data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
|
|
170 | --data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
|
|
171 | --data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
|
|
172 | --data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
|
|
173 | --data_f0_in_valid : IN STD_LOGIC; | |||
|
|
174 | --data_f1_in_valid : IN STD_LOGIC; | |||
|
|
175 | --data_f2_in_valid : IN STD_LOGIC; | |||
|
|
176 | --data_f3_in_valid : IN STD_LOGIC; | |||
|
|
177 | nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); | |||
|
|
178 | status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
179 | status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
180 | status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
181 | -- status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
182 | addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
183 | addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
184 | addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
185 | addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); | |||
|
|
186 | END COMPONENT; | |||
|
|
187 | ||||
|
|
188 | COMPONENT lpp_waveform_fifo_ctrl | |||
|
|
189 | GENERIC ( | |||
|
|
190 | offset : INTEGER; | |||
|
|
191 | length : INTEGER; | |||
|
|
192 | enable_ready : STD_LOGIC); | |||
|
|
193 | PORT ( | |||
|
|
194 | clk : IN STD_LOGIC; | |||
|
|
195 | rstn : IN STD_LOGIC; | |||
|
|
196 | ren : IN STD_LOGIC; | |||
|
|
197 | wen : IN STD_LOGIC; | |||
|
|
198 | mem_re : OUT STD_LOGIC; | |||
|
|
199 | mem_we : OUT STD_LOGIC; | |||
|
|
200 | mem_addr_ren : out STD_LOGIC_VECTOR(6 DOWNTO 0); | |||
|
|
201 | mem_addr_wen : out STD_LOGIC_VECTOR(6 DOWNTO 0); | |||
|
|
202 | ready : OUT STD_LOGIC); | |||
|
|
203 | END COMPONENT; | |||
|
|
204 | ||||
|
|
205 | COMPONENT lpp_waveform_fifo_arbiter | |||
|
|
206 | GENERIC ( | |||
|
|
207 | tech : INTEGER); | |||
|
|
208 | PORT ( | |||
|
|
209 | clk : IN STD_LOGIC; | |||
|
|
210 | rstn : IN STD_LOGIC; | |||
|
|
211 | data_f0_valid : IN STD_LOGIC; | |||
|
|
212 | data_f1_valid : IN STD_LOGIC; | |||
|
|
213 | data_f2_valid : IN STD_LOGIC; | |||
|
|
214 | data_f3_valid : IN STD_LOGIC; | |||
|
|
215 | data_valid_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
216 | data_f0 : IN STD_LOGIC_VECTOR(159 DOWNTO 0); | |||
|
|
217 | data_f1 : IN STD_LOGIC_VECTOR(159 DOWNTO 0); | |||
|
|
218 | data_f2 : IN STD_LOGIC_VECTOR(159 DOWNTO 0); | |||
|
|
219 | data_f3 : IN STD_LOGIC_VECTOR(159 DOWNTO 0); | |||
|
|
220 | ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
221 | time_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
222 | data_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
223 | data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); | |||
|
|
224 | END COMPONENT; | |||
|
|
225 | ||||
|
|
226 | COMPONENT lpp_waveform_fifo | |||
|
|
227 | GENERIC ( | |||
|
|
228 | tech : INTEGER); | |||
|
|
229 | PORT ( | |||
|
|
230 | clk : IN STD_LOGIC; | |||
|
|
231 | rstn : IN STD_LOGIC; | |||
|
|
232 | ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
233 | time_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
234 | data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
235 | rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
236 | time_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
237 | data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
238 | wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); | |||
|
|
239 | END COMPONENT; | |||
|
|
240 | ||||
|
|
241 | ||||
|
|
242 | ||||
|
|
243 | END lpp_waveform_pkg; | |||
| @@ -0,0 +1,80 | |||||
|
|
1 | LIBRARY IEEE; | |||
|
|
2 | USE IEEE.STD_LOGIC_1164.ALL; | |||
|
|
3 | USE ieee.numeric_std.ALL; | |||
|
|
4 | ||||
|
|
5 | ENTITY lpp_waveform_snapshot IS | |||
|
|
6 | ||||
|
|
7 | GENERIC ( | |||
|
|
8 | data_size : INTEGER := 16; | |||
|
|
9 | nb_snapshot_param_size : INTEGER := 11); | |||
|
|
10 | ||||
|
|
11 | PORT ( | |||
|
|
12 | clk : IN STD_LOGIC; | |||
|
|
13 | rstn : IN STD_LOGIC; | |||
|
|
14 | ||||
|
|
15 | enable : IN STD_LOGIC; | |||
|
|
16 | burst_enable : IN STD_LOGIC; | |||
|
|
17 | nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |||
|
|
18 | ||||
|
|
19 | start_snapshot : IN STD_LOGIC; | |||
|
|
20 | ||||
|
|
21 | data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
|
|
22 | data_in_valid : IN STD_LOGIC; | |||
|
|
23 | ||||
|
|
24 | data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
|
|
25 | data_out_valid : OUT STD_LOGIC | |||
|
|
26 | ); | |||
|
|
27 | ||||
|
|
28 | END lpp_waveform_snapshot; | |||
|
|
29 | ||||
|
|
30 | ARCHITECTURE beh OF lpp_waveform_snapshot IS | |||
|
|
31 | SIGNAL counter_points_snapshot : INTEGER; | |||
|
|
32 | BEGIN -- beh | |||
|
|
33 | ||||
|
|
34 | PROCESS (clk, rstn) | |||
|
|
35 | BEGIN | |||
|
|
36 | IF rstn = '0' THEN | |||
|
|
37 | data_out <= (OTHERS => '0'); | |||
|
|
38 | data_out_valid <= '0'; | |||
|
|
39 | counter_points_snapshot <= 0; | |||
|
|
40 | ELSIF clk'EVENT AND clk = '1' THEN | |||
|
|
41 | data_out <= data_in; | |||
|
|
42 | IF enable = '0' THEN | |||
|
|
43 | data_out_valid <= '0'; | |||
|
|
44 | counter_points_snapshot <= 0; | |||
|
|
45 | ELSE | |||
|
|
46 | IF burst_enable = '1' THEN | |||
|
|
47 | -- BURST ModE -- | |||
|
|
48 | data_out_valid <= data_in_valid; | |||
|
|
49 | counter_points_snapshot <= 0; | |||
|
|
50 | ELSE | |||
|
|
51 | -- SNAPShOT MODE -- | |||
|
|
52 | IF start_snapshot = '1' THEN | |||
|
|
53 | IF data_in_valid = '1' THEN | |||
|
|
54 | counter_points_snapshot <= to_integer(unsigned(nb_snapshot_param)) - 1; | |||
|
|
55 | data_out_valid <= '1'; | |||
|
|
56 | ELSE | |||
|
|
57 | counter_points_snapshot <= to_integer(unsigned(nb_snapshot_param)); | |||
|
|
58 | data_out_valid <= '0'; | |||
|
|
59 | END IF; | |||
|
|
60 | ELSE | |||
|
|
61 | IF data_in_valid = '1' THEN | |||
|
|
62 | IF counter_points_snapshot > 0 THEN | |||
|
|
63 | counter_points_snapshot <= counter_points_snapshot - 1; | |||
|
|
64 | data_out_valid <= '1'; | |||
|
|
65 | ELSE | |||
|
|
66 | counter_points_snapshot <= counter_points_snapshot; | |||
|
|
67 | data_out_valid <= '0'; | |||
|
|
68 | END IF; | |||
|
|
69 | ELSE | |||
|
|
70 | counter_points_snapshot <= counter_points_snapshot; | |||
|
|
71 | data_out_valid <= '0'; | |||
|
|
72 | END IF; | |||
|
|
73 | END IF; | |||
|
|
74 | ||||
|
|
75 | END IF; | |||
|
|
76 | END IF; | |||
|
|
77 | END IF; | |||
|
|
78 | END PROCESS; | |||
|
|
79 | ||||
|
|
80 | END beh; | |||
| @@ -0,0 +1,116 | |||||
|
|
1 | LIBRARY IEEE; | |||
|
|
2 | USE IEEE.STD_LOGIC_1164.ALL; | |||
|
|
3 | USE ieee.numeric_std.ALL; | |||
|
|
4 | ||||
|
|
5 | ENTITY lpp_waveform_snapshot_controler IS | |||
|
|
6 | ||||
|
|
7 | GENERIC ( | |||
|
|
8 | delta_snapshot_size : INTEGER := 16; | |||
|
|
9 | delta_f2_f0_size : INTEGER := 10; | |||
|
|
10 | delta_f2_f1_size : INTEGER := 10); | |||
|
|
11 | ||||
|
|
12 | PORT ( | |||
|
|
13 | clk : IN STD_LOGIC; | |||
|
|
14 | rstn : IN STD_LOGIC; | |||
|
|
15 | --config | |||
|
|
16 | delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); | |||
|
|
17 | delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); | |||
|
|
18 | delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); | |||
|
|
19 | ||||
|
|
20 | --input | |||
|
|
21 | coarse_time_0 : IN STD_LOGIC; | |||
|
|
22 | data_f0_in_valid : IN STD_LOGIC; | |||
|
|
23 | data_f2_in_valid : IN STD_LOGIC; | |||
|
|
24 | --output | |||
|
|
25 | start_snapshot_f0 : OUT STD_LOGIC; | |||
|
|
26 | start_snapshot_f1 : OUT STD_LOGIC; | |||
|
|
27 | start_snapshot_f2 : OUT STD_LOGIC | |||
|
|
28 | ); | |||
|
|
29 | ||||
|
|
30 | END lpp_waveform_snapshot_controler; | |||
|
|
31 | ||||
|
|
32 | ARCHITECTURE beh OF lpp_waveform_snapshot_controler IS | |||
|
|
33 | SIGNAL counter_delta_snapshot : INTEGER; | |||
|
|
34 | SIGNAL counter_delta_f0 : INTEGER; | |||
|
|
35 | ||||
|
|
36 | SIGNAL coarse_time_0_r : STD_LOGIC; | |||
|
|
37 | SIGNAL start_snapshot_f2_temp : STD_LOGIC; | |||
|
|
38 | SIGNAL start_snapshot_fothers_temp : STD_LOGIC; | |||
|
|
39 | SIGNAL start_snapshot_fothers_temp2 : STD_LOGIC; | |||
|
|
40 | BEGIN -- beh | |||
|
|
41 | ||||
|
|
42 | PROCESS (clk, rstn) | |||
|
|
43 | BEGIN | |||
|
|
44 | IF rstn = '0' THEN | |||
|
|
45 | start_snapshot_f0 <= '0'; | |||
|
|
46 | start_snapshot_f1 <= '0'; | |||
|
|
47 | start_snapshot_f2 <= '0'; | |||
|
|
48 | counter_delta_snapshot <= 0; | |||
|
|
49 | counter_delta_f0 <= 0; | |||
|
|
50 | coarse_time_0_r <= '0'; | |||
|
|
51 | start_snapshot_f2_temp <= '0'; | |||
|
|
52 | start_snapshot_fothers_temp <= '0'; | |||
|
|
53 | start_snapshot_fothers_temp2 <= '0'; | |||
|
|
54 | ELSIF clk'EVENT AND clk = '1' THEN | |||
|
|
55 | IF counter_delta_snapshot = UNSIGNED(delta_snapshot) THEN | |||
|
|
56 | start_snapshot_f2_temp <= '1'; | |||
|
|
57 | ELSE | |||
|
|
58 | start_snapshot_f2_temp <= '0'; | |||
|
|
59 | END IF; | |||
|
|
60 | ------------------------------------------------------------------------- | |||
|
|
61 | IF counter_delta_snapshot = UNSIGNED(delta_snapshot) AND start_snapshot_f2_temp = '0' THEN | |||
|
|
62 | start_snapshot_f2 <= '1'; | |||
|
|
63 | ELSE | |||
|
|
64 | start_snapshot_f2 <= '0'; | |||
|
|
65 | END IF; | |||
|
|
66 | ------------------------------------------------------------------------- | |||
|
|
67 | coarse_time_0_r <= coarse_time_0; | |||
|
|
68 | IF coarse_time_0 = NOT coarse_time_0_r AND coarse_time_0 = '1' THEN | |||
|
|
69 | IF counter_delta_snapshot = 0 THEN | |||
|
|
70 | counter_delta_snapshot <= to_integer(UNSIGNED(delta_snapshot)); | |||
|
|
71 | ELSE | |||
|
|
72 | counter_delta_snapshot <= counter_delta_snapshot - 1; | |||
|
|
73 | END IF; | |||
|
|
74 | END IF; | |||
|
|
75 | ||||
|
|
76 | ||||
|
|
77 | ------------------------------------------------------------------------- | |||
|
|
78 | ||||
|
|
79 | ||||
|
|
80 | ||||
|
|
81 | IF counter_delta_f0 = UNSIGNED(delta_f2_f1) THEN | |||
|
|
82 | start_snapshot_f1 <= '1'; | |||
|
|
83 | ELSE | |||
|
|
84 | start_snapshot_f1 <= '0'; | |||
|
|
85 | END IF; | |||
|
|
86 | ||||
|
|
87 | IF counter_delta_f0 = 1 THEN --UNSIGNED(delta_f2_f0) THEN | |||
|
|
88 | start_snapshot_f0 <= '1'; | |||
|
|
89 | ELSE | |||
|
|
90 | start_snapshot_f0 <= '0'; | |||
|
|
91 | END IF; | |||
|
|
92 | ||||
|
|
93 | IF counter_delta_snapshot = UNSIGNED(delta_snapshot) | |||
|
|
94 | AND start_snapshot_f2_temp = '0' | |||
|
|
95 | THEN -- | |||
|
|
96 | start_snapshot_fothers_temp <= '1'; | |||
|
|
97 | ELSIF counter_delta_f0 > 0 THEN | |||
|
|
98 | start_snapshot_fothers_temp <= '0'; | |||
|
|
99 | END IF; | |||
|
|
100 | ||||
|
|
101 | ||||
|
|
102 | ------------------------------------------------------------------------- | |||
|
|
103 | IF (start_snapshot_fothers_temp = '1' OR (counter_delta_snapshot = UNSIGNED(delta_snapshot) AND start_snapshot_f2_temp = '0')) AND data_f2_in_valid = '1' THEN | |||
|
|
104 | --counter_delta_snapshot = UNSIGNED(delta_snapshot) AND start_snapshot_f2_temp = '0' THEN -- | |||
|
|
105 | --counter_delta_snapshot = UNSIGNED(delta_snapshot) THEN | |||
|
|
106 | counter_delta_f0 <= to_integer(UNSIGNED(delta_f2_f0)); --0; | |||
|
|
107 | ELSE | |||
|
|
108 | IF (( counter_delta_f0 > 0 ) AND ( data_f0_in_valid = '1' )) THEN --<= UNSIGNED(delta_f2_f0) THEN | |||
|
|
109 | counter_delta_f0 <= counter_delta_f0 - 1;--counter_delta_f0 + 1; | |||
|
|
110 | END IF; | |||
|
|
111 | END IF; | |||
|
|
112 | ------------------------------------------------------------------------- | |||
|
|
113 | END IF; | |||
|
|
114 | END PROCESS; | |||
|
|
115 | ||||
|
|
116 | END beh; | |||
| @@ -0,0 +1,88 | |||||
|
|
1 | ------------------------------------------------------------------------------ | |||
|
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
|
3 | -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS | |||
|
|
4 | -- | |||
|
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
|
8 | -- (at your option) any later version. | |||
|
|
9 | -- | |||
|
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
|
13 | -- GNU General Public License for more details. | |||
|
|
14 | -- | |||
|
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
|
16 | -- along with this program; if not, write to the Free Software | |||
|
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
|
18 | ------------------------------------------------------------------------------ | |||
|
|
19 | -- Author : Jean-christophe PELLION | |||
|
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |||
|
|
21 | ------------------------------------------------------------------------------ | |||
|
|
22 | LIBRARY IEEE; | |||
|
|
23 | USE IEEE.std_logic_1164.ALL; | |||
|
|
24 | USE IEEE.numeric_std.ALL; | |||
|
|
25 | ||||
|
|
26 | LIBRARY lpp; | |||
|
|
27 | USE lpp.lpp_waveform_pkg.ALL; | |||
|
|
28 | ||||
|
|
29 | ENTITY lpp_waveform_valid_ack IS | |||
|
|
30 | PORT( | |||
|
|
31 | clk : IN STD_LOGIC; | |||
|
|
32 | rstn : IN STD_LOGIC; | |||
|
|
33 | ||||
|
|
34 | data_valid_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
35 | data_valid_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
36 | error_valid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) | |||
|
|
37 | ); | |||
|
|
38 | END ENTITY; | |||
|
|
39 | ||||
|
|
40 | ||||
|
|
41 | ARCHITECTURE ar_lpp_waveform_valid_ack OF lpp_waveform_valid_ack IS | |||
|
|
42 | ||||
|
|
43 | SIGNAL data_valid_temp : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
44 | ||||
|
|
45 | BEGIN | |||
|
|
46 | ||||
|
|
47 | all_input: FOR I IN 3 DOWNTO 0 GENERATE | |||
|
|
48 | ||||
|
|
49 | PROCESS (clk, rstn) | |||
|
|
50 | BEGIN | |||
|
|
51 | IF rstn = '0' THEN | |||
|
|
52 | data_valid_temp(I) <= '0'; | |||
|
|
53 | ELSIF clk'event AND clk = '1' THEN | |||
|
|
54 | data_valid_temp(I) <= data_valid_in(I); | |||
|
|
55 | data_valid_out(I) <= data_valid_in(I) AND ; | |||
|
|
56 | ||||
|
|
57 | END IF; | |||
|
|
58 | END PROCESS; | |||
|
|
59 | ||||
|
|
60 | END GENERATE all_input; | |||
|
|
61 | ||||
|
|
62 | END ARCHITECTURE; | |||
|
|
63 | ||||
|
|
64 | ||||
|
|
65 | ||||
|
|
66 | ||||
|
|
67 | ||||
|
|
68 | ||||
|
|
69 | ||||
|
|
70 | ||||
|
|
71 | ||||
|
|
72 | ||||
|
|
73 | ||||
|
|
74 | ||||
|
|
75 | ||||
|
|
76 | ||||
|
|
77 | ||||
|
|
78 | ||||
|
|
79 | ||||
|
|
80 | ||||
|
|
81 | ||||
|
|
82 | ||||
|
|
83 | ||||
|
|
84 | ||||
|
|
85 | ||||
|
|
86 | ||||
|
|
87 | ||||
|
|
88 | ||||
| @@ -0,0 +1,9 | |||||
|
|
1 | lpp_waveform_pkg.vhd | |||
|
|
2 | lpp_waveform.vhd | |||
|
|
3 | lpp_waveform_snapshot_controler.vhd | |||
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4 | lpp_waveform_snapshot.vhd | |||
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5 | lpp_waveform_burst.vhd | |||
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6 | lpp_waveform_dma.vhd | |||
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7 | lpp_waveform_dma_send_Nword.vhd | |||
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8 | lpp_waveform_dma_selectaddress.vhd | |||
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9 | lpp_waveform_dma_genvalid.vhd | |||
| This diff has been collapsed as it changes many lines, (536 lines changed) Show them Hide them | |||||
| @@ -1,188 +1,348 | |||||
| 1 | LIBRARY ieee; |
|
1 | LIBRARY ieee; | |
| 2 | USE ieee.std_logic_1164.ALL; |
|
2 | USE ieee.std_logic_1164.ALL; | |
| 3 | LIBRARY lpp; |
|
3 | ||
| 4 | USE lpp.lpp_ad_conv.ALL; |
|
4 | LIBRARY lpp; | |
| 5 |
|
5 | USE lpp.lpp_ad_conv.ALL; | ||
| 6 | ------------------------------------------------------------------------------- |
|
6 | USE lpp.lpp_top_lfr_pkg.ALL; | |
| 7 |
|
7 | USE lpp.lpp_waveform_pkg.ALL; | ||
| 8 | ENTITY TB_Data_Acquisition IS |
|
8 | ||
| 9 |
|
9 | LIBRARY grlib; | ||
| 10 | END TB_Data_Acquisition; |
|
10 | USE grlib.amba.ALL; | |
| 11 |
|
11 | USE grlib.stdlib.ALL; | ||
| 12 | ------------------------------------------------------------------------------- |
|
12 | USE grlib.devices.ALL; | |
| 13 |
|
13 | USE GRLIB.DMA2AHB_Package.ALL; | ||
| 14 | ARCHITECTURE tb OF TB_Data_Acquisition IS |
|
14 | ||
| 15 |
|
15 | LIBRARY techmap; | ||
| 16 | COMPONENT TestModule_ADS7886 |
|
16 | USE techmap.gencomp.ALL; | |
| 17 | GENERIC ( |
|
17 | ||
| 18 | freq : INTEGER; |
|
18 | ------------------------------------------------------------------------------- | |
| 19 | amplitude : INTEGER; |
|
19 | ||
| 20 | impulsion : INTEGER); |
|
20 | ENTITY TB_Data_Acquisition IS | |
| 21 | PORT ( |
|
21 | ||
| 22 | cnv_run : IN STD_LOGIC; |
|
22 | END TB_Data_Acquisition; | |
| 23 | cnv : IN STD_LOGIC; |
|
23 | ||
| 24 | sck : IN STD_LOGIC; |
|
24 | ------------------------------------------------------------------------------- | |
| 25 | sdo : OUT STD_LOGIC); |
|
25 | ||
| 26 | END COMPONENT; |
|
26 | ARCHITECTURE tb OF TB_Data_Acquisition IS | |
| 27 |
|
27 | |||
| 28 | COMPONENT Top_Data_Acquisition |
|
28 | COMPONENT TestModule_ADS7886 | |
| 29 |
|
|
29 | GENERIC ( | |
| 30 | cnv_run : IN STD_LOGIC; |
|
30 | freq : INTEGER; | |
| 31 | cnv : OUT STD_LOGIC; |
|
31 | amplitude : INTEGER; | |
| 32 | sck : OUT STD_LOGIC; |
|
32 | impulsion : INTEGER); | |
| 33 | sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
33 | PORT ( | |
| 34 |
cnv_ |
|
34 | cnv_run : IN STD_LOGIC; | |
| 35 |
cnv |
|
35 | cnv : IN STD_LOGIC; | |
| 36 |
c |
|
36 | sck : IN STD_LOGIC; | |
| 37 |
|
|
37 | sdo : OUT STD_LOGIC); | |
| 38 | -- |
|
38 | END COMPONENT; | |
| 39 | sample_f0_0_ren : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
39 | ||
| 40 | sample_f0_0_rdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); |
|
40 | --COMPONENT Top_Data_Acquisition | |
| 41 | sample_f0_0_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
41 | -- GENERIC ( | |
| 42 | sample_f0_0_empty : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
42 | -- hindex : INTEGER; | |
| 43 | -- |
|
43 | -- nb_burst_available_size : INTEGER := 11; | |
| 44 | sample_f0_1_ren : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
44 | -- nb_snapshot_param_size : INTEGER := 11; | |
| 45 | sample_f0_1_rdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); |
|
45 | -- delta_snapshot_size : INTEGER := 16; | |
| 46 | sample_f0_1_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
46 | -- delta_f2_f0_size : INTEGER := 10; | |
| 47 | sample_f0_1_empty : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
47 | -- delta_f2_f1_size : INTEGER := 10; | |
| 48 | -- |
|
48 | -- tech : integer); | |
| 49 | sample_f1_ren : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
49 | -- PORT ( | |
| 50 | sample_f1_rdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); |
|
50 | -- cnv_run : IN STD_LOGIC; | |
| 51 | sample_f1_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
51 | -- cnv : OUT STD_LOGIC; | |
| 52 | sample_f1_empty : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
52 | -- sck : OUT STD_LOGIC; | |
| 53 | -- |
|
53 | -- sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |
| 54 | sample_f3_ren : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
54 | -- cnv_clk : IN STD_LOGIC; | |
| 55 | sample_f3_rdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); |
|
55 | -- cnv_rstn : IN STD_LOGIC; | |
| 56 | sample_f3_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
56 | -- clk : IN STD_LOGIC; | |
| 57 | sample_f3_empty : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)); |
|
57 | -- rstn : IN STD_LOGIC; | |
| 58 | END COMPONENT; |
|
58 | -- sample_f0_wen : out STD_LOGIC_VECTOR(5 DOWNTO 0); | |
| 59 |
|
59 | -- sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | ||
| 60 | -- component ports |
|
60 | -- sample_f1_wen : out STD_LOGIC_VECTOR(5 DOWNTO 0); | |
| 61 | SIGNAL cnv_rstn : STD_LOGIC; |
|
61 | -- sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
| 62 | SIGNAL cnv : STD_LOGIC; |
|
62 | -- sample_f2_wen : out STD_LOGIC_VECTOR(5 DOWNTO 0); | |
| 63 | SIGNAL rstn : STD_LOGIC; |
|
63 | -- sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
| 64 | SIGNAL sck : STD_LOGIC; |
|
64 | -- sample_f3_wen : out STD_LOGIC_VECTOR(5 DOWNTO 0); | |
| 65 |
|
|
65 | -- sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
| 66 | SIGNAL run_cnv : STD_LOGIC; |
|
66 | -- AHB_Master_In : IN AHB_Mst_In_Type; | |
| 67 |
|
67 | -- AHB_Master_Out : OUT AHB_Mst_Out_Type; | ||
| 68 |
|
68 | -- coarse_time_0 : IN STD_LOGIC; | ||
| 69 | -- clock |
|
69 | -- data_shaping_SP0 : IN STD_LOGIC; | |
| 70 | signal Clk : STD_LOGIC := '1'; |
|
70 | -- data_shaping_SP1 : IN STD_LOGIC; | |
| 71 | SIGNAL cnv_clk : STD_LOGIC := '1'; |
|
71 | -- data_shaping_R0 : IN STD_LOGIC; | |
| 72 |
|
72 | -- data_shaping_R1 : IN STD_LOGIC; | ||
| 73 | ----------------------------------------------------------------------------- |
|
73 | -- delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); | |
| 74 | SIGNAL sample_f0_0_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
74 | -- delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); | |
| 75 | SIGNAL sample_f0_0_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); |
|
75 | -- delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); | |
| 76 | SIGNAL sample_f0_0_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
76 | -- enable_f0 : IN STD_LOGIC; | |
| 77 | SIGNAL sample_f0_0_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
77 | -- enable_f1 : IN STD_LOGIC; | |
| 78 | ----------------------------------------------------------------------------- |
|
78 | -- enable_f2 : IN STD_LOGIC; | |
| 79 | SIGNAL sample_f0_1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
79 | -- enable_f3 : IN STD_LOGIC; | |
| 80 | SIGNAL sample_f0_1_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); |
|
80 | -- burst_f0 : IN STD_LOGIC; | |
| 81 | SIGNAL sample_f0_1_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
81 | -- burst_f1 : IN STD_LOGIC; | |
| 82 | SIGNAL sample_f0_1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
82 | -- burst_f2 : IN STD_LOGIC; | |
| 83 | ----------------------------------------------------------------------------- |
|
83 | -- nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); | |
| 84 | SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
84 | -- nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
| 85 |
|
|
85 | -- status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
| 86 |
|
|
86 | -- status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
| 87 |
|
|
87 | -- status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
| 88 | ----------------------------------------------------------------------------- |
|
88 | -- status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
| 89 |
|
|
89 | -- addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 90 |
|
|
90 | -- addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 91 |
|
|
91 | -- addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 92 |
|
|
92 | -- addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); | |
| 93 |
|
93 | --END COMPONENT; | ||
| 94 |
|
94 | |||
| 95 | BEGIN -- tb |
|
95 | -- component ports | |
| 96 |
|
96 | SIGNAL cnv_rstn : STD_LOGIC; | ||
| 97 | MODULE_ADS7886: FOR I IN 0 TO 6 GENERATE |
|
97 | SIGNAL cnv : STD_LOGIC; | |
| 98 | TestModule_ADS7886_u: TestModule_ADS7886 |
|
98 | SIGNAL rstn : STD_LOGIC; | |
| 99 | GENERIC MAP ( |
|
99 | SIGNAL sck : STD_LOGIC; | |
| 100 | freq => 24*(I+1), |
|
100 | SIGNAL sdo : STD_LOGIC_VECTOR(7 DOWNTO 0); | |
| 101 | amplitude => 30000/(I+1), |
|
101 | SIGNAL run_cnv : STD_LOGIC; | |
| 102 | impulsion => 0) |
|
102 | ||
| 103 | PORT MAP ( |
|
103 | ||
| 104 | cnv_run => run_cnv, |
|
104 | -- clock | |
| 105 | cnv => cnv, |
|
105 | signal Clk : STD_LOGIC := '1'; | |
| 106 | sck => sck, |
|
106 | SIGNAL cnv_clk : STD_LOGIC := '1'; | |
| 107 | sdo => sdo(I)); |
|
107 | ||
| 108 | END GENERATE MODULE_ADS7886; |
|
108 | ----------------------------------------------------------------------------- | |
| 109 |
|
109 | SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); | ||
| 110 | TestModule_ADS7886_u: TestModule_ADS7886 |
|
110 | SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
| 111 | GENERIC MAP ( |
|
111 | ----------------------------------------------------------------------------- | |
| 112 | freq => 0, |
|
112 | SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); | |
| 113 | amplitude => 30000, |
|
113 | SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
| 114 | impulsion => 1) |
|
114 | ----------------------------------------------------------------------------- | |
| 115 | PORT MAP ( |
|
115 | SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); | |
| 116 | cnv_run => run_cnv, |
|
116 | SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
| 117 | cnv => cnv, |
|
117 | ----------------------------------------------------------------------------- | |
| 118 | sck => sck, |
|
118 | SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); | |
| 119 | sdo => sdo(7)); |
|
119 | SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
| 120 |
|
120 | |||
| 121 |
|
121 | ----------------------------------------------------------------------------- | ||
| 122 | -- clock generation |
|
122 | CONSTANT nb_burst_available_size : INTEGER := 11; | |
| 123 | Clk <= not Clk after 20 ns; -- 25 Mhz |
|
123 | CONSTANT nb_snapshot_param_size : INTEGER := 11; | |
| 124 | cnv_clk <= not cnv_clk after 10173 ps; -- 49.152 MHz |
|
124 | CONSTANT delta_snapshot_size : INTEGER := 16; | |
| 125 |
|
125 | CONSTANT delta_f2_f0_size : INTEGER := 10; | ||
| 126 | -- waveform generation |
|
126 | CONSTANT delta_f2_f1_size : INTEGER := 10; | |
| 127 | WaveGen_Proc: process |
|
127 | ||
| 128 | begin |
|
128 | SIGNAL AHB_Master_In : AHB_Mst_In_Type; | |
| 129 | -- insert signal assignments here |
|
129 | SIGNAL AHB_Master_Out : AHB_Mst_Out_Type; | |
| 130 | wait until Clk = '1'; |
|
130 | ||
| 131 | rstn <= '0'; |
|
131 | SIGNAL coarse_time_0 : STD_LOGIC; | |
| 132 | cnv_rstn <= '0'; |
|
132 | SIGNAL coarse_time_0_t : STD_LOGIC := '0'; | |
| 133 | run_cnv <= '0'; |
|
133 | SIGNAL coarse_time_0_t2 : STD_LOGIC := '0'; | |
| 134 | wait until Clk = '1'; |
|
134 | ||
| 135 | wait until Clk = '1'; |
|
135 | SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); | |
| 136 | wait until Clk = '1'; |
|
136 | SIGNAL delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); | |
| 137 | rstn <= '1'; |
|
137 | SIGNAL delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); | |
| 138 | cnv_rstn <= '1'; |
|
138 | ||
| 139 | wait until Clk = '1'; |
|
139 | SIGNAL enable_f0 : STD_LOGIC; | |
| 140 | wait until Clk = '1'; |
|
140 | SIGNAL enable_f1 : STD_LOGIC; | |
| 141 | wait until Clk = '1'; |
|
141 | SIGNAL enable_f2 : STD_LOGIC; | |
| 142 | wait until Clk = '1'; |
|
142 | SIGNAL enable_f3 : STD_LOGIC; | |
| 143 | wait until Clk = '1'; |
|
143 | ||
| 144 | wait until Clk = '1'; |
|
144 | SIGNAL burst_f0 : STD_LOGIC; | |
| 145 | run_cnv <= '1'; |
|
145 | SIGNAL burst_f1 : STD_LOGIC; | |
| 146 | wait; |
|
146 | SIGNAL burst_f2 : STD_LOGIC; | |
| 147 |
|
147 | |||
| 148 | end process WaveGen_Proc; |
|
148 | SIGNAL nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); | |
| 149 |
|
149 | SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | ||
| 150 | ----------------------------------------------------------------------------- |
|
150 | ||
| 151 |
|
151 | SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); | ||
| 152 | Top_Data_Acquisition_1: Top_Data_Acquisition |
|
152 | SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
| 153 | PORT MAP ( |
|
153 | SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
| 154 | cnv_run => run_cnv, |
|
154 | SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
| 155 | cnv => cnv, |
|
155 | ||
| 156 | sck => sck, |
|
156 | SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 157 | sdo => sdo, |
|
157 | SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 158 | cnv_clk => cnv_clk, |
|
158 | SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 159 | cnv_rstn => cnv_rstn, |
|
159 | SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 160 | clk => clk, |
|
160 | ||
| 161 | rstn => rstn, |
|
161 | ||
| 162 | -- |
|
162 | SIGNAL data_shaping_SP0 : STD_LOGIC; | |
| 163 | sample_f0_0_ren => sample_f0_0_ren, |
|
163 | SIGNAL data_shaping_SP1 : STD_LOGIC; | |
| 164 | sample_f0_0_rdata => sample_f0_0_rdata, |
|
164 | SIGNAL data_shaping_R0 : STD_LOGIC; | |
| 165 | sample_f0_0_full => sample_f0_0_full, |
|
165 | SIGNAL data_shaping_R1 : STD_LOGIC; | |
| 166 | sample_f0_0_empty => sample_f0_0_empty, |
|
166 | BEGIN -- tb | |
| 167 | -- |
|
167 | ||
| 168 | sample_f0_1_ren => sample_f0_1_ren, |
|
168 | MODULE_ADS7886: FOR I IN 0 TO 6 GENERATE | |
| 169 | sample_f0_1_rdata => sample_f0_1_rdata, |
|
169 | TestModule_ADS7886_u: TestModule_ADS7886 | |
| 170 | sample_f0_1_full => sample_f0_1_full, |
|
170 | GENERIC MAP ( | |
| 171 | sample_f0_1_empty => sample_f0_1_empty, |
|
171 | freq => 24*(I+1), | |
| 172 | -- |
|
172 | amplitude => 30000/(I+1), | |
| 173 | sample_f1_ren => sample_f1_ren, |
|
173 | impulsion => 0) | |
| 174 | sample_f1_rdata => sample_f1_rdata, |
|
174 | PORT MAP ( | |
| 175 | sample_f1_full => sample_f1_full, |
|
175 | cnv_run => run_cnv, | |
| 176 | sample_f1_empty => sample_f1_empty, |
|
176 | cnv => cnv, | |
| 177 | -- |
|
177 | sck => sck, | |
| 178 | sample_f3_ren => sample_f3_ren, |
|
178 | sdo => sdo(I)); | |
| 179 | sample_f3_rdata => sample_f3_rdata, |
|
179 | END GENERATE MODULE_ADS7886; | |
| 180 | sample_f3_full => sample_f3_full, |
|
180 | ||
| 181 | sample_f3_empty => sample_f3_empty |
|
181 | TestModule_ADS7886_u: TestModule_ADS7886 | |
| 182 | ); |
|
182 | GENERIC MAP ( | |
| 183 | sample_f0_0_ren <= (OTHERS => '1'); |
|
183 | freq => 0, | |
| 184 | sample_f0_1_ren <= (OTHERS => '1'); |
|
184 | amplitude => 30000, | |
| 185 | sample_f1_ren <= (OTHERS => '1'); |
|
185 | impulsion => 1) | |
| 186 | sample_f3_ren <= (OTHERS => '1'); |
|
186 | PORT MAP ( | |
| 187 |
|
187 | cnv_run => run_cnv, | ||
| 188 | END tb; |
|
188 | cnv => cnv, | |
|
|
189 | sck => sck, | |||
|
|
190 | sdo => sdo(7)); | |||
|
|
191 | ||||
|
|
192 | ||||
|
|
193 | -- clock generation | |||
|
|
194 | Clk <= not Clk after 20 ns; -- 25 Mhz | |||
|
|
195 | cnv_clk <= not cnv_clk after 10173 ps; -- 49.152 MHz | |||
|
|
196 | ||||
|
|
197 | -- waveform generation | |||
|
|
198 | WaveGen_Proc: process | |||
|
|
199 | begin | |||
|
|
200 | -- insert signal assignments here | |||
|
|
201 | wait until Clk = '1'; | |||
|
|
202 | rstn <= '0'; | |||
|
|
203 | cnv_rstn <= '0'; | |||
|
|
204 | run_cnv <= '0'; | |||
|
|
205 | wait until Clk = '1'; | |||
|
|
206 | wait until Clk = '1'; | |||
|
|
207 | wait until Clk = '1'; | |||
|
|
208 | rstn <= '1'; | |||
|
|
209 | cnv_rstn <= '1'; | |||
|
|
210 | wait until Clk = '1'; | |||
|
|
211 | wait until Clk = '1'; | |||
|
|
212 | wait until Clk = '1'; | |||
|
|
213 | wait until Clk = '1'; | |||
|
|
214 | wait until Clk = '1'; | |||
|
|
215 | wait until Clk = '1'; | |||
|
|
216 | run_cnv <= '1'; | |||
|
|
217 | wait; | |||
|
|
218 | ||||
|
|
219 | end process WaveGen_Proc; | |||
|
|
220 | ||||
|
|
221 | ----------------------------------------------------------------------------- | |||
|
|
222 | ||||
|
|
223 | Top_Data_Acquisition_2: lpp_top_lfr_wf_picker_ip | |||
|
|
224 | GENERIC MAP ( | |||
|
|
225 | hindex => 2, | |||
|
|
226 | nb_burst_available_size => nb_burst_available_size, | |||
|
|
227 | nb_snapshot_param_size => nb_snapshot_param_size, | |||
|
|
228 | delta_snapshot_size =>16, | |||
|
|
229 | delta_f2_f0_size =>10, | |||
|
|
230 | delta_f2_f1_size =>10, | |||
|
|
231 | tech => 0) | |||
|
|
232 | PORT MAP ( | |||
|
|
233 | cnv_run => run_cnv, | |||
|
|
234 | cnv => cnv, | |||
|
|
235 | sck => sck, | |||
|
|
236 | sdo => sdo, | |||
|
|
237 | cnv_clk => cnv_clk, | |||
|
|
238 | cnv_rstn => cnv_rstn, | |||
|
|
239 | clk => clk, | |||
|
|
240 | rstn => rstn, | |||
|
|
241 | sample_f0_wen => sample_f0_wen, | |||
|
|
242 | sample_f0_wdata => sample_f0_wdata, | |||
|
|
243 | sample_f1_wen => sample_f1_wen, | |||
|
|
244 | sample_f1_wdata => sample_f1_wdata, | |||
|
|
245 | sample_f2_wen => sample_f2_wen, | |||
|
|
246 | sample_f2_wdata => sample_f2_wdata, | |||
|
|
247 | sample_f3_wen => sample_f3_wen, | |||
|
|
248 | sample_f3_wdata => sample_f3_wdata, | |||
|
|
249 | AHB_Master_In => AHB_Master_In, | |||
|
|
250 | AHB_Master_Out => AHB_Master_Out, | |||
|
|
251 | coarse_time_0 => coarse_time_0, | |||
|
|
252 | data_shaping_SP0 => data_shaping_SP0, | |||
|
|
253 | data_shaping_SP1 => data_shaping_SP1, | |||
|
|
254 | data_shaping_R0 => data_shaping_R0, | |||
|
|
255 | data_shaping_R1 => data_shaping_R1, | |||
|
|
256 | delta_snapshot => delta_snapshot, | |||
|
|
257 | delta_f2_f1 => delta_f2_f1, | |||
|
|
258 | delta_f2_f0 => delta_f2_f0, | |||
|
|
259 | enable_f0 => enable_f0, | |||
|
|
260 | enable_f1 => enable_f1, | |||
|
|
261 | enable_f2 => enable_f2, | |||
|
|
262 | enable_f3 => enable_f3, | |||
|
|
263 | burst_f0 => burst_f0, | |||
|
|
264 | burst_f1 => burst_f1, | |||
|
|
265 | burst_f2 => burst_f2, | |||
|
|
266 | nb_burst_available => nb_burst_available, | |||
|
|
267 | nb_snapshot_param => nb_snapshot_param, | |||
|
|
268 | status_full => status_full, | |||
|
|
269 | status_full_ack => status_full_ack, | |||
|
|
270 | status_full_err => status_full_err, | |||
|
|
271 | status_new_err => status_new_err, | |||
|
|
272 | addr_data_f0 => addr_data_f0, | |||
|
|
273 | addr_data_f1 => addr_data_f1, | |||
|
|
274 | addr_data_f2 => addr_data_f2, | |||
|
|
275 | addr_data_f3 => addr_data_f3); | |||
|
|
276 | ||||
|
|
277 | PROCESS (clk, rstn) | |||
|
|
278 | BEGIN -- PROCESS | |||
|
|
279 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
|
|
280 | enable_f0 <= '0'; | |||
|
|
281 | enable_f1 <= '0'; | |||
|
|
282 | enable_f2 <= '0'; | |||
|
|
283 | enable_f3 <= '0'; | |||
|
|
284 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |||
|
|
285 | enable_f0 <= '1'; --TODO test | |||
|
|
286 | enable_f1 <= '1'; | |||
|
|
287 | enable_f2 <= '1'; | |||
|
|
288 | enable_f3 <= '1'; | |||
|
|
289 | END IF; | |||
|
|
290 | END PROCESS; | |||
|
|
291 | ||||
|
|
292 | burst_f0 <= '0'; --TODO test | |||
|
|
293 | burst_f1 <= '0'; --TODO test | |||
|
|
294 | burst_f2 <= '0'; | |||
|
|
295 | ||||
|
|
296 | data_shaping_SP0 <= '0'; | |||
|
|
297 | data_shaping_SP1 <= '0'; | |||
|
|
298 | data_shaping_R0 <= '1'; | |||
|
|
299 | data_shaping_R1 <= '1'; | |||
|
|
300 | ||||
|
|
301 | delta_snapshot <= "0000000000000001"; | |||
|
|
302 | --nb_snapshot_param <= "00000001110"; -- 14+1 = 15 | |||
|
|
303 | --delta_f2_f0 <= "1010011001";--665 = 14/2*96 -14/2 | |||
|
|
304 | --delta_f2_f1 <= "0000100110";-- 38 = 14/2*6 - 14/4 | |||
|
|
305 | ||||
|
|
306 | -- A redefinir car ca ne tombe pas correctement ... ??? | |||
|
|
307 | nb_burst_available <= "00000110010"; -- 3*16 + 2 = 34 | |||
|
|
308 | nb_snapshot_param <= "00000001111"; -- x+1 = 16 | |||
|
|
309 | delta_f2_f0 <= "1011001000";--712 = x/2*96 -x/2 | |||
|
|
310 | delta_f2_f1 <= "0000101001";-- 41 = x/2*6 - x/4 | |||
|
|
311 | ||||
|
|
312 | addr_data_f0 <= "00000000000000000000000000000000"; | |||
|
|
313 | addr_data_f1 <= "00010000000000000000000000000000"; | |||
|
|
314 | addr_data_f2 <= "00100000000000000000000000000000"; | |||
|
|
315 | addr_data_f3 <= "00110000000000000000000000000000"; | |||
|
|
316 | ||||
|
|
317 | PROCESS (clk, rstn) | |||
|
|
318 | BEGIN -- PROCESS | |||
|
|
319 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
|
|
320 | status_full_ack <= (OTHERS => '0'); | |||
|
|
321 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |||
|
|
322 | status_full_ack <= status_full; | |||
|
|
323 | END IF; | |||
|
|
324 | END PROCESS; | |||
|
|
325 | ||||
|
|
326 | ||||
|
|
327 | coarse_time_0_t <= not coarse_time_0_t after 50 ms; | |||
|
|
328 | ||||
|
|
329 | PROCESS (clk, rstn) | |||
|
|
330 | BEGIN -- PROCESS | |||
|
|
331 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
|
|
332 | coarse_time_0_t2 <= '0'; | |||
|
|
333 | coarse_time_0 <= '0'; | |||
|
|
334 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |||
|
|
335 | coarse_time_0_t2 <= coarse_time_0_t; | |||
|
|
336 | coarse_time_0 <= coarse_time_0_t AND (NOT coarse_time_0_t2); | |||
|
|
337 | END IF; | |||
|
|
338 | END PROCESS; | |||
|
|
339 | ||||
|
|
340 | ||||
|
|
341 | AHB_Master_In.HGRANT(2) <= '1'; | |||
|
|
342 | AHB_Master_In.HREADY <= '1'; | |||
|
|
343 | ||||
|
|
344 | ||||
|
|
345 | AHB_Master_In.HRESP <= HRESP_OKAY; | |||
|
|
346 | ||||
|
|
347 | ||||
|
|
348 | END tb; | |||
| This diff has been collapsed as it changes many lines, (597 lines changed) Show them Hide them | |||||
| @@ -1,50 +1,94 | |||||
| 1 | LIBRARY ieee; |
|
1 | LIBRARY ieee; | |
| 2 | USE ieee.std_logic_1164.ALL; |
|
2 | USE ieee.std_logic_1164.ALL; | |
|
|
3 | USE ieee.numeric_std.ALL; | |||
|
|
4 | ||||
| 3 | LIBRARY lpp; |
|
5 | LIBRARY lpp; | |
| 4 | USE lpp.lpp_ad_conv.ALL; |
|
6 | USE lpp.lpp_ad_conv.ALL; | |
| 5 | USE lpp.iir_filter.ALL; |
|
7 | USE lpp.iir_filter.ALL; | |
| 6 | USE lpp.FILTERcfg.ALL; |
|
8 | USE lpp.FILTERcfg.ALL; | |
| 7 | USE lpp.lpp_memory.ALL; |
|
9 | USE lpp.lpp_memory.ALL; | |
|
|
10 | USE lpp.lpp_waveform_pkg.ALL; | |||
|
|
11 | ||||
| 8 | LIBRARY techmap; |
|
12 | LIBRARY techmap; | |
| 9 | USE techmap.gencomp.ALL; |
|
13 | USE techmap.gencomp.ALL; | |
| 10 | --USE lpp.ALL; |
|
14 | ||
|
|
15 | LIBRARY grlib; | |||
|
|
16 | USE grlib.amba.ALL; | |||
|
|
17 | USE grlib.stdlib.ALL; | |||
|
|
18 | USE grlib.devices.ALL; | |||
|
|
19 | USE GRLIB.DMA2AHB_Package.ALL; | |||
| 11 |
|
20 | |||
| 12 | ENTITY Top_Data_Acquisition IS |
|
21 | ENTITY Top_Data_Acquisition IS | |
| 13 | generic( |
|
22 | GENERIC( | |
| 14 | tech : integer := 0 |
|
23 | hindex : INTEGER := 2; | |
|
|
24 | nb_burst_available_size : INTEGER := 11; | |||
|
|
25 | nb_snapshot_param_size : INTEGER := 11; | |||
|
|
26 | delta_snapshot_size : INTEGER := 16; | |||
|
|
27 | delta_f2_f0_size : INTEGER := 10; | |||
|
|
28 | delta_f2_f1_size : INTEGER := 10; | |||
|
|
29 | tech : INTEGER := 0 | |||
| 15 | ); |
|
30 | ); | |
| 16 | PORT ( |
|
31 | PORT ( | |
| 17 | -- ADS7886 |
|
32 | -- ADS7886 | |
| 18 | cnv_run : IN STD_LOGIC; |
|
33 | cnv_run : IN STD_LOGIC; | |
| 19 | cnv : OUT STD_LOGIC; |
|
34 | cnv : OUT STD_LOGIC; | |
| 20 | sck : OUT STD_LOGIC; |
|
35 | sck : OUT STD_LOGIC; | |
| 21 | sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
36 | sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |
|
|
37 | -- | |||
|
|
38 | cnv_clk : IN STD_LOGIC; | |||
|
|
39 | cnv_rstn : IN STD_LOGIC; | |||
| 22 | -- |
|
40 | -- | |
| 23 |
|
|
41 | clk : IN STD_LOGIC; | |
| 24 |
|
|
42 | rstn : IN STD_LOGIC; | |
|
|
43 | -- | |||
|
|
44 | sample_f0_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); | |||
|
|
45 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |||
| 25 | -- |
|
46 | -- | |
| 26 | clk : IN STD_LOGIC; |
|
47 | sample_f1_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); | |
| 27 | rstn : IN STD_LOGIC; |
|
48 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
|
|
49 | -- | |||
|
|
50 | sample_f2_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); | |||
|
|
51 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |||
| 28 | -- |
|
52 | -- | |
| 29 |
sample_f |
|
53 | sample_f3_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); | |
| 30 |
sample_f |
|
54 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
| 31 | sample_f0_0_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
55 | ||
| 32 | sample_f0_0_empty : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
56 | -- AMBA AHB Master Interface | |
| 33 | -- |
|
57 | AHB_Master_In : IN AHB_Mst_In_Type; | |
| 34 | sample_f0_1_ren : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
58 | AHB_Master_Out : OUT AHB_Mst_Out_Type; | |
| 35 | sample_f0_1_rdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); |
|
59 | ||
| 36 | sample_f0_1_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
60 | coarse_time_0 : IN STD_LOGIC; | |
| 37 | sample_f0_1_empty : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
61 | ||
| 38 | -- |
|
62 | --config | |
| 39 | sample_f1_ren : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
63 | data_shaping_SP0 : IN STD_LOGIC; | |
| 40 | sample_f1_rdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); |
|
64 | data_shaping_SP1 : IN STD_LOGIC; | |
| 41 | sample_f1_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
65 | data_shaping_R0 : IN STD_LOGIC; | |
| 42 | sample_f1_empty : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
66 | data_shaping_R1 : IN STD_LOGIC; | |
| 43 | -- |
|
67 | ||
| 44 |
|
|
68 | delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); | |
| 45 |
|
|
69 | delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); | |
| 46 |
|
|
70 | delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); | |
| 47 | sample_f3_empty : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) |
|
71 | ||
|
|
72 | enable_f0 : IN STD_LOGIC; | |||
|
|
73 | enable_f1 : IN STD_LOGIC; | |||
|
|
74 | enable_f2 : IN STD_LOGIC; | |||
|
|
75 | enable_f3 : IN STD_LOGIC; | |||
|
|
76 | ||||
|
|
77 | burst_f0 : IN STD_LOGIC; | |||
|
|
78 | burst_f1 : IN STD_LOGIC; | |||
|
|
79 | burst_f2 : IN STD_LOGIC; | |||
|
|
80 | ||||
|
|
81 | nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); | |||
|
|
82 | nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |||
|
|
83 | status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
84 | status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
85 | status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
86 | status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma | |||
|
|
87 | ||||
|
|
88 | addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
89 | addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
90 | addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
91 | addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) | |||
| 48 | ); |
|
92 | ); | |
| 49 | END Top_Data_Acquisition; |
|
93 | END Top_Data_Acquisition; | |
| 50 |
|
94 | |||
| @@ -79,49 +123,55 ARCHITECTURE tb OF Top_Data_Acquisition | |||||
| 79 | CONSTANT CoefPerCel : INTEGER := 5; |
|
123 | CONSTANT CoefPerCel : INTEGER := 5; | |
| 80 | CONSTANT Cels_count : INTEGER := 5; |
|
124 | CONSTANT Cels_count : INTEGER := 5; | |
| 81 |
|
125 | |||
| 82 |
SIGNAL coefs |
|
126 | SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0); | |
| 83 |
SIGNAL coefs_ |
|
127 | SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0); | |
| 84 |
SIGNAL sample_filter_in |
|
128 | SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
| 85 |
SIGNAL sample_filter_out |
|
129 | SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
| 86 | -- |
|
|||
| 87 | SIGNAL sample_filter_JC_out_val : STD_LOGIC; |
|
|||
| 88 | SIGNAL sample_filter_JC_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); |
|
|||
| 89 | -- |
|
|||
| 90 | SIGNAL sample_filter_JC_out_r_val : STD_LOGIC; |
|
|||
| 91 | SIGNAL sample_filter_JC_out_r : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); |
|
|||
| 92 | ----------------------------------------------------------------------------- |
|
|||
| 93 | SIGNAL downsampling_cnt : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
|||
| 94 | SIGNAL sample_downsampling_out_val : STD_LOGIC; |
|
|||
| 95 | SIGNAL sample_downsampling_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); |
|
|||
| 96 | -- |
|
130 | -- | |
| 97 |
SIGNAL sample_f |
|
131 | SIGNAL sample_filter_v2_out_val : STD_LOGIC; | |
| 98 |
SIGNAL sample_f |
|
132 | SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
| 99 | SIGNAL sample_f0_0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
133 | ----------------------------------------------------------------------------- | |
| 100 | SIGNAL sample_f0_1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
134 | SIGNAL sample_data_shaping_out_val : STD_LOGIC; | |
| 101 | SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); |
|
135 | SIGNAL sample_data_shaping_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
| 102 | -- |
|
136 | SIGNAL sample_data_shaping_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0); | |
| 103 | SIGNAL sample_f0_0_val : STD_LOGIC; |
|
137 | SIGNAL sample_data_shaping_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0); | |
| 104 | SIGNAL sample_f0_1_val : STD_LOGIC; |
|
138 | SIGNAL sample_data_shaping_f2_s : STD_LOGIC_VECTOR(17 DOWNTO 0); | |
| 105 | SIGNAL counter_f0 : INTEGER; |
|
139 | SIGNAL sample_data_shaping_f1_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0); | |
|
|
140 | SIGNAL sample_data_shaping_f2_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0); | |||
|
|
141 | ----------------------------------------------------------------------------- | |||
|
|
142 | SIGNAL sample_filter_v2_out_val_s : STD_LOGIC; | |||
|
|
143 | SIGNAL sample_filter_v2_out_s : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0); | |||
| 106 | ----------------------------------------------------------------------------- |
|
144 | ----------------------------------------------------------------------------- | |
| 107 |
SIGNAL sample_f |
|
145 | SIGNAL sample_f0_val : STD_LOGIC; | |
| 108 |
SIGNAL sample_f |
|
146 | SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0); | |
| 109 |
SIGNAL sample_f |
|
147 | SIGNAL sample_f0_s : samplT(5 DOWNTO 0, 15 DOWNTO 0); | |
| 110 | SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); |
|
148 | -- | |
|
|
149 | SIGNAL sample_f1_val : STD_LOGIC; | |||
|
|
150 | SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0); | |||
|
|
151 | SIGNAL sample_f1_s : samplT(5 DOWNTO 0, 15 DOWNTO 0); | |||
|
|
152 | -- | |||
|
|
153 | SIGNAL sample_f2_val : STD_LOGIC; | |||
|
|
154 | SIGNAL sample_f2 : samplT(5 DOWNTO 0, 15 DOWNTO 0); | |||
| 111 | -- |
|
155 | -- | |
| 112 |
SIGNAL sample_f |
|
156 | SIGNAL sample_f3_val : STD_LOGIC; | |
| 113 |
SIGNAL sample_f |
|
157 | SIGNAL sample_f3 : samplT(5 DOWNTO 0, 15 DOWNTO 0); | |
| 114 | -- |
|
158 | ||
| 115 | SIGNAL sample_f3_val : STD_LOGIC; |
|
159 | ----------------------------------------------------------------------------- | |
| 116 | SIGNAL sample_f3 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); |
|
160 | SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); | |
| 117 |
SIGNAL |
|
161 | SIGNAL data_f1_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); | |
| 118 | SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); |
|
162 | SIGNAL data_f2_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); | |
|
|
163 | SIGNAL data_f3_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); | |||
|
|
164 | ----------------------------------------------------------------------------- | |||
| 119 |
|
165 | |||
|
|
166 | SIGNAL sample_f0_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |||
|
|
167 | SIGNAL sample_f1_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |||
|
|
168 | SIGNAL sample_f2_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |||
|
|
169 | SIGNAL sample_f3_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |||
| 120 | BEGIN |
|
170 | BEGIN | |
| 121 |
|
171 | |||
| 122 | -- component instantiation |
|
172 | -- component instantiation | |
| 123 | ----------------------------------------------------------------------------- |
|
173 | ----------------------------------------------------------------------------- | |
| 124 |
DIGITAL_acquisition : AD |
|
174 | DIGITAL_acquisition : AD7688_drvr | |
| 125 | GENERIC MAP ( |
|
175 | GENERIC MAP ( | |
| 126 | ChanelCount => ChanelCount, |
|
176 | ChanelCount => ChanelCount, | |
| 127 | ncycle_cnv_high => ncycle_cnv_high, |
|
177 | ncycle_cnv_high => ncycle_cnv_high, | |
| @@ -159,166 +209,126 BEGIN | |||||
| 159 | sample_filter_in(i, 17) <= sample(i)(15); |
|
209 | sample_filter_in(i, 17) <= sample(i)(15); | |
| 160 | END GENERATE; |
|
210 | END GENERATE; | |
| 161 |
|
211 | |||
| 162 |
|
|
212 | coefs_v2 <= CoefsInitValCst_v2; | |
| 163 | coefs_JC <= CoefsInitValCst_v2; |
|
|||
| 164 |
|
||||
| 165 | --FILTER : IIR_CEL_CTRLR |
|
|||
| 166 | -- GENERIC MAP ( |
|
|||
| 167 | -- tech => 0, |
|
|||
| 168 | -- Sample_SZ => 18, |
|
|||
| 169 | -- ChanelsCount => ChanelCount, |
|
|||
| 170 | -- Coef_SZ => Coef_SZ, |
|
|||
| 171 | -- CoefCntPerCel => CoefCntPerCel, |
|
|||
| 172 | -- Cels_count => Cels_count, |
|
|||
| 173 | -- Mem_use => use_CEL) -- use_CEL for SIMU, use_RAM for synthesis |
|
|||
| 174 | -- PORT MAP ( |
|
|||
| 175 | -- reset => rstn, |
|
|||
| 176 | -- clk => clk, |
|
|||
| 177 | -- sample_clk => sample_val_delay, |
|
|||
| 178 | -- sample_in => sample_filter_in, |
|
|||
| 179 | -- sample_out => sample_filter_out, |
|
|||
| 180 | -- virg_pos => 7, |
|
|||
| 181 | -- GOtest => OPEN, |
|
|||
| 182 | -- coefs => coefs); |
|
|||
| 183 |
|
213 | |||
| 184 | IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 |
|
214 | IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 | |
| 185 | GENERIC MAP ( |
|
215 | GENERIC MAP ( | |
| 186 | tech => 0, |
|
216 | tech => 0, | |
| 187 |
Mem_use => use_ |
|
217 | Mem_use => use_CEL, -- use_RAM | |
| 188 | Sample_SZ => 18, |
|
218 | Sample_SZ => 18, | |
| 189 | Coef_SZ => Coef_SZ, |
|
219 | Coef_SZ => Coef_SZ, | |
| 190 |
Coef_Nb => 25, |
|
220 | Coef_Nb => 25, | |
| 191 |
Coef_sel_SZ => 5, |
|
221 | Coef_sel_SZ => 5, | |
| 192 | Cels_count => Cels_count, |
|
222 | Cels_count => Cels_count, | |
| 193 | ChanelsCount => ChanelCount) |
|
223 | ChanelsCount => ChanelCount) | |
| 194 | PORT MAP ( |
|
224 | PORT MAP ( | |
| 195 | rstn => rstn, |
|
225 | rstn => rstn, | |
| 196 | clk => clk, |
|
226 | clk => clk, | |
| 197 | virg_pos => 7, |
|
227 | virg_pos => 7, | |
| 198 |
coefs => coefs_ |
|
228 | coefs => coefs_v2, | |
| 199 | sample_in_val => sample_val_delay, |
|
229 | sample_in_val => sample_val_delay, | |
| 200 | sample_in => sample_filter_in, |
|
230 | sample_in => sample_filter_in, | |
| 201 |
sample_out_val => sample_filter_ |
|
231 | sample_out_val => sample_filter_v2_out_val, | |
| 202 |
sample_out => sample_filter_ |
|
232 | sample_out => sample_filter_v2_out); | |
| 203 |
|
233 | |||
| 204 | ----------------------------------------------------------------------------- |
|
234 | ----------------------------------------------------------------------------- | |
|
|
235 | -- DATA_SHAPING | |||
|
|
236 | ----------------------------------------------------------------------------- | |||
|
|
237 | all_data_shaping_in_loop: FOR I IN 17 DOWNTO 0 GENERATE | |||
|
|
238 | sample_data_shaping_f0_s(I) <= sample_filter_v2_out(0,I); | |||
|
|
239 | sample_data_shaping_f1_s(I) <= sample_filter_v2_out(1,I); | |||
|
|
240 | sample_data_shaping_f2_s(I) <= sample_filter_v2_out(2,I); | |||
|
|
241 | END GENERATE all_data_shaping_in_loop; | |||
|
|
242 | ||||
|
|
243 | sample_data_shaping_f1_f0_s <= sample_data_shaping_f1_s - sample_data_shaping_f0_s; | |||
|
|
244 | sample_data_shaping_f2_f1_s <= sample_data_shaping_f2_s - sample_data_shaping_f1_s; | |||
|
|
245 | ||||
| 205 | PROCESS (clk, rstn) |
|
246 | PROCESS (clk, rstn) | |
| 206 | BEGIN -- PROCESS |
|
247 | BEGIN -- PROCESS | |
| 207 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
248 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
| 208 |
sample_ |
|
249 | sample_data_shaping_out_val <= '0'; | |
| 209 | rst_all_chanel : FOR I IN ChanelCount-1 DOWNTO 0 LOOP |
|
250 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
| 210 | rst_all_bits : FOR J IN 17 DOWNTO 0 LOOP |
|
251 | sample_data_shaping_out_val <= sample_filter_v2_out_val; | |
| 211 | sample_filter_JC_out_r(I, J) <= '0'; |
|
|||
| 212 | END LOOP rst_all_bits; |
|
|||
| 213 | END LOOP rst_all_chanel; |
|
|||
| 214 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
|||
| 215 | sample_filter_JC_out_r_val <= sample_filter_JC_out_val; |
|
|||
| 216 | IF sample_filter_JC_out_val = '1' THEN |
|
|||
| 217 | sample_filter_JC_out_r <= sample_filter_JC_out; |
|
|||
| 218 | END IF; |
|
|||
| 219 | END IF; |
|
252 | END IF; | |
| 220 | END PROCESS; |
|
253 | END PROCESS; | |
| 221 |
|
254 | |||
|
|
255 | SampleLoop_data_shaping: FOR j IN 0 TO 17 GENERATE | |||
|
|
256 | PROCESS (clk, rstn) | |||
|
|
257 | BEGIN | |||
|
|
258 | IF rstn = '0' THEN | |||
|
|
259 | sample_data_shaping_out(0,j) <= '0'; | |||
|
|
260 | sample_data_shaping_out(1,j) <= '0'; | |||
|
|
261 | sample_data_shaping_out(2,j) <= '0'; | |||
|
|
262 | sample_data_shaping_out(3,j) <= '0'; | |||
|
|
263 | sample_data_shaping_out(4,j) <= '0'; | |||
|
|
264 | sample_data_shaping_out(5,j) <= '0'; | |||
|
|
265 | sample_data_shaping_out(6,j) <= '0'; | |||
|
|
266 | sample_data_shaping_out(7,j) <= '0'; | |||
|
|
267 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |||
|
|
268 | sample_data_shaping_out(0,j) <= sample_filter_v2_out(0,j); | |||
|
|
269 | IF data_shaping_SP0 = '1' THEN | |||
|
|
270 | sample_data_shaping_out(1,j) <= sample_data_shaping_f1_f0_s(j); | |||
|
|
271 | ELSE | |||
|
|
272 | sample_data_shaping_out(1,j) <= sample_filter_v2_out(1,j); | |||
|
|
273 | END IF; | |||
|
|
274 | IF data_shaping_SP1 = '1' THEN | |||
|
|
275 | sample_data_shaping_out(2,j) <= sample_data_shaping_f2_f1_s(j); | |||
|
|
276 | ELSE | |||
|
|
277 | sample_data_shaping_out(2,j) <= sample_filter_v2_out(2,j); | |||
|
|
278 | END IF; | |||
|
|
279 | sample_data_shaping_out(4,j) <= sample_filter_v2_out(4,j); | |||
|
|
280 | sample_data_shaping_out(5,j) <= sample_filter_v2_out(5,j); | |||
|
|
281 | sample_data_shaping_out(6,j) <= sample_filter_v2_out(6,j); | |||
|
|
282 | sample_data_shaping_out(7,j) <= sample_filter_v2_out(7,j); | |||
|
|
283 | END IF; | |||
|
|
284 | END PROCESS; | |||
|
|
285 | END GENERATE; | |||
|
|
286 | ||||
|
|
287 | sample_filter_v2_out_val_s <= sample_data_shaping_out_val; | |||
|
|
288 | ChanelLoopOut : FOR i IN 0 TO 7 GENERATE | |||
|
|
289 | SampleLoopOut : FOR j IN 0 TO 15 GENERATE | |||
|
|
290 | sample_filter_v2_out_s(i,j) <= sample_data_shaping_out(i,j); | |||
|
|
291 | END GENERATE; | |||
|
|
292 | END GENERATE; | |||
| 222 | ----------------------------------------------------------------------------- |
|
293 | ----------------------------------------------------------------------------- | |
| 223 | -- F0 -- @24.576 kHz |
|
294 | -- F0 -- @24.576 kHz | |
| 224 | ----------------------------------------------------------------------------- |
|
295 | ----------------------------------------------------------------------------- | |
| 225 | Downsampling_f0 : Downsampling |
|
296 | Downsampling_f0 : Downsampling | |
| 226 | GENERIC MAP ( |
|
297 | GENERIC MAP ( | |
| 227 |
ChanelCount => |
|
298 | ChanelCount => 8, | |
| 228 |
SampleSize => 1 |
|
299 | SampleSize => 16, | |
| 229 | DivideParam => 4) |
|
300 | DivideParam => 4) | |
| 230 | PORT MAP ( |
|
301 | PORT MAP ( | |
| 231 | clk => clk, |
|
302 | clk => clk, | |
| 232 | rstn => rstn, |
|
303 | rstn => rstn, | |
| 233 |
sample_in_val => sample_filter_ |
|
304 | sample_in_val => sample_filter_v2_out_val_s, | |
| 234 |
sample_in => sample_filter_ |
|
305 | sample_in => sample_filter_v2_out_s, | |
| 235 | sample_out_val => sample_f0_val, |
|
306 | sample_out_val => sample_f0_val, | |
| 236 | sample_out => sample_f0); |
|
307 | sample_out => sample_f0); | |
| 237 |
|
308 | |||
| 238 |
all_bit_sample_f0: FOR I IN 1 |
|
309 | all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE | |
| 239 |
sample_f0_wdata( |
|
310 | sample_f0_wdata_s(I) <= sample_f0(0, I); -- V | |
| 240 |
sample_f0_wdata(1 |
|
311 | sample_f0_wdata_s(16*1+I) <= sample_f0(1, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(3, I); -- E1 | |
| 241 |
sample_f0_wdata(1 |
|
312 | sample_f0_wdata_s(16*2+I) <= sample_f0(2, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(4, I); -- E2 | |
| 242 |
sample_f0_wdata(1 |
|
313 | sample_f0_wdata_s(16*3+I) <= sample_f0(5, I); -- B1 | |
| 243 |
sample_f0_wdata(1 |
|
314 | sample_f0_wdata_s(16*4+I) <= sample_f0(6, I); -- B2 | |
|
|
315 | sample_f0_wdata_s(16*5+I) <= sample_f0(7, I); -- B3 | |||
| 244 | END GENERATE all_bit_sample_f0; |
|
316 | END GENERATE all_bit_sample_f0; | |
| 245 |
|
317 | |||
| 246 | PROCESS (clk, rstn) |
|
318 | sample_f0_wen <= NOT(sample_f0_val) & | |
| 247 | BEGIN -- PROCESS |
|
319 | NOT(sample_f0_val) & | |
| 248 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
320 | NOT(sample_f0_val) & | |
| 249 | counter_f0 <= 0; |
|
321 | NOT(sample_f0_val) & | |
| 250 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
|
322 | NOT(sample_f0_val) & | |
| 251 | IF sample_f0_val = '1' THEN |
|
323 | NOT(sample_f0_val); | |
| 252 | IF counter_f0 = 511 THEN |
|
|||
| 253 | counter_f0 <= 0; |
|
|||
| 254 | ELSE |
|
|||
| 255 | counter_f0 <= counter_f0 + 1; |
|
|||
| 256 | END IF; |
|
|||
| 257 | END IF; |
|
|||
| 258 | END IF; |
|
|||
| 259 | END PROCESS; |
|
|||
| 260 |
|
||||
| 261 | sample_f0_0_val <= sample_f0_val WHEN counter_f0 < 256 ELSE '0'; |
|
|||
| 262 | sample_f0_0_wen <= NOT(sample_f0_0_val) & |
|
|||
| 263 | NOT(sample_f0_0_val) & |
|
|||
| 264 | NOT(sample_f0_0_val) & |
|
|||
| 265 | NOT(sample_f0_0_val) & |
|
|||
| 266 | NOT(sample_f0_0_val); |
|
|||
| 267 |
|
||||
| 268 | lppFIFO_f0_0: lppFIFOxN |
|
|||
| 269 | GENERIC MAP ( |
|
|||
| 270 | tech => tech, |
|
|||
| 271 | Data_sz => 18, |
|
|||
| 272 | FifoCnt => 5, |
|
|||
| 273 | Enable_ReUse => '0') |
|
|||
| 274 | PORT MAP ( |
|
|||
| 275 | rst => rstn, |
|
|||
| 276 | wclk => clk, |
|
|||
| 277 | rclk => clk, |
|
|||
| 278 | ReUse => (OTHERS => '0'), |
|
|||
| 279 |
|
||||
| 280 | wen => sample_f0_0_wen, |
|
|||
| 281 | ren => sample_f0_0_ren, |
|
|||
| 282 | wdata => sample_f0_wdata, |
|
|||
| 283 | rdata => sample_f0_0_rdata, |
|
|||
| 284 | full => sample_f0_0_full, |
|
|||
| 285 | empty => sample_f0_0_empty); |
|
|||
| 286 |
|
||||
| 287 | sample_f0_1_val <= sample_f0_val WHEN counter_f0 > 255 ELSE '0'; |
|
|||
| 288 | sample_f0_1_wen <= NOT(sample_f0_1_val) & |
|
|||
| 289 | NOT(sample_f0_1_val) & |
|
|||
| 290 | NOT(sample_f0_1_val) & |
|
|||
| 291 | NOT(sample_f0_1_val) & |
|
|||
| 292 | NOT(sample_f0_1_val); |
|
|||
| 293 |
|
||||
| 294 | lppFIFO_f0_1: lppFIFOxN |
|
|||
| 295 | GENERIC MAP ( |
|
|||
| 296 | tech => tech, |
|
|||
| 297 | Data_sz => 18, |
|
|||
| 298 | FifoCnt => 5, |
|
|||
| 299 | Enable_ReUse => '0') |
|
|||
| 300 | PORT MAP ( |
|
|||
| 301 | rst => rstn, |
|
|||
| 302 | wclk => clk, |
|
|||
| 303 | rclk => clk, |
|
|||
| 304 | ReUse => (OTHERS => '0'), |
|
|||
| 305 |
|
||||
| 306 | wen => sample_f0_1_wen, |
|
|||
| 307 | ren => sample_f0_1_ren, |
|
|||
| 308 | wdata => sample_f0_wdata, |
|
|||
| 309 | rdata => sample_f0_1_rdata, |
|
|||
| 310 | full => sample_f0_1_full, |
|
|||
| 311 | empty => sample_f0_1_empty); |
|
|||
| 312 |
|
324 | |||
| 313 |
|
||||
| 314 |
|
||||
| 315 | ----------------------------------------------------------------------------- |
|
325 | ----------------------------------------------------------------------------- | |
| 316 | -- F1 -- @4096 Hz |
|
326 | -- F1 -- @4096 Hz | |
| 317 | ----------------------------------------------------------------------------- |
|
327 | ----------------------------------------------------------------------------- | |
| 318 | Downsampling_f1 : Downsampling |
|
328 | Downsampling_f1 : Downsampling | |
| 319 | GENERIC MAP ( |
|
329 | GENERIC MAP ( | |
| 320 |
ChanelCount => |
|
330 | ChanelCount => 8, | |
| 321 |
SampleSize => 1 |
|
331 | SampleSize => 16, | |
| 322 | DivideParam => 6) |
|
332 | DivideParam => 6) | |
| 323 | PORT MAP ( |
|
333 | PORT MAP ( | |
| 324 | clk => clk, |
|
334 | clk => clk, | |
| @@ -327,105 +337,162 BEGIN | |||||
| 327 | sample_in => sample_f0, |
|
337 | sample_in => sample_f0, | |
| 328 | sample_out_val => sample_f1_val, |
|
338 | sample_out_val => sample_f1_val, | |
| 329 | sample_out => sample_f1); |
|
339 | sample_out => sample_f1); | |
| 330 |
|
340 | |||
| 331 | sample_f1_wen <= NOT(sample_f1_val) & |
|
341 | all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE | |
| 332 | NOT(sample_f1_val) & |
|
342 | sample_f1_wdata_s(I) <= sample_f1(0, I); -- V | |
| 333 | NOT(sample_f1_val) & |
|
343 | sample_f1_wdata_s(16*1+I) <= sample_f1(1, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(3, I); -- E1 | |
| 334 | NOT(sample_f1_val) & |
|
344 | sample_f1_wdata_s(16*2+I) <= sample_f1(2, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(4, I); -- E2 | |
| 335 | NOT(sample_f1_val); |
|
345 | sample_f1_wdata_s(16*3+I) <= sample_f1(5, I); -- B1 | |
| 336 |
|
346 | sample_f1_wdata_s(16*4+I) <= sample_f1(6, I); -- B2 | ||
| 337 | all_bit_sample_f1: FOR I IN 17 DOWNTO 0 GENERATE |
|
347 | sample_f1_wdata_s(16*5+I) <= sample_f1(7, I); -- B3 | |
| 338 | sample_f1_wdata( I) <= sample_f1(0,I); |
|
|||
| 339 | sample_f1_wdata(18*1+I) <= sample_f1(1,I); |
|
|||
| 340 | sample_f1_wdata(18*2+I) <= sample_f1(2,I); |
|
|||
| 341 | sample_f1_wdata(18*3+I) <= sample_f1(6,I); |
|
|||
| 342 | sample_f1_wdata(18*4+I) <= sample_f1(7,I); |
|
|||
| 343 | END GENERATE all_bit_sample_f1; |
|
348 | END GENERATE all_bit_sample_f1; | |
| 344 |
|
|
349 | ||
| 345 | lppFIFO_f1: lppFIFOxN |
|
350 | sample_f1_wen <= NOT(sample_f1_val) & | |
| 346 | GENERIC MAP ( |
|
351 | NOT(sample_f1_val) & | |
| 347 | tech => tech, |
|
352 | NOT(sample_f1_val) & | |
| 348 | Data_sz => 18, |
|
353 | NOT(sample_f1_val) & | |
| 349 | FifoCnt => 5, |
|
354 | NOT(sample_f1_val) & | |
| 350 | Enable_ReUse => '0') |
|
355 | NOT(sample_f1_val); | |
| 351 | PORT MAP ( |
|
|||
| 352 | rst => rstn, |
|
|||
| 353 | wclk => clk, |
|
|||
| 354 | rclk => clk, |
|
|||
| 355 | ReUse => (OTHERS => '0'), |
|
|||
| 356 |
|
||||
| 357 | wen => sample_f1_wen, |
|
|||
| 358 | ren => sample_f1_ren, |
|
|||
| 359 | wdata => sample_f1_wdata, |
|
|||
| 360 | rdata => sample_f1_rdata, |
|
|||
| 361 | full => sample_f1_full, |
|
|||
| 362 | empty => sample_f1_empty); |
|
|||
| 363 |
|
356 | |||
| 364 | ----------------------------------------------------------------------------- |
|
357 | ----------------------------------------------------------------------------- | |
| 365 |
-- F2 -- @ |
|
358 | -- F2 -- @256 Hz | |
| 366 | ----------------------------------------------------------------------------- |
|
359 | ----------------------------------------------------------------------------- | |
|
|
360 | all_bit_sample_f0_s : FOR I IN 15 DOWNTO 0 GENERATE | |||
|
|
361 | sample_f0_s(0, I) <= sample_f0(0, I); -- V | |||
|
|
362 | sample_f0_s(1, I) <= sample_f0(1, I); -- E1 | |||
|
|
363 | sample_f0_s(2, I) <= sample_f0(2, I); -- E2 | |||
|
|
364 | sample_f0_s(3, I) <= sample_f0(5, I); -- B1 | |||
|
|
365 | sample_f0_s(4, I) <= sample_f0(6, I); -- B2 | |||
|
|
366 | sample_f0_s(5, I) <= sample_f0(7, I); -- B3 | |||
|
|
367 | END GENERATE all_bit_sample_f0_s; | |||
|
|
368 | ||||
| 367 |
|
|
369 | Downsampling_f2 : Downsampling | |
| 368 | GENERIC MAP ( |
|
370 | GENERIC MAP ( | |
| 369 |
ChanelCount => |
|
371 | ChanelCount => 6, | |
| 370 |
SampleSize => 1 |
|
372 | SampleSize => 16, | |
|
|
373 | DivideParam => 96) | |||
|
|
374 | PORT MAP ( | |||
|
|
375 | clk => clk, | |||
|
|
376 | rstn => rstn, | |||
|
|
377 | sample_in_val => sample_f0_val , | |||
|
|
378 | sample_in => sample_f0_s, | |||
|
|
379 | sample_out_val => sample_f2_val, | |||
|
|
380 | sample_out => sample_f2); | |||
|
|
381 | ||||
|
|
382 | sample_f2_wen <= NOT(sample_f2_val) & | |||
|
|
383 | NOT(sample_f2_val) & | |||
|
|
384 | NOT(sample_f2_val) & | |||
|
|
385 | NOT(sample_f2_val) & | |||
|
|
386 | NOT(sample_f2_val) & | |||
|
|
387 | NOT(sample_f2_val); | |||
|
|
388 | ||||
|
|
389 | all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE | |||
|
|
390 | sample_f2_wdata_s(I) <= sample_f2(0, I); | |||
|
|
391 | sample_f2_wdata_s(16*1+I) <= sample_f2(1, I); | |||
|
|
392 | sample_f2_wdata_s(16*2+I) <= sample_f2(2, I); | |||
|
|
393 | sample_f2_wdata_s(16*3+I) <= sample_f2(3, I); | |||
|
|
394 | sample_f2_wdata_s(16*4+I) <= sample_f2(4, I); | |||
|
|
395 | sample_f2_wdata_s(16*5+I) <= sample_f2(5, I); | |||
|
|
396 | END GENERATE all_bit_sample_f2; | |||
|
|
397 | ||||
|
|
398 | ----------------------------------------------------------------------------- | |||
|
|
399 | -- F3 -- @16 Hz | |||
|
|
400 | ----------------------------------------------------------------------------- | |||
|
|
401 | all_bit_sample_f1_s : FOR I IN 15 DOWNTO 0 GENERATE | |||
|
|
402 | sample_f1_s(0, I) <= sample_f1(0, I); -- V | |||
|
|
403 | sample_f1_s(1, I) <= sample_f1(1, I); -- E1 | |||
|
|
404 | sample_f1_s(2, I) <= sample_f1(2, I); -- E2 | |||
|
|
405 | sample_f1_s(3, I) <= sample_f1(5, I); -- B1 | |||
|
|
406 | sample_f1_s(4, I) <= sample_f1(6, I); -- B2 | |||
|
|
407 | sample_f1_s(5, I) <= sample_f1(7, I); -- B3 | |||
|
|
408 | END GENERATE all_bit_sample_f1_s; | |||
|
|
409 | ||||
|
|
410 | Downsampling_f3 : Downsampling | |||
|
|
411 | GENERIC MAP ( | |||
|
|
412 | ChanelCount => 6, | |||
|
|
413 | SampleSize => 16, | |||
| 371 | DivideParam => 256) |
|
414 | DivideParam => 256) | |
| 372 | PORT MAP ( |
|
415 | PORT MAP ( | |
| 373 | clk => clk, |
|
416 | clk => clk, | |
| 374 | rstn => rstn, |
|
417 | rstn => rstn, | |
| 375 | sample_in_val => sample_f1_val , |
|
418 | sample_in_val => sample_f1_val , | |
| 376 | sample_in => sample_f1, |
|
419 | sample_in => sample_f1_s, | |
| 377 | sample_out_val => sample_f2_val, |
|
|||
| 378 | sample_out => sample_f2); |
|
|||
| 379 |
|
||||
| 380 | ----------------------------------------------------------------------------- |
|
|||
| 381 | -- F3 -- @256 Hz |
|
|||
| 382 | ----------------------------------------------------------------------------- |
|
|||
| 383 | Downsampling_f3 : Downsampling |
|
|||
| 384 | GENERIC MAP ( |
|
|||
| 385 | ChanelCount => ChanelCount, |
|
|||
| 386 | SampleSize => 18, |
|
|||
| 387 | DivideParam => 96) |
|
|||
| 388 | PORT MAP ( |
|
|||
| 389 | clk => clk, |
|
|||
| 390 | rstn => rstn, |
|
|||
| 391 | sample_in_val => sample_f0_val , |
|
|||
| 392 | sample_in => sample_f0, |
|
|||
| 393 | sample_out_val => sample_f3_val, |
|
420 | sample_out_val => sample_f3_val, | |
| 394 | sample_out => sample_f3); |
|
421 | sample_out => sample_f3); | |
| 395 |
|
422 | |||
| 396 |
sample_f3_wen |
|
423 | sample_f3_wen <= (NOT sample_f3_val) & | |
| 397 |
|
|
424 | (NOT sample_f3_val) & | |
| 398 |
|
|
425 | (NOT sample_f3_val) & | |
| 399 |
|
|
426 | (NOT sample_f3_val) & | |
| 400 |
|
|
427 | (NOT sample_f3_val) & | |
|
|
428 | (NOT sample_f3_val); | |||
| 401 |
|
429 | |||
| 402 |
all_bit_sample_f3: FOR I IN 1 |
|
430 | all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE | |
| 403 |
sample_f3_wdata( |
|
431 | sample_f3_wdata_s(I) <= sample_f3(0, I); | |
| 404 |
sample_f3_wdata(1 |
|
432 | sample_f3_wdata_s(16*1+I) <= sample_f3(1, I); | |
| 405 |
sample_f3_wdata(1 |
|
433 | sample_f3_wdata_s(16*2+I) <= sample_f3(2, I); | |
| 406 |
sample_f3_wdata(1 |
|
434 | sample_f3_wdata_s(16*3+I) <= sample_f3(3, I); | |
| 407 |
sample_f3_wdata(1 |
|
435 | sample_f3_wdata_s(16*4+I) <= sample_f3(4, I); | |
|
|
436 | sample_f3_wdata_s(16*5+I) <= sample_f3(5, I); | |||
| 408 | END GENERATE all_bit_sample_f3; |
|
437 | END GENERATE all_bit_sample_f3; | |
| 409 |
|
438 | |||
| 410 | lppFIFO_f3: lppFIFOxN |
|
439 | lpp_waveform_1 : lpp_waveform | |
| 411 | GENERIC MAP ( |
|
440 | GENERIC MAP ( | |
| 412 |
|
|
441 | hindex => hindex, | |
| 413 | Data_sz => 18, |
|
442 | tech => tech, | |
| 414 | FifoCnt => 5, |
|
443 | data_size => 160, | |
| 415 | Enable_ReUse => '0') |
|
444 | nb_burst_available_size => nb_burst_available_size, | |
|
|
445 | nb_snapshot_param_size => nb_snapshot_param_size, | |||
|
|
446 | delta_snapshot_size => delta_snapshot_size, | |||
|
|
447 | delta_f2_f0_size => delta_f2_f0_size, | |||
|
|
448 | delta_f2_f1_size => delta_f2_f1_size) | |||
| 416 | PORT MAP ( |
|
449 | PORT MAP ( | |
| 417 |
|
|
450 | clk => clk, | |
| 418 | wclk => clk, |
|
451 | rstn => rstn, | |
| 419 | rclk => clk, |
|
452 | ||
| 420 | ReUse => (OTHERS => '0'), |
|
453 | AHB_Master_In => AHB_Master_In, | |
| 421 |
|
454 | AHB_Master_Out => AHB_Master_Out, | ||
| 422 | wen => sample_f3_wen, |
|
455 | ||
| 423 | ren => sample_f3_ren, |
|
456 | coarse_time_0 => coarse_time_0, -- IN | |
| 424 | wdata => sample_f3_wdata, |
|
457 | delta_snapshot => delta_snapshot, -- IN | |
| 425 | rdata => sample_f3_rdata, |
|
458 | delta_f2_f1 => delta_f2_f1, -- IN | |
| 426 | full => sample_f3_full, |
|
459 | delta_f2_f0 => delta_f2_f0, -- IN | |
| 427 | empty => sample_f3_empty); |
|
460 | enable_f0 => enable_f0, -- IN | |
|
|
461 | enable_f1 => enable_f1, -- IN | |||
|
|
462 | enable_f2 => enable_f2, -- IN | |||
|
|
463 | enable_f3 => enable_f3, -- IN | |||
|
|
464 | burst_f0 => burst_f0, -- IN | |||
|
|
465 | burst_f1 => burst_f1, -- IN | |||
|
|
466 | burst_f2 => burst_f2, -- IN | |||
|
|
467 | nb_burst_available => nb_burst_available, | |||
|
|
468 | nb_snapshot_param => nb_snapshot_param, | |||
|
|
469 | status_full => status_full, | |||
|
|
470 | status_full_ack => status_full_ack, -- IN | |||
|
|
471 | status_full_err => status_full_err, | |||
|
|
472 | status_new_err => status_new_err, | |||
| 428 |
|
473 | |||
| 429 |
|
474 | addr_data_f0 => addr_data_f0, -- IN | ||
|
|
475 | addr_data_f1 => addr_data_f1, -- IN | |||
|
|
476 | addr_data_f2 => addr_data_f2, -- IN | |||
|
|
477 | addr_data_f3 => addr_data_f3, -- IN | |||
|
|
478 | ||||
|
|
479 | data_f0_in => data_f0_in_valid, | |||
|
|
480 | data_f1_in => data_f1_in_valid, | |||
|
|
481 | data_f2_in => data_f2_in_valid, | |||
|
|
482 | data_f3_in => data_f3_in_valid, | |||
|
|
483 | data_f0_in_valid => sample_f0_val, | |||
|
|
484 | data_f1_in_valid => sample_f1_val, | |||
|
|
485 | data_f2_in_valid => sample_f2_val, | |||
|
|
486 | data_f3_in_valid => sample_f3_val); | |||
|
|
487 | ||||
|
|
488 | data_f0_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f0_wdata_s; | |||
|
|
489 | data_f1_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f1_wdata_s; | |||
|
|
490 | data_f2_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f2_wdata_s; | |||
|
|
491 | data_f3_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f3_wdata_s; | |||
|
|
492 | ||||
|
|
493 | sample_f0_wdata <= sample_f0_wdata_s; | |||
|
|
494 | sample_f1_wdata <= sample_f1_wdata_s; | |||
|
|
495 | sample_f2_wdata <= sample_f2_wdata_s; | |||
|
|
496 | sample_f3_wdata <= sample_f3_wdata_s; | |||
| 430 |
|
497 | |||
| 431 | END tb; |
|
498 | END tb; | |
| @@ -1,49 +1,72 | |||||
| 1 |
|
1 | |||
| 2 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/general_purpose.vhd |
|
2 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/general_purpose.vhd | |
| 3 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/SYNC_FF.vhd |
|
3 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/SYNC_FF.vhd | |
| 4 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MUXN.vhd |
|
4 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MUXN.vhd | |
| 5 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MUX2.vhd |
|
5 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MUX2.vhd | |
| 6 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/REG.vhd |
|
6 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/REG.vhd | |
| 7 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC.vhd |
|
7 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC.vhd | |
| 8 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_CONTROLER.vhd |
|
8 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_CONTROLER.vhd | |
| 9 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_REG.vhd |
|
9 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_REG.vhd | |
| 10 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_MUX.vhd |
|
10 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_MUX.vhd | |
| 11 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_MUX2.vhd |
|
11 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_MUX2.vhd | |
| 12 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/Shifter.vhd |
|
12 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/Shifter.vhd | |
| 13 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MULTIPLIER.vhd |
|
13 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MULTIPLIER.vhd | |
| 14 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ADDER.vhd |
|
14 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ADDER.vhd | |
| 15 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ALU.vhd |
|
15 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ALU.vhd | |
| 16 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ADDRcntr.vhd |
|
16 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ADDRcntr.vhd | |
| 17 |
|
17 | |||
| 18 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/iir_filter.vhd |
|
18 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/iir_filter.vhd | |
| 19 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/FILTERcfg.vhd |
|
19 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/FILTERcfg.vhd | |
| 20 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CEL.vhd |
|
20 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CEL.vhd | |
| 21 |
vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_C |
|
21 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CEL_N.vhd | |
| 22 |
|
|
22 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR2.vhd | |
| 23 |
|
23 | #vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR.vhd | ||
| 24 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd |
|
24 | ||
| 25 |
vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/ |
|
25 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd | |
| 26 |
vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_ |
|
26 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd | |
| 27 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd |
|
27 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd | |
| 28 |
|
28 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd | ||
| 29 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lpp_memory.vhd |
|
29 | ||
| 30 |
vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lpp_ |
|
30 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lpp_memory.vhd | |
| 31 |
vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lppFIFO |
|
31 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lpp_FIFO.vhd | |
| 32 |
|
32 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lppFIFOxN.vhd | ||
| 33 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/lpp_downsampling/Downsampling.vhd |
|
33 | ||
| 34 |
|
34 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/lpp_downsampling/Downsampling.vhd | ||
| 35 | vcom -quiet -93 -work lpp e:/opt/tortoiseHG_vhdlib/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd |
|
35 | ||
| 36 |
vcom -quiet -93 -work lpp e:/opt/tortoiseHG_vhdlib/lib/lpp/lpp_top_lfr/lpp_top_ |
|
36 | vcom -quiet -93 -work lpp e:/opt/tortoiseHG_vhdlib/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd | |
| 37 |
|
37 | vcom -quiet -93 -work lpp e:/opt/tortoiseHG_vhdlib/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd | ||
| 38 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/lpp_ad_conv.vhd |
|
38 | ||
| 39 |
vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/ |
|
39 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/lpp_ad_conv.vhd | |
| 40 |
vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/ |
|
40 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/AD7688_drvr.vhd | |
| 41 |
|
41 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/TestModule_ADS7886.vhd | ||
| 42 | vcom -quiet -93 -work work Top_Data_Acquisition.vhd |
|
42 | ||
| 43 | vcom -quiet -93 -work work TB_Data_Acquisition.vhd |
|
43 | ||
| 44 |
|
44 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd | ||
| 45 | #vsim work.TB_Data_Acquisition |
|
45 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_acq.vhd | |
| 46 |
|
46 | #vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_lfr.vhd | ||
| 47 | #log -r * |
|
47 | ||
| 48 | #do wave_data_acquisition.do |
|
48 | vcom -quiet -93 -work lpp ../../lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd | |
|
|
49 | vcom -quiet -93 -work lpp ../../lib/lpp/lfr_time_management/apb_lfr_time_management.vhd | |||
|
|
50 | vcom -quiet -93 -work lpp ../../lib/lpp/lfr_time_management/lfr_time_management.vhd | |||
|
|
51 | ||||
|
|
52 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/lpp_dma_pkg.vhd | |||
|
|
53 | ||||
|
|
54 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd | |||
|
|
55 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform.vhd | |||
|
|
56 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_snapshot_controler.vhd | |||
|
|
57 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_snapshot.vhd | |||
|
|
58 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_burst.vhd | |||
|
|
59 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_dma.vhd | |||
|
|
60 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_dma_send_Nword.vhd | |||
|
|
61 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_dma_selectaddress.vhd | |||
|
|
62 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_dma_genvalid.vhd | |||
|
|
63 | ||||
|
|
64 | vcom -quiet -93 -work work Top_Data_Acquisition.vhd | |||
|
|
65 | ||||
|
|
66 | vcom -quiet -93 -work work TB_Data_Acquisition.vhd | |||
|
|
67 | ||||
|
|
68 | #vsim work.TB_Data_Acquisition | |||
|
|
69 | ||||
|
|
70 | #log -r * | |||
|
|
71 | #do wave_data_acquisition.do | |||
| 49 | #run 5 ms No newline at end of file |
|
72 | #run 5 ms | |
| @@ -1,231 +1,38 | |||||
| 1 | onerror {resume} |
|
1 | onerror {resume} | |
| 2 | quietly WaveActivateNextPane {} 0 |
|
2 | quietly WaveActivateNextPane {} 0 | |
| 3 |
add wave -noupdate -group { |
|
3 | add wave -noupdate -expand -group {Data Acq & Filter} -expand -group DIGITAL_ACQ /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/sample | |
| 4 |
add wave -noupdate -group { |
|
4 | add wave -noupdate -expand -group {Data Acq & Filter} -expand -group DIGITAL_ACQ /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/sample_val | |
| 5 |
add wave -noupdate -group { |
|
5 | add wave -noupdate -expand -group {Data Acq & Filter} -group FILTER /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in_val | |
| 6 |
add wave -noupdate -group { |
|
6 | add wave -noupdate -expand -group {Data Acq & Filter} -group FILTER /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in | |
| 7 |
add wave -noupdate -group { |
|
7 | add wave -noupdate -expand -group {Data Acq & Filter} -group FILTER /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_val | |
| 8 |
add wave -noupdate -group { |
|
8 | add wave -noupdate -expand -group {Data Acq & Filter} -group FILTER /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out | |
| 9 |
add wave -noupdate -group { |
|
9 | add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f0} /tb_data_acquisition/top_data_acquisition_1/downsampling_f0/sample_in_val | |
| 10 |
add wave -noupdate -group { |
|
10 | add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f0} /tb_data_acquisition/top_data_acquisition_1/downsampling_f0/sample_in | |
| 11 |
add wave -noupdate -group { |
|
11 | add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f0} /tb_data_acquisition/top_data_acquisition_1/downsampling_f0/sample_out_val | |
| 12 |
add wave -noupdate -group { |
|
12 | add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f0} /tb_data_acquisition/top_data_acquisition_1/downsampling_f0/sample_out | |
| 13 |
add wave -noupdate -group { |
|
13 | add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f1} /tb_data_acquisition/top_data_acquisition_1/downsampling_f1/sample_in_val | |
| 14 |
add wave -noupdate -group { |
|
14 | add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f1} /tb_data_acquisition/top_data_acquisition_1/downsampling_f1/sample_in | |
| 15 |
add wave -noupdate -group { |
|
15 | add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f1} /tb_data_acquisition/top_data_acquisition_1/downsampling_f1/sample_out_val | |
| 16 |
add wave -noupdate -group { |
|
16 | add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f1} /tb_data_acquisition/top_data_acquisition_1/downsampling_f1/sample_out | |
| 17 |
add wave -noupdate -group { |
|
17 | add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f2} /tb_data_acquisition/top_data_acquisition_1/downsampling_f2/sample_in_val | |
| 18 |
add wave -noupdate -group { |
|
18 | add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f2} /tb_data_acquisition/top_data_acquisition_1/downsampling_f2/sample_in | |
| 19 |
add wave -noupdate -group { |
|
19 | add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f2} /tb_data_acquisition/top_data_acquisition_1/downsampling_f2/sample_out_val | |
| 20 |
add wave -noupdate -group { |
|
20 | add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f2} /tb_data_acquisition/top_data_acquisition_1/downsampling_f2/sample_out | |
| 21 |
add wave -noupdate -group { |
|
21 | add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f3} /tb_data_acquisition/top_data_acquisition_1/downsampling_f3/sample_in_val | |
| 22 |
add wave -noupdate -group { |
|
22 | add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f3} /tb_data_acquisition/top_data_acquisition_1/downsampling_f3/sample_in | |
| 23 |
add wave -noupdate -group { |
|
23 | add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f3} /tb_data_acquisition/top_data_acquisition_1/downsampling_f3/sample_out_val | |
| 24 |
add wave -noupdate -group F |
|
24 | add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f3} /tb_data_acquisition/top_data_acquisition_1/downsampling_f3/sample_out | |
| 25 |
add wave -noupdate -group FI |
|
25 | add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f0_wen | |
| 26 |
add wave -noupdate -group FI |
|
26 | add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f0_wdata | |
| 27 |
add wave -noupdate -group FI |
|
27 | add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f1_wen | |
| 28 |
add wave -noupdate -group FI |
|
28 | add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f1_wdata | |
| 29 |
add wave -noupdate -group FI |
|
29 | add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f2_wen | |
| 30 |
add wave -noupdate -group FI |
|
30 | add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f2_wdata | |
| 31 |
add wave -noupdate -group FI |
|
31 | add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f3_wen | |
| 32 |
add wave -noupdate -group FI |
|
32 | add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f3_wdata | |
| 33 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/sample_clk |
|
|||
| 34 | add wave -noupdate -group FILTER -radix decimal -subitemconfig {/tb_data_acquisition/top_data_acquisition_1/filter/sample_in(7) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in(6) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in(5) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in(4) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in(3) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in(2) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in(1) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in(0) {-height 15 -radix decimal}} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in |
|
|||
| 35 | add wave -noupdate -group FILTER -subitemconfig {/tb_data_acquisition/top_data_acquisition_1/filter/sample_out(7) {-height 15 -radix unsigned} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out(6) {-height 15 -radix unsigned} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out(5) {-height 15 -radix unsigned} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out(4) {-height 15 -radix unsigned} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out(3) {-height 15 -radix unsigned} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out(2) {-height 15 -radix unsigned} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out(1) {-height 15 -radix unsigned} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out(0) {-height 15 -radix unsigned}} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out |
|
|||
| 36 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/virg_pos |
|
|||
| 37 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/gotest |
|
|||
| 38 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/coefs |
|
|||
| 39 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/smpl_clk_old |
|
|||
| 40 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/wd_sel |
|
|||
| 41 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/read |
|
|||
| 42 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/svg_addr |
|
|||
| 43 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/count |
|
|||
| 44 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/write |
|
|||
| 45 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/waddr_sel |
|
|||
| 46 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/go_0 |
|
|||
| 47 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/ram_sample_in |
|
|||
| 48 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/ram_sample_in_bk |
|
|||
| 49 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/ram_sample_out |
|
|||
| 50 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/alu_ctrl |
|
|||
| 51 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/alu_sample_in |
|
|||
| 52 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/alu_coef_in |
|
|||
| 53 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/alu_out |
|
|||
| 54 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/curentcel |
|
|||
| 55 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/curentchan |
|
|||
| 56 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/sample_in_buff |
|
|||
| 57 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/sample_out_buff |
|
|||
| 58 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/coefsreg |
|
|||
| 59 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/iir_cel_state |
|
|||
| 60 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/cnv_run |
|
|||
| 61 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/cnv |
|
|||
| 62 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/sck |
|
|||
| 63 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/sdo |
|
|||
| 64 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/cnv_clk |
|
|||
| 65 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/cnv_rstn |
|
|||
| 66 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/clk |
|
|||
| 67 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/rstn |
|
|||
| 68 | add wave -noupdate -expand -subitemconfig {/tb_data_acquisition/top_data_acquisition_1/sample(7) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/sample(6) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/sample(5) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/sample(4) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/sample(3) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/sample(2) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/sample(1) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/sample(0) {-height 15 -radix decimal}} /tb_data_acquisition/top_data_acquisition_1/sample |
|
|||
| 69 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/sample_val |
|
|||
| 70 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/coefs |
|
|||
| 71 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/sample_filter_in |
|
|||
| 72 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/sample_filter_out |
|
|||
| 73 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/iir_cel_state |
|
|||
| 74 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/alu_selected_coeff |
|
|||
| 75 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/chanel_ongoing |
|
|||
| 76 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/cel_ongoing |
|
|||
| 77 | add wave -noupdate -expand -group ALU /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/clk |
|
|||
| 78 | add wave -noupdate -expand -group ALU /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/reset |
|
|||
| 79 | add wave -noupdate -expand -group ALU /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/ctrl |
|
|||
| 80 | add wave -noupdate -expand -group ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/op1 |
|
|||
| 81 | add wave -noupdate -expand -group ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/op2 |
|
|||
| 82 | add wave -noupdate -expand -group ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/res |
|
|||
| 83 | add wave -noupdate -group ALU_MUX_INPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_sel_input |
|
|||
| 84 | add wave -noupdate -group ALU_MUX_INPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/reg_sample_in |
|
|||
| 85 | add wave -noupdate -group ALU_MUX_INPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_output |
|
|||
| 86 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/rstn |
|
|||
| 87 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/clk |
|
|||
| 88 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/virg_pos |
|
|||
| 89 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/coefs |
|
|||
| 90 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/in_sel_src |
|
|||
| 91 | add wave -noupdate -group DATA_FLOW -radix hexadecimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_sel_wdata |
|
|||
| 92 | add wave -noupdate -group DATA_FLOW -radix unsigned /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_input |
|
|||
| 93 | add wave -noupdate -group DATA_FLOW -radix hexadecimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_write |
|
|||
| 94 | add wave -noupdate -group DATA_FLOW -radix hexadecimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_read |
|
|||
| 95 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/raddr_rst |
|
|||
| 96 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/raddr_add1 |
|
|||
| 97 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/waddr_previous |
|
|||
| 98 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_sel_input |
|
|||
| 99 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_sel_coeff |
|
|||
| 100 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_ctrl |
|
|||
| 101 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/sample_in |
|
|||
| 102 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/sample_out |
|
|||
| 103 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/reg_sample_in |
|
|||
| 104 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_output |
|
|||
| 105 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_output |
|
|||
| 106 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_sample |
|
|||
| 107 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_output_s |
|
|||
| 108 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/arraycoeff |
|
|||
| 109 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_coef_s |
|
|||
| 110 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_coef |
|
|||
| 111 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/rstn |
|
|||
| 112 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/clk |
|
|||
| 113 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/virg_pos |
|
|||
| 114 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/coefs |
|
|||
| 115 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in_val |
|
|||
| 116 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in |
|
|||
| 117 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_val |
|
|||
| 118 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out |
|
|||
| 119 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/in_sel_src |
|
|||
| 120 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/ram_sel_wdata |
|
|||
| 121 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/ram_write |
|
|||
| 122 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/ram_read |
|
|||
| 123 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/raddr_rst |
|
|||
| 124 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/raddr_add1 |
|
|||
| 125 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/waddr_previous |
|
|||
| 126 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/alu_sel_input |
|
|||
| 127 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/alu_sel_coeff |
|
|||
| 128 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/alu_ctrl |
|
|||
| 129 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in_buf |
|
|||
| 130 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in_rotate |
|
|||
| 131 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in_s |
|
|||
| 132 | add wave -noupdate -group IIR_CEL_FILTER_v2 -radix unsigned /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_val_s |
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| 133 | add wave -noupdate -group IIR_CEL_FILTER_v2 -radix unsigned /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_val_s2 |
|
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| 134 | add wave -noupdate -group IIR_CEL_FILTER_v2 -radix unsigned /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_rot_s |
|
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| 135 | add wave -noupdate -group IIR_CEL_FILTER_v2 -radix unsigned -subitemconfig {/tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(17) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(16) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(15) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(14) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(13) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(12) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(11) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(10) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(9) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(8) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(7) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(6) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(5) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(4) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(3) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(2) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(1) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(0) {-radix unsigned}} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s |
|
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| 136 | add wave -noupdate -group IIR_CEL_FILTER_v2 -radix unsigned -expand -subitemconfig {/tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(7) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(6) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(5) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(4) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(3) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(2) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(1) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(0) {-radix unsigned}} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2 |
|
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| 137 | add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_INPUT_MUX -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/in_sel_src |
|
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| 138 | add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_INPUT_MUX -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_output |
|
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| 139 | add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_INPUT_MUX -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_output |
|
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| 140 | add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_INPUT_MUX -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/sample_in |
|
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| 141 | add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_INPUT_MUX -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/reg_sample_in |
|
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| 142 | add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/waddr_previous |
|
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| 143 | add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_write |
|
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| 144 | add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_RAM -radix hexadecimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_sel_wdata |
|
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| 145 | add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_RAM -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/reg_sample_in |
|
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| 146 | add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_RAM -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_output |
|
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| 147 | add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_RAM -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_output |
|
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| 148 | add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_RAM -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_input |
|
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| 149 | add wave -noupdate -group DATAFLOW -group DATAFLOW_OUTPUT_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_read |
|
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| 150 | add wave -noupdate -group DATAFLOW -group DATAFLOW_OUTPUT_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/raddr_rst |
|
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| 151 | add wave -noupdate -group DATAFLOW -group DATAFLOW_OUTPUT_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/raddr_add1 |
|
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| 152 | add wave -noupdate -group DATAFLOW -group DATAFLOW_OUTPUT_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_output |
|
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| 153 | add wave -noupdate -group DATAFLOW -group DATAFLOW_SELECT_COEFF /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/arraycoeff |
|
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| 154 | add wave -noupdate -group DATAFLOW -group DATAFLOW_SELECT_COEFF /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_coef_s |
|
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| 155 | add wave -noupdate -group DATAFLOW -group DATAFLOW_SELECT_COEFF -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_coef |
|
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| 156 | add wave -noupdate -group DATAFLOW -group DATAFLOW_SELECT_COEFF -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_sel_coeff |
|
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| 157 | add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_ALU_MUX /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_sel_input |
|
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| 158 | add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_ALU_MUX -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/reg_sample_in |
|
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| 159 | add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_ALU_MUX -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_output |
|
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| 160 | add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_ctrl |
|
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| 161 | add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_coef |
|
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| 162 | add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_sample |
|
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| 163 | add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_output_s |
|
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| 164 | add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_output |
|
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| 165 | add wave -noupdate -group DATAFLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/iir_cel_state |
|
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| 166 | add wave -noupdate -group DATAFLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/chanel_ongoing |
|
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| 167 | add wave -noupdate -group DATAFLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/cel_ongoing |
|
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| 168 | add wave -noupdate -group DATAFLOW -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/sample_out |
|
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| 169 | add wave -noupdate -group DATAFLOW_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/rstn |
|
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| 170 | add wave -noupdate -group DATAFLOW_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/clk |
|
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| 171 | add wave -noupdate -group DATAFLOW_RAM -subitemconfig {/tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(0) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(1) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(2) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(3) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(4) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(5) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(6) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(7) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(8) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(9) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(10) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(11) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(12) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(13) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(14) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(15) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(16) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(17) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(18) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(19) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(20) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(21) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(22) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(23) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(24) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(25) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(26) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(27) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(28) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(29) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(30) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(31) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(32) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(33) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(34) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(35) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(36) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(37) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(38) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(39) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(40) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(41) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(42) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(43) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(44) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(45) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(46) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(47) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(48) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(49) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(50) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(51) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(52) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(53) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(54) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(55) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(56) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(57) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(58) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(59) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(60) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(61) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(62) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(63) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(64) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(65) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(66) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(67) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(68) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(69) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(70) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(71) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(72) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(73) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(74) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(75) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(76) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(77) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(78) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(79) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(80) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(81) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(82) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(83) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(84) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(85) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(86) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(87) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(88) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(89) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(90) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(91) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(92) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(93) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(94) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(95) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(96) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(97) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(98) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(99) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(100) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(101) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(102) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(103) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(104) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(105) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(106) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(107) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(108) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(109) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(110) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(111) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(112) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(113) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(114) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(115) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(116) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(117) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(118) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(119) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(120) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(121) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(122) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(123) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(124) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(125) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(126) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(127) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(128) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(129) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(130) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(131) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(132) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(133) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(134) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(135) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(136) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(137) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(138) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(139) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(140) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(141) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(142) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(143) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(144) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(145) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(146) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(147) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(148) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(149) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(150) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(151) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(152) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(153) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(154) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(155) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(156) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(157) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(158) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(159) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(160) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(161) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(162) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(163) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(164) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(165) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(166) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(167) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(168) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(169) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(170) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(171) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(172) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(173) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(174) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(175) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(176) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(177) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(178) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(179) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(180) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(181) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(182) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(183) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(184) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(185) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(186) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(187) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(188) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(189) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(190) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(191) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(192) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(193) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(194) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(195) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(196) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(197) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(198) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(199) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(200) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(201) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(202) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(203) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(204) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(205) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(206) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(207) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(208) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(209) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(210) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(211) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(212) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(213) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(214) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(215) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(216) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(217) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(218) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(219) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(220) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(221) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(222) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(223) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(224) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(225) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(226) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(227) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(228) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(229) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(230) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(231) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(232) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(233) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(234) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(235) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(236) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(237) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(238) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(239) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(240) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(241) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(242) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(243) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(244) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(245) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(246) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(247) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(248) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(249) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(250) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(251) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(252) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(253) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(254) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(255) {-height 15 -radix decimal}} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray |
|
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| 172 | add wave -noupdate -group DATAFLOW_RAM -group COUNTER -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/counter |
|
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| 173 | add wave -noupdate -group DATAFLOW_RAM -group COUNTER /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/raddr_rst |
|
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| 174 | add wave -noupdate -group DATAFLOW_RAM -group COUNTER /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/raddr_add1 |
|
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| 175 | add wave -noupdate -group DATAFLOW_RAM -group COUNTER /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/waddr_previous |
|
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| 176 | add wave -noupdate -group DATAFLOW_RAM -group WRITE /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/ram_write |
|
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| 177 | add wave -noupdate -group DATAFLOW_RAM -group WRITE /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/wen |
|
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| 178 | add wave -noupdate -group DATAFLOW_RAM -group WRITE -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/waddr |
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| 179 | add wave -noupdate -group DATAFLOW_RAM -group WRITE -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/wd |
|
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| 180 | add wave -noupdate -group DATAFLOW_RAM -group WRITE -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/sample_in |
|
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| 181 | add wave -noupdate -group DATAFLOW_RAM -group READ /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/ram_read |
|
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| 182 | add wave -noupdate -group DATAFLOW_RAM -group READ /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/ren |
|
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| 183 | add wave -noupdate -group DATAFLOW_RAM -group READ -radix unsigned /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/raddr |
|
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| 184 | add wave -noupdate -group DATAFLOW_RAM -group READ /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/rd |
|
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| 185 | add wave -noupdate -group DATAFLOW_RAM -group READ /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/sample_out |
|
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| 186 | add wave -noupdate -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in_val |
|
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| 187 | add wave -noupdate -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in |
|
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| 188 | add wave -noupdate -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_val |
|
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| 189 | add wave -noupdate -radix decimal -subitemconfig {/tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(7) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(6) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(5) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(4) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(3) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(2) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(1) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(0) {-height 15 -radix decimal}} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out |
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| 190 | add wave -noupdate -height 15 -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(4) |
|
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| 191 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/clk |
|
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| 192 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/reset |
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| 193 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/clr_mac |
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| 194 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/mac_mul_add |
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| 195 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/op1 |
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| 196 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/op2 |
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| 197 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/res |
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| 198 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/add |
|
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| 199 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/mult |
|
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| 200 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/multout |
|
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| 201 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/adderina |
|
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| 202 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/adderinb |
|
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| 203 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/adderout |
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| 204 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/macmuxsel |
|
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| 205 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/op1_d_resz |
|
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| 206 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/op2_d_resz |
|
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| 207 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/macmux2sel |
|
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| 208 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/add_d |
|
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| 209 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/op1_d |
|
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| 210 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/op2_d |
|
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| 211 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/multout_d |
|
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| 212 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/macmuxsel_d |
|
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| 213 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/macmux2sel_d |
|
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| 214 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/macmux2sel_d_d |
|
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| 215 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/clr_mac_d |
|
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| 216 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/clr_mac_d_d |
|
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| 217 | add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/sample_out_val |
|
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| 218 | add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/sample_out_rot |
|
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| 219 | add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/iir_cel_state |
|
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| 220 | add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/sample_out |
|
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| 221 | add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_val_s |
|
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| 222 | add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_val_s2 |
|
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| 223 | add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_rot_s |
|
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| 224 | add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s |
|
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| 225 | add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2 |
|
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| 226 | TreeUpdate [SetDefaultTree] |
|
33 | TreeUpdate [SetDefaultTree] | |
| 227 |
WaveRestoreCursors {{Cursor 1} { |
|
34 | WaveRestoreCursors {{Cursor 1} {0 ps} 0} | |
| 228 |
configure wave -namecolwidth |
|
35 | configure wave -namecolwidth 430 | |
| 229 | configure wave -valuecolwidth 100 |
|
36 | configure wave -valuecolwidth 100 | |
| 230 | configure wave -justifyvalue left |
|
37 | configure wave -justifyvalue left | |
| 231 | configure wave -signalnamewidth 0 |
|
38 | configure wave -signalnamewidth 0 | |
| @@ -239,4 +46,4 configure wave -griddelta 40 | |||||
| 239 | configure wave -timeline 0 |
|
46 | configure wave -timeline 0 | |
| 240 | configure wave -timelineunits ns |
|
47 | configure wave -timelineunits ns | |
| 241 | update |
|
48 | update | |
| 242 |
WaveRestoreZoom { |
|
49 | WaveRestoreZoom {0 ps} {754717 ps} | |
| @@ -1,212 +1,213 | |||||
| 1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
| 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
| 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
| 4 | -- |
|
4 | -- | |
| 5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
| 6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
| 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
| 8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
| 9 | -- |
|
9 | -- | |
| 10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
| 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
| 14 | -- |
|
14 | -- | |
| 15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
| 16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
| 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
| 19 | -- Author : Alexis Jeandet |
|
19 | -- Author : Alexis Jeandet | |
| 20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr |
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |
| 21 | ------------------------------------------------------------------------------- |
|
21 | ------------------------------------------------------------------------------- | |
| 22 | library ieee; |
|
22 | library ieee; | |
| 23 | use ieee.std_logic_1164.all; |
|
23 | use ieee.std_logic_1164.all; | |
| 24 | use ieee.numeric_std.all; |
|
24 | use ieee.numeric_std.all; | |
| 25 | library grlib; |
|
25 | library grlib; | |
| 26 | use grlib.amba.all; |
|
26 | use grlib.amba.all; | |
| 27 | use grlib.stdlib.all; |
|
27 | use grlib.stdlib.all; | |
| 28 | use grlib.devices.all; |
|
28 | use grlib.devices.all; | |
| 29 | library lpp; |
|
29 | library lpp; | |
| 30 | use lpp.iir_filter.all; |
|
30 | use lpp.iir_filter.all; | |
| 31 | use lpp.general_purpose.all; |
|
31 | use lpp.general_purpose.all; | |
| 32 | use lpp.lpp_amba.all; |
|
32 | use lpp.lpp_amba.all; | |
| 33 | use lpp.apb_devices_list.all; |
|
33 | use lpp.apb_devices_list.all; | |
| 34 |
|
34 | |||
| 35 | entity APB_IIR_CEL is |
|
35 | entity APB_IIR_CEL is | |
| 36 | generic ( |
|
36 | generic ( | |
| 37 | tech : integer := 0; |
|
37 | tech : integer := 0; | |
| 38 | pindex : integer := 0; |
|
38 | pindex : integer := 0; | |
| 39 | paddr : integer := 0; |
|
39 | paddr : integer := 0; | |
| 40 | pmask : integer := 16#fff#; |
|
40 | pmask : integer := 16#fff#; | |
| 41 | pirq : integer := 0; |
|
41 | pirq : integer := 0; | |
| 42 | abits : integer := 8; |
|
42 | abits : integer := 8; | |
| 43 | Sample_SZ : integer := 16; |
|
43 | Sample_SZ : integer := 16; | |
| 44 | ChanelsCount : integer := 1; |
|
44 | ChanelsCount : integer := 1; | |
| 45 | Coef_SZ : integer := 9; |
|
45 | Coef_SZ : integer := 9; | |
| 46 | CoefCntPerCel: integer := 6; |
|
46 | CoefCntPerCel: integer := 6; | |
| 47 | Cels_count : integer := 5; |
|
47 | Cels_count : integer := 5; | |
| 48 | virgPos : integer := 3; |
|
48 | virgPos : integer := 3; | |
| 49 | Mem_use : integer := use_RAM |
|
49 | Mem_use : integer := use_RAM | |
| 50 | ); |
|
50 | ); | |
| 51 | port ( |
|
51 | port ( | |
| 52 | rst : in std_logic; |
|
52 | rst : in std_logic; | |
| 53 | clk : in std_logic; |
|
53 | clk : in std_logic; | |
| 54 | apbi : in apb_slv_in_type; |
|
54 | apbi : in apb_slv_in_type; | |
| 55 | apbo : out apb_slv_out_type; |
|
55 | apbo : out apb_slv_out_type; | |
| 56 | sample_clk : in std_logic; |
|
56 | sample_clk : in std_logic; | |
| 57 | sample_clk_out : out std_logic; |
|
57 | sample_clk_out : out std_logic; | |
| 58 | sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0); |
|
58 | sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0); | |
| 59 | sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0); |
|
59 | sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0); | |
| 60 | CoefsInitVal : in std_logic_vector((Cels_count*CoefCntPerCel*Coef_SZ)-1 downto 0) := (others => '1') |
|
60 | CoefsInitVal : in std_logic_vector((Cels_count*CoefCntPerCel*Coef_SZ)-1 downto 0) := (others => '1') | |
| 61 | ); |
|
61 | ); | |
| 62 | end; |
|
62 | end; | |
| 63 |
|
63 | |||
| 64 |
|
64 | |||
| 65 | architecture AR_APB_IIR_CEL of APB_IIR_CEL is |
|
65 | architecture AR_APB_IIR_CEL of APB_IIR_CEL is | |
| 66 |
|
66 | |||
| 67 | constant REVISION : integer := 1; |
|
67 | constant REVISION : integer := 1; | |
| 68 |
|
68 | |||
| 69 | constant pconfig : apb_config_type := ( |
|
69 | constant pconfig : apb_config_type := ( | |
| 70 | 0 => ahb_device_reg (VENDOR_LPP, LPP_IIR_CEL_FILTER, 0, REVISION, 0), |
|
70 | 0 => ahb_device_reg (VENDOR_LPP, LPP_IIR_CEL_FILTER, 0, REVISION, 0), | |
| 71 | 1 => apb_iobar(paddr, pmask)); |
|
71 | 1 => apb_iobar(paddr, pmask)); | |
| 72 |
|
72 | |||
| 73 |
|
73 | |||
| 74 |
|
74 | |||
| 75 | type FILTERreg is record |
|
75 | type FILTERreg is record | |
| 76 | regin : in_IIR_CEL_reg; |
|
76 | regin : in_IIR_CEL_reg; | |
| 77 | regout : out_IIR_CEL_reg; |
|
77 | regout : out_IIR_CEL_reg; | |
| 78 | end record; |
|
78 | end record; | |
| 79 |
|
79 | |||
| 80 | signal Rdata : std_logic_vector(31 downto 0); |
|
80 | signal Rdata : std_logic_vector(31 downto 0); | |
| 81 | signal r : FILTERreg; |
|
81 | signal r : FILTERreg; | |
| 82 | signal filter_reset : std_logic:='0'; |
|
82 | signal filter_reset : std_logic:='0'; | |
| 83 | signal smp_cnt : integer :=0; |
|
83 | signal smp_cnt : integer :=0; | |
| 84 | signal sample_clk_out_R : std_logic; |
|
84 | signal sample_clk_out_R : std_logic; | |
| 85 | signal RawCoefs : std_logic_vector(((Coef_SZ*CoefCntPerCel*Cels_count)-1) downto 0); |
|
85 | signal RawCoefs : std_logic_vector(((Coef_SZ*CoefCntPerCel*Cels_count)-1) downto 0); | |
| 86 |
|
86 | |||
| 87 | type CoefCelT is array(0 to (CoefCntPerCel/2)-1) of std_logic_vector(Coef_SZ-1 downto 0); |
|
87 | type CoefCelT is array(0 to (CoefCntPerCel/2)-1) of std_logic_vector(Coef_SZ-1 downto 0); | |
| 88 | type CoefTblT is array(0 to Cels_count-1) of CoefCelT; |
|
88 | type CoefTblT is array(0 to Cels_count-1) of CoefCelT; | |
| 89 |
|
89 | |||
| 90 | type CoefsRegT is record |
|
90 | type CoefsRegT is record | |
| 91 | numCoefs : CoefTblT; |
|
91 | numCoefs : CoefTblT; | |
| 92 | denCoefs : CoefTblT; |
|
92 | denCoefs : CoefTblT; | |
| 93 | end record; |
|
93 | end record; | |
| 94 |
|
94 | |||
| 95 | signal CoefsReg : CoefsRegT; |
|
95 | signal CoefsReg : CoefsRegT; | |
| 96 | signal CoefsReg_d : CoefsRegT; |
|
96 | signal CoefsReg_d : CoefsRegT; | |
| 97 |
|
97 | |||
| 98 |
|
98 | |||
| 99 | begin |
|
99 | begin | |
| 100 |
|
100 | |||
| 101 | filter_reset <= rst and r.regin.config(0); |
|
101 | filter_reset <= rst and r.regin.config(0); | |
| 102 | sample_clk_out <= sample_clk_out_R; |
|
102 | sample_clk_out <= sample_clk_out_R; | |
| 103 | -- |
|
103 | -- | |
| 104 | filter : IIR_CEL_FILTER |
|
104 | filter : IIR_CEL_FILTER | |
| 105 | generic map(tech,Sample_SZ,ChanelsCount,Coef_SZ,CoefCntPerCel,Cels_count,Mem_use) |
|
105 | generic map(tech,Sample_SZ,ChanelsCount,Coef_SZ,CoefCntPerCel,Cels_count,Mem_use) | |
| 106 | port map( |
|
106 | port map( | |
| 107 | reset => filter_reset, |
|
107 | reset => filter_reset, | |
| 108 | clk => clk, |
|
108 | clk => clk, | |
| 109 | sample_clk => sample_clk, |
|
109 | sample_clk => sample_clk, | |
| 110 | regs_in => r.regin, |
|
110 | regs_in => r.regin, | |
| 111 | regs_out => r.regout, |
|
111 | regs_out => r.regout, | |
| 112 | sample_in => sample_in, |
|
112 | sample_in => sample_in, | |
| 113 | sample_out => sample_out, |
|
113 | sample_out => sample_out, | |
| 114 | coefs => RawCoefs |
|
114 | coefs => RawCoefs | |
| 115 | ); |
|
115 | ); | |
| 116 |
|
116 | |||
| 117 | process(rst,sample_clk) |
|
117 | process(rst,sample_clk) | |
| 118 | begin |
|
118 | begin | |
| 119 | if rst = '0' then |
|
119 | if rst = '0' then | |
| 120 | smp_cnt <= 0; |
|
120 | smp_cnt <= 0; | |
| 121 | sample_clk_out_R <= '0'; |
|
121 | sample_clk_out_R <= '0'; | |
| 122 | elsif sample_clk'event and sample_clk = '1' then |
|
122 | elsif sample_clk'event and sample_clk = '1' then | |
| 123 | if smp_cnt = 1 then |
|
123 | if smp_cnt = 1 then | |
| 124 | smp_cnt <= 0; |
|
124 | smp_cnt <= 0; | |
| 125 | sample_clk_out_R <= not sample_clk_out_R; |
|
125 | sample_clk_out_R <= not sample_clk_out_R; | |
| 126 | else |
|
126 | else | |
| 127 | smp_cnt <= smp_cnt +1; |
|
127 | smp_cnt <= smp_cnt +1; | |
| 128 | end if; |
|
128 | end if; | |
| 129 | end if; |
|
129 | end if; | |
| 130 | end process; |
|
130 | end process; | |
| 131 |
|
131 | |||
| 132 |
|
132 | |||
| 133 | coefsConnectL0: for z in 0 to Cels_count-1 generate |
|
133 | coefsConnectL0: for z in 0 to Cels_count-1 generate | |
| 134 | coefsConnectL1: for y in 0 to (CoefCntPerCel/2)-1 generate |
|
134 | coefsConnectL1: for y in 0 to (CoefCntPerCel/2)-1 generate | |
| 135 | RawCoefs(((((z*CoefCntPerCel+y)+1)*Coef_SZ)-1) downto (((z*CoefCntPerCel+y))*Coef_SZ) ) <= CoefsReg_d.numCoefs(z)(y)(Coef_SZ-1 downto 0); |
|
135 | RawCoefs(((((z*CoefCntPerCel+y)+1)*Coef_SZ)-1) downto (((z*CoefCntPerCel+y))*Coef_SZ) ) <= CoefsReg_d.numCoefs(z)(y)(Coef_SZ-1 downto 0); | |
| 136 | RawCoefs(((((z*CoefCntPerCel+y+(CoefCntPerCel/2))+1)*Coef_SZ)-1) downto ((z*CoefCntPerCel+y+(CoefCntPerCel/2))*Coef_SZ)) <= CoefsReg_d.denCoefs(z)(y)(Coef_SZ-1 downto 0); |
|
136 | RawCoefs(((((z*CoefCntPerCel+y+(CoefCntPerCel/2))+1)*Coef_SZ)-1) downto ((z*CoefCntPerCel+y+(CoefCntPerCel/2))*Coef_SZ)) <= CoefsReg_d.denCoefs(z)(y)(Coef_SZ-1 downto 0); | |
| 137 | end generate; |
|
137 | end generate; | |
| 138 | end generate; |
|
138 | end generate; | |
| 139 |
|
139 | |||
| 140 |
|
140 | |||
| 141 | process(rst,clk) |
|
141 | process(rst,clk) | |
| 142 | begin |
|
142 | begin | |
| 143 | if rst = '0' then |
|
143 | if rst = '0' then | |
| 144 | r.regin.virgPos <= std_logic_vector(to_unsigned(virgPos,5)); |
|
144 | r.regin.virgPos <= std_logic_vector(to_unsigned(virgPos,5)); | |
| 145 | coefsRstL0: for z in 0 to Cels_count-1 loop |
|
145 | coefsRstL0: for z in 0 to Cels_count-1 loop | |
| 146 | coefsRstL1: for y in 0 to (CoefCntPerCel/2)-1 loop |
|
146 | coefsRstL1: for y in 0 to (CoefCntPerCel/2)-1 loop | |
| 147 | CoefsReg.numCoefs(z)(y) <= CoefsInitVal(((((z*CoefCntPerCel+y)+1)*Coef_SZ)-1) downto (((z*CoefCntPerCel+y))*Coef_SZ) ); |
|
147 | CoefsReg.numCoefs(z)(y) <= CoefsInitVal(((((z*CoefCntPerCel+y)+1)*Coef_SZ)-1) downto (((z*CoefCntPerCel+y))*Coef_SZ) ); | |
| 148 | CoefsReg.denCoefs(z)(y) <= CoefsInitVal(((((z*CoefCntPerCel+y+(CoefCntPerCel/2))+1)*Coef_SZ)-1) downto ((z*CoefCntPerCel+y+(CoefCntPerCel/2))*Coef_SZ)); |
|
148 | CoefsReg.denCoefs(z)(y) <= CoefsInitVal(((((z*CoefCntPerCel+y+(CoefCntPerCel/2))+1)*Coef_SZ)-1) downto ((z*CoefCntPerCel+y+(CoefCntPerCel/2))*Coef_SZ)); | |
| 149 | end loop; |
|
149 | end loop; | |
| 150 | end loop; |
|
150 | end loop; | |
| 151 | elsif clk'event and clk = '1' then |
|
151 | elsif clk'event and clk = '1' then | |
| 152 | CoefsReg_d <= CoefsReg; |
|
152 | CoefsReg_d <= CoefsReg; | |
| 153 |
|
153 | |||
| 154 | --APB Write OP |
|
154 | --APB Write OP | |
| 155 | if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then |
|
155 | if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then | |
| 156 | if apbi.paddr(7 downto 2) = "000000" then |
|
156 | if apbi.paddr(7 downto 2) = "000000" then | |
| 157 | r.regin.config(0) <= apbi.pwdata(0); |
|
157 | r.regin.config(0) <= apbi.pwdata(0); | |
| 158 | elsif apbi.paddr(7 downto 2) = "000001" then |
|
158 | elsif apbi.paddr(7 downto 2) = "000001" then | |
| 159 | r.regin.virgPos <= apbi.pwdata(4 downto 0); |
|
159 | r.regin.virgPos <= apbi.pwdata(4 downto 0); | |
| 160 | else |
|
160 | else | |
| 161 | for i in 0 to Cels_count-1 loop |
|
161 | for i in 0 to Cels_count-1 loop | |
| 162 | for j in 0 to (CoefCntPerCel/2) - 1 loop |
|
162 | for j in 0 to (CoefCntPerCel/2) - 1 loop | |
| 163 | if apbi.paddr(9 downto 2) = std_logic_vector(TO_UNSIGNED((2+ (i*(CoefCntPerCel/2))+j),8)) then |
|
163 | if apbi.paddr(9 downto 2) = std_logic_vector(TO_UNSIGNED((2+ (i*(CoefCntPerCel/2))+j),8)) then | |
| 164 | CoefsReg.numCoefs(i)(j) <= apbi.pwdata(Coef_SZ-1 downto 0); |
|
164 | CoefsReg.numCoefs(i)(j) <= apbi.pwdata(Coef_SZ-1 downto 0); | |
| 165 | CoefsReg.denCoefs(i)(j) <= apbi.pwdata((Coef_SZ+15) downto 16); |
|
165 | CoefsReg.denCoefs(i)(j) <= apbi.pwdata((Coef_SZ+15) downto 16); | |
| 166 | end if; |
|
166 | end if; | |
| 167 | end loop; |
|
167 | end loop; | |
| 168 | end loop; |
|
168 | end loop; | |
| 169 | end if; |
|
169 | end if; | |
| 170 | end if; |
|
170 | end if; | |
| 171 |
|
171 | |||
| 172 | --APB READ OP |
|
172 | --APB READ OP | |
| 173 | if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then |
|
173 | if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then | |
| 174 | if apbi.paddr(7 downto 2) = "000000" then |
|
174 | if apbi.paddr(7 downto 2) = "000000" then | |
| 175 | Rdata(7 downto 0) <= std_logic_vector(TO_UNSIGNED(ChanelsCount,8)); |
|
175 | Rdata(7 downto 0) <= std_logic_vector(TO_UNSIGNED(ChanelsCount,8)); | |
| 176 | Rdata(15 downto 8) <= std_logic_vector(TO_UNSIGNED(Sample_SZ,8)); |
|
176 | Rdata(15 downto 8) <= std_logic_vector(TO_UNSIGNED(Sample_SZ,8)); | |
| 177 | Rdata(23 downto 16) <= std_logic_vector(TO_UNSIGNED(CoefCntPerCel,8)); |
|
177 | Rdata(23 downto 16) <= std_logic_vector(TO_UNSIGNED(CoefCntPerCel,8)); | |
| 178 | Rdata(31 downto 24) <= std_logic_vector(TO_UNSIGNED(Cels_count,8)); |
|
178 | Rdata(31 downto 24) <= std_logic_vector(TO_UNSIGNED(Cels_count,8)); | |
| 179 | elsif apbi.paddr(7 downto 2) = "000001" then |
|
179 | elsif apbi.paddr(7 downto 2) = "000001" then | |
| 180 | Rdata(4 downto 0) <= r.regin.virgPos; |
|
180 | Rdata(4 downto 0) <= r.regin.virgPos; | |
| 181 | Rdata(15 downto 8) <= std_logic_vector(TO_UNSIGNED(Coef_SZ,8)); |
|
181 | Rdata(15 downto 8) <= std_logic_vector(TO_UNSIGNED(Coef_SZ,8)); | |
| 182 | Rdata(7 downto 5) <= (others => '0'); |
|
182 | Rdata(7 downto 5) <= (others => '0'); | |
| 183 | Rdata(31 downto 16) <= (others => '0'); |
|
183 | Rdata(31 downto 16) <= (others => '0'); | |
| 184 | else |
|
184 | else | |
| 185 | for i in 0 to Cels_count-1 loop |
|
185 | for i in 0 to Cels_count-1 loop | |
| 186 | for j in 0 to (CoefCntPerCel/2) - 1 loop |
|
186 | for j in 0 to (CoefCntPerCel/2) - 1 loop | |
| 187 | if apbi.paddr(9 downto 2) = std_logic_vector(TO_UNSIGNED((2+ (i*(CoefCntPerCel/2))+j),8)) then |
|
187 | if apbi.paddr(9 downto 2) = std_logic_vector(TO_UNSIGNED((2+ (i*(CoefCntPerCel/2))+j),8)) then | |
| 188 | Rdata(Coef_SZ-1 downto 0) <= CoefsReg_d.numCoefs(i)(j); |
|
188 | Rdata(Coef_SZ-1 downto 0) <= CoefsReg_d.numCoefs(i)(j); | |
| 189 | Rdata((Coef_SZ+15) downto 16) <= CoefsReg_d.denCoefs(i)(j); |
|
189 | Rdata((Coef_SZ+15) downto 16) <= CoefsReg_d.denCoefs(i)(j); | |
| 190 | end if; |
|
190 | end if; | |
| 191 | end loop; |
|
191 | end loop; | |
| 192 | end loop; |
|
192 | end loop; | |
| 193 | end if; |
|
193 | end if; | |
| 194 | end if; |
|
194 | end if; | |
| 195 | end if; |
|
195 | end if; | |
| 196 | apbo.pconfig <= pconfig; |
|
196 | apbo.pconfig <= pconfig; | |
| 197 | end process; |
|
197 | end process; | |
| 198 |
|
198 | |||
| 199 | apbo.prdata <= Rdata when apbi.penable = '1' ; |
|
199 | apbo.prdata <= Rdata when apbi.penable = '1' ; | |
| 200 |
|
200 | |||
| 201 | -- pragma translate_off |
|
201 | -- pragma translate_off | |
| 202 | bootmsg : report_version |
|
202 | bootmsg : report_version | |
| 203 | generic map ("apb IIR filter" & tost(pindex) & |
|
203 | generic map ("apb IIR filter" & tost(pindex) & | |
| 204 |
": IIR filter rev " & tost(REVISION) |
|
204 | ": IIR filter rev " & tost(REVISION)& | |
| 205 |
|
|
205 | --", fifo " & tost(fifosize) & | |
| 206 | -- pragma translate_on |
|
206 | ", irq " & tost(pirq)); | |
| 207 |
|
207 | -- pragma translate_on | ||
| 208 |
|
208 | |||
| 209 |
|
209 | |||
| 210 |
|
210 | |||
| 211 | end ar_APB_IIR_CEL; |
|
211 | ||
| 212 |
|
212 | end ar_APB_IIR_CEL; | ||
|
|
213 | ||||
| @@ -63,7 +63,7 begin | |||||
| 63 | --============================================================== |
|
63 | --============================================================== | |
| 64 | --=========================A L U================================ |
|
64 | --=========================A L U================================ | |
| 65 | --============================================================== |
|
65 | --============================================================== | |
| 66 |
ALU1 : |
|
66 | ALU1 : ALU | |
| 67 | generic map( |
|
67 | generic map( | |
| 68 | Arith_en => 1, |
|
68 | Arith_en => 1, | |
| 69 | Logic_en => 0, |
|
69 | Logic_en => 0, | |
| @@ -196,7 +196,8 BEGIN | |||||
| 196 | GENERIC MAP ( |
|
196 | GENERIC MAP ( | |
| 197 | Arith_en => 1, |
|
197 | Arith_en => 1, | |
| 198 | Input_SZ_1 => Sample_SZ, |
|
198 | Input_SZ_1 => Sample_SZ, | |
| 199 |
Input_SZ_2 => Coef_SZ |
|
199 | Input_SZ_2 => Coef_SZ, | |
|
|
200 | COMP_EN => 1) | |||
| 200 | PORT MAP ( |
|
201 | PORT MAP ( | |
| 201 | clk => clk, |
|
202 | clk => clk, | |
| 202 | reset => rstn, |
|
203 | reset => rstn, | |
| @@ -72,7 +72,7 BEGIN | |||||
| 72 | memCEL : IF Mem_use = use_CEL GENERATE |
|
72 | memCEL : IF Mem_use = use_CEL GENERATE | |
| 73 | WEN <= NOT ram_write; |
|
73 | WEN <= NOT ram_write; | |
| 74 | REN <= NOT ram_read; |
|
74 | REN <= NOT ram_read; | |
| 75 | RAMblk : RAM_CEL |
|
75 | RAMblk : RAM_CEL_N | |
| 76 | GENERIC MAP(Input_SZ_1) |
|
76 | GENERIC MAP(Input_SZ_1) | |
| 77 | PORT MAP( |
|
77 | PORT MAP( | |
| 78 | WD => WD, |
|
78 | WD => WD, | |
| @@ -216,6 +216,18 PACKAGE iir_filter IS | |||||
| 216 | RWCLK, RESET : IN STD_LOGIC); |
|
216 | RWCLK, RESET : IN STD_LOGIC); | |
| 217 | END COMPONENT; |
|
217 | END COMPONENT; | |
| 218 |
|
218 | |||
|
|
219 | COMPONENT RAM_CEL_N | |||
|
|
220 | GENERIC ( | |||
|
|
221 | size : INTEGER); | |||
|
|
222 | PORT ( | |||
|
|
223 | WD : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0); | |||
|
|
224 | RD : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0); | |||
|
|
225 | WEN, REN : IN STD_LOGIC; | |||
|
|
226 | WADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |||
|
|
227 | RADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |||
|
|
228 | RWCLK, RESET : IN STD_LOGIC); | |||
|
|
229 | END COMPONENT; | |||
|
|
230 | ||||
| 219 | COMPONENT IIR_CEL_FILTER IS |
|
231 | COMPONENT IIR_CEL_FILTER IS | |
| 220 | GENERIC( |
|
232 | GENERIC( | |
| 221 | tech : INTEGER := 0; |
|
233 | tech : INTEGER := 0; | |
| @@ -22,9 +22,10 | |||||
| 22 | library IEEE; |
|
22 | library IEEE; | |
| 23 | use IEEE.std_logic_1164.all; |
|
23 | use IEEE.std_logic_1164.all; | |
| 24 | use IEEE.numeric_std.all; |
|
24 | use IEEE.numeric_std.all; | |
| 25 | library lpp; |
|
25 | use work.fft_components.all; | |
| 26 | use lpp.lpp_fft.all; |
|
26 | use lpp.lpp_fft.all; | |
| 27 | use work.fft_components.all; |
|
27 | ||
|
|
28 | -- Update possible lecture (ren) de fifo en continu, pendant un Load, au lieu d'une lecture "cr�neau" | |||
| 28 |
|
29 | |||
| 29 | entity FFT is |
|
30 | entity FFT is | |
| 30 | generic( |
|
31 | generic( | |
| @@ -36,6 +37,7 entity FFT is | |||||
| 36 | FifoIN_Empty : in std_logic_vector(4 downto 0); |
|
37 | FifoIN_Empty : in std_logic_vector(4 downto 0); | |
| 37 | FifoIN_Data : in std_logic_vector(79 downto 0); |
|
38 | FifoIN_Data : in std_logic_vector(79 downto 0); | |
| 38 | FifoOUT_Full : in std_logic_vector(4 downto 0); |
|
39 | FifoOUT_Full : in std_logic_vector(4 downto 0); | |
|
|
40 | Load : out std_logic; | |||
| 39 | Read : out std_logic_vector(4 downto 0); |
|
41 | Read : out std_logic_vector(4 downto 0); | |
| 40 | Write : out std_logic_vector(4 downto 0); |
|
42 | Write : out std_logic_vector(4 downto 0); | |
| 41 | ReUse : out std_logic_vector(4 downto 0); |
|
43 | ReUse : out std_logic_vector(4 downto 0); | |
| @@ -62,6 +64,7 signal Link_Read : std_logic; | |||||
| 62 | begin |
|
64 | begin | |
| 63 |
|
65 | |||
| 64 | Start <= '0'; |
|
66 | Start <= '0'; | |
|
|
67 | Load <= FFT_Load; | |||
| 65 |
|
68 | |||
| 66 | DRIVE : Driver_FFT |
|
69 | DRIVE : Driver_FFT | |
| 67 | generic map(Data_sz,NbData) |
|
70 | generic map(Data_sz,NbData) | |
| @@ -84,6 +84,7 component FFT is | |||||
| 84 | FifoIN_Empty : in std_logic_vector(4 downto 0); |
|
84 | FifoIN_Empty : in std_logic_vector(4 downto 0); | |
| 85 | FifoIN_Data : in std_logic_vector(79 downto 0); |
|
85 | FifoIN_Data : in std_logic_vector(79 downto 0); | |
| 86 | FifoOUT_Full : in std_logic_vector(4 downto 0); |
|
86 | FifoOUT_Full : in std_logic_vector(4 downto 0); | |
|
|
87 | Load : out std_logic; | |||
| 87 | Read : out std_logic_vector(4 downto 0); |
|
88 | Read : out std_logic_vector(4 downto 0); | |
| 88 | Write : out std_logic_vector(4 downto 0); |
|
89 | Write : out std_logic_vector(4 downto 0); | |
| 89 | ReUse : out std_logic_vector(4 downto 0); |
|
90 | ReUse : out std_logic_vector(4 downto 0); | |
| @@ -32,7 +32,9 generic( | |||||
| 32 | Arith_en : integer := 1; |
|
32 | Arith_en : integer := 1; | |
| 33 | Logic_en : integer := 1; |
|
33 | Logic_en : integer := 1; | |
| 34 | Input_SZ_1 : integer := 16; |
|
34 | Input_SZ_1 : integer := 16; | |
| 35 |
Input_SZ_2 : integer := 16 |
|
35 | Input_SZ_2 : integer := 16; | |
|
|
36 | COMP_EN : INTEGER := 0 -- 1 => No Comp | |||
|
|
37 | ); | |||
| 36 | port( |
|
38 | port( | |
| 37 | clk : in std_logic; --! Horloge du composant |
|
39 | clk : in std_logic; --! Horloge du composant | |
| 38 | reset : in std_logic; --! Reset general du composant |
|
40 | reset : in std_logic; --! Reset general du composant | |
| @@ -56,8 +58,8 begin | |||||
| 56 |
|
58 | |||
| 57 | arith : if Arith_en = 1 generate |
|
59 | arith : if Arith_en = 1 generate | |
| 58 | MACinst : MAC |
|
60 | MACinst : MAC | |
| 59 | generic map(Input_SZ_1,Input_SZ_2) |
|
61 | generic map(Input_SZ_1,Input_SZ_2,COMP_EN) | |
| 60 | port map(clk,reset,ctrl(2),ctrl(1 downto 0),comp,OP1,OP2,RES); |
|
62 | port map(clk,reset,ctrl(2),ctrl(1 downto 0),comp,OP1,OP2,RES); | |
| 61 | end generate; |
|
63 | end generate; | |
| 62 |
|
64 | |||
| 63 | end architecture; No newline at end of file |
|
65 | end architecture; | |
| @@ -22,10 +22,6 | |||||
| 22 | LIBRARY IEEE; |
|
22 | LIBRARY IEEE; | |
| 23 | USE IEEE.numeric_std.ALL; |
|
23 | USE IEEE.numeric_std.ALL; | |
| 24 | USE IEEE.std_logic_1164.ALL; |
|
24 | USE IEEE.std_logic_1164.ALL; | |
| 25 | LIBRARY lpp; |
|
|||
| 26 | USE lpp.general_purpose.ALL; |
|
|||
| 27 |
|
||||
| 28 |
|
||||
| 29 |
|
25 | |||
| 30 | ENTITY Adder IS |
|
26 | ENTITY Adder IS | |
| 31 | GENERIC( |
|
27 | GENERIC( | |
| @@ -32,7 +32,8 USE lpp.general_purpose.ALL; | |||||
| 32 | ENTITY MAC IS |
|
32 | ENTITY MAC IS | |
| 33 | GENERIC( |
|
33 | GENERIC( | |
| 34 | Input_SZ_A : INTEGER := 8; |
|
34 | Input_SZ_A : INTEGER := 8; | |
| 35 | Input_SZ_B : INTEGER := 8 |
|
35 | Input_SZ_B : INTEGER := 8; | |
|
|
36 | COMP_EN : INTEGER := 0 -- 1 => No Comp | |||
| 36 |
|
37 | |||
| 37 | ); |
|
38 | ); | |
| 38 | PORT( |
|
39 | PORT( | |
| @@ -52,35 +53,35 END MAC; | |||||
| 52 |
|
53 | |||
| 53 | ARCHITECTURE ar_MAC OF MAC IS |
|
54 | ARCHITECTURE ar_MAC OF MAC IS | |
| 54 |
|
55 | |||
| 55 | signal add,mult : std_logic; |
|
56 | SIGNAL add, mult : STD_LOGIC; | |
| 56 |
|
|
57 | SIGNAL MULTout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); | |
| 57 |
|
58 | |||
| 58 |
|
|
59 | SIGNAL ADDERinA : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); | |
| 59 |
|
|
60 | SIGNAL ADDERinB : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); | |
| 60 |
|
|
61 | SIGNAL ADDERout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); | |
| 61 |
|
62 | |||
| 62 | signal MACMUXsel : std_logic; |
|
63 | SIGNAL MACMUXsel : STD_LOGIC; | |
| 63 |
|
|
64 | SIGNAL OP1_2C_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); | |
| 64 |
|
|
65 | SIGNAL OP2_2C_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); | |
| 65 |
|
66 | |||
| 66 | signal OP1_2C : std_logic_vector(Input_SZ_A-1 downto 0); |
|
67 | SIGNAL OP1_2C : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); | |
| 67 | signal OP2_2C : std_logic_vector(Input_SZ_B-1 downto 0); |
|
68 | SIGNAL OP2_2C : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); | |
| 68 |
|
69 | |||
| 69 | signal MACMUX2sel : std_logic; |
|
70 | SIGNAL MACMUX2sel : STD_LOGIC; | |
| 70 |
|
71 | |||
| 71 | signal add_D : std_logic; |
|
72 | SIGNAL add_D : STD_LOGIC; | |
| 72 | signal OP1_2C_D : std_logic_vector(Input_SZ_A-1 downto 0); |
|
73 | SIGNAL OP1_2C_D : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); | |
| 73 | signal OP2_2C_D : std_logic_vector(Input_SZ_B-1 downto 0); |
|
74 | SIGNAL OP2_2C_D : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); | |
| 74 |
|
|
75 | SIGNAL MULTout_D : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); | |
| 75 | signal MACMUXsel_D : std_logic; |
|
76 | SIGNAL MACMUXsel_D : STD_LOGIC; | |
| 76 | signal MACMUX2sel_D : std_logic; |
|
77 | SIGNAL MACMUX2sel_D : STD_LOGIC; | |
| 77 | signal MACMUX2sel_D_D : std_logic; |
|
78 | SIGNAL MACMUX2sel_D_D : STD_LOGIC; | |
| 78 | signal clr_MAC_D : std_logic; |
|
79 | SIGNAL clr_MAC_D : STD_LOGIC; | |
| 79 | signal clr_MAC_D_D : std_logic; |
|
80 | SIGNAL clr_MAC_D_D : STD_LOGIC; | |
| 80 | signal MAC_MUL_ADD_2C_D : std_logic_vector(1 downto 0); |
|
81 | SIGNAL MAC_MUL_ADD_2C_D : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
| 81 |
|
82 | |||
| 82 | SIGNAL load_mult_result : STD_LOGIC; |
|
83 | SIGNAL load_mult_result : STD_LOGIC; | |
| 83 | SIGNAL load_mult_result_D : STD_LOGIC; |
|
84 | SIGNAL load_mult_result_D : STD_LOGIC; | |
| 84 |
|
85 | |||
| 85 | BEGIN |
|
86 | BEGIN | |
| 86 |
|
87 | |||
| @@ -113,25 +114,25 BEGIN | |||||
| 113 | Input_SZ_A => Input_SZ_A, |
|
114 | Input_SZ_A => Input_SZ_A, | |
| 114 | Input_SZ_B => Input_SZ_B |
|
115 | Input_SZ_B => Input_SZ_B | |
| 115 | ) |
|
116 | ) | |
| 116 | port map( |
|
117 | PORT MAP( | |
| 117 |
clk |
|
118 | clk => clk, | |
| 118 |
reset |
|
119 | reset => reset, | |
| 119 |
mult |
|
120 | mult => mult, | |
| 120 |
OP1 |
|
121 | OP1 => OP1_2C, | |
| 121 |
OP2 |
|
122 | OP2 => OP2_2C, | |
| 122 |
RES |
|
123 | RES => MULTout | |
| 123 | ); |
|
124 | ); | |
| 124 | --============================================================== |
|
125 | --============================================================== | |
| 125 |
|
126 | |||
| 126 | PROCESS (clk, reset) |
|
127 | PROCESS (clk, reset) | |
| 127 | BEGIN -- PROCESS |
|
128 | BEGIN -- PROCESS | |
| 128 | IF reset = '0' THEN -- asynchronous reset (active low) |
|
129 | IF reset = '0' THEN -- asynchronous reset (active low) | |
| 129 | load_mult_result_D <= '0'; |
|
130 | load_mult_result_D <= '0'; | |
| 130 |
ELSIF clk' |
|
131 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
| 131 | load_mult_result_D <= load_mult_result; |
|
132 | load_mult_result_D <= load_mult_result; | |
| 132 | END IF; |
|
133 | END IF; | |
| 133 | END PROCESS; |
|
134 | END PROCESS; | |
| 134 |
|
135 | |||
| 135 | --============================================================== |
|
136 | --============================================================== | |
| 136 | --======================A D D E R ============================== |
|
137 | --======================A D D E R ============================== | |
| 137 | --============================================================== |
|
138 | --============================================================== | |
| @@ -154,32 +155,38 port map( | |||||
| 154 | --============================================================== |
|
155 | --============================================================== | |
| 155 | --===================TWO COMPLEMENTERS========================== |
|
156 | --===================TWO COMPLEMENTERS========================== | |
| 156 | --============================================================== |
|
157 | --============================================================== | |
| 157 | TWO_COMPLEMENTER1 : TwoComplementer |
|
158 | gen_comp : IF COMP_EN = 0 GENERATE | |
| 158 | generic map( |
|
159 | TWO_COMPLEMENTER1 : TwoComplementer | |
| 159 | Input_SZ => Input_SZ_A |
|
160 | GENERIC MAP( | |
| 160 | ) |
|
161 | Input_SZ => Input_SZ_A | |
| 161 | port map( |
|
162 | ) | |
| 162 | clk => clk, |
|
163 | PORT MAP( | |
| 163 |
|
|
164 | clk => clk, | |
| 164 | clr => clr_MAC, |
|
165 | reset => reset, | |
| 165 | TwoComp => Comp_2C(0), |
|
166 | clr => clr_MAC, | |
| 166 | OP => OP1, |
|
167 | TwoComp => Comp_2C(0), | |
| 167 |
|
|
168 | OP => OP1, | |
| 168 | ); |
|
169 | RES => OP1_2C | |
|
|
170 | ); | |||
| 169 |
|
171 | |||
| 170 |
|
172 | TWO_COMPLEMENTER2 : TwoComplementer | ||
| 171 | TWO_COMPLEMENTER2 : TwoComplementer |
|
173 | GENERIC MAP( | |
| 172 | generic map( |
|
174 | Input_SZ => Input_SZ_B | |
| 173 | Input_SZ => Input_SZ_B |
|
175 | ) | |
| 174 | ) |
|
176 | PORT MAP( | |
| 175 | port map( |
|
177 | clk => clk, | |
| 176 | clk => clk, |
|
178 | reset => reset, | |
| 177 |
|
|
179 | clr => clr_MAC, | |
| 178 | clr => clr_MAC, |
|
180 | TwoComp => Comp_2C(1), | |
| 179 | TwoComp => Comp_2C(1), |
|
181 | OP => OP2, | |
| 180 |
|
|
182 | RES => OP2_2C | |
| 181 | RES => OP2_2C |
|
183 | ); | |
| 182 | ); |
|
184 | END GENERATE gen_comp; | |
|
|
185 | ||||
|
|
186 | no_gen_comp : IF COMP_EN = 1 GENERATE | |||
|
|
187 | OP2_2C <= OP2; | |||
|
|
188 | OP1_2C <= OP1; | |||
|
|
189 | END GENERATE no_gen_comp; | |||
| 183 | --============================================================== |
|
190 | --============================================================== | |
| 184 |
|
191 | |||
| 185 | clr_MACREG1 : MAC_REG |
|
192 | clr_MACREG1 : MAC_REG | |
| @@ -200,24 +207,24 port map( | |||||
| 200 | Q(0) => add_D |
|
207 | Q(0) => add_D | |
| 201 | ); |
|
208 | ); | |
| 202 |
|
209 | |||
| 203 | OP1REG : MAC_REG |
|
210 | OP1REG : MAC_REG | |
| 204 |
|
|
211 | GENERIC MAP(size => Input_SZ_A) | |
| 205 | port map( |
|
212 | PORT MAP( | |
| 206 |
reset |
|
213 | reset => reset, | |
| 207 |
clk |
|
214 | clk => clk, | |
| 208 |
D |
|
215 | D => OP1_2C, | |
| 209 |
Q |
|
216 | Q => OP1_2C_D | |
| 210 | ); |
|
217 | ); | |
| 211 |
|
218 | |||
| 212 |
|
219 | |||
| 213 | OP2REG : MAC_REG |
|
220 | OP2REG : MAC_REG | |
| 214 |
|
|
221 | GENERIC MAP(size => Input_SZ_B) | |
| 215 | port map( |
|
222 | PORT MAP( | |
| 216 |
reset |
|
223 | reset => reset, | |
| 217 |
clk |
|
224 | clk => clk, | |
| 218 |
D |
|
225 | D => OP2_2C, | |
| 219 |
Q |
|
226 | Q => OP2_2C_D | |
| 220 | ); |
|
227 | ); | |
| 221 |
|
228 | |||
| 222 | MULToutREG : MAC_REG |
|
229 | MULToutREG : MAC_REG | |
| 223 | GENERIC MAP(size => Input_SZ_A+Input_SZ_B) |
|
230 | GENERIC MAP(size => Input_SZ_A+Input_SZ_B) | |
| @@ -22,9 +22,6 | |||||
| 22 | library IEEE; |
|
22 | library IEEE; | |
| 23 | use IEEE.numeric_std.all; |
|
23 | use IEEE.numeric_std.all; | |
| 24 | use IEEE.std_logic_1164.all; |
|
24 | use IEEE.std_logic_1164.all; | |
| 25 | library lpp; |
|
|||
| 26 | use lpp.general_purpose.all; |
|
|||
| 27 |
|
||||
| 28 |
|
25 | |||
| 29 | --IDLE =00 MAC =01 MULT =10 ADD =11 |
|
26 | --IDLE =00 MAC =01 MULT =10 ADD =11 | |
| 30 |
|
27 | |||
| @@ -22,10 +22,6 | |||||
| 22 | library IEEE; |
|
22 | library IEEE; | |
| 23 | use IEEE.numeric_std.all; |
|
23 | use IEEE.numeric_std.all; | |
| 24 | use IEEE.std_logic_1164.all; |
|
24 | use IEEE.std_logic_1164.all; | |
| 25 | library lpp; |
|
|||
| 26 | use lpp.general_purpose.all; |
|
|||
| 27 |
|
||||
| 28 |
|
||||
| 29 |
|
25 | |||
| 30 | entity MAC_MUX is |
|
26 | entity MAC_MUX is | |
| 31 | generic( |
|
27 | generic( | |
| @@ -22,9 +22,6 | |||||
| 22 | library IEEE; |
|
22 | library IEEE; | |
| 23 | use IEEE.numeric_std.all; |
|
23 | use IEEE.numeric_std.all; | |
| 24 | use IEEE.std_logic_1164.all; |
|
24 | use IEEE.std_logic_1164.all; | |
| 25 | library lpp; |
|
|||
| 26 | use lpp.general_purpose.all; |
|
|||
| 27 |
|
||||
| 28 |
|
25 | |||
| 29 |
|
26 | |||
| 30 | entity MAC_MUX2 is |
|
27 | entity MAC_MUX2 is | |
| @@ -22,10 +22,6 | |||||
| 22 | library IEEE; |
|
22 | library IEEE; | |
| 23 | use IEEE.numeric_std.all; |
|
23 | use IEEE.numeric_std.all; | |
| 24 | use IEEE.std_logic_1164.all; |
|
24 | use IEEE.std_logic_1164.all; | |
| 25 | library lpp; |
|
|||
| 26 | use lpp.general_purpose.all; |
|
|||
| 27 |
|
||||
| 28 |
|
||||
| 29 |
|
25 | |||
| 30 | entity MAC_REG is |
|
26 | entity MAC_REG is | |
| 31 | generic(size : integer := 16); |
|
27 | generic(size : integer := 16); | |
| @@ -23,11 +23,6 library IEEE; | |||||
| 23 | use IEEE.numeric_std.all; |
|
23 | use IEEE.numeric_std.all; | |
| 24 | use IEEE.std_logic_1164.all; |
|
24 | use IEEE.std_logic_1164.all; | |
| 25 |
|
25 | |||
| 26 | library lpp; |
|
|||
| 27 | use lpp.general_purpose.all; |
|
|||
| 28 |
|
||||
| 29 |
|
||||
| 30 |
|
||||
| 31 | entity Multiplier is |
|
26 | entity Multiplier is | |
| 32 | generic( |
|
27 | generic( | |
| 33 | Input_SZ_A : integer := 16; |
|
28 | Input_SZ_A : integer := 16; | |
| @@ -83,7 +83,8 PACKAGE general_purpose IS | |||||
| 83 | Arith_en : INTEGER := 1; |
|
83 | Arith_en : INTEGER := 1; | |
| 84 | Logic_en : INTEGER := 1; |
|
84 | Logic_en : INTEGER := 1; | |
| 85 | Input_SZ_1 : INTEGER := 16; |
|
85 | Input_SZ_1 : INTEGER := 16; | |
| 86 | Input_SZ_2 : INTEGER := 9 |
|
86 | Input_SZ_2 : INTEGER := 9; | |
|
|
87 | COMP_EN : INTEGER := 0 -- 1 => No Comp | |||
| 87 |
|
88 | |||
| 88 | ); |
|
89 | ); | |
| 89 | PORT( |
|
90 | PORT( | |
| @@ -110,8 +111,8 Constant ctrl_CLRMAC : std_logic_vector( | |||||
| 110 | COMPONENT MAC IS |
|
111 | COMPONENT MAC IS | |
| 111 | GENERIC( |
|
112 | GENERIC( | |
| 112 | Input_SZ_A : INTEGER := 8; |
|
113 | Input_SZ_A : INTEGER := 8; | |
| 113 | Input_SZ_B : INTEGER := 8 |
|
114 | Input_SZ_B : INTEGER := 8; | |
| 114 |
|
115 | COMP_EN : INTEGER := 0 -- 1 => No Comp | ||
| 115 | ); |
|
116 | ); | |
| 116 | PORT( |
|
117 | PORT( | |
| 117 | clk : IN STD_LOGIC; |
|
118 | clk : IN STD_LOGIC; | |
| @@ -15,3 +15,4 REG.vhd | |||||
| 15 | SYNC_FF.vhd |
|
15 | SYNC_FF.vhd | |
| 16 | Shifter.vhd |
|
16 | Shifter.vhd | |
| 17 | general_purpose.vhd |
|
17 | general_purpose.vhd | |
|
|
18 | TwoComplementer.vhd | |||
| @@ -98,14 +98,14 entity leon3mp is | |||||
| 98 | UART_RXD : in std_logic; |
|
98 | UART_RXD : in std_logic; | |
| 99 | UART_TXD : out std_logic; |
|
99 | UART_TXD : out std_logic; | |
| 100 | -- ACQ |
|
100 | -- ACQ | |
| 101 | Clk_49Mhz : IN STD_LOGIC; |
|
|||
| 102 | CNV_CH1 : OUT STD_LOGIC; |
|
101 | CNV_CH1 : OUT STD_LOGIC; | |
| 103 | SCK_CH1 : OUT STD_LOGIC; |
|
102 | SCK_CH1 : OUT STD_LOGIC; | |
| 104 | SDO_CH1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
103 | SDO_CH1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |
|
|
104 | Bias_Fails : out std_logic; | |||
| 105 | -- ADC |
|
105 | -- ADC | |
| 106 | -- ADC_in : in AD7688_in(4 downto 0); |
|
106 | -- ADC_in : in AD7688_in(4 downto 0); | |
| 107 | -- ADC_out : out AD7688_out; |
|
107 | -- ADC_out : out AD7688_out; | |
| 108 | -- Bias_Fails : out std_logic; |
|
108 | ||
| 109 | -- CNA |
|
109 | -- CNA | |
| 110 | -- DAC_SYNC : out std_logic; |
|
110 | -- DAC_SYNC : out std_logic; | |
| 111 | -- DAC_SCLK : out std_logic; |
|
111 | -- DAC_SCLK : out std_logic; | |
| @@ -177,25 +177,17 signal dsuo : dsu_out_type; | |||||
| 177 | --- AJOUT TEST ------------------------Signaux---------------------- |
|
177 | --- AJOUT TEST ------------------------Signaux---------------------- | |
| 178 | --------------------------------------------------------------------- |
|
178 | --------------------------------------------------------------------- | |
| 179 | -- FIFOs |
|
179 | -- FIFOs | |
| 180 |
signal FifoF0 |
|
180 | signal FifoF0_Empty : std_logic_vector(4 downto 0); | |
| 181 |
signal FifoF0 |
|
181 | signal FifoF0_Data : std_logic_vector(79 downto 0); | |
| 182 | signal FifoF0a_Data : std_logic_vector(79 downto 0); |
|
|||
| 183 | signal FifoF0b_Full : std_logic_vector(4 downto 0); |
|
|||
| 184 | signal FifoF0b_Empty : std_logic_vector(4 downto 0); |
|
|||
| 185 | signal FifoF0b_Data : std_logic_vector(79 downto 0); |
|
|||
| 186 | signal FifoF1_Full : std_logic_vector(4 downto 0); |
|
|||
| 187 | signal FifoF1_Empty : std_logic_vector(4 downto 0); |
|
182 | signal FifoF1_Empty : std_logic_vector(4 downto 0); | |
| 188 | signal FifoF1_Data : std_logic_vector(79 downto 0); |
|
183 | signal FifoF1_Data : std_logic_vector(79 downto 0); | |
| 189 | signal FifoF3_Full : std_logic_vector(4 downto 0); |
|
|||
| 190 | signal FifoF3_Empty : std_logic_vector(4 downto 0); |
|
184 | signal FifoF3_Empty : std_logic_vector(4 downto 0); | |
| 191 | signal FifoF3_Data : std_logic_vector(79 downto 0); |
|
185 | signal FifoF3_Data : std_logic_vector(79 downto 0); | |
| 192 |
|
186 | |||
| 193 | signal FifoINT_Full : std_logic_vector(4 downto 0); |
|
187 | signal FifoINT_Full : std_logic_vector(4 downto 0); | |
| 194 | signal FifoINT_Data : std_logic_vector(79 downto 0); |
|
188 | signal FifoINT_Data : std_logic_vector(79 downto 0); | |
| 195 |
|
189 | |||
| 196 | --signal FifoOUT_FullV : std_logic; |
|
|||
| 197 | signal FifoOUT_Full : std_logic_vector(1 downto 0); |
|
190 | signal FifoOUT_Full : std_logic_vector(1 downto 0); | |
| 198 | --signal Matrix_WriteV : std_logic_vector(0 downto 0); |
|
|||
| 199 |
|
191 | |||
| 200 | -- MATRICE SPECTRALE |
|
192 | -- MATRICE SPECTRALE | |
| 201 | signal SM_FlagError : std_logic; |
|
193 | signal SM_FlagError : std_logic; | |
| @@ -207,19 +199,23 signal SM_Data : std_logic_vector(6 | |||||
| 207 | signal Dma_acq : std_logic; |
|
199 | signal Dma_acq : std_logic; | |
| 208 |
|
200 | |||
| 209 | -- FFT |
|
201 | -- FFT | |
|
|
202 | signal FFT_Load : std_logic; | |||
| 210 | signal FFT_Read : std_logic_vector(4 downto 0); |
|
203 | signal FFT_Read : std_logic_vector(4 downto 0); | |
| 211 | signal FFT_Write : std_logic_vector(4 downto 0); |
|
204 | signal FFT_Write : std_logic_vector(4 downto 0); | |
| 212 | signal FFT_ReUse : std_logic_vector(4 downto 0); |
|
205 | signal FFT_ReUse : std_logic_vector(4 downto 0); | |
| 213 | signal FFT_Data : std_logic_vector(79 downto 0); |
|
206 | signal FFT_Data : std_logic_vector(79 downto 0); | |
| 214 |
|
207 | |||
| 215 | -- DEMUX |
|
208 | -- DEMUX | |
| 216 |
signal DEMU_Read : std_logic_vector(1 |
|
209 | signal DEMU_Read : std_logic_vector(14 downto 0); | |
| 217 | signal DEMU_Empty : std_logic_vector(4 downto 0); |
|
210 | signal DEMU_Empty : std_logic_vector(4 downto 0); | |
| 218 | signal DEMU_Data : std_logic_vector(79 downto 0); |
|
211 | signal DEMU_Data : std_logic_vector(79 downto 0); | |
| 219 |
|
212 | |||
| 220 | -- ACQ |
|
213 | -- ACQ | |
| 221 | signal TopACQ_WenF0a : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
214 | ||
| 222 | signal TopACQ_WenF0b : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
215 | signal sample_val : STD_LOGIC; | |
|
|
216 | signal sample : Samples(8-1 DOWNTO 0); | |||
|
|
217 | ||||
|
|
218 | signal TopACQ_WenF0 : STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
| 223 | signal TopACQ_DataF0 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
219 | signal TopACQ_DataF0 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
| 224 | signal TopACQ_WenF1 : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
220 | signal TopACQ_WenF1 : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 225 | signal TopACQ_DataF1 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
221 | signal TopACQ_DataF1 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
| @@ -311,7 +307,7 led(1 downto 0) <= gpio(1 downto 0); | |||||
| 311 | -- port map (clkm,rstn,SmplClk,ADC_DataReady,Fuller,WG_ReUse,WG_Write); |
|
307 | -- port map (clkm,rstn,SmplClk,ADC_DataReady,Fuller,WG_ReUse,WG_Write); | |
| 312 | -- |
|
308 | -- | |
| 313 | --enableADC <= gpio(0); |
|
309 | --enableADC <= gpio(0); | |
| 314 | --Bias_Fails <= '0'; |
|
310 | ||
| 315 | --WG_DATA <= ADC_SmplOut(4) & ADC_SmplOut(3) & ADC_SmplOut(2) & ADC_SmplOut(1) & ADC_SmplOut(0); |
|
311 | --WG_DATA <= ADC_SmplOut(4) & ADC_SmplOut(3) & ADC_SmplOut(2) & ADC_SmplOut(1) & ADC_SmplOut(0); | |
| 316 | -- |
|
312 | -- | |
| 317 | -- |
|
313 | -- | |
| @@ -319,32 +315,68 led(1 downto 0) <= gpio(1 downto 0); | |||||
| 319 | -- generic map (pindex => 6, paddr => 6, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) |
|
315 | -- generic map (pindex => 6, paddr => 6, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) | |
| 320 | -- port map (clkm,rstn,clkm,clkm,WG_ReUse,(others => '1'),WG_Write,open,Fuller,open,WG_DATA,open,open,apbi,apbo(6)); |
|
316 | -- port map (clkm,rstn,clkm,clkm,WG_ReUse,(others => '1'),WG_Write,open,Fuller,open,WG_DATA,open,open,apbi,apbo(6)); | |
| 321 |
|
317 | |||
| 322 | TopACQ : lpp_top_acq |
|
318 | DIGITAL_acquisition : ADS7886_drvr | |
| 323 | port map('1',CNV_CH1,SCK_CH1,SDO_CH1,Clk_49Mhz,rstn,clkm,rstn,TopACQ_WenF0a,TopACQ_WenF0b,TopACQ_DataF0,TopACQ_WenF1,TopACQ_DataF1,open,open,TopACQ_WenF3,TopACQ_DataF3); |
|
319 | GENERIC MAP ( | |
|
|
320 | ChanelCount => 8, | |||
|
|
321 | ncycle_cnv_high => 79, | |||
|
|
322 | ncycle_cnv => 500) | |||
|
|
323 | PORT MAP ( | |||
|
|
324 | cnv_clk => clk50MHz, -- | |||
|
|
325 | cnv_rstn => rstn, -- | |||
|
|
326 | cnv_run => '1', -- | |||
|
|
327 | cnv => CNV_CH1, -- | |||
|
|
328 | clk => clkm, -- | |||
|
|
329 | rstn => rstn, -- | |||
|
|
330 | sck => SCK_CH1, -- | |||
|
|
331 | sdo => SDO_CH1, -- | |||
|
|
332 | sample => sample, | |||
|
|
333 | sample_val => sample_val); | |||
|
|
334 | -- | |||
|
|
335 | TopACQ_WenF0 <= not sample_val & not sample_val & not sample_val & not sample_val & not sample_val; | |||
|
|
336 | TopACQ_DataF0 <= sample(4) & sample(3) & sample(2) & sample(1) & sample(0); | |||
|
|
337 | -- | |||
|
|
338 | TEST(0) <= TopACQ_WenF0(1); | |||
|
|
339 | TEST(1) <= SDO_CH1(1); | |||
|
|
340 | -- | |||
|
|
341 | -- | |||
|
|
342 | -- | |||
|
|
343 | --process(clkm,rstn) | |||
|
|
344 | --begin | |||
|
|
345 | -- if(rstn='0')then | |||
|
|
346 | -- TopACQ_WenF0a <= (others => '1'); | |||
|
|
347 | -- | |||
|
|
348 | -- elsif(clkm'event and clkm='1')then | |||
|
|
349 | -- TopACQ_WenF0a <= not sample_val & not sample_val & not sample_val & not sample_val & not sample_val; | |||
|
|
350 | -- | |||
|
|
351 | -- end if; | |||
|
|
352 | --end process; | |||
| 324 |
|
353 | |||
|
|
354 | -- TopACQ : lpp_top_acq | |||
|
|
355 | -- port map('1',CNV_CH1,SCK_CH1,SDO_CH1,clk50MHz,rstn,clkm,rstn,TopACQ_WenF0,TopACQ_DataF0,TopACQ_WenF1,TopACQ_DataF1,open,open,TopACQ_WenF3,TopACQ_DataF3); | |||
|
|
356 | ||||
|
|
357 | Bias_Fails <= '0'; | |||
| 325 | --- FIFO IN ------------------------------------------------------------- |
|
358 | --- FIFO IN ------------------------------------------------------------- | |
| 326 |
|
359 | |||
| 327 |
Mem |
|
360 | MemOut : APB_FIFO | |
| 328 |
generic map( |
|
361 | generic map (pindex => 9, paddr => 9, FifoCnt => 5, Data_sz => 16, Addr_sz => 9, Enable_ReUse => '0', R => 1, W => 0) | |
| 329 | port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF0a,DEMU_Read(4 downto 0),TopACQ_DataF0,FifoF0a_Data,FifoF0a_Full,FifoF0a_Empty); |
|
362 | port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),TopACQ_WenF0,FifoF0_Empty,open,open,TopACQ_DataF0,open,open,apbi,apbo(9)); | |
|
|
363 | -- Memf0 : lppFIFOxN | |||
|
|
364 | -- generic map(Data_sz => 16, Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0') | |||
|
|
365 | -- port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF0,DEMU_Read(4 downto 0),TopACQ_DataF0,FifoF0_Data,open,FifoF0_Empty); | |||
| 330 |
|
366 | |||
| 331 | Memf0b : lppFIFOxN |
|
|||
| 332 | generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '0') |
|
|||
| 333 | port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF0b,DEMU_Read(9 downto 5),TopACQ_DataF0,FifoF0b_Data,FifoF0b_Full,FifoF0b_Empty); |
|
|||
| 334 |
|
||||
| 335 |
|
|
367 | Memf1 : lppFIFOxN | |
| 336 | generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '0') |
|
368 | generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') | |
| 337 |
port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF1,DEMU_Read( |
|
369 | port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF1,DEMU_Read(9 downto 5),TopACQ_DataF1,FifoF1_Data,open,FifoF1_Empty); | |
| 338 |
|
370 | |||
| 339 | Memf3 : lppFIFOxN |
|
371 | Memf3 : lppFIFOxN | |
| 340 | generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '0') |
|
372 | generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') | |
| 341 |
port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF3,DEMU_Read(1 |
|
373 | port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF3,DEMU_Read(14 downto 10),TopACQ_DataF3,FifoF3_Data,open,FifoF3_Empty); | |
| 342 |
|
374 | |||
| 343 | --- DEMUX ------------------------------------------------------------- |
|
375 | --- DEMUX ------------------------------------------------------------- | |
| 344 |
|
376 | |||
| 345 |
DEMU |
|
377 | DEMU0 : DEMUX | |
| 346 | generic map(Data_sz => 16) |
|
378 | generic map(Data_sz => 16) | |
| 347 |
port map(clkm,rstn,FFT_Read,F |
|
379 | port map(clkm,rstn,FFT_Read,FFT_Load,FifoF0_Empty,FifoF1_Empty,FifoF3_Empty,FifoF0_Data,FifoF1_Data,FifoF3_Data,DEMU_Read,DEMU_Empty,DEMU_Data); | |
| 348 |
|
380 | |||
| 349 | --- FFT ------------------------------------------------------------- |
|
381 | --- FFT ------------------------------------------------------------- | |
| 350 |
|
382 | |||
| @@ -354,18 +386,18 led(1 downto 0) <= gpio(1 downto 0); | |||||
| 354 |
|
386 | |||
| 355 | FFT0 : FFT |
|
387 | FFT0 : FFT | |
| 356 | generic map(Data_sz => 16,NbData => 256) |
|
388 | generic map(Data_sz => 16,NbData => 256) | |
| 357 | port map(clkm,rstn,DEMU_Empty,DEMU_Data,FifoINT_Full,FFT_Read,FFT_Write,FFT_ReUse,FFT_Data); |
|
389 | port map(clkm,rstn,DEMU_Empty,DEMU_Data,FifoINT_Full,FFT_Load,FFT_Read,FFT_Write,FFT_ReUse,FFT_Data); | |
| 358 |
|
390 | |||
| 359 | ----- LINK MEMORY ------------------------------------------------------- |
|
391 | ----- LINK MEMORY ------------------------------------------------------- | |
| 360 |
|
392 | |||
| 361 | -- MemOut : APB_FIFO |
|
393 | -- MemOut : APB_FIFO | |
| 362 | -- generic map (pindex => 9, paddr => 9, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 0) |
|
394 | -- generic map (pindex => 9, paddr => 9, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 0) | |
| 363 |
-- port map (clkm,rstn,clkm,clkm, |
|
395 | -- port map (clkm,rstn,clkm,clkm,FFT_ReUse,(others =>'1'),FFT_Write,open,FifoINT_Full,open,FFT_Data,open,open,apbi,apbo(9)); | |
| 364 |
|
396 | |||
| 365 | MemInt : lppFIFOxN |
|
397 | MemInt : lppFIFOxN | |
| 366 | generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '1') |
|
398 | generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '1') | |
| 367 | port map(rstn,clkm,clkm,FFT_ReUse,FFT_Write,SM_Read,FFT_Data,FifoINT_Data,FifoINT_Full,open); |
|
399 | port map(rstn,clkm,clkm,FFT_ReUse,FFT_Write,SM_Read,FFT_Data,FifoINT_Data,FifoINT_Full,open); | |
| 368 |
|
400 | -- | ||
| 369 | -- MemIn : APB_FIFO |
|
401 | -- MemIn : APB_FIFO | |
| 370 | -- generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 0, W => 1) |
|
402 | -- generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 0, W => 1) | |
| 371 | -- port map (clkm,rstn,clkm,clkm,(others => '0'),TopSM_Read,(others => '1'),open,FifoINT_Full,FifoINT_Data,(others => '0'),open,open,apbi,apbo(8)); |
|
403 | -- port map (clkm,rstn,clkm,clkm,(others => '0'),TopSM_Read,(others => '1'),open,FifoINT_Full,FifoINT_Data,(others => '0'),open,open,apbi,apbo(8)); | |
| @@ -378,9 +410,9 led(1 downto 0) <= gpio(1 downto 0); | |||||
| 378 |
|
410 | |||
| 379 | Dma_acq <= '1'; |
|
411 | Dma_acq <= '1'; | |
| 380 |
|
412 | |||
| 381 | MemOut : APB_FIFO |
|
413 | -- MemOut : APB_FIFO | |
| 382 | generic map (pindex => 9, paddr => 9, FifoCnt => 2, Data_sz => 32, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) |
|
414 | -- generic map (pindex => 9, paddr => 9, FifoCnt => 2, Data_sz => 32, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) | |
| 383 | port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),SM_Write,open,FifoOUT_Full,open,SM_Data,open,open,apbi,apbo(9)); |
|
415 | -- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),SM_Write,open,FifoOUT_Full,open,SM_Data,open,open,apbi,apbo(9)); | |
| 384 |
|
416 | |||
| 385 | ----- FIFO ------------------------------------------------------------- |
|
417 | ----- FIFO ------------------------------------------------------------- | |
| 386 |
|
418 | |||
| @@ -17,158 +17,158 | |||||
| 17 | -- Additional Comments: |
|
17 | -- Additional Comments: | |
| 18 | -- |
|
18 | -- | |
| 19 | ---------------------------------------------------------------------------------- |
|
19 | ---------------------------------------------------------------------------------- | |
| 20 | library IEEE; |
|
20 | LIBRARY IEEE; | |
| 21 |
|
|
21 | USE IEEE.STD_LOGIC_1164.ALL; | |
| 22 |
|
|
22 | USE IEEE.NUMERIC_STD.ALL; | |
| 23 | library grlib; |
|
23 | LIBRARY grlib; | |
| 24 |
|
|
24 | USE grlib.amba.ALL; | |
| 25 |
|
|
25 | USE grlib.stdlib.ALL; | |
| 26 |
|
|
26 | USE grlib.devices.ALL; | |
| 27 | library lpp; |
|
27 | LIBRARY lpp; | |
| 28 |
|
|
28 | USE lpp.apb_devices_list.ALL; | |
| 29 |
|
|
29 | USE lpp.lpp_lfr_time_management.ALL; | |
| 30 |
|
30 | |||
| 31 |
|
|
31 | ENTITY apb_lfr_time_management IS | |
| 32 |
|
32 | |||
| 33 | generic( |
|
33 | GENERIC( | |
| 34 |
|
|
34 | pindex : INTEGER := 0; --! APB slave index | |
| 35 |
|
|
35 | paddr : INTEGER := 0; --! ADDR field of the APB BAR | |
| 36 |
|
|
36 | pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR | |
| 37 |
|
|
37 | pirq : INTEGER := 0; --! 2 consecutive IRQ lines are used | |
| 38 |
|
|
38 | masterclk : INTEGER := 25000000; --! master clock in Hz | |
| 39 |
|
|
39 | otherclk : INTEGER := 49152000; --! other clock in Hz | |
| 40 |
|
|
40 | finetimeclk : INTEGER := 65536 --! divided clock used for the fine time counter | |
| 41 | ); |
|
41 | ); | |
| 42 |
|
42 | |||
| 43 | Port ( |
|
43 | PORT ( | |
| 44 |
|
|
44 | clk25MHz : IN STD_LOGIC; --! Clock | |
| 45 |
|
|
45 | clk49_152MHz : IN STD_LOGIC; --! secondary clock | |
| 46 |
|
|
46 | resetn : IN STD_LOGIC; --! Reset | |
| 47 |
|
|
47 | grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received | |
| 48 |
|
|
48 | apbi : IN apb_slv_in_type; --! APB slave input signals | |
| 49 |
|
|
49 | apbo : OUT apb_slv_out_type; --! APB slave output signals | |
| 50 | coarse_time : out std_logic_vector(31 downto 0); --! coarse time |
|
50 | coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time | |
| 51 | fine_time : out std_logic_vector(31 downto 0) --! fine time |
|
51 | fine_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) --! fine time | |
| 52 | ); |
|
52 | ); | |
| 53 |
|
||||
| 54 | end apb_lfr_time_management; |
|
|||
| 55 |
|
53 | |||
| 56 | architecture Behavioral of apb_lfr_time_management is |
|
54 | END apb_lfr_time_management; | |
| 57 |
|
55 | |||
| 58 | constant REVISION : integer := 1; |
|
56 | ARCHITECTURE Behavioral OF apb_lfr_time_management IS | |
|
|
57 | ||||
|
|
58 | CONSTANT REVISION : INTEGER := 1; | |||
| 59 |
|
59 | |||
| 60 | --! the following types are defined in the grlib amba package |
|
60 | --! the following types are defined in the grlib amba package | |
| 61 | --! subtype amba_config_word is std_logic_vector(31 downto 0); |
|
61 | --! subtype amba_config_word is std_logic_vector(31 downto 0); | |
| 62 | --! type apb_config_type is array (0 to NAPBCFG-1) of amba_config_word; |
|
62 | --! type apb_config_type is array (0 to NAPBCFG-1) of amba_config_word; | |
| 63 |
|
|
63 | CONSTANT pconfig : apb_config_type := ( | |
| 64 | --! 0 => ahb_device_reg (VENDOR_LPP, LPP_ROTARY, 0, REVISION, 0), |
|
64 | --! 0 => ahb_device_reg (VENDOR_LPP, LPP_ROTARY, 0, REVISION, 0), | |
| 65 |
|
|
65 | 0 => ahb_device_reg (19, 14, 0, REVISION, pirq), | |
| 66 |
|
|
66 | 1 => apb_iobar(paddr, pmask)); | |
| 67 |
|
67 | |||
| 68 |
|
|
68 | TYPE apb_lfr_time_management_Reg IS RECORD | |
| 69 | ctrl : std_logic_vector(31 downto 0); |
|
69 | ctrl : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 70 | coarse_time_load : std_logic_vector(31 downto 0); |
|
70 | coarse_time_load : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 71 | coarse_time : std_logic_vector(31 downto 0); |
|
71 | coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 72 | fine_time : std_logic_vector(31 downto 0); |
|
72 | fine_time : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 73 |
next_commutation |
|
73 | next_commutation : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 74 | end record; |
|
74 | END RECORD; | |
| 75 |
|
75 | |||
| 76 |
|
|
76 | SIGNAL r : apb_lfr_time_management_Reg; | |
| 77 | signal Rdata : std_logic_vector(31 downto 0); |
|
77 | SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 78 | signal force_tick : std_logic; |
|
78 | SIGNAL force_tick : STD_LOGIC; | |
| 79 |
|
|
79 | SIGNAL previous_force_tick : STD_LOGIC; | |
| 80 | signal soft_tick : std_logic; |
|
80 | SIGNAL soft_tick : STD_LOGIC; | |
| 81 |
|
|
81 | SIGNAL reset_next_commutation : STD_LOGIC; | |
| 82 |
|
82 | |||
| 83 | begin |
|
83 | BEGIN | |
| 84 |
|
84 | |||
| 85 | lfrtimemanagement0: lfr_time_management |
|
85 | lfrtimemanagement0 : lfr_time_management | |
| 86 |
|
|
86 | GENERIC MAP(masterclk => masterclk, timeclk => otherclk, finetimeclk => finetimeclk) | |
| 87 |
|
|
87 | PORT MAP(master_clock => clk25MHz, time_clock => clk49_152MHz, resetn => resetn, | |
| 88 |
|
|
88 | grspw_tick => grspw_tick, soft_tick => soft_tick, | |
| 89 |
|
|
89 | coarse_time_load => r.coarse_time_load, coarse_time => r.coarse_time, fine_time => r.fine_time, | |
| 90 |
|
|
90 | next_commutation => r.next_commutation, reset_next_commutation => reset_next_commutation, | |
| 91 |
|
|
91 | irq1 => apbo.pirq(pirq), irq2 => apbo.pirq(pirq+1)); | |
| 92 |
|
92 | |||
| 93 |
|
|
93 | PROCESS(resetn, clk25MHz, reset_next_commutation) | |
| 94 | begin |
|
94 | BEGIN | |
| 95 |
|
95 | |||
| 96 |
|
|
96 | IF resetn = '0' THEN | |
| 97 |
|
|
97 | r.coarse_time_load <= x"80000000"; | |
| 98 |
|
|
98 | r.ctrl <= x"00000000"; | |
| 99 |
|
|
99 | r.next_commutation <= x"ffffffff"; | |
| 100 |
|
|
100 | force_tick <= '0'; | |
| 101 |
|
|
101 | previous_force_tick <= '0'; | |
| 102 | soft_tick <= '0'; |
|
102 | soft_tick <= '0'; | |
| 103 |
|
103 | |||
| 104 |
|
|
104 | ELSIF reset_next_commutation = '1' THEN | |
| 105 |
|
|
105 | r.next_commutation <= x"ffffffff"; | |
| 106 |
|
106 | |||
| 107 | elsif clk25MHz'event and clk25MHz = '1' then |
|
107 | ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN | |
| 108 |
|
108 | |||
| 109 |
|
|
109 | previous_force_tick <= force_tick; | |
| 110 |
|
|
110 | force_tick <= r.ctrl(0); | |
| 111 |
|
|
111 | IF (previous_force_tick = '0') AND (force_tick = '1') THEN | |
| 112 |
|
|
112 | soft_tick <= '1'; | |
| 113 | else |
|
113 | ELSE | |
| 114 |
|
|
114 | soft_tick <= '0'; | |
| 115 | end if; |
|
115 | END IF; | |
| 116 |
|
116 | |||
| 117 | --APB Write OP |
|
117 | --APB Write OP | |
| 118 |
|
|
118 | IF (apbi.psel(pindex) AND apbi.penable AND apbi.pwrite) = '1' THEN | |
| 119 | case apbi.paddr(7 downto 2) is |
|
119 | CASE apbi.paddr(7 DOWNTO 2) IS | |
| 120 | when "000000" => |
|
120 | WHEN "000000" => | |
| 121 |
|
|
121 | r.ctrl <= apbi.pwdata(31 DOWNTO 0); | |
| 122 | when "000001" => |
|
122 | WHEN "000001" => | |
| 123 |
|
|
123 | r.coarse_time_load <= apbi.pwdata(31 DOWNTO 0); | |
| 124 |
|
|
124 | WHEN "000100" => | |
| 125 |
|
|
125 | r.next_commutation <= apbi.pwdata(31 DOWNTO 0); | |
| 126 | when others => |
|
126 | WHEN OTHERS => | |
| 127 |
|
|
127 | r.coarse_time_load <= x"00000000"; | |
| 128 | end case; |
|
128 | END CASE; | |
| 129 | elsif r.ctrl(0) = '1' then |
|
129 | ELSIF r.ctrl(0) = '1' THEN | |
| 130 |
|
|
130 | r.ctrl(0) <= '0'; | |
| 131 | end if; |
|
131 | END IF; | |
| 132 |
|
132 | |||
| 133 | --APB READ OP |
|
133 | --APB READ OP | |
| 134 |
|
|
134 | IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN | |
| 135 | case apbi.paddr(7 downto 2) is |
|
135 | CASE apbi.paddr(7 DOWNTO 2) IS | |
| 136 | when "000000" => |
|
136 | WHEN "000000" => | |
| 137 | Rdata(31 downto 24) <= r.ctrl(31 downto 24); |
|
137 | Rdata(31 DOWNTO 24) <= r.ctrl(31 DOWNTO 24); | |
| 138 | Rdata(23 downto 16) <= r.ctrl(23 downto 16); |
|
138 | Rdata(23 DOWNTO 16) <= r.ctrl(23 DOWNTO 16); | |
| 139 | Rdata(15 downto 8) <= r.ctrl(15 downto 8); |
|
139 | Rdata(15 DOWNTO 8) <= r.ctrl(15 DOWNTO 8); | |
| 140 | Rdata(7 downto 0) <= r.ctrl(7 downto 0); |
|
140 | Rdata(7 DOWNTO 0) <= r.ctrl(7 DOWNTO 0); | |
| 141 | when "000001" => |
|
141 | WHEN "000001" => | |
| 142 |
|
|
142 | Rdata(31 DOWNTO 24) <= r.coarse_time_load(31 DOWNTO 24); | |
| 143 |
|
|
143 | Rdata(23 DOWNTO 16) <= r.coarse_time_load(23 DOWNTO 16); | |
| 144 |
|
|
144 | Rdata(15 DOWNTO 8) <= r.coarse_time_load(15 DOWNTO 8); | |
| 145 |
|
|
145 | Rdata(7 DOWNTO 0) <= r.coarse_time_load(7 DOWNTO 0); | |
| 146 | when "000010" => |
|
146 | WHEN "000010" => | |
| 147 |
|
|
147 | Rdata(31 DOWNTO 24) <= r.coarse_time(31 DOWNTO 24); | |
| 148 |
|
|
148 | Rdata(23 DOWNTO 16) <= r.coarse_time(23 DOWNTO 16); | |
| 149 |
|
|
149 | Rdata(15 DOWNTO 8) <= r.coarse_time(15 DOWNTO 8); | |
| 150 |
|
|
150 | Rdata(7 DOWNTO 0) <= r.coarse_time(7 DOWNTO 0); | |
| 151 | when "000011" => |
|
151 | WHEN "000011" => | |
| 152 |
|
|
152 | Rdata(31 DOWNTO 24) <= r.fine_time(31 DOWNTO 24); | |
| 153 |
|
|
153 | Rdata(23 DOWNTO 16) <= r.fine_time(23 DOWNTO 16); | |
| 154 |
|
|
154 | Rdata(15 DOWNTO 8) <= r.fine_time(15 DOWNTO 8); | |
| 155 | Rdata(7 downto 0) <= r.fine_time(7 downto 0); |
|
155 | Rdata(7 DOWNTO 0) <= r.fine_time(7 DOWNTO 0); | |
| 156 |
|
|
156 | WHEN "000100" => | |
| 157 |
|
|
157 | Rdata(31 DOWNTO 24) <= r.next_commutation(31 DOWNTO 24); | |
| 158 |
|
|
158 | Rdata(23 DOWNTO 16) <= r.next_commutation(23 DOWNTO 16); | |
| 159 |
|
|
159 | Rdata(15 DOWNTO 8) <= r.next_commutation(15 DOWNTO 8); | |
| 160 |
|
|
160 | Rdata(7 DOWNTO 0) <= r.next_commutation(7 DOWNTO 0); | |
| 161 | when others => |
|
161 | WHEN OTHERS => | |
| 162 |
|
|
162 | Rdata(31 DOWNTO 0) <= x"00000000"; | |
| 163 | end case; |
|
163 | END CASE; | |
| 164 | end if; |
|
164 | END IF; | |
| 165 |
|
165 | |||
| 166 | end if; |
|
166 | END IF; | |
| 167 |
|
|
167 | apbo.pconfig <= pconfig; | |
| 168 | end process; |
|
168 | END PROCESS; | |
| 169 |
|
169 | |||
| 170 |
apbo.prdata <= |
|
170 | apbo.prdata <= Rdata WHEN apbi.penable = '1'; | |
| 171 | coarse_time <= r.coarse_time; |
|
171 | coarse_time <= r.coarse_time; | |
| 172 | fine_time <= r.fine_time; |
|
172 | fine_time <= r.fine_time; | |
| 173 |
|
173 | |||
| 174 |
|
|
174 | END Behavioral; | |
| @@ -18,97 +18,180 | |||||
| 18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
| 19 | -- Author : Alexis Jeandet |
|
19 | -- Author : Alexis Jeandet | |
| 20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr |
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |
| 21 | ---------------------------------------------------------------------------- |
|
21 | ------------------------------------------------------------------------------- | |
| 22 | library IEEE; |
|
22 | -- MODIFIED by Jean-christophe PELLION | |
| 23 | use IEEE.STD_LOGIC_1164.ALL; |
|
23 | -- jean-christophe.pellion@lpp.polytechnique.fr | |
| 24 | library lpp; |
|
24 | ------------------------------------------------------------------------------- | |
| 25 | use lpp.lpp_ad_conv.all; |
|
25 | LIBRARY IEEE; | |
| 26 | use lpp.general_purpose.Clk_divider; |
|
26 | USE IEEE.STD_LOGIC_1164.ALL; | |
| 27 |
|
27 | LIBRARY lpp; | ||
| 28 | --! \brief AD7688 driver, generates all needed signal to drive this ADC. |
|
28 | USE lpp.lpp_ad_conv.ALL; | |
| 29 | --! |
|
29 | USE lpp.general_purpose.SYNC_FF; | |
| 30 | --! \author Alexis Jeandet alexis.jeandet@lpp.polytechnique.fr |
|
|||
| 31 |
|
30 | |||
| 32 |
|
|
31 | ENTITY AD7688_drvr IS | |
| 33 | generic( |
|
32 | GENERIC( | |
| 34 | ChanelCount :integer; --! Number of ADC you whant to drive |
|
33 | ChanelCount : INTEGER; | |
| 35 | clkkHz :integer --! System clock frequency in kHz usefull to generate some pulses with good width. |
|
34 | ncycle_cnv_high : INTEGER := 79; | |
| 36 | ); |
|
35 | ncycle_cnv : INTEGER := 500); | |
| 37 | Port( |
|
36 | PORT ( | |
| 38 | clk : in STD_LOGIC; --! System clock |
|
37 | -- CONV -- | |
| 39 | rstn : in STD_LOGIC; --! System reset |
|
38 | cnv_clk : IN STD_LOGIC; | |
| 40 | enable : in std_logic; --! Negative enable |
|
39 | cnv_rstn : IN STD_LOGIC; | |
| 41 | smplClk : in STD_LOGIC; --! Sampling clock |
|
40 | cnv_run : IN STD_LOGIC; | |
| 42 | DataReady : out std_logic; --! New sample available |
|
41 | cnv : OUT STD_LOGIC; | |
| 43 | smpout : out Samples_out(ChanelCount-1 downto 0); --! Samples |
|
|||
| 44 | AD_in : in AD7688_in(ChanelCount-1 downto 0); --! Input signals for ADC see lpp.lpp_ad_conv |
|
|||
| 45 | AD_out : out AD7688_out --! Output signals for ADC see lpp.lpp_ad_conv |
|
|||
| 46 | ); |
|
|||
| 47 | end AD7688_drvr; |
|
|||
| 48 |
|
||||
| 49 | architecture ar_AD7688_drvr of AD7688_drvr is |
|
|||
| 50 |
|
||||
| 51 | constant convTrigger : integer:= clkkHz*16/10000; --tconv = 1.6µs |
|
|||
| 52 |
|
||||
| 53 | signal i : integer range 0 to convTrigger :=0; |
|
|||
| 54 | signal clk_int : std_logic; |
|
|||
| 55 | signal clk_int_inv : std_logic; |
|
|||
| 56 | signal smplClk_reg : std_logic; |
|
|||
| 57 | signal cnv_int : std_logic; |
|
|||
| 58 | signal reset : std_logic; |
|
|||
| 59 |
|
42 | |||
| 60 | begin |
|
43 | -- DATA -- | |
| 61 |
|
44 | clk : IN STD_LOGIC; | ||
| 62 | clkdiv: if clkkHz>=66000 generate |
|
45 | rstn : IN STD_LOGIC; | |
| 63 | clkdivider: entity work.Clk_divider |
|
46 | sck : OUT STD_LOGIC; | |
| 64 | generic map(clkkHz*1000,60000000) |
|
47 | sdo : IN STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0); | |
| 65 | Port map( clk ,reset,clk_int); |
|
|||
| 66 | end generate; |
|
|||
| 67 |
|
48 | |||
| 68 | clknodiv: if clkkHz<66000 generate |
|
49 | sample : OUT Samples(ChanelCount-1 DOWNTO 0); | |
| 69 | nodiv: clk_int <= clk; |
|
50 | sample_val : OUT STD_LOGIC | |
| 70 | end generate; |
|
51 | ); | |
| 71 |
|
52 | END AD7688_drvr; | ||
| 72 | clk_int_inv <= not clk_int; |
|
|||
| 73 |
|
||||
| 74 | AD_out.CNV <= cnv_int; |
|
|||
| 75 | AD_out.SCK <= clk_int; |
|
|||
| 76 | reset <= rstn and enable; |
|
|||
| 77 |
|
53 | |||
| 78 | sckgen: process(clk,reset) |
|
54 | ARCHITECTURE ar_AD7688_drvr OF AD7688_drvr IS | |
| 79 | begin |
|
55 | ||
| 80 | if reset = '0' then |
|
56 | COMPONENT SYNC_FF | |
| 81 | i <= 0; |
|
57 | GENERIC ( | |
| 82 | cnv_int <= '0'; |
|
58 | NB_FF_OF_SYNC : INTEGER); | |
| 83 | smplClk_reg <= '0'; |
|
59 | PORT ( | |
| 84 | elsif clk'event and clk = '1' then |
|
60 | clk : IN STD_LOGIC; | |
| 85 | if smplClk = '1' and smplClk_reg = '0' then |
|
61 | rstn : IN STD_LOGIC; | |
| 86 | if i = convTrigger then |
|
62 | A : IN STD_LOGIC; | |
| 87 | smplClk_reg <= '1'; |
|
63 | A_sync : OUT STD_LOGIC); | |
| 88 | i <= 0; |
|
64 | END COMPONENT; | |
| 89 | cnv_int <= '0'; |
|
|||
| 90 | else |
|
|||
| 91 | i <= i+1; |
|
|||
| 92 | cnv_int <= '1'; |
|
|||
| 93 | end if; |
|
|||
| 94 | elsif smplClk = '0' and smplClk_reg = '1' then |
|
|||
| 95 | smplClk_reg <= '0'; |
|
|||
| 96 | end if; |
|
|||
| 97 | end if; |
|
|||
| 98 | end process; |
|
|||
| 99 |
|
65 | |||
| 100 |
|
66 | |||
|
|
67 | SIGNAL cnv_cycle_counter : INTEGER; | |||
|
|
68 | SIGNAL cnv_s : STD_LOGIC; | |||
|
|
69 | SIGNAL cnv_sync : STD_LOGIC; | |||
|
|
70 | SIGNAL cnv_sync_r : STD_LOGIC; | |||
|
|
71 | SIGNAL cnv_done : STD_LOGIC; | |||
|
|
72 | SIGNAL sample_bit_counter : INTEGER; | |||
|
|
73 | SIGNAL shift_reg : Samples(ChanelCount-1 DOWNTO 0); | |||
| 101 |
|
74 | |||
| 102 | spidrvr: entity work.AD7688_spi_if |
|
75 | SIGNAL cnv_run_sync : STD_LOGIC; | |
| 103 | generic map(ChanelCount) |
|
76 | ||
| 104 | Port map(clk_int_inv,reset,cnv_int,DataReady,AD_in,smpout); |
|
77 | BEGIN | |
|
|
78 | ----------------------------------------------------------------------------- | |||
|
|
79 | -- CONV | |||
|
|
80 | ----------------------------------------------------------------------------- | |||
|
|
81 | PROCESS (cnv_clk, cnv_rstn) | |||
|
|
82 | BEGIN -- PROCESS | |||
|
|
83 | IF cnv_rstn = '0' THEN -- asynchronous reset (active low) | |||
|
|
84 | cnv_cycle_counter <= 0; | |||
|
|
85 | cnv_s <= '0'; | |||
|
|
86 | ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge | |||
|
|
87 | IF cnv_run = '1' THEN | |||
|
|
88 | IF cnv_cycle_counter < ncycle_cnv THEN | |||
|
|
89 | cnv_cycle_counter <= cnv_cycle_counter +1; | |||
|
|
90 | IF cnv_cycle_counter < ncycle_cnv_high THEN | |||
|
|
91 | cnv_s <= '1'; | |||
|
|
92 | ELSE | |||
|
|
93 | cnv_s <= '0'; | |||
|
|
94 | END IF; | |||
|
|
95 | ELSE | |||
|
|
96 | cnv_s <= '1'; | |||
|
|
97 | cnv_cycle_counter <= 0; | |||
|
|
98 | END IF; | |||
|
|
99 | ELSE | |||
|
|
100 | cnv_s <= '0'; | |||
|
|
101 | cnv_cycle_counter <= 0; | |||
|
|
102 | END IF; | |||
|
|
103 | END IF; | |||
|
|
104 | END PROCESS; | |||
| 105 |
|
105 | |||
|
|
106 | cnv <= cnv_s; | |||
|
|
107 | ||||
|
|
108 | ----------------------------------------------------------------------------- | |||
| 106 |
|
109 | |||
| 107 |
|
110 | |||
| 108 | end ar_AD7688_drvr; |
|
111 | ----------------------------------------------------------------------------- | |
|
|
112 | -- SYNC CNV | |||
|
|
113 | ----------------------------------------------------------------------------- | |||
|
|
114 | ||||
|
|
115 | SYNC_FF_cnv : SYNC_FF | |||
|
|
116 | GENERIC MAP ( | |||
|
|
117 | NB_FF_OF_SYNC => 2) | |||
|
|
118 | PORT MAP ( | |||
|
|
119 | clk => clk, | |||
|
|
120 | rstn => rstn, | |||
|
|
121 | A => cnv_s, | |||
|
|
122 | A_sync => cnv_sync); | |||
| 109 |
|
123 | |||
|
|
124 | PROCESS (clk, rstn) | |||
|
|
125 | BEGIN | |||
|
|
126 | IF rstn = '0' THEN | |||
|
|
127 | cnv_sync_r <= '0'; | |||
|
|
128 | cnv_done <= '0'; | |||
|
|
129 | ELSIF clk'EVENT AND clk = '1' THEN | |||
|
|
130 | cnv_sync_r <= cnv_sync; | |||
|
|
131 | cnv_done <= (NOT cnv_sync) AND cnv_sync_r; | |||
|
|
132 | END IF; | |||
|
|
133 | END PROCESS; | |||
|
|
134 | ||||
|
|
135 | ----------------------------------------------------------------------------- | |||
|
|
136 | ||||
|
|
137 | SYNC_FF_run : SYNC_FF | |||
|
|
138 | GENERIC MAP ( | |||
|
|
139 | NB_FF_OF_SYNC => 2) | |||
|
|
140 | PORT MAP ( | |||
|
|
141 | clk => clk, | |||
|
|
142 | rstn => rstn, | |||
|
|
143 | A => cnv_run, | |||
|
|
144 | A_sync => cnv_run_sync); | |||
| 110 |
|
145 | |||
| 111 |
|
146 | |||
| 112 |
|
147 | |||
|
|
148 | ----------------------------------------------------------------------------- | |||
|
|
149 | -- DATA | |||
|
|
150 | ----------------------------------------------------------------------------- | |||
|
|
151 | PROCESS (clk, rstn) | |||
|
|
152 | BEGIN -- PROCESS | |||
|
|
153 | IF rstn = '0' THEN | |||
|
|
154 | FOR l IN 0 TO ChanelCount-1 LOOP | |||
|
|
155 | shift_reg(l) <= (OTHERS => '0'); | |||
|
|
156 | END LOOP; | |||
|
|
157 | sample_bit_counter <= 0; | |||
|
|
158 | sample_val <= '0'; | |||
|
|
159 | SCK <= '1'; | |||
|
|
160 | ELSIF clk'EVENT AND clk = '1' THEN | |||
|
|
161 | ||||
|
|
162 | IF cnv_run_sync = '0' THEN | |||
|
|
163 | sample_bit_counter <= 0; | |||
|
|
164 | ELSIF cnv_done = '1' THEN | |||
|
|
165 | sample_bit_counter <= 1; | |||
|
|
166 | ELSIF sample_bit_counter > 0 AND sample_bit_counter < 32 THEN | |||
|
|
167 | sample_bit_counter <= sample_bit_counter + 1; | |||
|
|
168 | END IF; | |||
| 113 |
|
169 | |||
|
|
170 | IF (sample_bit_counter MOD 2) = 1 THEN | |||
|
|
171 | FOR l IN 0 TO ChanelCount-1 LOOP | |||
|
|
172 | --shift_reg(l)(15) <= sdo(l); | |||
|
|
173 | --shift_reg(l)(14 DOWNTO 0) <= shift_reg(l)(15 DOWNTO 1); | |||
|
|
174 | shift_reg(l)(0) <= sdo(l); | |||
|
|
175 | shift_reg(l)(15 DOWNTO 1) <= shift_reg(l)(14 DOWNTO 0); | |||
|
|
176 | END LOOP; | |||
|
|
177 | SCK <= '0'; | |||
|
|
178 | ELSE | |||
|
|
179 | SCK <= '1'; | |||
|
|
180 | END IF; | |||
| 114 |
|
181 | |||
|
|
182 | IF sample_bit_counter = 31 THEN | |||
|
|
183 | sample_val <= '1'; | |||
|
|
184 | FOR l IN 0 TO ChanelCount-1 LOOP | |||
|
|
185 | --sample(l)(15) <= sdo(l); | |||
|
|
186 | --sample(l)(14 DOWNTO 0) <= shift_reg(l)(15 DOWNTO 1); | |||
|
|
187 | sample(l)(0) <= sdo(l); | |||
|
|
188 | sample(l)(15 DOWNTO 1) <= shift_reg(l)(14 DOWNTO 0); | |||
|
|
189 | END LOOP; | |||
|
|
190 | ELSE | |||
|
|
191 | sample_val <= '0'; | |||
|
|
192 | END IF; | |||
|
|
193 | END IF; | |||
|
|
194 | END PROCESS; | |||
|
|
195 | ||||
|
|
196 | END ar_AD7688_drvr; | |||
|
|
197 | ||||
| @@ -50,7 +50,7 PACKAGE lpp_ad_conv IS | |||||
| 50 |
|
50 | |||
| 51 | TYPE Samples IS ARRAY(NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
51 | TYPE Samples IS ARRAY(NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0); | |
| 52 |
|
52 | |||
| 53 |
COMPONENT AD |
|
53 | COMPONENT AD7688_drvr | |
| 54 | GENERIC ( |
|
54 | GENERIC ( | |
| 55 | ChanelCount : INTEGER; |
|
55 | ChanelCount : INTEGER; | |
| 56 | ncycle_cnv_high : INTEGER := 79; |
|
56 | ncycle_cnv_high : INTEGER := 79; | |
| @@ -162,26 +162,26 Type ADS127X_config is | |||||
| 162 | MODE : ADS127X_MODE_Type; |
|
162 | MODE : ADS127X_MODE_Type; | |
| 163 | end record; |
|
163 | end record; | |
| 164 |
|
164 | |||
| 165 | COMPONENT ADS1274_DRIVER is |
|
165 | COMPONENT ADS1274_DRIVER is | |
| 166 | generic(modeCfg : ADS127X_MODE_Type := ADS127X_MODE_low_power; formatCfg : ADS127X_FORMAT_Type := ADS127X_FSYNC_FORMAT); |
|
166 | generic(modeCfg : ADS127X_MODE_Type := ADS127X_MODE_low_power; formatCfg : ADS127X_FORMAT_Type := ADS127X_FSYNC_FORMAT); | |
| 167 | port( |
|
167 | port( | |
| 168 | Clk : in std_logic; |
|
168 | Clk : in std_logic; | |
| 169 | reset : in std_logic; |
|
169 | reset : in std_logic; | |
| 170 | SpiClk : out std_logic; |
|
170 | SpiClk : out std_logic; | |
| 171 | DIN : in std_logic_vector(3 downto 0); |
|
171 | DIN : in std_logic_vector(3 downto 0); | |
| 172 | Ready : in std_logic; |
|
172 | Ready : in std_logic; | |
| 173 | Format : out std_logic_vector(2 downto 0); |
|
173 | Format : out std_logic_vector(2 downto 0); | |
| 174 | Mode : out std_logic_vector(1 downto 0); |
|
174 | Mode : out std_logic_vector(1 downto 0); | |
| 175 | ClkDiv : out std_logic; |
|
175 | ClkDiv : out std_logic; | |
| 176 | PWDOWN : out std_logic_vector(3 downto 0); |
|
176 | PWDOWN : out std_logic_vector(3 downto 0); | |
| 177 | SmplClk : in std_logic; |
|
177 | SmplClk : in std_logic; | |
| 178 | OUT0 : out std_logic_vector(23 downto 0); |
|
178 | OUT0 : out std_logic_vector(23 downto 0); | |
| 179 | OUT1 : out std_logic_vector(23 downto 0); |
|
179 | OUT1 : out std_logic_vector(23 downto 0); | |
| 180 | OUT2 : out std_logic_vector(23 downto 0); |
|
180 | OUT2 : out std_logic_vector(23 downto 0); | |
| 181 | OUT3 : out std_logic_vector(23 downto 0); |
|
181 | OUT3 : out std_logic_vector(23 downto 0); | |
| 182 | FSynch : out std_logic; |
|
182 | FSynch : out std_logic; | |
| 183 | test : out std_logic |
|
183 | test : out std_logic | |
| 184 | ); |
|
184 | ); | |
| 185 | end COMPONENT; |
|
185 | end COMPONENT; | |
| 186 |
|
186 | |||
| 187 |
|
187 | |||
| @@ -31,19 +31,17 port( | |||||
| 31 | rstn : in std_logic; |
|
31 | rstn : in std_logic; | |
| 32 |
|
32 | |||
| 33 | Read : in std_logic_vector(4 downto 0); |
|
33 | Read : in std_logic_vector(4 downto 0); | |
| 34 | DataCpt : in std_logic_vector(3 downto 0); -- f2 f1 f0b f0a |
|
34 | Load : in std_logic; | |
| 35 |
|
35 | |||
| 36 |
EmptyF0 |
|
36 | EmptyF0 : in std_logic_vector(4 downto 0); | |
| 37 | EmptyF0b : in std_logic_vector(4 downto 0); |
|
|||
| 38 | EmptyF1 : in std_logic_vector(4 downto 0); |
|
37 | EmptyF1 : in std_logic_vector(4 downto 0); | |
| 39 | EmptyF2 : in std_logic_vector(4 downto 0); |
|
38 | EmptyF2 : in std_logic_vector(4 downto 0); | |
| 40 |
|
39 | |||
| 41 |
DataF0 |
|
40 | DataF0 : in std_logic_vector((5*Data_sz)-1 downto 0); | |
| 42 | DataF0b : in std_logic_vector((5*Data_sz)-1 downto 0); |
|
|||
| 43 | DataF1 : in std_logic_vector((5*Data_sz)-1 downto 0); |
|
41 | DataF1 : in std_logic_vector((5*Data_sz)-1 downto 0); | |
| 44 | DataF2 : in std_logic_vector((5*Data_sz)-1 downto 0); |
|
42 | DataF2 : in std_logic_vector((5*Data_sz)-1 downto 0); | |
| 45 |
|
43 | |||
| 46 |
Read_DEMUX : out std_logic_vector(1 |
|
44 | Read_DEMUX : out std_logic_vector(14 downto 0); | |
| 47 | Empty : out std_logic_vector(4 downto 0); |
|
45 | Empty : out std_logic_vector(4 downto 0); | |
| 48 | Data : out std_logic_vector((5*Data_sz)-1 downto 0) |
|
46 | Data : out std_logic_vector((5*Data_sz)-1 downto 0) | |
| 49 | ); |
|
47 | ); | |
| @@ -55,9 +53,8 architecture ar_DEMUX of DEMUX is | |||||
| 55 | type etat is (eX,e0,e1,e2,e3); |
|
53 | type etat is (eX,e0,e1,e2,e3); | |
| 56 | signal ect : etat; |
|
54 | signal ect : etat; | |
| 57 |
|
55 | |||
| 58 | signal pong : std_logic; |
|
|||
| 59 |
|
56 | |||
| 60 |
signal |
|
57 | signal load_reg : std_logic; | |
| 61 | constant Dummy_Read : std_logic_vector(4 downto 0) := (others => '1'); |
|
58 | constant Dummy_Read : std_logic_vector(4 downto 0) := (others => '1'); | |
| 62 |
|
59 | |||
| 63 | signal Countf0 : integer; |
|
60 | signal Countf0 : integer; | |
| @@ -68,61 +65,40 begin | |||||
| 68 | begin |
|
65 | begin | |
| 69 | if(rstn='0')then |
|
66 | if(rstn='0')then | |
| 70 | ect <= e0; |
|
67 | ect <= e0; | |
| 71 |
|
|
68 | load_reg <= '0'; | |
| 72 |
Countf0 <= |
|
69 | Countf0 <= 5; | |
| 73 | Countf1 <= 0; |
|
70 | Countf1 <= 0; | |
| 74 |
|
71 | |||
| 75 | elsif(clk'event and clk='1')then |
|
72 | elsif(clk'event and clk='1')then | |
| 76 |
|
|
73 | load_reg <= Load; | |
| 77 |
|
74 | |||
| 78 | case ect is |
|
75 | case ect is | |
| 79 |
|
76 | |||
| 80 | when e0 => |
|
77 | when e0 => | |
| 81 |
if( |
|
78 | if(load_reg = '1' and Load = '0')then | |
| 82 |
|
|
79 | if(Countf0 = 24)then | |
| 83 | if(Countf0 = 5)then |
|
|||
| 84 | Countf0 <= 0; |
|
80 | Countf0 <= 0; | |
| 85 |
ect <= e |
|
81 | ect <= e1; | |
| 86 | else |
|
82 | else | |
| 87 | Countf0 <= Countf0 + 1; |
|
83 | Countf0 <= Countf0 + 1; | |
| 88 |
ect <= e |
|
84 | ect <= e0; | |
| 89 | end if; |
|
85 | end if; | |
| 90 | end if; |
|
86 | end if; | |
| 91 |
|
87 | |||
| 92 | when e1 => |
|
88 | when e1 => | |
| 93 |
if( |
|
89 | if(load_reg = '1' and Load = '0')then | |
| 94 |
|
|
90 | if(Countf1 = 74)then | |
| 95 |
|
|
91 | Countf1 <= 0; | |
| 96 | Countf0 <= 0; |
|
|||
| 97 | ect <= e2; |
|
92 | ect <= e2; | |
| 98 | else |
|
93 | else | |
| 99 |
Countf |
|
94 | Countf1 <= Countf1 + 1; | |
| 100 | ect <= e0; |
|
95 | ect <= e0; | |
| 101 | end if; |
|
96 | end if; | |
| 102 | end if; |
|
97 | end if; | |
| 103 |
|
98 | |||
| 104 | when e2 => |
|
99 | when e2 => | |
| 105 |
if( |
|
100 | if(load_reg = '1' and Load = '0')then | |
| 106 |
|
|
101 | ect <= e0; | |
| 107 | Countf1 <= 0; |
|
|||
| 108 | ect <= e3; |
|
|||
| 109 | else |
|
|||
| 110 | Countf1 <= Countf1 + 1; |
|
|||
| 111 | if(pong = '0')then |
|
|||
| 112 | ect <= e0; |
|
|||
| 113 | else |
|
|||
| 114 | ect <= e1; |
|
|||
| 115 | end if; |
|
|||
| 116 | end if; |
|
|||
| 117 | end if; |
|
|||
| 118 |
|
||||
| 119 | when e3 => |
|
|||
| 120 | if(DataCpt_reg(3) = '1' and DataCpt(3) = '0')then |
|
|||
| 121 | if(pong = '0')then |
|
|||
| 122 | ect <= e0; |
|
|||
| 123 | else |
|
|||
| 124 | ect <= e1; |
|
|||
| 125 | end if; |
|
|||
| 126 | end if; |
|
102 | end if; | |
| 127 |
|
103 | |||
| 128 | when others => |
|
104 | when others => | |
| @@ -133,29 +109,23 begin | |||||
| 133 | end process; |
|
109 | end process; | |
| 134 |
|
110 | |||
| 135 | with ect select |
|
111 | with ect select | |
| 136 |
Empty <= EmptyF0 |
|
112 | Empty <= EmptyF0 when e0, | |
| 137 |
EmptyF |
|
113 | EmptyF1 when e1, | |
| 138 |
EmptyF |
|
114 | EmptyF2 when e2, | |
| 139 | EmptyF2 when e3, |
|
|||
| 140 | (others => '1') when others; |
|
115 | (others => '1') when others; | |
| 141 |
|
116 | |||
| 142 | with ect select |
|
117 | with ect select | |
| 143 |
Data <= DataF0 |
|
118 | Data <= DataF0 when e0, | |
| 144 |
DataF |
|
119 | DataF1 when e1, | |
| 145 |
DataF |
|
120 | DataF2 when e2, | |
| 146 | DataF2 when e3, |
|
|||
| 147 | (others => '0') when others; |
|
121 | (others => '0') when others; | |
| 148 |
|
122 | |||
| 149 | with ect select |
|
123 | with ect select | |
| 150 |
Read_DEMUX <= Dummy_Read & Dummy_Read & |
|
124 | Read_DEMUX <= Dummy_Read & Dummy_Read & Read when e0, | |
| 151 |
|
|
125 | Dummy_Read & Read & Dummy_Read when e1, | |
| 152 |
|
|
126 | Read & Dummy_Read & Dummy_Read when e2, | |
| 153 | Read & Dummy_Read & Dummy_Read & Dummy_Read when e3, |
|
|||
| 154 | (others => '1') when others; |
|
127 | (others => '1') when others; | |
| 155 |
|
128 | |||
| 156 |
|
||||
| 157 |
|
||||
| 158 |
|
||||
| 159 | end architecture; |
|
129 | end architecture; | |
| 160 |
|
130 | |||
| 161 |
|
131 | |||
| @@ -29,34 +29,7 use lpp.lpp_amba.all; | |||||
| 29 |
|
29 | |||
| 30 | --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on |
|
30 | --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on | |
| 31 |
|
31 | |||
| 32 | package lpp_demux is |
|
32 | package lpp_demux is | |
| 33 |
|
||||
| 34 |
|
||||
| 35 | component Demultiplex is |
|
|||
| 36 | generic( |
|
|||
| 37 | Data_sz : integer range 1 to 32 := 16); |
|
|||
| 38 | port( |
|
|||
| 39 | clk : in std_logic; |
|
|||
| 40 | rstn : in std_logic; |
|
|||
| 41 |
|
||||
| 42 | Read : in std_logic_vector(4 downto 0); |
|
|||
| 43 |
|
||||
| 44 | EmptyF0a : in std_logic_vector(4 downto 0); |
|
|||
| 45 | EmptyF0b : in std_logic_vector(4 downto 0); |
|
|||
| 46 | EmptyF1 : in std_logic_vector(4 downto 0); |
|
|||
| 47 | EmptyF2 : in std_logic_vector(4 downto 0); |
|
|||
| 48 |
|
||||
| 49 | DataF0a : in std_logic_vector((5*Data_sz)-1 downto 0); |
|
|||
| 50 | DataF0b : in std_logic_vector((5*Data_sz)-1 downto 0); |
|
|||
| 51 | DataF1 : in std_logic_vector((5*Data_sz)-1 downto 0); |
|
|||
| 52 | DataF2 : in std_logic_vector((5*Data_sz)-1 downto 0); |
|
|||
| 53 |
|
||||
| 54 | Read_DEMUX : out std_logic_vector(19 downto 0); |
|
|||
| 55 | Empty : out std_logic_vector(4 downto 0); |
|
|||
| 56 | Data : out std_logic_vector((5*Data_sz)-1 downto 0) |
|
|||
| 57 | ); |
|
|||
| 58 | end component; |
|
|||
| 59 |
|
||||
| 60 |
|
|
33 | ||
| 61 | component DEMUX is |
|
34 | component DEMUX is | |
| 62 | generic( |
|
35 | generic( | |
| @@ -66,38 +39,20 port( | |||||
| 66 | rstn : in std_logic; |
|
39 | rstn : in std_logic; | |
| 67 |
|
40 | |||
| 68 | Read : in std_logic_vector(4 downto 0); |
|
41 | Read : in std_logic_vector(4 downto 0); | |
| 69 | DataCpt : in std_logic_vector(3 downto 0); -- f2 f1 f0b f0a |
|
42 | Load : in std_logic; | |
| 70 |
|
43 | |||
| 71 |
EmptyF0 |
|
44 | EmptyF0 : in std_logic_vector(4 downto 0); | |
| 72 | EmptyF0b : in std_logic_vector(4 downto 0); |
|
|||
| 73 | EmptyF1 : in std_logic_vector(4 downto 0); |
|
45 | EmptyF1 : in std_logic_vector(4 downto 0); | |
| 74 | EmptyF2 : in std_logic_vector(4 downto 0); |
|
46 | EmptyF2 : in std_logic_vector(4 downto 0); | |
| 75 |
|
47 | |||
| 76 |
DataF0 |
|
48 | DataF0 : in std_logic_vector((5*Data_sz)-1 downto 0); | |
| 77 | DataF0b : in std_logic_vector((5*Data_sz)-1 downto 0); |
|
|||
| 78 | DataF1 : in std_logic_vector((5*Data_sz)-1 downto 0); |
|
49 | DataF1 : in std_logic_vector((5*Data_sz)-1 downto 0); | |
| 79 | DataF2 : in std_logic_vector((5*Data_sz)-1 downto 0); |
|
50 | DataF2 : in std_logic_vector((5*Data_sz)-1 downto 0); | |
| 80 |
|
51 | |||
| 81 |
Read_DEMUX : out std_logic_vector(1 |
|
52 | Read_DEMUX : out std_logic_vector(14 downto 0); | |
| 82 | Empty : out std_logic_vector(4 downto 0); |
|
53 | Empty : out std_logic_vector(4 downto 0); | |
| 83 | Data : out std_logic_vector((5*Data_sz)-1 downto 0) |
|
54 | Data : out std_logic_vector((5*Data_sz)-1 downto 0) | |
| 84 | ); |
|
55 | ); | |
| 85 | end component; |
|
56 | end component; | |
| 86 |
|
57 | |||
| 87 |
|
||||
| 88 | component WatchFlag is |
|
|||
| 89 | port( |
|
|||
| 90 | clk : in std_logic; |
|
|||
| 91 | rstn : in std_logic; |
|
|||
| 92 |
|
||||
| 93 | EmptyF0a : in std_logic_vector(4 downto 0); |
|
|||
| 94 | EmptyF0b : in std_logic_vector(4 downto 0); |
|
|||
| 95 | EmptyF1 : in std_logic_vector(4 downto 0); |
|
|||
| 96 | EmptyF2 : in std_logic_vector(4 downto 0); |
|
|||
| 97 |
|
||||
| 98 | DataCpt : out std_logic_vector(3 downto 0) -- f2 f1 f0b f0a |
|
|||
| 99 | ); |
|
|||
| 100 | end component; |
|
|||
| 101 |
|
||||
| 102 |
|
||||
| 103 | end; No newline at end of file |
|
58 | end; | |
| @@ -1,7 +1,6 | |||||
| 1 | fifo_latency_correction.vhd |
|
1 | fifo_latency_correction.vhd | |
| 2 | lpp_dma.vhd |
|
2 | lpp_dma.vhd | |
| 3 | lpp_dma_apbreg.vhd |
|
3 | lpp_dma_apbreg.vhd | |
| 4 | lpp_dma_fsm.vhd |
|
|||
| 5 | lpp_dma_ip.vhd |
|
4 | lpp_dma_ip.vhd | |
| 6 | lpp_dma_pkg.vhd |
|
5 | lpp_dma_pkg.vhd | |
| 7 | lpp_dma_send_16word.vhd |
|
6 | lpp_dma_send_16word.vhd | |
| @@ -22,7 +22,6 | |||||
| 22 | library IEEE; |
|
22 | library IEEE; | |
| 23 | use IEEE.numeric_std.all; |
|
23 | use IEEE.numeric_std.all; | |
| 24 | use IEEE.std_logic_1164.all; |
|
24 | use IEEE.std_logic_1164.all; | |
| 25 | library lpp; |
|
|||
| 26 | use lpp.general_purpose.all; |
|
25 | use lpp.general_purpose.all; | |
| 27 |
|
26 | |||
| 28 | --! Driver de l'ALU |
|
27 | --! Driver de l'ALU | |
| @@ -22,8 +22,8 | |||||
| 22 | library IEEE; |
|
22 | library IEEE; | |
| 23 | use IEEE.std_logic_1164.all; |
|
23 | use IEEE.std_logic_1164.all; | |
| 24 | use IEEE.numeric_std.all; |
|
24 | use IEEE.numeric_std.all; | |
| 25 | library lpp; |
|
25 | --library lpp; | |
| 26 | use lpp.lpp_matrix.all; |
|
26 | --use lpp.lpp_matrix.all; | |
| 27 |
|
27 | |||
| 28 | entity MatriceSpectrale is |
|
28 | entity MatriceSpectrale is | |
| 29 | generic( |
|
29 | generic( | |
| @@ -34,14 +34,17 entity MatriceSpectrale is | |||||
| 34 | rstn : in std_logic; |
|
34 | rstn : in std_logic; | |
| 35 |
|
35 | |||
| 36 | FifoIN_Full : in std_logic_vector(4 downto 0); |
|
36 | FifoIN_Full : in std_logic_vector(4 downto 0); | |
|
|
37 | SetReUse : in std_logic_vector(4 downto 0); | |||
| 37 | FifoOUT_Full : in std_logic_vector(1 downto 0); |
|
38 | FifoOUT_Full : in std_logic_vector(1 downto 0); | |
| 38 |
Data_IN : in std_logic_vector( |
|
39 | Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0); | |
| 39 | ACQ : in std_logic; |
|
40 | ACQ : in std_logic; | |
| 40 | FlagError : out std_logic; |
|
41 | FlagError : out std_logic; | |
| 41 | Pong : out std_logic; |
|
42 | Pong : out std_logic; | |
|
|
43 | Statu : out std_logic_vector(3 downto 0); | |||
| 42 | Write : out std_logic_vector(1 downto 0); |
|
44 | Write : out std_logic_vector(1 downto 0); | |
| 43 | Read : out std_logic_vector(4 downto 0); |
|
45 | Read : out std_logic_vector(4 downto 0); | |
| 44 |
|
|
46 | ReUse : out std_logic_vector(4 downto 0); | |
|
|
47 | Data_OUT : out std_logic_vector((2*Result_SZ)-1 downto 0) | |||
| 45 | ); |
|
48 | ); | |
| 46 | end entity; |
|
49 | end entity; | |
| 47 |
|
50 | |||
| @@ -59,18 +62,23 signal TopSM_Data2 : std_logic_vect | |||||
| 59 |
|
62 | |||
| 60 | begin |
|
63 | begin | |
| 61 |
|
64 | |||
| 62 | TopSM : TopSpecMatrix |
|
65 | CTRL0 : entity work.ReUse_CTRLR | |
|
|
66 | port map(clkm,rstn,SetReUse,TopSM_Statu,ReUse); | |||
|
|
67 | ||||
|
|
68 | ||||
|
|
69 | TopSM : entity work.TopSpecMatrix | |||
| 63 | generic map (Input_SZ) |
|
70 | generic map (Input_SZ) | |
| 64 | port map(clkm,rstn,Matrix_Write,Matrix_Read,FifoIN_Full,Data_IN,TopSM_Start,Read,TopSM_Statu,TopSM_Data1,TopSM_Data2); |
|
71 | port map(clkm,rstn,Matrix_Write,Matrix_Read,FifoIN_Full,Data_IN,TopSM_Start,Read,TopSM_Statu,TopSM_Data1,TopSM_Data2); | |
| 65 |
|
72 | |||
| 66 | SM : SpectralMatrix |
|
73 | SM : entity work.SpectralMatrix | |
| 67 | generic map (Input_SZ,Result_SZ) |
|
74 | generic map (Input_SZ,Result_SZ) | |
| 68 | port map(clkm,rstn,TopSM_Start,TopSM_Data1,TopSM_Data2,TopSM_Statu,Matrix_Read,Matrix_Write,Matrix_Result); |
|
75 | port map(clkm,rstn,TopSM_Start,TopSM_Data1,TopSM_Data2,TopSM_Statu,Matrix_Read,Matrix_Write,Matrix_Result); | |
| 69 |
|
76 | |||
| 70 | DISP : Dispatch |
|
77 | DISP : entity work.Dispatch | |
| 71 | generic map(Result_SZ) |
|
78 | generic map(Result_SZ) | |
| 72 | port map(clkm,rstn,ACQ,Matrix_Result,Matrix_Write,FifoOUT_Full,Data_OUT,Write,Pong,FlagError); |
|
79 | port map(clkm,rstn,ACQ,Matrix_Result,Matrix_Write,FifoOUT_Full,Data_OUT,Write,Pong,FlagError); | |
| 73 |
|
80 | |||
|
|
81 | Statu <= TopSM_Statu; | |||
| 74 |
|
82 | |||
| 75 | end architecture; |
|
83 | end architecture; | |
| 76 |
|
84 | |||
| @@ -65,14 +65,17 component MatriceSpectrale is | |||||
| 65 | rstn : in std_logic; |
|
65 | rstn : in std_logic; | |
| 66 |
|
66 | |||
| 67 | FifoIN_Full : in std_logic_vector(4 downto 0); |
|
67 | FifoIN_Full : in std_logic_vector(4 downto 0); | |
|
|
68 | SetReUse : in std_logic_vector(4 downto 0); | |||
| 68 | FifoOUT_Full : in std_logic_vector(1 downto 0); |
|
69 | FifoOUT_Full : in std_logic_vector(1 downto 0); | |
| 69 |
Data_IN : in std_logic_vector( |
|
70 | Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0); | |
| 70 | ACQ : in std_logic; |
|
71 | ACQ : in std_logic; | |
| 71 | FlagError : out std_logic; |
|
72 | FlagError : out std_logic; | |
| 72 | Pong : out std_logic; |
|
73 | Pong : out std_logic; | |
|
|
74 | Statu : out std_logic_vector(3 downto 0); | |||
| 73 | Write : out std_logic_vector(1 downto 0); |
|
75 | Write : out std_logic_vector(1 downto 0); | |
| 74 | Read : out std_logic_vector(4 downto 0); |
|
76 | Read : out std_logic_vector(4 downto 0); | |
| 75 |
|
|
77 | ReUse : out std_logic_vector(4 downto 0); | |
|
|
78 | Data_OUT : out std_logic_vector((2*Result_SZ)-1 downto 0) | |||
| 76 | ); |
|
79 | ); | |
| 77 | end component; |
|
80 | end component; | |
| 78 |
|
81 | |||
| @@ -250,4 +253,14 component ALU_Driver is | |||||
| 250 | ); |
|
253 | ); | |
| 251 | end component; |
|
254 | end component; | |
| 252 |
|
255 | |||
|
|
256 | component ReUse_CTRLR is | |||
|
|
257 | port( | |||
|
|
258 | clk : in std_logic; | |||
|
|
259 | reset : in std_logic; | |||
|
|
260 | SetReUse : in std_logic_vector(4 downto 0); | |||
|
|
261 | Statu : in std_logic_vector(3 downto 0); | |||
|
|
262 | ReUse : out std_logic_vector(4 downto 0) | |||
|
|
263 | ); | |||
|
|
264 | end component; | |||
|
|
265 | ||||
| 253 | end; No newline at end of file |
|
266 | end; | |
| @@ -31,6 +31,7 entity lppFIFOxN is | |||||
| 31 | generic( |
|
31 | generic( | |
| 32 | tech : integer := 0; |
|
32 | tech : integer := 0; | |
| 33 | Data_sz : integer range 1 to 32 := 8; |
|
33 | Data_sz : integer range 1 to 32 := 8; | |
|
|
34 | Addr_sz : integer range 1 to 32 := 8; | |||
| 34 | FifoCnt : integer := 1; |
|
35 | FifoCnt : integer := 1; | |
| 35 | Enable_ReUse : std_logic := '0' |
|
36 | Enable_ReUse : std_logic := '0' | |
| 36 | ); |
|
37 | ); | |
| @@ -55,32 +56,9 begin | |||||
| 55 |
|
56 | |||
| 56 | fifos: for i in 0 to FifoCnt-1 generate |
|
57 | fifos: for i in 0 to FifoCnt-1 generate | |
| 57 | FIFO0 : lpp_fifo |
|
58 | FIFO0 : lpp_fifo | |
| 58 |
generic map (tech,Enable_ReUse,Data_sz, |
|
59 | generic map (tech,Enable_ReUse,Data_sz,Addr_sz) | |
| 59 | port map(rst,ReUse(i),rclk,ren(i),rdata((i+1)*Data_sz-1 downto i*Data_sz),empty(i),open,wclk,wen(i),wdata((i+1)*Data_sz-1 downto i*Data_sz),full(i),open); |
|
60 | port map(rst,ReUse(i),rclk,ren(i),rdata((i+1)*Data_sz-1 downto i*Data_sz),empty(i),open,wclk,wen(i),wdata((i+1)*Data_sz-1 downto i*Data_sz),full(i),open); | |
| 60 | end generate; |
|
61 | end generate; | |
| 61 |
|
62 | |||
| 62 |
|
||||
| 63 |
|
||||
| 64 | -- fifoB1 : entity work.lpp_fifo |
|
|||
| 65 | -- generic map (tech,Enable_ReUse,Data_sz,8) |
|
|||
| 66 | -- port map(rst,ReUse(0),rclk,ren(0),rdata(Data_sz-1 downto 0),empty(0),open,wclk,wen(0),wdata(Data_sz-1 downto 0),full(0),open); |
|
|||
| 67 | -- |
|
|||
| 68 | -- fifoB2 : entity work.lpp_fifo |
|
|||
| 69 | -- generic map (tech,Enable_ReUse,Data_sz,8) |
|
|||
| 70 | -- port map(rst,ReUse(1),rclk,ren(1),rdata((2*Data_sz)-1 downto Data_sz),empty(1),open,wclk,wen(1),wdata((2*Data_sz)-1 downto Data_sz),full(1),open); |
|
|||
| 71 | -- |
|
|||
| 72 | -- fifoB3 : entity work.lpp_fifo |
|
|||
| 73 | -- generic map (tech,Enable_ReUse,Data_sz,8) |
|
|||
| 74 | -- port map(rst,ReUse(2),rclk,ren(2),rdata((3*Data_sz)-1 downto 2*Data_sz),empty(2),open,wclk,wen(2),wdata((3*Data_sz)-1 downto 2*Data_sz),full(2),open); |
|
|||
| 75 | -- |
|
|||
| 76 | -- fifoE1 : entity work.lpp_fifo |
|
|||
| 77 | -- generic map (tech,Enable_ReUse,Data_sz,8) |
|
|||
| 78 | -- port map(rst,ReUse(3),rclk,ren(3),rdata((4*Data_sz)-1 downto 3*Data_sz),empty(3),open,wclk,wen(3),wdata((4*Data_sz)-1 downto 3*Data_sz),full(3),open); |
|
|||
| 79 | -- |
|
|||
| 80 | -- fifoE2 : entity work.lpp_fifo |
|
|||
| 81 | -- generic map (tech,Enable_ReUse,Data_sz,8) |
|
|||
| 82 | -- port map(rst,ReUse(4),rclk,ren(4),rdata((5*Data_sz)-1 downto 4*Data_sz),empty(4),open,wclk,wen(4),wdata((5*Data_sz)-1 downto 4*Data_sz),full(4),open); |
|
|||
| 83 |
|
||||
| 84 |
|
||||
| 85 | end architecture; |
|
63 | end architecture; | |
| 86 |
|
64 | |||
| @@ -99,6 +99,7 component lppFIFOxN is | |||||
| 99 | generic( |
|
99 | generic( | |
| 100 | tech : integer := 0; |
|
100 | tech : integer := 0; | |
| 101 | Data_sz : integer range 1 to 32 := 8; |
|
101 | Data_sz : integer range 1 to 32 := 8; | |
|
|
102 | Addr_sz : integer range 1 to 32 := 8; | |||
| 102 | FifoCnt : integer := 1; |
|
103 | FifoCnt : integer := 1; | |
| 103 | Enable_ReUse : std_logic := '0' |
|
104 | Enable_ReUse : std_logic := '0' | |
| 104 | ); |
|
105 | ); | |
| This diff has been collapsed as it changes many lines, (635 lines changed) Show them Hide them | |||||
| @@ -1,332 +1,303 | |||||
| 1 | LIBRARY ieee; |
|
1 | LIBRARY ieee; | |
| 2 | USE ieee.std_logic_1164.ALL; |
|
2 | USE ieee.std_logic_1164.ALL; | |
| 3 | LIBRARY lpp; |
|
3 | LIBRARY lpp; | |
| 4 | USE lpp.lpp_ad_conv.ALL; |
|
4 | USE lpp.lpp_ad_conv.ALL; | |
| 5 | USE lpp.iir_filter.ALL; |
|
5 | USE lpp.iir_filter.ALL; | |
| 6 | USE lpp.FILTERcfg.ALL; |
|
6 | USE lpp.FILTERcfg.ALL; | |
| 7 | USE lpp.lpp_memory.ALL; |
|
7 | USE lpp.lpp_memory.ALL; | |
| 8 | USE lpp.lpp_top_lfr_pkg.ALL; |
|
8 | USE lpp.lpp_top_lfr_pkg.ALL; | |
| 9 | LIBRARY techmap; |
|
9 | LIBRARY techmap; | |
| 10 | USE techmap.gencomp.ALL; |
|
10 | USE techmap.gencomp.ALL; | |
| 11 |
|
11 | |||
| 12 | ENTITY lpp_top_acq IS |
|
12 | ENTITY lpp_top_acq IS | |
| 13 | GENERIC( |
|
13 | GENERIC( | |
| 14 | tech : INTEGER := 0 |
|
14 | tech : INTEGER := 0 | |
| 15 | ); |
|
15 | ); | |
| 16 | PORT ( |
|
16 | PORT ( | |
| 17 | -- ADS7886 |
|
17 | -- ADS7886 | |
| 18 | cnv_run : IN STD_LOGIC; |
|
18 | cnv_run : IN STD_LOGIC; | |
| 19 | cnv : OUT STD_LOGIC; |
|
19 | cnv : OUT STD_LOGIC; | |
| 20 | sck : OUT STD_LOGIC; |
|
20 | sck : OUT STD_LOGIC; | |
| 21 | sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
21 | sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |
| 22 | -- |
|
22 | -- | |
| 23 | cnv_clk : IN STD_LOGIC; -- 49 MHz |
|
23 | cnv_clk : IN STD_LOGIC; -- 49 MHz | |
| 24 | cnv_rstn : IN STD_LOGIC; |
|
24 | cnv_rstn : IN STD_LOGIC; | |
| 25 | -- |
|
25 | -- | |
| 26 | clk : IN STD_LOGIC; -- 25 MHz |
|
26 | clk : IN STD_LOGIC; -- 25 MHz | |
| 27 | rstn : IN STD_LOGIC; |
|
27 | rstn : IN STD_LOGIC; | |
| 28 | -- |
|
28 | -- | |
| 29 |
sample_f0_ |
|
29 | sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 30 |
sample_f0_ |
|
30 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
| 31 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
31 | -- | |
| 32 | -- |
|
32 | sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 33 |
sample_f1_w |
|
33 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
| 34 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
34 | -- | |
| 35 | -- |
|
35 | sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 36 |
sample_f2_w |
|
36 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
| 37 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
37 | -- | |
| 38 | -- |
|
38 | sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 39 |
sample_f3_w |
|
39 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0) | |
| 40 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0) |
|
40 | ); | |
| 41 | ); |
|
41 | END lpp_top_acq; | |
| 42 | END lpp_top_acq; |
|
42 | ||
| 43 |
|
43 | ARCHITECTURE tb OF lpp_top_acq IS | ||
| 44 | ARCHITECTURE tb OF lpp_top_acq IS |
|
44 | ||
| 45 |
|
45 | COMPONENT Downsampling | ||
| 46 | COMPONENT Downsampling |
|
46 | GENERIC ( | |
| 47 | GENERIC ( |
|
47 | ChanelCount : INTEGER; | |
| 48 |
|
|
48 | SampleSize : INTEGER; | |
| 49 |
|
|
49 | DivideParam : INTEGER); | |
| 50 | DivideParam : INTEGER); |
|
50 | PORT ( | |
| 51 | PORT ( |
|
51 | clk : IN STD_LOGIC; | |
| 52 |
|
|
52 | rstn : IN STD_LOGIC; | |
| 53 |
|
|
53 | sample_in_val : IN STD_LOGIC; | |
| 54 | sample_in_val : IN STD_LOGIC; |
|
54 | sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0); | |
| 55 | sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0); |
|
55 | sample_out_val : OUT STD_LOGIC; | |
| 56 | sample_out_val : OUT STD_LOGIC; |
|
56 | sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0)); | |
| 57 | sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0)); |
|
57 | END COMPONENT; | |
| 58 | END COMPONENT; |
|
58 | ||
| 59 |
|
59 | ----------------------------------------------------------------------------- | ||
| 60 | ----------------------------------------------------------------------------- |
|
60 | CONSTANT ChanelCount : INTEGER := 8; | |
| 61 |
CONSTANT |
|
61 | CONSTANT ncycle_cnv_high : INTEGER := 79; | |
| 62 |
CONSTANT ncycle_cnv |
|
62 | CONSTANT ncycle_cnv : INTEGER := 500; | |
| 63 | CONSTANT ncycle_cnv : INTEGER := 500; |
|
63 | ||
| 64 |
|
64 | ----------------------------------------------------------------------------- | ||
| 65 | ----------------------------------------------------------------------------- |
|
65 | SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0); | |
| 66 | SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0); |
|
66 | SIGNAL sample_val : STD_LOGIC; | |
| 67 |
SIGNAL sample_val |
|
67 | SIGNAL sample_val_delay : STD_LOGIC; | |
| 68 | SIGNAL sample_val_delay : STD_LOGIC; |
|
68 | ----------------------------------------------------------------------------- | |
| 69 | ----------------------------------------------------------------------------- |
|
69 | CONSTANT Coef_SZ : INTEGER := 9; | |
| 70 |
CONSTANT Coef |
|
70 | CONSTANT CoefCntPerCel : INTEGER := 6; | |
| 71 |
CONSTANT Coef |
|
71 | CONSTANT CoefPerCel : INTEGER := 5; | |
| 72 |
CONSTANT |
|
72 | CONSTANT Cels_count : INTEGER := 5; | |
| 73 | CONSTANT Cels_count : INTEGER := 5; |
|
73 | ||
| 74 |
|
74 | SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0); | ||
| 75 | SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0); |
|
75 | SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
| 76 | SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); |
|
76 | -- | |
| 77 | -- |
|
77 | SIGNAL sample_filter_v2_out_val : STD_LOGIC; | |
| 78 | SIGNAL sample_filter_v2_out_val : STD_LOGIC; |
|
78 | SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
| 79 | SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); |
|
79 | -- | |
| 80 | -- |
|
80 | SIGNAL sample_filter_v2_out_r_val : STD_LOGIC; | |
| 81 | SIGNAL sample_filter_v2_out_r_val : STD_LOGIC; |
|
81 | SIGNAL sample_filter_v2_out_r : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
| 82 | SIGNAL sample_filter_v2_out_r : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); |
|
82 | ----------------------------------------------------------------------------- | |
| 83 | ----------------------------------------------------------------------------- |
|
83 | SIGNAL downsampling_cnt : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
| 84 |
SIGNAL downsampling_ |
|
84 | SIGNAL sample_downsampling_out_val : STD_LOGIC; | |
| 85 | SIGNAL sample_downsampling_out_val : STD_LOGIC; |
|
85 | SIGNAL sample_downsampling_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
| 86 | SIGNAL sample_downsampling_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); |
|
86 | -- | |
| 87 | -- |
|
87 | SIGNAL sample_f0_val : STD_LOGIC; | |
| 88 | SIGNAL sample_f0_val : STD_LOGIC; |
|
88 | SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
| 89 | SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); |
|
89 | ----------------------------------------------------------------------------- | |
| 90 | -- |
|
90 | SIGNAL sample_f1_val : STD_LOGIC; | |
| 91 | SIGNAL sample_f0_0_val : STD_LOGIC; |
|
91 | SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
| 92 | SIGNAL sample_f0_1_val : STD_LOGIC; |
|
92 | -- | |
| 93 |
SIGNAL |
|
93 | SIGNAL sample_f2_val : STD_LOGIC; | |
| 94 | ----------------------------------------------------------------------------- |
|
94 | SIGNAL sample_f2 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
| 95 | SIGNAL sample_f1_val : STD_LOGIC; |
|
95 | -- | |
| 96 | SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); |
|
96 | SIGNAL sample_f3_val : STD_LOGIC; | |
| 97 | -- |
|
97 | SIGNAL sample_f3 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
| 98 | SIGNAL sample_f2_val : STD_LOGIC; |
|
98 | ||
| 99 | SIGNAL sample_f2 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); |
|
99 | BEGIN | |
| 100 | -- |
|
100 | ||
| 101 | SIGNAL sample_f3_val : STD_LOGIC; |
|
101 | -- component instantiation | |
| 102 | SIGNAL sample_f3 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); |
|
102 | ----------------------------------------------------------------------------- | |
| 103 |
|
103 | DIGITAL_acquisition : AD7688_drvr | ||
| 104 | BEGIN |
|
104 | GENERIC MAP ( | |
| 105 |
|
105 | ChanelCount => ChanelCount, | ||
| 106 | -- component instantiation |
|
106 | ncycle_cnv_high => ncycle_cnv_high, | |
| 107 | ----------------------------------------------------------------------------- |
|
107 | ncycle_cnv => ncycle_cnv) | |
| 108 | DIGITAL_acquisition : ADS7886_drvr |
|
108 | PORT MAP ( | |
| 109 | GENERIC MAP ( |
|
109 | cnv_clk => cnv_clk, -- | |
| 110 | ChanelCount => ChanelCount, |
|
110 | cnv_rstn => cnv_rstn, -- | |
| 111 | ncycle_cnv_high => ncycle_cnv_high, |
|
111 | cnv_run => cnv_run, -- | |
| 112 | ncycle_cnv => ncycle_cnv) |
|
112 | cnv => cnv, -- | |
| 113 | PORT MAP ( |
|
113 | clk => clk, -- | |
| 114 |
|
|
114 | rstn => rstn, -- | |
| 115 |
|
|
115 | sck => sck, -- | |
| 116 | cnv_run => cnv_run, -- |
|
116 | sdo => sdo(ChanelCount-1 DOWNTO 0), -- | |
| 117 | cnv => cnv, -- |
|
117 | sample => sample, | |
| 118 | clk => clk, -- |
|
118 | sample_val => sample_val); | |
| 119 | rstn => rstn, -- |
|
119 | ||
| 120 | sck => sck, -- |
|
120 | ----------------------------------------------------------------------------- | |
| 121 | sdo => sdo(ChanelCount-1 DOWNTO 0), -- |
|
121 | ||
| 122 | sample => sample, |
|
122 | PROCESS (clk, rstn) | |
| 123 | sample_val => sample_val); |
|
123 | BEGIN -- PROCESS | |
| 124 |
|
124 | IF rstn = '0' THEN -- asynchronous reset (active low) | ||
| 125 | ----------------------------------------------------------------------------- |
|
125 | sample_val_delay <= '0'; | |
| 126 |
|
126 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | ||
| 127 | PROCESS (clk, rstn) |
|
127 | sample_val_delay <= sample_val; | |
| 128 | BEGIN -- PROCESS |
|
128 | END IF; | |
| 129 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
129 | END PROCESS; | |
| 130 | sample_val_delay <= '0'; |
|
130 | ||
| 131 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
131 | ----------------------------------------------------------------------------- | |
| 132 | sample_val_delay <= sample_val; |
|
132 | ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE | |
| 133 | END IF; |
|
133 | SampleLoop : FOR j IN 0 TO 15 GENERATE | |
| 134 | END PROCESS; |
|
134 | sample_filter_in(i, j) <= sample(i)(j); | |
| 135 |
|
135 | END GENERATE; | ||
| 136 | ----------------------------------------------------------------------------- |
|
136 | ||
| 137 | ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE |
|
137 | sample_filter_in(i, 16) <= sample(i)(15); | |
| 138 | SampleLoop : FOR j IN 0 TO 15 GENERATE |
|
138 | sample_filter_in(i, 17) <= sample(i)(15); | |
| 139 | sample_filter_in(i, j) <= sample(i)(j); |
|
139 | END GENERATE; | |
| 140 | END GENERATE; |
|
140 | ||
| 141 |
|
141 | coefs_v2 <= CoefsInitValCst_v2; | ||
| 142 | sample_filter_in(i, 16) <= sample(i)(15); |
|
142 | ||
| 143 | sample_filter_in(i, 17) <= sample(i)(15); |
|
143 | IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 | |
| 144 | END GENERATE; |
|
144 | GENERIC MAP ( | |
| 145 |
|
145 | tech => 0, | ||
| 146 | coefs_v2 <= CoefsInitValCst_v2; |
|
146 | Mem_use => use_RAM, | |
| 147 |
|
147 | Sample_SZ => 18, | ||
| 148 | IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 |
|
148 | Coef_SZ => Coef_SZ, | |
| 149 | GENERIC MAP ( |
|
149 | Coef_Nb => 25, -- TODO | |
| 150 | tech => 0, |
|
150 | Coef_sel_SZ => 5, -- TODO | |
| 151 | Mem_use => use_RAM, |
|
151 | Cels_count => Cels_count, | |
| 152 | Sample_SZ => 18, |
|
152 | ChanelsCount => ChanelCount) | |
| 153 | Coef_SZ => Coef_SZ, |
|
153 | PORT MAP ( | |
| 154 | Coef_Nb => 25, -- TODO |
|
154 | rstn => rstn, | |
| 155 | Coef_sel_SZ => 5, -- TODO |
|
155 | clk => clk, | |
| 156 | Cels_count => Cels_count, |
|
156 | virg_pos => 7, | |
| 157 | ChanelsCount => ChanelCount) |
|
157 | coefs => coefs_v2, | |
| 158 | PORT MAP ( |
|
158 | sample_in_val => sample_val_delay, | |
| 159 | rstn => rstn, |
|
159 | sample_in => sample_filter_in, | |
| 160 | clk => clk, |
|
160 | sample_out_val => sample_filter_v2_out_val, | |
| 161 | virg_pos => 7, |
|
161 | sample_out => sample_filter_v2_out); | |
| 162 | coefs => coefs_v2, |
|
162 | ||
| 163 | sample_in_val => sample_val_delay, |
|
163 | ----------------------------------------------------------------------------- | |
| 164 | sample_in => sample_filter_in, |
|
164 | PROCESS (clk, rstn) | |
| 165 | sample_out_val => sample_filter_v2_out_val, |
|
165 | BEGIN -- PROCESS | |
| 166 | sample_out => sample_filter_v2_out); |
|
166 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
| 167 |
|
167 | sample_filter_v2_out_r_val <= '0'; | ||
| 168 | ----------------------------------------------------------------------------- |
|
168 | rst_all_chanel : FOR I IN ChanelCount-1 DOWNTO 0 LOOP | |
| 169 | PROCESS (clk, rstn) |
|
169 | rst_all_bits : FOR J IN 17 DOWNTO 0 LOOP | |
| 170 | BEGIN -- PROCESS |
|
170 | sample_filter_v2_out_r(I, J) <= '0'; | |
| 171 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
171 | END LOOP rst_all_bits; | |
| 172 | sample_filter_v2_out_r_val <= '0'; |
|
172 | END LOOP rst_all_chanel; | |
| 173 | rst_all_chanel : FOR I IN ChanelCount-1 DOWNTO 0 LOOP |
|
173 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
| 174 | rst_all_bits : FOR J IN 17 DOWNTO 0 LOOP |
|
174 | sample_filter_v2_out_r_val <= sample_filter_v2_out_val; | |
| 175 |
|
|
175 | IF sample_filter_v2_out_val = '1' THEN | |
| 176 | END LOOP rst_all_bits; |
|
176 | sample_filter_v2_out_r <= sample_filter_v2_out; | |
| 177 | END LOOP rst_all_chanel; |
|
177 | END IF; | |
| 178 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
178 | END IF; | |
| 179 | sample_filter_v2_out_r_val <= sample_filter_v2_out_val; |
|
179 | END PROCESS; | |
| 180 | IF sample_filter_v2_out_val = '1' THEN |
|
180 | ||
| 181 | sample_filter_v2_out_r <= sample_filter_v2_out; |
|
181 | ----------------------------------------------------------------------------- | |
| 182 | END IF; |
|
182 | -- F0 -- @24.576 kHz | |
| 183 | END IF; |
|
183 | ----------------------------------------------------------------------------- | |
| 184 | END PROCESS; |
|
184 | Downsampling_f0 : Downsampling | |
| 185 |
|
185 | GENERIC MAP ( | ||
| 186 | ----------------------------------------------------------------------------- |
|
186 | ChanelCount => ChanelCount, | |
| 187 | -- F0 -- @24.576 kHz |
|
187 | SampleSize => 18, | |
| 188 | ----------------------------------------------------------------------------- |
|
188 | DivideParam => 4) | |
| 189 | Downsampling_f0 : Downsampling |
|
189 | PORT MAP ( | |
| 190 | GENERIC MAP ( |
|
190 | clk => clk, | |
| 191 | ChanelCount => ChanelCount, |
|
191 | rstn => rstn, | |
| 192 | SampleSize => 18, |
|
192 | sample_in_val => sample_filter_v2_out_val , | |
| 193 | DivideParam => 4) |
|
193 | sample_in => sample_filter_v2_out, | |
| 194 | PORT MAP ( |
|
194 | sample_out_val => sample_f0_val, | |
| 195 | clk => clk, |
|
195 | sample_out => sample_f0); | |
| 196 | rstn => rstn, |
|
196 | ||
| 197 | sample_in_val => sample_filter_v2_out_val , |
|
197 | all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE | |
| 198 |
|
|
198 | sample_f0_wdata(I) <= sample_f0(0, I); | |
| 199 |
|
|
199 | sample_f0_wdata(16*1+I) <= sample_f0(1, I); | |
| 200 |
|
|
200 | sample_f0_wdata(16*2+I) <= sample_f0(2, I); | |
| 201 |
|
201 | sample_f0_wdata(16*3+I) <= sample_f0(6, I); | ||
| 202 | all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE |
|
202 | sample_f0_wdata(16*4+I) <= sample_f0(7, I); | |
| 203 | sample_f0_wdata(I) <= sample_f0(0, I); |
|
203 | END GENERATE all_bit_sample_f0; | |
| 204 | sample_f0_wdata(16*1+I) <= sample_f0(1, I); |
|
204 | ||
| 205 |
sample_f0_w |
|
205 | sample_f0_wen <= NOT(sample_f0_val) & | |
| 206 | sample_f0_wdata(16*3+I) <= sample_f0(6, I); |
|
206 | NOT(sample_f0_val) & | |
| 207 | sample_f0_wdata(16*4+I) <= sample_f0(7, I); |
|
207 | NOT(sample_f0_val) & | |
| 208 | END GENERATE all_bit_sample_f0; |
|
208 | NOT(sample_f0_val) & | |
| 209 |
|
209 | NOT(sample_f0_val); | ||
| 210 | PROCESS (clk, rstn) |
|
210 | ||
| 211 | BEGIN -- PROCESS |
|
211 | ----------------------------------------------------------------------------- | |
| 212 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
212 | -- F1 -- @4096 Hz | |
| 213 | counter_f0 <= 0; |
|
213 | ----------------------------------------------------------------------------- | |
| 214 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
214 | Downsampling_f1 : Downsampling | |
| 215 | IF sample_f0_val = '1' THEN |
|
215 | GENERIC MAP ( | |
| 216 | IF counter_f0 = 511 THEN |
|
216 | ChanelCount => ChanelCount, | |
| 217 | counter_f0 <= 0; |
|
217 | SampleSize => 18, | |
| 218 | ELSE |
|
218 | DivideParam => 6) | |
| 219 | counter_f0 <= counter_f0 + 1; |
|
219 | PORT MAP ( | |
| 220 | END IF; |
|
220 | clk => clk, | |
| 221 | END IF; |
|
221 | rstn => rstn, | |
| 222 | END IF; |
|
222 | sample_in_val => sample_f0_val , | |
| 223 | END PROCESS; |
|
223 | sample_in => sample_f0, | |
| 224 |
|
224 | sample_out_val => sample_f1_val, | ||
| 225 | sample_f0_0_val <= sample_f0_val WHEN counter_f0 < 256 ELSE '0'; |
|
225 | sample_out => sample_f1); | |
| 226 | sample_f0_0_wen <= NOT(sample_f0_0_val) & |
|
226 | ||
| 227 | NOT(sample_f0_0_val) & |
|
227 | sample_f1_wen <= NOT(sample_f1_val) & | |
| 228 |
|
|
228 | NOT(sample_f1_val) & | |
| 229 |
|
|
229 | NOT(sample_f1_val) & | |
| 230 |
|
|
230 | NOT(sample_f1_val) & | |
| 231 |
|
231 | NOT(sample_f1_val); | ||
| 232 | sample_f0_1_val <= sample_f0_val WHEN counter_f0 > 255 ELSE '0'; |
|
232 | ||
| 233 | sample_f0_1_wen <= NOT(sample_f0_1_val) & |
|
233 | all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE | |
| 234 | NOT(sample_f0_1_val) & |
|
234 | sample_f1_wdata(I) <= sample_f1(0, I); | |
| 235 | NOT(sample_f0_1_val) & |
|
235 | sample_f1_wdata(16*1+I) <= sample_f1(1, I); | |
| 236 | NOT(sample_f0_1_val) & |
|
236 | sample_f1_wdata(16*2+I) <= sample_f1(2, I); | |
| 237 | NOT(sample_f0_1_val); |
|
237 | sample_f1_wdata(16*3+I) <= sample_f1(6, I); | |
| 238 |
|
238 | sample_f1_wdata(16*4+I) <= sample_f1(7, I); | ||
| 239 |
|
239 | END GENERATE all_bit_sample_f1; | ||
| 240 | ----------------------------------------------------------------------------- |
|
240 | ||
| 241 | -- F1 -- @4096 Hz |
|
241 | ----------------------------------------------------------------------------- | |
| 242 | ----------------------------------------------------------------------------- |
|
242 | -- F2 -- @16 Hz | |
| 243 | Downsampling_f1 : Downsampling |
|
243 | ----------------------------------------------------------------------------- | |
| 244 | GENERIC MAP ( |
|
244 | Downsampling_f2 : Downsampling | |
| 245 | ChanelCount => ChanelCount, |
|
245 | GENERIC MAP ( | |
| 246 | SampleSize => 18, |
|
246 | ChanelCount => ChanelCount, | |
| 247 | DivideParam => 6) |
|
247 | SampleSize => 18, | |
| 248 | PORT MAP ( |
|
248 | DivideParam => 96) | |
| 249 | clk => clk, |
|
249 | PORT MAP ( | |
| 250 |
|
|
250 | clk => clk, | |
| 251 | sample_in_val => sample_f0_val , |
|
251 | rstn => rstn, | |
| 252 |
sample_in |
|
252 | sample_in_val => sample_f1_val , | |
| 253 |
sample_ |
|
253 | sample_in => sample_f1, | |
| 254 |
sample_out |
|
254 | sample_out_val => sample_f2_val, | |
| 255 |
|
255 | sample_out => sample_f2); | ||
| 256 | sample_f1_wen <= NOT(sample_f1_val) & |
|
256 | ||
| 257 | NOT(sample_f1_val) & |
|
257 | sample_f2_wen <= NOT(sample_f2_val) & | |
| 258 |
NOT(sample_f |
|
258 | NOT(sample_f2_val) & | |
| 259 |
NOT(sample_f |
|
259 | NOT(sample_f2_val) & | |
| 260 |
NOT(sample_f |
|
260 | NOT(sample_f2_val) & | |
| 261 |
|
261 | NOT(sample_f2_val); | ||
| 262 | all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE |
|
262 | ||
| 263 | sample_f1_wdata(I) <= sample_f1(0, I); |
|
263 | all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE | |
| 264 |
sample_f |
|
264 | sample_f2_wdata(I) <= sample_f2(0, I); | |
| 265 |
sample_f |
|
265 | sample_f2_wdata(16*1+I) <= sample_f2(1, I); | |
| 266 |
sample_f |
|
266 | sample_f2_wdata(16*2+I) <= sample_f2(2, I); | |
| 267 |
sample_f |
|
267 | sample_f2_wdata(16*3+I) <= sample_f2(6, I); | |
| 268 | END GENERATE all_bit_sample_f1; |
|
268 | sample_f2_wdata(16*4+I) <= sample_f2(7, I); | |
| 269 |
|
269 | END GENERATE all_bit_sample_f2; | ||
| 270 | ----------------------------------------------------------------------------- |
|
270 | ||
| 271 | -- F2 -- @16 Hz |
|
271 | ----------------------------------------------------------------------------- | |
| 272 | ----------------------------------------------------------------------------- |
|
272 | -- F3 -- @256 Hz | |
| 273 | Downsampling_f2 : Downsampling |
|
273 | ----------------------------------------------------------------------------- | |
| 274 | GENERIC MAP ( |
|
274 | Downsampling_f3 : Downsampling | |
| 275 | ChanelCount => ChanelCount, |
|
275 | GENERIC MAP ( | |
| 276 | SampleSize => 18, |
|
276 | ChanelCount => ChanelCount, | |
| 277 | DivideParam => 256) |
|
277 | SampleSize => 18, | |
| 278 | PORT MAP ( |
|
278 | DivideParam => 256) | |
| 279 | clk => clk, |
|
279 | PORT MAP ( | |
| 280 |
|
|
280 | clk => clk, | |
| 281 | sample_in_val => sample_f1_val , |
|
281 | rstn => rstn, | |
| 282 |
sample_in |
|
282 | sample_in_val => sample_f0_val , | |
| 283 |
sample_ |
|
283 | sample_in => sample_f0, | |
| 284 |
sample_out |
|
284 | sample_out_val => sample_f3_val, | |
| 285 |
|
285 | sample_out => sample_f3); | ||
| 286 | sample_f2_wen <= NOT(sample_f2_val) & |
|
286 | ||
| 287 | NOT(sample_f2_val) & |
|
287 | sample_f3_wen <= (NOT sample_f3_val) & | |
| 288 |
NOT |
|
288 | (NOT sample_f3_val) & | |
| 289 |
NOT |
|
289 | (NOT sample_f3_val) & | |
| 290 |
NOT |
|
290 | (NOT sample_f3_val) & | |
| 291 |
|
291 | (NOT sample_f3_val); | ||
| 292 | all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE |
|
292 | ||
| 293 | sample_f2_wdata(I) <= sample_f2(0, I); |
|
293 | all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE | |
| 294 |
sample_f |
|
294 | sample_f3_wdata(I) <= sample_f3(0, I); | |
| 295 |
sample_f |
|
295 | sample_f3_wdata(16*1+I) <= sample_f3(1, I); | |
| 296 |
sample_f |
|
296 | sample_f3_wdata(16*2+I) <= sample_f3(2, I); | |
| 297 |
sample_f |
|
297 | sample_f3_wdata(16*3+I) <= sample_f3(6, I); | |
| 298 | END GENERATE all_bit_sample_f2; |
|
298 | sample_f3_wdata(16*4+I) <= sample_f3(7, I); | |
| 299 |
|
299 | END GENERATE all_bit_sample_f3; | ||
| 300 | ----------------------------------------------------------------------------- |
|
300 | ||
| 301 | -- F3 -- @256 Hz |
|
301 | ||
| 302 | ----------------------------------------------------------------------------- |
|
302 | ||
| 303 | Downsampling_f3 : Downsampling |
|
303 | END tb; | |
| 304 | GENERIC MAP ( |
|
|||
| 305 | ChanelCount => ChanelCount, |
|
|||
| 306 | SampleSize => 18, |
|
|||
| 307 | DivideParam => 96) |
|
|||
| 308 | PORT MAP ( |
|
|||
| 309 | clk => clk, |
|
|||
| 310 | rstn => rstn, |
|
|||
| 311 | sample_in_val => sample_f0_val , |
|
|||
| 312 | sample_in => sample_f0, |
|
|||
| 313 | sample_out_val => sample_f3_val, |
|
|||
| 314 | sample_out => sample_f3); |
|
|||
| 315 |
|
||||
| 316 | sample_f3_wen <= (NOT sample_f3_val) & |
|
|||
| 317 | (NOT sample_f3_val) & |
|
|||
| 318 | (NOT sample_f3_val) & |
|
|||
| 319 | (NOT sample_f3_val) & |
|
|||
| 320 | (NOT sample_f3_val); |
|
|||
| 321 |
|
||||
| 322 | all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE |
|
|||
| 323 | sample_f3_wdata(I) <= sample_f3(0, I); |
|
|||
| 324 | sample_f3_wdata(16*1+I) <= sample_f3(1, I); |
|
|||
| 325 | sample_f3_wdata(16*2+I) <= sample_f3(2, I); |
|
|||
| 326 | sample_f3_wdata(16*3+I) <= sample_f3(6, I); |
|
|||
| 327 | sample_f3_wdata(16*4+I) <= sample_f3(7, I); |
|
|||
| 328 | END GENERATE all_bit_sample_f3; |
|
|||
| 329 |
|
||||
| 330 |
|
||||
| 331 |
|
||||
| 332 | END tb; |
|
|||
| @@ -36,6 +36,12 USE techmap.gencomp.ALL; | |||||
| 36 |
|
36 | |||
| 37 | ENTITY lpp_top_apbreg IS |
|
37 | ENTITY lpp_top_apbreg IS | |
| 38 | GENERIC ( |
|
38 | GENERIC ( | |
|
|
39 | nb_burst_available_size : INTEGER := 11; | |||
|
|
40 | nb_snapshot_param_size : INTEGER := 11; | |||
|
|
41 | delta_snapshot_size : INTEGER := 16; | |||
|
|
42 | delta_f2_f0_size : INTEGER := 10; | |||
|
|
43 | delta_f2_f1_size : INTEGER := 10; | |||
|
|
44 | ||||
| 39 | pindex : INTEGER := 4; |
|
45 | pindex : INTEGER := 4; | |
| 40 | paddr : INTEGER := 4; |
|
46 | paddr : INTEGER := 4; | |
| 41 | pmask : INTEGER := 16#fff#; |
|
47 | pmask : INTEGER := 16#fff#; | |
| @@ -49,6 +55,8 ENTITY lpp_top_apbreg IS | |||||
| 49 | apbi : IN apb_slv_in_type; |
|
55 | apbi : IN apb_slv_in_type; | |
| 50 | apbo : OUT apb_slv_out_type; |
|
56 | apbo : OUT apb_slv_out_type; | |
| 51 |
|
57 | |||
|
|
58 | --------------------------------------------------------------------------- | |||
|
|
59 | -- Spectral Matrix Reg | |||
| 52 | -- IN |
|
60 | -- IN | |
| 53 | ready_matrix_f0_0 : IN STD_LOGIC; |
|
61 | ready_matrix_f0_0 : IN STD_LOGIC; | |
| 54 | ready_matrix_f0_1 : IN STD_LOGIC; |
|
62 | ready_matrix_f0_1 : IN STD_LOGIC; | |
| @@ -71,7 +79,43 ENTITY lpp_top_apbreg IS | |||||
| 71 | addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
79 | addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 72 | addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
80 | addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 73 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
81 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 74 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
82 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
|
83 | --------------------------------------------------------------------------- | |||
|
|
84 | --------------------------------------------------------------------------- | |||
|
|
85 | -- WaveForm picker Reg | |||
|
|
86 | status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
87 | status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
88 | status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
89 | status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
90 | ||||
|
|
91 | -- OUT | |||
|
|
92 | data_shaping_BW : OUT STD_LOGIC; | |||
|
|
93 | data_shaping_SP0 : OUT STD_LOGIC; | |||
|
|
94 | data_shaping_SP1 : OUT STD_LOGIC; | |||
|
|
95 | data_shaping_R0 : OUT STD_LOGIC; | |||
|
|
96 | data_shaping_R1 : OUT STD_LOGIC; | |||
|
|
97 | ||||
|
|
98 | delta_snapshot : OUT STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); | |||
|
|
99 | delta_f2_f1 : OUT STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); | |||
|
|
100 | delta_f2_f0 : OUT STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); | |||
|
|
101 | nb_burst_available : OUT STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); | |||
|
|
102 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |||
|
|
103 | ||||
|
|
104 | enable_f0 : OUT STD_LOGIC; | |||
|
|
105 | enable_f1 : OUT STD_LOGIC; | |||
|
|
106 | enable_f2 : OUT STD_LOGIC; | |||
|
|
107 | enable_f3 : OUT STD_LOGIC; | |||
|
|
108 | ||||
|
|
109 | burst_f0 : OUT STD_LOGIC; | |||
|
|
110 | burst_f1 : OUT STD_LOGIC; | |||
|
|
111 | burst_f2 : OUT STD_LOGIC; | |||
|
|
112 | ||||
|
|
113 | addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
114 | addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
115 | addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
116 | addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |||
|
|
117 | ||||
|
|
118 | --------------------------------------------------------------------------- | |||
| 75 | ); |
|
119 | ); | |
| 76 |
|
120 | |||
| 77 | END lpp_top_apbreg; |
|
121 | END lpp_top_apbreg; | |
| @@ -84,7 +128,7 ARCHITECTURE beh OF lpp_top_apbreg IS | |||||
| 84 | 0 => ahb_device_reg (VENDOR_LPP, LPP_DMA_TYPE, 0, REVISION, pirq), |
|
128 | 0 => ahb_device_reg (VENDOR_LPP, LPP_DMA_TYPE, 0, REVISION, pirq), | |
| 85 | 1 => apb_iobar(paddr, pmask)); |
|
129 | 1 => apb_iobar(paddr, pmask)); | |
| 86 |
|
130 | |||
| 87 |
TYPE lpp_ |
|
131 | TYPE lpp_SpectralMatrix_regs IS RECORD | |
| 88 | config_active_interruption_onNewMatrix : STD_LOGIC; |
|
132 | config_active_interruption_onNewMatrix : STD_LOGIC; | |
| 89 | config_active_interruption_onError : STD_LOGIC; |
|
133 | config_active_interruption_onError : STD_LOGIC; | |
| 90 | status_ready_matrix_f0_0 : STD_LOGIC; |
|
134 | status_ready_matrix_f0_0 : STD_LOGIC; | |
| @@ -98,53 +142,144 ARCHITECTURE beh OF lpp_top_apbreg IS | |||||
| 98 | addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
142 | addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 99 | addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
143 | addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 100 | END RECORD; |
|
144 | END RECORD; | |
|
|
145 | SIGNAL reg_sp : lpp_SpectralMatrix_regs; | |||
| 101 |
|
146 | |||
| 102 | SIGNAL reg : lpp_dma_regs; |
|
147 | TYPE lpp_WaveformPicker_regs IS RECORD | |
|
|
148 | status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
149 | status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
150 | status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
151 | data_shaping_BW : STD_LOGIC; | |||
|
|
152 | data_shaping_SP0 : STD_LOGIC; | |||
|
|
153 | data_shaping_SP1 : STD_LOGIC; | |||
|
|
154 | data_shaping_R0 : STD_LOGIC; | |||
|
|
155 | data_shaping_R1 : STD_LOGIC; | |||
|
|
156 | delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); | |||
|
|
157 | delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); | |||
|
|
158 | delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); | |||
|
|
159 | nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); | |||
|
|
160 | nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |||
|
|
161 | enable_f0 : STD_LOGIC; | |||
|
|
162 | enable_f1 : STD_LOGIC; | |||
|
|
163 | enable_f2 : STD_LOGIC; | |||
|
|
164 | enable_f3 : STD_LOGIC; | |||
|
|
165 | burst_f0 : STD_LOGIC; | |||
|
|
166 | burst_f1 : STD_LOGIC; | |||
|
|
167 | burst_f2 : STD_LOGIC; | |||
|
|
168 | addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
169 | addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
170 | addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
171 | addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
172 | END RECORD; | |||
|
|
173 | SIGNAL reg_wp : lpp_WaveformPicker_regs; | |||
| 103 |
|
174 | |||
| 104 | SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
175 | SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 105 |
|
176 | |||
| 106 | BEGIN -- beh |
|
177 | BEGIN -- beh | |
| 107 |
|
178 | |||
| 108 | status_ready_matrix_f0_0 <= reg.status_ready_matrix_f0_0; |
|
179 | status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0; | |
| 109 | status_ready_matrix_f0_1 <= reg.status_ready_matrix_f0_1; |
|
180 | status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1; | |
| 110 | status_ready_matrix_f1 <= reg.status_ready_matrix_f1; |
|
181 | status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1; | |
| 111 | status_ready_matrix_f2 <= reg.status_ready_matrix_f2; |
|
182 | status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2; | |
| 112 | status_error_anticipating_empty_fifo <= reg.status_error_anticipating_empty_fifo; |
|
183 | status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo; | |
| 113 | status_error_bad_component_error <= reg.status_error_bad_component_error; |
|
184 | status_error_bad_component_error <= reg_sp.status_error_bad_component_error; | |
|
|
185 | ||||
|
|
186 | config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix; | |||
|
|
187 | config_active_interruption_onError <= reg_sp.config_active_interruption_onError; | |||
|
|
188 | addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0; | |||
|
|
189 | addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1; | |||
|
|
190 | addr_matrix_f1 <= reg_sp.addr_matrix_f1; | |||
|
|
191 | addr_matrix_f2 <= reg_sp.addr_matrix_f2; | |||
|
|
192 | ||||
| 114 |
|
193 | |||
| 115 | config_active_interruption_onNewMatrix <= reg.config_active_interruption_onNewMatrix; |
|
194 | ||
| 116 | config_active_interruption_onError <= reg.config_active_interruption_onError; |
|
195 | ||
| 117 | addr_matrix_f0_0 <= reg.addr_matrix_f0_0; |
|
196 | data_shaping_BW <= reg_wp.data_shaping_BW; | |
| 118 | addr_matrix_f0_1 <= reg.addr_matrix_f0_1; |
|
197 | data_shaping_SP0 <= reg_wp.data_shaping_SP0; | |
| 119 | addr_matrix_f1 <= reg.addr_matrix_f1; |
|
198 | data_shaping_SP1 <= reg_wp.data_shaping_SP1; | |
| 120 | addr_matrix_f2 <= reg.addr_matrix_f2; |
|
199 | data_shaping_R0 <= reg_wp.data_shaping_R0; | |
|
|
200 | data_shaping_R1 <= reg_wp.data_shaping_R1; | |||
|
|
201 | ||||
|
|
202 | delta_snapshot <= reg_wp.delta_snapshot; | |||
|
|
203 | delta_f2_f1 <= reg_wp.delta_f2_f1; | |||
|
|
204 | delta_f2_f0 <= reg_wp.delta_f2_f0; | |||
|
|
205 | nb_burst_available <= reg_wp.nb_burst_available; | |||
|
|
206 | nb_snapshot_param <= reg_wp.nb_snapshot_param; | |||
|
|
207 | ||||
|
|
208 | enable_f0 <= reg_wp.enable_f0; | |||
|
|
209 | enable_f1 <= reg_wp.enable_f1; | |||
|
|
210 | enable_f2 <= reg_wp.enable_f2; | |||
|
|
211 | enable_f3 <= reg_wp.enable_f3; | |||
|
|
212 | ||||
|
|
213 | burst_f0 <= reg_wp.burst_f0; | |||
|
|
214 | burst_f1 <= reg_wp.burst_f1; | |||
|
|
215 | burst_f2 <= reg_wp.burst_f2; | |||
|
|
216 | ||||
|
|
217 | addr_data_f0 <= reg_wp.addr_data_f0; | |||
|
|
218 | addr_data_f1 <= reg_wp.addr_data_f1; | |||
|
|
219 | addr_data_f2 <= reg_wp.addr_data_f2; | |||
|
|
220 | addr_data_f3 <= reg_wp.addr_data_f3; | |||
| 121 |
|
221 | |||
| 122 | lpp_top_apbreg : PROCESS (HCLK, HRESETn) |
|
222 | lpp_top_apbreg : PROCESS (HCLK, HRESETn) | |
| 123 | VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2); |
|
223 | VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2); | |
| 124 | BEGIN -- PROCESS lpp_dma_top |
|
224 | BEGIN -- PROCESS lpp_dma_top | |
| 125 |
IF HRESETn = '0' THEN |
|
225 | IF HRESETn = '0' THEN -- asynchronous reset (active low) | |
| 126 | reg.config_active_interruption_onNewMatrix <= '0'; |
|
226 | reg_sp.config_active_interruption_onNewMatrix <= '0'; | |
| 127 | reg.config_active_interruption_onError <= '0'; |
|
227 | reg_sp.config_active_interruption_onError <= '0'; | |
| 128 | reg.status_ready_matrix_f0_0 <= '0'; |
|
228 | reg_sp.status_ready_matrix_f0_0 <= '0'; | |
| 129 | reg.status_ready_matrix_f0_1 <= '0'; |
|
229 | reg_sp.status_ready_matrix_f0_1 <= '0'; | |
| 130 | reg.status_ready_matrix_f1 <= '0'; |
|
230 | reg_sp.status_ready_matrix_f1 <= '0'; | |
| 131 | reg.status_ready_matrix_f2 <= '0'; |
|
231 | reg_sp.status_ready_matrix_f2 <= '0'; | |
| 132 | reg.status_error_anticipating_empty_fifo <= '0'; |
|
232 | reg_sp.status_error_anticipating_empty_fifo <= '0'; | |
| 133 | reg.status_error_bad_component_error <= '0'; |
|
233 | reg_sp.status_error_bad_component_error <= '0'; | |
| 134 | reg.addr_matrix_f0_0 <= (OTHERS => '0'); |
|
234 | reg_sp.addr_matrix_f0_0 <= (OTHERS => '0'); | |
| 135 | reg.addr_matrix_f0_1 <= (OTHERS => '0'); |
|
235 | reg_sp.addr_matrix_f0_1 <= (OTHERS => '0'); | |
| 136 | reg.addr_matrix_f1 <= (OTHERS => '0'); |
|
236 | reg_sp.addr_matrix_f1 <= (OTHERS => '0'); | |
| 137 | reg.addr_matrix_f2 <= (OTHERS => '0'); |
|
237 | reg_sp.addr_matrix_f2 <= (OTHERS => '0'); | |
| 138 | prdata <= (OTHERS => '0'); |
|
238 | prdata <= (OTHERS => '0'); | |
|
|
239 | ||||
|
|
240 | apbo.pirq <= (OTHERS => '0'); | |||
|
|
241 | ||||
|
|
242 | status_full_ack <= (OTHERS => '0'); | |||
|
|
243 | ||||
|
|
244 | reg_wp.data_shaping_BW <= '0'; | |||
|
|
245 | reg_wp.data_shaping_SP0 <= '0'; | |||
|
|
246 | reg_wp.data_shaping_SP1 <= '0'; | |||
|
|
247 | reg_wp.data_shaping_R0 <= '0'; | |||
|
|
248 | reg_wp.data_shaping_R1 <= '0'; | |||
|
|
249 | reg_wp.enable_f0 <= '0'; | |||
|
|
250 | reg_wp.enable_f1 <= '0'; | |||
|
|
251 | reg_wp.enable_f2 <= '0'; | |||
|
|
252 | reg_wp.enable_f3 <= '0'; | |||
|
|
253 | reg_wp.burst_f0 <= '0'; | |||
|
|
254 | reg_wp.burst_f1 <= '0'; | |||
|
|
255 | reg_wp.burst_f2 <= '0'; | |||
|
|
256 | reg_wp.addr_data_f0 <= (OTHERS => '0'); | |||
|
|
257 | reg_wp.addr_data_f1 <= (OTHERS => '0'); | |||
|
|
258 | reg_wp.addr_data_f2 <= (OTHERS => '0'); | |||
|
|
259 | reg_wp.addr_data_f3 <= (OTHERS => '0'); | |||
|
|
260 | reg_wp.status_full <= (OTHERS => '0'); | |||
|
|
261 | reg_wp.status_full_err <= (OTHERS => '0'); | |||
|
|
262 | reg_wp.status_new_err <= (OTHERS => '0'); | |||
|
|
263 | reg_wp.delta_snapshot <= (OTHERS => '0'); | |||
|
|
264 | reg_wp.delta_f2_f1 <= (OTHERS => '0'); | |||
|
|
265 | reg_wp.delta_f2_f0 <= (OTHERS => '0'); | |||
|
|
266 | reg_wp.nb_burst_available <= (OTHERS => '0'); | |||
|
|
267 | reg_wp.nb_snapshot_param <= (OTHERS => '0'); | |||
|
|
268 | ||||
| 139 |
|
|
269 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge | |
|
|
270 | status_full_ack <= (OTHERS => '0'); | |||
| 140 |
|
271 | |||
| 141 | reg.status_ready_matrix_f0_0 <= reg.status_ready_matrix_f0_0 OR ready_matrix_f0_0; |
|
272 | reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0; | |
| 142 | reg.status_ready_matrix_f0_1 <= reg.status_ready_matrix_f0_1 OR ready_matrix_f0_1; |
|
273 | reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1; | |
| 143 | reg.status_ready_matrix_f1 <= reg.status_ready_matrix_f1 OR ready_matrix_f1; |
|
274 | reg_sp.status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1 OR ready_matrix_f1; | |
| 144 | reg.status_ready_matrix_f2 <= reg.status_ready_matrix_f2 OR ready_matrix_f2; |
|
275 | reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2; | |
| 145 |
|
276 | |||
| 146 | reg.status_error_anticipating_empty_fifo <= reg.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo; |
|
277 | reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo; | |
| 147 | reg.status_error_bad_component_error <= reg.status_error_bad_component_error OR error_bad_component_error; |
|
278 | reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error; | |
|
|
279 | ||||
|
|
280 | reg_wp.status_full <= reg_wp.status_full OR status_full; | |||
|
|
281 | reg_wp.status_full_err <= reg_wp.status_full_err OR status_full_err; | |||
|
|
282 | reg_wp.status_new_err <= reg_wp.status_new_err OR status_new_err; | |||
| 148 |
|
283 | |||
| 149 | paddr := "000000"; |
|
284 | paddr := "000000"; | |
| 150 | paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2); |
|
285 | paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2); | |
| @@ -152,44 +287,119 BEGIN -- beh | |||||
| 152 | IF apbi.psel(pindex) = '1' THEN |
|
287 | IF apbi.psel(pindex) = '1' THEN | |
| 153 | -- APB DMA READ -- |
|
288 | -- APB DMA READ -- | |
| 154 | CASE paddr(7 DOWNTO 2) IS |
|
289 | CASE paddr(7 DOWNTO 2) IS | |
| 155 | WHEN "000000" => prdata(0) <= reg.config_active_interruption_onNewMatrix; |
|
290 | -- | |
| 156 |
|
|
291 | WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix; | |
| 157 | WHEN "000001" => prdata(0) <= reg.status_ready_matrix_f0_0; |
|
292 | prdata(1) <= reg_sp.config_active_interruption_onError; | |
| 158 |
|
|
293 | WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0; | |
| 159 |
prdata( |
|
294 | prdata(1) <= reg_sp.status_ready_matrix_f0_1; | |
| 160 |
prdata( |
|
295 | prdata(2) <= reg_sp.status_ready_matrix_f1; | |
| 161 |
prdata( |
|
296 | prdata(3) <= reg_sp.status_ready_matrix_f2; | |
| 162 |
prdata( |
|
297 | prdata(4) <= reg_sp.status_error_anticipating_empty_fifo; | |
| 163 | WHEN "000010" => prdata <= reg.addr_matrix_f0_0; |
|
298 | prdata(5) <= reg_sp.status_error_bad_component_error; | |
| 164 |
WHEN "00001 |
|
299 | WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0; | |
| 165 |
WHEN "000 |
|
300 | WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1; | |
| 166 |
WHEN "00010 |
|
301 | WHEN "000100" => prdata <= reg_sp.addr_matrix_f1; | |
| 167 |
WHEN "0001 |
|
302 | WHEN "000101" => prdata <= reg_sp.addr_matrix_f2; | |
|
|
303 | WHEN "000110" => prdata <= debug_reg; | |||
|
|
304 | -- | |||
|
|
305 | WHEN "001000" => prdata(0) <= reg_wp.data_shaping_BW; | |||
|
|
306 | prdata(1) <= reg_wp.data_shaping_SP0; | |||
|
|
307 | prdata(2) <= reg_wp.data_shaping_SP1; | |||
|
|
308 | prdata(3) <= reg_wp.data_shaping_R0; | |||
|
|
309 | prdata(4) <= reg_wp.data_shaping_R1; | |||
|
|
310 | WHEN "001001" => prdata(0) <= reg_wp.enable_f0; | |||
|
|
311 | prdata(1) <= reg_wp.enable_f1; | |||
|
|
312 | prdata(2) <= reg_wp.enable_f2; | |||
|
|
313 | prdata(3) <= reg_wp.enable_f3; | |||
|
|
314 | prdata(4) <= reg_wp.burst_f0; | |||
|
|
315 | prdata(5) <= reg_wp.burst_f1; | |||
|
|
316 | prdata(6) <= reg_wp.burst_f2; | |||
|
|
317 | WHEN "001010" => prdata <= reg_wp.addr_data_f0; | |||
|
|
318 | WHEN "001011" => prdata <= reg_wp.addr_data_f1; | |||
|
|
319 | WHEN "001100" => prdata <= reg_wp.addr_data_f2; | |||
|
|
320 | WHEN "001101" => prdata <= reg_wp.addr_data_f3; | |||
|
|
321 | WHEN "001110" => prdata(3 DOWNTO 0) <= reg_wp.status_full; | |||
|
|
322 | prdata(7 DOWNTO 4) <= reg_wp.status_full_err; | |||
|
|
323 | prdata(11 DOWNTO 8) <= reg_wp.status_new_err; | |||
|
|
324 | WHEN "001111" => prdata(delta_snapshot_size-1 DOWNTO 0) <= reg_wp.delta_snapshot; | |||
|
|
325 | WHEN "010000" => prdata(delta_f2_f1_size-1 DOWNTO 0) <= reg_wp.delta_f2_f1; | |||
|
|
326 | WHEN "010001" => prdata(delta_f2_f0_size-1 DOWNTO 0) <= reg_wp.delta_f2_f0; | |||
|
|
327 | WHEN "010010" => prdata(nb_burst_available_size-1 DOWNTO 0) <= reg_wp.nb_burst_available; | |||
|
|
328 | WHEN "010011" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param; | |||
|
|
329 | -- | |||
| 168 | WHEN OTHERS => NULL; |
|
330 | WHEN OTHERS => NULL; | |
| 169 | END CASE; |
|
331 | END CASE; | |
| 170 | IF (apbi.pwrite AND apbi.penable) = '1' THEN |
|
332 | IF (apbi.pwrite AND apbi.penable) = '1' THEN | |
| 171 | -- APB DMA WRITE -- |
|
333 | -- APB DMA WRITE -- | |
| 172 | CASE paddr(7 DOWNTO 2) IS |
|
334 | CASE paddr(7 DOWNTO 2) IS | |
| 173 | WHEN "000000" => reg.config_active_interruption_onNewMatrix <= apbi.pwdata(0); |
|
335 | -- | |
| 174 |
|
|
336 | WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0); | |
| 175 | WHEN "000001" => reg.status_ready_matrix_f0_0 <= apbi.pwdata(0); |
|
337 | reg_sp.config_active_interruption_onError <= apbi.pwdata(1); | |
| 176 |
|
|
338 | WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0); | |
| 177 |
reg.status_ready_matrix_f1 |
|
339 | reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1); | |
| 178 |
reg.status_ready_matrix_f |
|
340 | reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2); | |
| 179 |
reg.status_ |
|
341 | reg_sp.status_ready_matrix_f2 <= apbi.pwdata(3); | |
| 180 |
reg.status_error_ |
|
342 | reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4); | |
| 181 | WHEN "000010" => reg.addr_matrix_f0_0 <= apbi.pwdata; |
|
343 | reg_sp.status_error_bad_component_error <= apbi.pwdata(5); | |
| 182 |
WHEN "00001 |
|
344 | WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata; | |
| 183 |
WHEN "000 |
|
345 | WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata; | |
| 184 |
WHEN "00010 |
|
346 | WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata; | |
|
|
347 | WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata; | |||
|
|
348 | -- | |||
|
|
349 | WHEN "001000" => reg_wp.data_shaping_BW <= apbi.pwdata(0); | |||
|
|
350 | reg_wp.data_shaping_SP0 <= apbi.pwdata(1); | |||
|
|
351 | reg_wp.data_shaping_SP1 <= apbi.pwdata(2); | |||
|
|
352 | reg_wp.data_shaping_R0 <= apbi.pwdata(3); | |||
|
|
353 | reg_wp.data_shaping_R1 <= apbi.pwdata(4); | |||
|
|
354 | WHEN "001001" => reg_wp.enable_f0 <= apbi.pwdata(0); | |||
|
|
355 | reg_wp.enable_f1 <= apbi.pwdata(1); | |||
|
|
356 | reg_wp.enable_f2 <= apbi.pwdata(2); | |||
|
|
357 | reg_wp.enable_f3 <= apbi.pwdata(3); | |||
|
|
358 | reg_wp.burst_f0 <= apbi.pwdata(4); | |||
|
|
359 | reg_wp.burst_f1 <= apbi.pwdata(5); | |||
|
|
360 | reg_wp.burst_f2 <= apbi.pwdata(6); | |||
|
|
361 | WHEN "001010" => reg_wp.addr_data_f0 <= apbi.pwdata; | |||
|
|
362 | WHEN "001011" => reg_wp.addr_data_f1 <= apbi.pwdata; | |||
|
|
363 | WHEN "001100" => reg_wp.addr_data_f2 <= apbi.pwdata; | |||
|
|
364 | WHEN "001101" => reg_wp.addr_data_f3 <= apbi.pwdata; | |||
|
|
365 | WHEN "001110" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0); | |||
|
|
366 | reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4); | |||
|
|
367 | reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8); | |||
|
|
368 | status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0); | |||
|
|
369 | status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1); | |||
|
|
370 | status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2); | |||
|
|
371 | status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3); | |||
|
|
372 | WHEN "001111" => reg_wp.delta_snapshot <= apbi.pwdata(delta_snapshot_size-1 DOWNTO 0); | |||
|
|
373 | WHEN "010000" => reg_wp.delta_f2_f1 <= apbi.pwdata(delta_f2_f1_size-1 DOWNTO 0); | |||
|
|
374 | WHEN "010001" => reg_wp.delta_f2_f0 <= apbi.pwdata(delta_f2_f0_size-1 DOWNTO 0); | |||
|
|
375 | WHEN "010010" => reg_wp.nb_burst_available <= apbi.pwdata(nb_burst_available_size-1 DOWNTO 0); | |||
|
|
376 | WHEN "010011" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0); | |||
|
|
377 | -- | |||
| 185 | WHEN OTHERS => NULL; |
|
378 | WHEN OTHERS => NULL; | |
| 186 | END CASE; |
|
379 | END CASE; | |
| 187 | END IF; |
|
380 | END IF; | |
| 188 | END IF; |
|
381 | END IF; | |
|
|
382 | ||||
|
|
383 | apbo.pirq(pirq) <= (reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR | |||
|
|
384 | ready_matrix_f0_1 OR | |||
|
|
385 | ready_matrix_f1 OR | |||
|
|
386 | ready_matrix_f2) | |||
|
|
387 | ) | |||
|
|
388 | OR | |||
|
|
389 | (reg_sp.config_active_interruption_onError AND (error_anticipating_empty_fifo OR | |||
|
|
390 | error_bad_component_error) | |||
|
|
391 | ) | |||
|
|
392 | OR | |||
|
|
393 | (status_full(0) OR status_full_err(0) OR status_new_err(0) OR | |||
|
|
394 | status_full(1) OR status_full_err(1) OR status_new_err(1) OR | |||
|
|
395 | status_full(2) OR status_full_err(2) OR status_new_err(2) OR | |||
|
|
396 | status_full(3) OR status_full_err(3) OR status_new_err(3) | |||
|
|
397 | ); | |||
|
|
398 | ||||
|
|
399 | ||||
| 189 |
|
|
400 | END IF; | |
| 190 | END PROCESS lpp_top_apbreg; |
|
401 | END PROCESS lpp_top_apbreg; | |
| 191 |
|
402 | |||
| 192 | apbo.pirq <= (OTHERS => '0'); |
|
|||
| 193 | apbo.pindex <= pindex; |
|
403 | apbo.pindex <= pindex; | |
| 194 | apbo.pconfig <= pconfig; |
|
404 | apbo.pconfig <= pconfig; | |
| 195 | apbo.prdata <= prdata; |
|
405 | apbo.prdata <= prdata; | |
| @@ -14,7 +14,8 USE lpp.lpp_top_lfr_pkg.ALL; | |||||
| 14 | USE lpp.lpp_dma_pkg.ALL; |
|
14 | USE lpp.lpp_dma_pkg.ALL; | |
| 15 | USE lpp.lpp_demux.ALL; |
|
15 | USE lpp.lpp_demux.ALL; | |
| 16 | USE lpp.lpp_fft.ALL; |
|
16 | USE lpp.lpp_fft.ALL; | |
| 17 |
|
|
17 | USE lpp.lpp_matrix.ALL; | |
|
|
18 | USE lpp.lpp_waveform_pkg.ALL; | |||
| 18 | LIBRARY techmap; |
|
19 | LIBRARY techmap; | |
| 19 | USE techmap.gencomp.ALL; |
|
20 | USE techmap.gencomp.ALL; | |
| 20 |
|
21 | |||
| @@ -46,6 +47,10 ENTITY lpp_top_lfr IS | |||||
| 46 | -- AMBA AHB Master Interface |
|
47 | -- AMBA AHB Master Interface | |
| 47 | AHB_DMA_SpectralMatrix_In : IN AHB_Mst_In_Type; |
|
48 | AHB_DMA_SpectralMatrix_In : IN AHB_Mst_In_Type; | |
| 48 | AHB_DMA_SpectralMatrix_Out : OUT AHB_Mst_Out_Type |
|
49 | AHB_DMA_SpectralMatrix_Out : OUT AHB_Mst_Out_Type | |
|
|
50 | ||||
|
|
51 | -- Time | |||
|
|
52 | coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time | |||
|
|
53 | fine_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) --! fine time | |||
| 49 | ); |
|
54 | ); | |
| 50 | END lpp_top_lfr; |
|
55 | END lpp_top_lfr; | |
| 51 |
|
56 | |||
| @@ -53,8 +58,7 ARCHITECTURE tb OF lpp_top_lfr IS | |||||
| 53 |
|
58 | |||
| 54 | ----------------------------------------------------------------------------- |
|
59 | ----------------------------------------------------------------------------- | |
| 55 | -- f0 |
|
60 | -- f0 | |
| 56 |
SIGNAL sample_f0_ |
|
61 | SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 57 | SIGNAL sample_f0_1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
|||
| 58 | SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
62 | SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
| 59 | -- |
|
63 | -- | |
| 60 | SIGNAL sample_f0_0_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
64 | SIGNAL sample_f0_0_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| @@ -104,9 +108,9 ARCHITECTURE tb OF lpp_top_lfr IS | |||||
| 104 | SIGNAL fft_fifo_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
108 | SIGNAL fft_fifo_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 105 | SIGNAL fft_fifo_reuse : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
109 | SIGNAL fft_fifo_reuse : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 106 |
|
110 | |||
| 107 |
SIGNAL SP_fifo_data |
|
111 | SIGNAL SP_fifo_data : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
| 108 | SIGNAL SP_fifo_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
112 | SIGNAL SP_fifo_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 109 |
|
113 | |||
| 110 | SIGNAL fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
114 | SIGNAL fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 111 | SIGNAL fifo_empty : STD_LOGIC; |
|
115 | SIGNAL fifo_empty : STD_LOGIC; | |
| 112 | SIGNAL fifo_ren : STD_LOGIC; |
|
116 | SIGNAL fifo_ren : STD_LOGIC; | |
| @@ -136,6 +140,35 ARCHITECTURE tb OF lpp_top_lfr IS | |||||
| 136 | SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
140 | SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 137 | SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
141 | SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 138 | SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
142 | SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
|
143 | ||||
|
|
144 | ----------------------------------------------------------------------------- | |||
|
|
145 | -- | |||
|
|
146 | ----------------------------------------------------------------------------- | |||
|
|
147 | ||||
|
|
148 | CONSTANT nb_snapshot_param_size : INTEGER := 11; | |||
|
|
149 | CONSTANT delta_snapshot_size : INTEGER := 16; | |||
|
|
150 | CONSTANT delta_f2_f0_size : INTEGER := 10; | |||
|
|
151 | CONSTANT delta_f2_f1_size : INTEGER := 10; | |||
|
|
152 | ||||
|
|
153 | SIGNAL waveform_enable_f0 : STD_LOGIC; | |||
|
|
154 | SIGNAL waveform_enable_f1 : STD_LOGIC; | |||
|
|
155 | SIGNAL waveform_enable_f2 : STD_LOGIC; | |||
|
|
156 | SIGNAL waveform_enable_f3 : STD_LOGIC; | |||
|
|
157 | ||||
|
|
158 | SIGNAL waveform_burst_f0 : STD_LOGIC; | |||
|
|
159 | SIGNAL waveform_burst_f1 : STD_LOGIC; | |||
|
|
160 | SIGNAL waveform_burst_f2 : STD_LOGIC; | |||
|
|
161 | ||||
|
|
162 | SIGNAL waveform_nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |||
|
|
163 | SIGNAL waveform_delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); | |||
|
|
164 | SIGNAL waveform_delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); | |||
|
|
165 | SIGNAL waveform_delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); | |||
|
|
166 | ||||
|
|
167 | SIGNAL data_f0_in_valid : STD_LOGIC; | |||
|
|
168 | SIGNAL data_f0_in_valid_r : STD_LOGIC; | |||
|
|
169 | SIGNAL data_f1_in_valid : STD_LOGIC; | |||
|
|
170 | SIGNAL data_f2_in_valid : STD_LOGIC; | |||
|
|
171 | SIGNAL data_f3_in_valid : STD_LOGIC; | |||
| 139 |
|
172 | |||
| 140 | BEGIN |
|
173 | BEGIN | |
| 141 |
|
174 | |||
| @@ -155,8 +188,7 BEGIN | |||||
| 155 | clk => clk, |
|
188 | clk => clk, | |
| 156 | rstn => rstn, |
|
189 | rstn => rstn, | |
| 157 |
|
190 | |||
| 158 |
sample_f0_ |
|
191 | sample_f0_wen => sample_f0_wen, | |
| 159 | sample_f0_1_wen => sample_f0_1_wen, |
|
|||
| 160 | sample_f0_wdata => sample_f0_wdata, |
|
192 | sample_f0_wdata => sample_f0_wdata, | |
| 161 | sample_f1_wen => sample_f1_wen, |
|
193 | sample_f1_wen => sample_f1_wen, | |
| 162 | sample_f1_wdata => sample_f1_wdata, |
|
194 | sample_f1_wdata => sample_f1_wdata, | |
| @@ -169,7 +201,7 BEGIN | |||||
| 169 | -- FIFO |
|
201 | -- FIFO | |
| 170 | ----------------------------------------------------------------------------- |
|
202 | ----------------------------------------------------------------------------- | |
| 171 |
|
203 | |||
| 172 |
lppFIFO_f0 |
|
204 | lppFIFO_f0 : lppFIFOxN | |
| 173 | GENERIC MAP ( |
|
205 | GENERIC MAP ( | |
| 174 | tech => tech, |
|
206 | tech => tech, | |
| 175 | Data_sz => 16, |
|
207 | Data_sz => 16, | |
| @@ -181,31 +213,12 BEGIN | |||||
| 181 | rclk => clk, |
|
213 | rclk => clk, | |
| 182 | ReUse => (OTHERS => '0'), |
|
214 | ReUse => (OTHERS => '0'), | |
| 183 |
|
215 | |||
| 184 |
wen => sample_f0_ |
|
216 | wen => sample_f0_wen, | |
| 185 |
ren => sample_f0_ |
|
217 | ren => sample_f0_ren, | |
| 186 | wdata => sample_f0_wdata, |
|
218 | wdata => sample_f0_wdata, | |
| 187 |
rdata => sample_f0_ |
|
219 | rdata => sample_f0_rdata, | |
| 188 |
full => sample_f0_ |
|
220 | full => sample_f0_full, | |
| 189 |
empty => sample_f0_ |
|
221 | empty => sample_f0_empty); | |
| 190 |
|
||||
| 191 | lppFIFO_f0_1 : lppFIFOxN |
|
|||
| 192 | GENERIC MAP ( |
|
|||
| 193 | tech => tech, |
|
|||
| 194 | Data_sz => 16, |
|
|||
| 195 | FifoCnt => 5, |
|
|||
| 196 | Enable_ReUse => '0') |
|
|||
| 197 | PORT MAP ( |
|
|||
| 198 | rst => rstn, |
|
|||
| 199 | wclk => clk, |
|
|||
| 200 | rclk => clk, |
|
|||
| 201 | ReUse => (OTHERS => '0'), |
|
|||
| 202 |
|
||||
| 203 | wen => sample_f0_1_wen, |
|
|||
| 204 | ren => sample_f0_1_ren, |
|
|||
| 205 | wdata => sample_f0_wdata, |
|
|||
| 206 | rdata => sample_f0_1_rdata, |
|
|||
| 207 | full => sample_f0_1_full, |
|
|||
| 208 | empty => sample_f0_1_empty); |
|
|||
| 209 |
|
222 | |||
| 210 | lppFIFO_f1 : lppFIFOxN |
|
223 | lppFIFO_f1 : lppFIFOxN | |
| 211 | GENERIC MAP ( |
|
224 | GENERIC MAP ( | |
| @@ -226,7 +239,7 BEGIN | |||||
| 226 | full => sample_f1_full, |
|
239 | full => sample_f1_full, | |
| 227 | empty => sample_f1_empty); |
|
240 | empty => sample_f1_empty); | |
| 228 |
|
241 | |||
| 229 |
lppFIFO_f |
|
242 | lppFIFO_f2 : lppFIFOxN | |
| 230 | GENERIC MAP ( |
|
243 | GENERIC MAP ( | |
| 231 | tech => tech, |
|
244 | tech => tech, | |
| 232 | Data_sz => 16, |
|
245 | Data_sz => 16, | |
| @@ -238,92 +251,91 BEGIN | |||||
| 238 | rclk => clk, |
|
251 | rclk => clk, | |
| 239 | ReUse => (OTHERS => '0'), |
|
252 | ReUse => (OTHERS => '0'), | |
| 240 |
|
253 | |||
| 241 |
wen => sample_f |
|
254 | wen => sample_f2_wen, | |
| 242 |
ren => sample_f |
|
255 | ren => sample_f2_ren, | |
| 243 |
wdata => sample_f |
|
256 | wdata => sample_f2_wdata, | |
| 244 |
rdata => sample_f |
|
257 | rdata => sample_f2_rdata, | |
| 245 |
full => sample_f |
|
258 | full => sample_f2_full, | |
| 246 |
empty => sample_f |
|
259 | empty => sample_f2_empty); | |
| 247 |
|
260 | |||
| 248 | ----------------------------------------------------------------------------- |
|
261 | ----------------------------------------------------------------------------- | |
| 249 | -- SPECTRAL MATRIX |
|
262 | -- SPECTRAL MATRIX | |
| 250 | ----------------------------------------------------------------------------- |
|
263 | ----------------------------------------------------------------------------- | |
| 251 |
sample_f |
|
264 | --sample_f0_ren <= sample_ren(4 DOWNTO 0); | |
| 252 |
sample_f |
|
265 | --sample_f1_ren <= sample_ren(14 DOWNTO 10); | |
| 253 |
sample_f |
|
266 | --sample_f2_ren <= sample_ren(19 DOWNTO 15); | |
| 254 | sample_f3_ren <= sample_ren(19 DOWNTO 15); |
|
|||
| 255 |
|
267 | |||
| 256 | Demultiplex_1 : Demultiplex |
|
268 | --Demultiplex_1 : Demultiplex | |
| 257 | GENERIC MAP ( |
|
269 | -- GENERIC MAP ( | |
| 258 | Data_sz => 16) |
|
270 | -- Data_sz => 16) | |
| 259 | PORT MAP ( |
|
271 | -- PORT MAP ( | |
| 260 |
|
|
272 | -- clk => clk, | |
| 261 | rstn => rstn, |
|
273 | -- rstn => rstn, | |
| 262 |
|
274 | |||
| 263 | Read => demux_ren, |
|
275 | -- Read => demux_ren, | |
| 264 | EmptyF0a => sample_f0_0_empty, |
|
276 | -- EmptyF0a => sample_f0_0_empty, | |
| 265 | EmptyF0b => sample_f0_0_empty, |
|
277 | -- EmptyF0b => sample_f0_0_empty, | |
| 266 | EmptyF1 => sample_f1_empty, |
|
278 | -- EmptyF1 => sample_f1_empty, | |
| 267 | EmptyF2 => sample_f3_empty, |
|
279 | -- EmptyF2 => sample_f3_empty, | |
| 268 | DataF0a => sample_f0_0_rdata, |
|
280 | -- DataF0a => sample_f0_0_rdata, | |
| 269 | DataF0b => sample_f0_1_rdata, |
|
281 | -- DataF0b => sample_f0_1_rdata, | |
| 270 | DataF1 => sample_f1_rdata, |
|
282 | -- DataF1 => sample_f1_rdata, | |
| 271 | DataF2 => sample_f3_rdata, |
|
283 | -- DataF2 => sample_f3_rdata, | |
| 272 | Read_DEMUX => sample_ren, |
|
284 | -- Read_DEMUX => sample_ren, | |
| 273 | Empty => demux_empty, |
|
285 | -- Empty => demux_empty, | |
| 274 | Data => demux_data); |
|
286 | -- Data => demux_data); | |
| 275 |
|
287 | |||
| 276 | FFT_1 : FFT |
|
288 | --FFT_1 : FFT | |
| 277 | GENERIC MAP ( |
|
289 | -- GENERIC MAP ( | |
| 278 | Data_sz => 16, |
|
290 | -- Data_sz => 16, | |
| 279 |
|
|
291 | -- NbData => 256) | |
| 280 | PORT MAP ( |
|
292 | -- PORT MAP ( | |
| 281 | clkm => clk, |
|
293 | -- clkm => clk, | |
| 282 | rstn => rstn, |
|
294 | -- rstn => rstn, | |
| 283 | FifoIN_Empty => demux_empty, |
|
295 | -- FifoIN_Empty => demux_empty, | |
| 284 |
|
|
296 | -- FifoIN_Data => demux_data, | |
| 285 |
FifoOUT_Full => fft_fifo_full, |
|
297 | -- FifoOUT_Full => fft_fifo_full, | |
| 286 |
|
|
298 | -- Read => demux_ren, | |
| 287 |
Write => fft_fifo_wen, |
|
299 | -- Write => fft_fifo_wen, | |
| 288 |
ReUse => fft_fifo_reuse, |
|
300 | -- ReUse => fft_fifo_reuse, | |
| 289 | Data => fft_fifo_data); |
|
301 | -- Data => fft_fifo_data); | |
| 290 |
|
302 | |||
| 291 | lppFIFO_fft : lppFIFOxN |
|
303 | --lppFIFO_fft : lppFIFOxN | |
| 292 | GENERIC MAP ( |
|
304 | -- GENERIC MAP ( | |
| 293 | tech => tech, |
|
305 | -- tech => tech, | |
| 294 | Data_sz => 16, |
|
306 | -- Data_sz => 16, | |
| 295 | FifoCnt => 5, |
|
307 | -- FifoCnt => 5, | |
| 296 | Enable_ReUse => '1') |
|
308 | -- Enable_ReUse => '1') | |
| 297 | PORT MAP ( |
|
309 | -- PORT MAP ( | |
| 298 | rst => rstn, |
|
310 | -- rst => rstn, | |
| 299 |
|
|
311 | -- wclk => clk, | |
| 300 |
|
|
312 | -- rclk => clk, | |
| 301 | ReUse => fft_fifo_reuse, |
|
313 | -- ReUse => fft_fifo_reuse, | |
| 302 | wen => fft_fifo_wen, |
|
314 | -- wen => fft_fifo_wen, | |
| 303 | ren => SP_fifo_ren, |
|
315 | -- ren => SP_fifo_ren, | |
| 304 | wdata => fft_fifo_data, |
|
316 | -- wdata => fft_fifo_data, | |
| 305 | rdata => SP_fifo_data, |
|
317 | -- rdata => SP_fifo_data, | |
| 306 |
|
|
318 | -- full => fft_fifo_full, | |
| 307 | empty => OPEN); |
|
319 | -- empty => OPEN); | |
| 308 |
|
320 | |||
| 309 | MatriceSpectrale_1: MatriceSpectrale |
|
321 | --MatriceSpectrale_1 : MatriceSpectrale | |
| 310 | GENERIC MAP ( |
|
322 | -- GENERIC MAP ( | |
| 311 |
|
|
323 | -- Input_SZ => 16, | |
| 312 | Result_SZ => 32) |
|
324 | -- Result_SZ => 32) | |
| 313 | PORT MAP ( |
|
325 | -- PORT MAP ( | |
| 314 |
clkm |
|
326 | -- clkm => clk, | |
| 315 |
rstn |
|
327 | -- rstn => rstn, | |
| 316 |
|
328 | |||
| 317 |
|
|
329 | -- FifoIN_Full => fft_fifo_full, | |
| 318 | FifoOUT_Full => , -- TODO |
|
330 | -- FifoOUT_Full => , -- TODO | |
| 319 | Data_IN => SP_fifo_data, |
|
331 | -- Data_IN => SP_fifo_data, | |
| 320 | ACQ => , -- TODO |
|
332 | -- ACQ => , -- TODO | |
| 321 | FlagError => , -- TODO |
|
333 | -- FlagError => , -- TODO | |
| 322 | Pong => , -- TODO |
|
334 | -- Pong => , -- TODO | |
| 323 | Write => , -- TODO |
|
335 | -- Write => , -- TODO | |
| 324 | Read => SP_fifo_ren, |
|
336 | -- Read => SP_fifo_ren, | |
| 325 | Data_OUT => ); -- TODO |
|
337 | -- Data_OUT => ); -- TODO | |
| 326 |
|
338 | |||
| 327 |
|
339 | |||
| 328 | ----------------------------------------------------------------------------- |
|
340 | ----------------------------------------------------------------------------- | |
| 329 | -- DMA SPECTRAL MATRIX |
|
341 | -- DMA SPECTRAL MATRIX | |
| @@ -401,8 +413,73 BEGIN | |||||
| 401 | addr_matrix_f2 => addr_matrix_f2); |
|
413 | addr_matrix_f2 => addr_matrix_f2); | |
| 402 |
|
414 | |||
| 403 |
|
415 | |||
| 404 | --TODO : add the irq alert for DMA matrix transfert ending |
|
416 | ----------------------------------------------------------------------------- | |
|
|
417 | -- WAVEFORM | |||
|
|
418 | ----------------------------------------------------------------------------- | |||
|
|
419 | ||||
|
|
420 | ----------------------------------------------------------------------------- | |||
|
|
421 | delay_valid_waveform : PROCESS (clk, rstn) | |||
|
|
422 | BEGIN | |||
|
|
423 | IF rstn = '0' THEN | |||
|
|
424 | data_f0_in_valid <= '0'; | |||
|
|
425 | data_f1_in_valid <= '0'; | |||
|
|
426 | ELSIF clk'EVENT AND clk = '1' THEN | |||
|
|
427 | data_f0_in_valid_r <= NOT sample_f0_wen; | |||
|
|
428 | data_f0_in_valid <= NOT data_f0_in_valid_r; | |||
|
|
429 | data_f1_in_valid <= NOT sample_f1_wen; | |||
|
|
430 | END IF; | |||
|
|
431 | END PROCESS delay_valid_waveform; | |||
|
|
432 | ||||
|
|
433 | data_f2_in_valid <= NOT sample_f2_wen; | |||
|
|
434 | data_f3_in_valid <= NOT sample_f3_wen; | |||
|
|
435 | ||||
|
|
436 | ----------------------------------------------------------------------------- | |||
|
|
437 | lpp_waveform_1 : lpp_waveform | |||
|
|
438 | GENERIC MAP ( | |||
|
|
439 | data_size => 16, | |||
|
|
440 | nb_snapshot_param_size => nb_snapshot_param_size, | |||
|
|
441 | delta_snapshot_size => delta_snapshot_size, | |||
|
|
442 | delta_f2_f0_size => delta_f2_f0_size, | |||
|
|
443 | delta_f2_f1_size => delta_f2_f1_size) | |||
|
|
444 | PORT MAP ( | |||
|
|
445 | clk => clk, | |||
|
|
446 | rstn => rstn, | |||
|
|
447 | ||||
|
|
448 | coarse_time_0 => coarse_time(0), | |||
|
|
449 | delta_snapshot => waveform_delta_snapshot, | |||
|
|
450 | delta_f2_f1 => waveform_delta_f2_f1, | |||
|
|
451 | delta_f2_f0 => waveform_delta_f2_f0, | |||
|
|
452 | ||||
|
|
453 | enable_f0 => waveform_enable_f0, | |||
|
|
454 | enable_f1 => waveform_enable_f1, | |||
|
|
455 | enable_f2 => waveform_enable_f2, | |||
|
|
456 | enable_f3 => waveform_enable_f3, | |||
|
|
457 | ||||
|
|
458 | burst_f0 => waveform_burst_f0, | |||
|
|
459 | burst_f1 => waveform_burst_f1, | |||
|
|
460 | burst_f2 => waveform_burst_f2, | |||
|
|
461 | ||||
|
|
462 | nb_snapshot_param => waveform_nb_snapshot_param, | |||
|
|
463 | ||||
|
|
464 | data_f0_in => sample_f0_wdata, | |||
|
|
465 | data_f1_in => sample_f1_wdata, | |||
|
|
466 | data_f2_in => sample_f2_wdata, | |||
|
|
467 | data_f3_in => sample_f3_wdata, | |||
|
|
468 | ||||
|
|
469 | data_f0_in_valid => data_f0_in_valid, | |||
|
|
470 | data_f1_in_valid => data_f1_in_valid, | |||
|
|
471 | data_f2_in_valid => data_f2_in_valid, | |||
|
|
472 | data_f3_in_valid => data_f3_in_valid); | |||
|
|
473 | ||||
|
|
474 | ----------------------------------------------------------------------------- | |||
|
|
475 | -- | |||
|
|
476 | ----------------------------------------------------------------------------- | |||
|
|
477 | ||||
|
|
478 | --DONE : add the irq alert for DMA matrix transfert ending | |||
|
|
479 | ||||
| 405 | --TODO : add 5 bit register into APB to control the DATA SHIPING |
|
480 | --TODO : add 5 bit register into APB to control the DATA SHIPING | |
|
|
481 | --TODO : data shiping | |||
|
|
482 | ||||
| 406 | --TODO : add Spectral Matrix (FFT + SP) |
|
483 | --TODO : add Spectral Matrix (FFT + SP) | |
| 407 | --TODO : add DMA for WaveForms Picker |
|
484 | --TODO : add DMA for WaveForms Picker | |
| 408 | --TODO : add APB Reg to control WaveForms Picker |
|
485 | --TODO : add APB Reg to control WaveForms Picker | |
| @@ -15,34 +15,47 USE techmap.gencomp.ALL; | |||||
| 15 | PACKAGE lpp_top_lfr_pkg IS |
|
15 | PACKAGE lpp_top_lfr_pkg IS | |
| 16 |
|
16 | |||
| 17 | COMPONENT lpp_top_acq |
|
17 | COMPONENT lpp_top_acq | |
| 18 |
|
|
18 | GENERIC( | |
| 19 | tech : integer); |
|
19 | tech : INTEGER := 0 | |
| 20 | PORT ( |
|
20 | ); | |
| 21 | cnv_run : IN STD_LOGIC; |
|
21 | PORT ( | |
| 22 | cnv : OUT STD_LOGIC; |
|
22 | -- ADS7886 | |
| 23 |
|
|
23 | cnv_run : IN STD_LOGIC; | |
| 24 |
|
|
24 | cnv : OUT STD_LOGIC; | |
| 25 |
|
|
25 | sck : OUT STD_LOGIC; | |
| 26 |
|
|
26 | sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |
| 27 | clk : IN STD_LOGIC; |
|
27 | -- | |
| 28 |
|
|
28 | cnv_clk : IN STD_LOGIC; -- 49 MHz | |
| 29 | sample_f0_0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
29 | cnv_rstn : IN STD_LOGIC; | |
| 30 | sample_f0_1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
30 | -- | |
| 31 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
31 | clk : IN STD_LOGIC; -- 25 MHz | |
| 32 | sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
32 | rstn : IN STD_LOGIC; | |
| 33 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
33 | -- | |
| 34 |
|
|
34 | sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 35 |
|
|
35 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
| 36 | sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
36 | -- | |
| 37 |
|
|
37 | sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
|
38 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |||
|
|
39 | -- | |||
|
|
40 | sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
|
41 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |||
|
|
42 | -- | |||
|
|
43 | sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
|
44 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0) | |||
|
|
45 | ); | |||
| 38 | END COMPONENT; |
|
46 | END COMPONENT; | |
| 39 |
|
47 | |||
| 40 | COMPONENT lpp_top_apbreg |
|
48 | COMPONENT lpp_top_apbreg | |
| 41 | GENERIC ( |
|
49 | GENERIC ( | |
| 42 |
|
|
50 | nb_burst_available_size : INTEGER; | |
| 43 |
pa |
|
51 | nb_snapshot_param_size : INTEGER; | |
| 44 |
|
|
52 | delta_snapshot_size : INTEGER; | |
| 45 |
|
|
53 | delta_f2_f0_size : INTEGER; | |
|
|
54 | delta_f2_f1_size : INTEGER; | |||
|
|
55 | pindex : INTEGER; | |||
|
|
56 | paddr : INTEGER; | |||
|
|
57 | pmask : INTEGER; | |||
|
|
58 | pirq : INTEGER); | |||
| 46 | PORT ( |
|
59 | PORT ( | |
| 47 | HCLK : IN STD_ULOGIC; |
|
60 | HCLK : IN STD_ULOGIC; | |
| 48 | HRESETn : IN STD_ULOGIC; |
|
61 | HRESETn : IN STD_ULOGIC; | |
| @@ -66,7 +79,120 PACKAGE lpp_top_lfr_pkg IS | |||||
| 66 | addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
79 | addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 67 | addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
80 | addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 68 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
81 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 69 |
addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
82 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
|
83 | status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
84 | status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
85 | status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
86 | status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
87 | data_shaping_BW : OUT STD_LOGIC; | |||
|
|
88 | data_shaping_SP0 : OUT STD_LOGIC; | |||
|
|
89 | data_shaping_SP1 : OUT STD_LOGIC; | |||
|
|
90 | data_shaping_R0 : OUT STD_LOGIC; | |||
|
|
91 | data_shaping_R1 : OUT STD_LOGIC; | |||
|
|
92 | delta_snapshot : OUT STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); | |||
|
|
93 | delta_f2_f1 : OUT STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); | |||
|
|
94 | delta_f2_f0 : OUT STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); | |||
|
|
95 | nb_burst_available : OUT STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); | |||
|
|
96 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |||
|
|
97 | enable_f0 : OUT STD_LOGIC; | |||
|
|
98 | enable_f1 : OUT STD_LOGIC; | |||
|
|
99 | enable_f2 : OUT STD_LOGIC; | |||
|
|
100 | enable_f3 : OUT STD_LOGIC; | |||
|
|
101 | burst_f0 : OUT STD_LOGIC; | |||
|
|
102 | burst_f1 : OUT STD_LOGIC; | |||
|
|
103 | burst_f2 : OUT STD_LOGIC; | |||
|
|
104 | addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
105 | addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
106 | addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
107 | addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); | |||
|
|
108 | END COMPONENT; | |||
|
|
109 | ||||
|
|
110 | COMPONENT lpp_top_lfr_wf_picker | |||
|
|
111 | GENERIC ( | |||
|
|
112 | hindex : INTEGER; | |||
|
|
113 | pindex : INTEGER; | |||
|
|
114 | paddr : INTEGER; | |||
|
|
115 | pmask : INTEGER; | |||
|
|
116 | pirq : INTEGER; | |||
|
|
117 | tech : INTEGER; | |||
|
|
118 | nb_burst_available_size : INTEGER; | |||
|
|
119 | nb_snapshot_param_size : INTEGER; | |||
|
|
120 | delta_snapshot_size : INTEGER; | |||
|
|
121 | delta_f2_f0_size : INTEGER; | |||
|
|
122 | delta_f2_f1_size : INTEGER); | |||
|
|
123 | PORT ( | |||
|
|
124 | cnv_run : IN STD_LOGIC; | |||
|
|
125 | cnv : OUT STD_LOGIC; | |||
|
|
126 | sck : OUT STD_LOGIC; | |||
|
|
127 | sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |||
|
|
128 | cnv_clk : IN STD_LOGIC; | |||
|
|
129 | cnv_rstn : IN STD_LOGIC; | |||
|
|
130 | HCLK : IN STD_ULOGIC; | |||
|
|
131 | HRESETn : IN STD_ULOGIC; | |||
|
|
132 | apbi : IN apb_slv_in_type; | |||
|
|
133 | apbo : OUT apb_slv_out_type; | |||
|
|
134 | AHB_Master_In : IN AHB_Mst_In_Type; | |||
|
|
135 | AHB_Master_Out : OUT AHB_Mst_Out_Type; | |||
|
|
136 | coarse_time_0 : IN STD_LOGIC; | |||
|
|
137 | data_shaping_BW : OUT STD_LOGIC); | |||
| 70 | END COMPONENT; |
|
138 | END COMPONENT; | |
| 71 |
|
139 | |||
| 72 | END lpp_top_lfr_pkg; No newline at end of file |
|
140 | ||
|
|
141 | COMPONENT lpp_top_lfr_wf_picker_ip | |||
|
|
142 | GENERIC ( | |||
|
|
143 | hindex : INTEGER; | |||
|
|
144 | nb_burst_available_size : INTEGER; | |||
|
|
145 | nb_snapshot_param_size : INTEGER; | |||
|
|
146 | delta_snapshot_size : INTEGER; | |||
|
|
147 | delta_f2_f0_size : INTEGER; | |||
|
|
148 | delta_f2_f1_size : INTEGER; | |||
|
|
149 | tech : INTEGER); | |||
|
|
150 | PORT ( | |||
|
|
151 | cnv_run : IN STD_LOGIC; | |||
|
|
152 | cnv : OUT STD_LOGIC; | |||
|
|
153 | sck : OUT STD_LOGIC; | |||
|
|
154 | sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |||
|
|
155 | cnv_clk : IN STD_LOGIC; | |||
|
|
156 | cnv_rstn : IN STD_LOGIC; | |||
|
|
157 | clk : IN STD_LOGIC; | |||
|
|
158 | rstn : IN STD_LOGIC; | |||
|
|
159 | sample_f0_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); | |||
|
|
160 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |||
|
|
161 | sample_f1_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); | |||
|
|
162 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |||
|
|
163 | sample_f2_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); | |||
|
|
164 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |||
|
|
165 | sample_f3_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); | |||
|
|
166 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |||
|
|
167 | AHB_Master_In : IN AHB_Mst_In_Type; | |||
|
|
168 | AHB_Master_Out : OUT AHB_Mst_Out_Type; | |||
|
|
169 | coarse_time_0 : IN STD_LOGIC; | |||
|
|
170 | data_shaping_SP0 : IN STD_LOGIC; | |||
|
|
171 | data_shaping_SP1 : IN STD_LOGIC; | |||
|
|
172 | data_shaping_R0 : IN STD_LOGIC; | |||
|
|
173 | data_shaping_R1 : IN STD_LOGIC; | |||
|
|
174 | delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); | |||
|
|
175 | delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); | |||
|
|
176 | delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); | |||
|
|
177 | enable_f0 : IN STD_LOGIC; | |||
|
|
178 | enable_f1 : IN STD_LOGIC; | |||
|
|
179 | enable_f2 : IN STD_LOGIC; | |||
|
|
180 | enable_f3 : IN STD_LOGIC; | |||
|
|
181 | burst_f0 : IN STD_LOGIC; | |||
|
|
182 | burst_f1 : IN STD_LOGIC; | |||
|
|
183 | burst_f2 : IN STD_LOGIC; | |||
|
|
184 | nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); | |||
|
|
185 | nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |||
|
|
186 | status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
187 | status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
188 | status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
189 | status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
190 | addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
191 | addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
192 | addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
193 | addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); | |||
|
|
194 | END COMPONENT; | |||
|
|
195 | ||||
|
|
196 | ||||
|
|
197 | ||||
|
|
198 | END lpp_top_lfr_pkg; | |||
| 1 | NO CONTENT: file was removed |
|
NO CONTENT: file was removed |
| 1 | NO CONTENT: file was removed |
|
NO CONTENT: file was removed |
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