# HG changeset patch # User paul # Date 2013-05-02 11:56:13 # Node ID 5f4e3290e6b68f618a9f2c47f387e3be7a76c663 # Parent e5d8d2760efcffbacc9824fd1caad4bad57f8c26 # Parent 7b269012117520ae6cd9c7483f09e62774b91ad6 Fusion avec JC diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/TB_Data_Acquisition.vhd b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/TB_Data_Acquisition.vhd --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/TB_Data_Acquisition.vhd +++ b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/TB_Data_Acquisition.vhd @@ -1,188 +1,348 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -LIBRARY lpp; -USE lpp.lpp_ad_conv.ALL; - -------------------------------------------------------------------------------- - -ENTITY TB_Data_Acquisition IS - -END TB_Data_Acquisition; - -------------------------------------------------------------------------------- - -ARCHITECTURE tb OF TB_Data_Acquisition IS - - COMPONENT TestModule_ADS7886 - GENERIC ( - freq : INTEGER; - amplitude : INTEGER; - impulsion : INTEGER); - PORT ( - cnv_run : IN STD_LOGIC; - cnv : IN STD_LOGIC; - sck : IN STD_LOGIC; - sdo : OUT STD_LOGIC); - END COMPONENT; - - COMPONENT Top_Data_Acquisition - PORT ( - cnv_run : IN STD_LOGIC; - cnv : OUT STD_LOGIC; - sck : OUT STD_LOGIC; - sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - cnv_clk : IN STD_LOGIC; - cnv_rstn : IN STD_LOGIC; - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; - -- - sample_f0_0_ren : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f0_0_rdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); - sample_f0_0_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f0_0_empty : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - -- - sample_f0_1_ren : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f0_1_rdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); - sample_f0_1_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f0_1_empty : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - -- - sample_f1_ren : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f1_rdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); - sample_f1_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f1_empty : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - -- - sample_f3_ren : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f3_rdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); - sample_f3_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f3_empty : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)); - END COMPONENT; - - -- component ports - SIGNAL cnv_rstn : STD_LOGIC; - SIGNAL cnv : STD_LOGIC; - SIGNAL rstn : STD_LOGIC; - SIGNAL sck : STD_LOGIC; - SIGNAL sdo : STD_LOGIC_VECTOR(7 DOWNTO 0); - SIGNAL run_cnv : STD_LOGIC; - - - -- clock - signal Clk : STD_LOGIC := '1'; - SIGNAL cnv_clk : STD_LOGIC := '1'; - - ----------------------------------------------------------------------------- - SIGNAL sample_f0_0_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f0_0_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); - SIGNAL sample_f0_0_full : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f0_0_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); - ----------------------------------------------------------------------------- - SIGNAL sample_f0_1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f0_1_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); - SIGNAL sample_f0_1_full : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f0_1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); - ----------------------------------------------------------------------------- - SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); - SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); - ----------------------------------------------------------------------------- - SIGNAL sample_f3_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f3_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); - SIGNAL sample_f3_full : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f3_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); - - -BEGIN -- tb - - MODULE_ADS7886: FOR I IN 0 TO 6 GENERATE - TestModule_ADS7886_u: TestModule_ADS7886 - GENERIC MAP ( - freq => 24*(I+1), - amplitude => 30000/(I+1), - impulsion => 0) - PORT MAP ( - cnv_run => run_cnv, - cnv => cnv, - sck => sck, - sdo => sdo(I)); - END GENERATE MODULE_ADS7886; - - TestModule_ADS7886_u: TestModule_ADS7886 - GENERIC MAP ( - freq => 0, - amplitude => 30000, - impulsion => 1) - PORT MAP ( - cnv_run => run_cnv, - cnv => cnv, - sck => sck, - sdo => sdo(7)); - - - -- clock generation - Clk <= not Clk after 20 ns; -- 25 Mhz - cnv_clk <= not cnv_clk after 10173 ps; -- 49.152 MHz - - -- waveform generation - WaveGen_Proc: process - begin - -- insert signal assignments here - wait until Clk = '1'; - rstn <= '0'; - cnv_rstn <= '0'; - run_cnv <= '0'; - wait until Clk = '1'; - wait until Clk = '1'; - wait until Clk = '1'; - rstn <= '1'; - cnv_rstn <= '1'; - wait until Clk = '1'; - wait until Clk = '1'; - wait until Clk = '1'; - wait until Clk = '1'; - wait until Clk = '1'; - wait until Clk = '1'; - run_cnv <= '1'; - wait; - - end process WaveGen_Proc; - - ----------------------------------------------------------------------------- - - Top_Data_Acquisition_1: Top_Data_Acquisition - PORT MAP ( - cnv_run => run_cnv, - cnv => cnv, - sck => sck, - sdo => sdo, - cnv_clk => cnv_clk, - cnv_rstn => cnv_rstn, - clk => clk, - rstn => rstn, - -- - sample_f0_0_ren => sample_f0_0_ren, - sample_f0_0_rdata => sample_f0_0_rdata, - sample_f0_0_full => sample_f0_0_full, - sample_f0_0_empty => sample_f0_0_empty, - -- - sample_f0_1_ren => sample_f0_1_ren, - sample_f0_1_rdata => sample_f0_1_rdata, - sample_f0_1_full => sample_f0_1_full, - sample_f0_1_empty => sample_f0_1_empty, - -- - sample_f1_ren => sample_f1_ren, - sample_f1_rdata => sample_f1_rdata, - sample_f1_full => sample_f1_full, - sample_f1_empty => sample_f1_empty, - -- - sample_f3_ren => sample_f3_ren, - sample_f3_rdata => sample_f3_rdata, - sample_f3_full => sample_f3_full, - sample_f3_empty => sample_f3_empty - ); - sample_f0_0_ren <= (OTHERS => '1'); - sample_f0_1_ren <= (OTHERS => '1'); - sample_f1_ren <= (OTHERS => '1'); - sample_f3_ren <= (OTHERS => '1'); - -END tb; +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +LIBRARY lpp; +USE lpp.lpp_ad_conv.ALL; +USE lpp.lpp_top_lfr_pkg.ALL; +USE lpp.lpp_waveform_pkg.ALL; + +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; +USE GRLIB.DMA2AHB_Package.ALL; + +LIBRARY techmap; +USE techmap.gencomp.ALL; + +------------------------------------------------------------------------------- + +ENTITY TB_Data_Acquisition IS + +END TB_Data_Acquisition; + +------------------------------------------------------------------------------- + +ARCHITECTURE tb OF TB_Data_Acquisition IS + + COMPONENT TestModule_ADS7886 + GENERIC ( + freq : INTEGER; + amplitude : INTEGER; + impulsion : INTEGER); + PORT ( + cnv_run : IN STD_LOGIC; + cnv : IN STD_LOGIC; + sck : IN STD_LOGIC; + sdo : OUT STD_LOGIC); + END COMPONENT; + + --COMPONENT Top_Data_Acquisition + -- GENERIC ( + -- hindex : INTEGER; + -- nb_burst_available_size : INTEGER := 11; + -- nb_snapshot_param_size : INTEGER := 11; + -- delta_snapshot_size : INTEGER := 16; + -- delta_f2_f0_size : INTEGER := 10; + -- delta_f2_f1_size : INTEGER := 10; + -- tech : integer); + -- PORT ( + -- cnv_run : IN STD_LOGIC; + -- cnv : OUT STD_LOGIC; + -- sck : OUT STD_LOGIC; + -- sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + -- cnv_clk : IN STD_LOGIC; + -- cnv_rstn : IN STD_LOGIC; + -- clk : IN STD_LOGIC; + -- rstn : IN STD_LOGIC; + -- sample_f0_wen : out STD_LOGIC_VECTOR(5 DOWNTO 0); + -- sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + -- sample_f1_wen : out STD_LOGIC_VECTOR(5 DOWNTO 0); + -- sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + -- sample_f2_wen : out STD_LOGIC_VECTOR(5 DOWNTO 0); + -- sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + -- sample_f3_wen : out STD_LOGIC_VECTOR(5 DOWNTO 0); + -- sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + -- AHB_Master_In : IN AHB_Mst_In_Type; + -- AHB_Master_Out : OUT AHB_Mst_Out_Type; + -- coarse_time_0 : IN STD_LOGIC; + -- data_shaping_SP0 : IN STD_LOGIC; + -- data_shaping_SP1 : IN STD_LOGIC; + -- data_shaping_R0 : IN STD_LOGIC; + -- data_shaping_R1 : IN STD_LOGIC; + -- delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); + -- delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); + -- delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); + -- enable_f0 : IN STD_LOGIC; + -- enable_f1 : IN STD_LOGIC; + -- enable_f2 : IN STD_LOGIC; + -- enable_f3 : IN STD_LOGIC; + -- burst_f0 : IN STD_LOGIC; + -- burst_f1 : IN STD_LOGIC; + -- burst_f2 : IN STD_LOGIC; + -- nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); + -- nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); + -- status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + -- status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + -- status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + -- status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + -- addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + -- addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + -- addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + -- addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); + --END COMPONENT; + + -- component ports + SIGNAL cnv_rstn : STD_LOGIC; + SIGNAL cnv : STD_LOGIC; + SIGNAL rstn : STD_LOGIC; + SIGNAL sck : STD_LOGIC; + SIGNAL sdo : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL run_cnv : STD_LOGIC; + + + -- clock + signal Clk : STD_LOGIC := '1'; + SIGNAL cnv_clk : STD_LOGIC := '1'; + + ----------------------------------------------------------------------------- + SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); + SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + ----------------------------------------------------------------------------- + SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); + SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + ----------------------------------------------------------------------------- + SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); + SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + ----------------------------------------------------------------------------- + SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); + SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + + ----------------------------------------------------------------------------- + CONSTANT nb_burst_available_size : INTEGER := 11; + CONSTANT nb_snapshot_param_size : INTEGER := 11; + CONSTANT delta_snapshot_size : INTEGER := 16; + CONSTANT delta_f2_f0_size : INTEGER := 10; + CONSTANT delta_f2_f1_size : INTEGER := 10; + + SIGNAL AHB_Master_In : AHB_Mst_In_Type; + SIGNAL AHB_Master_Out : AHB_Mst_Out_Type; + + SIGNAL coarse_time_0 : STD_LOGIC; + SIGNAL coarse_time_0_t : STD_LOGIC := '0'; + SIGNAL coarse_time_0_t2 : STD_LOGIC := '0'; + + SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); + SIGNAL delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); + SIGNAL delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); + + SIGNAL enable_f0 : STD_LOGIC; + SIGNAL enable_f1 : STD_LOGIC; + SIGNAL enable_f2 : STD_LOGIC; + SIGNAL enable_f3 : STD_LOGIC; + + SIGNAL burst_f0 : STD_LOGIC; + SIGNAL burst_f1 : STD_LOGIC; + SIGNAL burst_f2 : STD_LOGIC; + + SIGNAL nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); + SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); + + SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); + + SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); + + + SIGNAL data_shaping_SP0 : STD_LOGIC; + SIGNAL data_shaping_SP1 : STD_LOGIC; + SIGNAL data_shaping_R0 : STD_LOGIC; + SIGNAL data_shaping_R1 : STD_LOGIC; +BEGIN -- tb + + MODULE_ADS7886: FOR I IN 0 TO 6 GENERATE + TestModule_ADS7886_u: TestModule_ADS7886 + GENERIC MAP ( + freq => 24*(I+1), + amplitude => 30000/(I+1), + impulsion => 0) + PORT MAP ( + cnv_run => run_cnv, + cnv => cnv, + sck => sck, + sdo => sdo(I)); + END GENERATE MODULE_ADS7886; + + TestModule_ADS7886_u: TestModule_ADS7886 + GENERIC MAP ( + freq => 0, + amplitude => 30000, + impulsion => 1) + PORT MAP ( + cnv_run => run_cnv, + cnv => cnv, + sck => sck, + sdo => sdo(7)); + + + -- clock generation + Clk <= not Clk after 20 ns; -- 25 Mhz + cnv_clk <= not cnv_clk after 10173 ps; -- 49.152 MHz + + -- waveform generation + WaveGen_Proc: process + begin + -- insert signal assignments here + wait until Clk = '1'; + rstn <= '0'; + cnv_rstn <= '0'; + run_cnv <= '0'; + wait until Clk = '1'; + wait until Clk = '1'; + wait until Clk = '1'; + rstn <= '1'; + cnv_rstn <= '1'; + wait until Clk = '1'; + wait until Clk = '1'; + wait until Clk = '1'; + wait until Clk = '1'; + wait until Clk = '1'; + wait until Clk = '1'; + run_cnv <= '1'; + wait; + + end process WaveGen_Proc; + + ----------------------------------------------------------------------------- + + Top_Data_Acquisition_2: lpp_top_lfr_wf_picker_ip + GENERIC MAP ( + hindex => 2, + nb_burst_available_size => nb_burst_available_size, + nb_snapshot_param_size => nb_snapshot_param_size, + delta_snapshot_size =>16, + delta_f2_f0_size =>10, + delta_f2_f1_size =>10, + tech => 0) + PORT MAP ( + cnv_run => run_cnv, + cnv => cnv, + sck => sck, + sdo => sdo, + cnv_clk => cnv_clk, + cnv_rstn => cnv_rstn, + clk => clk, + rstn => rstn, + sample_f0_wen => sample_f0_wen, + sample_f0_wdata => sample_f0_wdata, + sample_f1_wen => sample_f1_wen, + sample_f1_wdata => sample_f1_wdata, + sample_f2_wen => sample_f2_wen, + sample_f2_wdata => sample_f2_wdata, + sample_f3_wen => sample_f3_wen, + sample_f3_wdata => sample_f3_wdata, + AHB_Master_In => AHB_Master_In, + AHB_Master_Out => AHB_Master_Out, + coarse_time_0 => coarse_time_0, + data_shaping_SP0 => data_shaping_SP0, + data_shaping_SP1 => data_shaping_SP1, + data_shaping_R0 => data_shaping_R0, + data_shaping_R1 => data_shaping_R1, + delta_snapshot => delta_snapshot, + delta_f2_f1 => delta_f2_f1, + delta_f2_f0 => delta_f2_f0, + enable_f0 => enable_f0, + enable_f1 => enable_f1, + enable_f2 => enable_f2, + enable_f3 => enable_f3, + burst_f0 => burst_f0, + burst_f1 => burst_f1, + burst_f2 => burst_f2, + nb_burst_available => nb_burst_available, + nb_snapshot_param => nb_snapshot_param, + status_full => status_full, + status_full_ack => status_full_ack, + status_full_err => status_full_err, + status_new_err => status_new_err, + addr_data_f0 => addr_data_f0, + addr_data_f1 => addr_data_f1, + addr_data_f2 => addr_data_f2, + addr_data_f3 => addr_data_f3); + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + enable_f0 <= '0'; + enable_f1 <= '0'; + enable_f2 <= '0'; + enable_f3 <= '0'; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + enable_f0 <= '1'; --TODO test + enable_f1 <= '1'; + enable_f2 <= '1'; + enable_f3 <= '1'; + END IF; + END PROCESS; + + burst_f0 <= '0'; --TODO test + burst_f1 <= '0'; --TODO test + burst_f2 <= '0'; + + data_shaping_SP0 <= '0'; + data_shaping_SP1 <= '0'; + data_shaping_R0 <= '1'; + data_shaping_R1 <= '1'; + + delta_snapshot <= "0000000000000001"; + --nb_snapshot_param <= "00000001110"; -- 14+1 = 15 + --delta_f2_f0 <= "1010011001";--665 = 14/2*96 -14/2 + --delta_f2_f1 <= "0000100110";-- 38 = 14/2*6 - 14/4 + + -- A redefinir car ca ne tombe pas correctement ... ??? + nb_burst_available <= "00000110010"; -- 3*16 + 2 = 34 + nb_snapshot_param <= "00000001111"; -- x+1 = 16 + delta_f2_f0 <= "1011001000";--712 = x/2*96 -x/2 + delta_f2_f1 <= "0000101001";-- 41 = x/2*6 - x/4 + + addr_data_f0 <= "00000000000000000000000000000000"; + addr_data_f1 <= "00010000000000000000000000000000"; + addr_data_f2 <= "00100000000000000000000000000000"; + addr_data_f3 <= "00110000000000000000000000000000"; + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + status_full_ack <= (OTHERS => '0'); + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + status_full_ack <= status_full; + END IF; + END PROCESS; + + + coarse_time_0_t <= not coarse_time_0_t after 50 ms; + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + coarse_time_0_t2 <= '0'; + coarse_time_0 <= '0'; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + coarse_time_0_t2 <= coarse_time_0_t; + coarse_time_0 <= coarse_time_0_t AND (NOT coarse_time_0_t2); + END IF; + END PROCESS; + + + AHB_Master_In.HGRANT(2) <= '1'; + AHB_Master_In.HREADY <= '1'; + + + AHB_Master_In.HRESP <= HRESP_OKAY; + + +END tb; diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/Top_Data_Acquisition.vhd b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/Top_Data_Acquisition.vhd --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/Top_Data_Acquisition.vhd +++ b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/Top_Data_Acquisition.vhd @@ -1,50 +1,94 @@ LIBRARY ieee; USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + LIBRARY lpp; USE lpp.lpp_ad_conv.ALL; USE lpp.iir_filter.ALL; USE lpp.FILTERcfg.ALL; USE lpp.lpp_memory.ALL; +USE lpp.lpp_waveform_pkg.ALL; + LIBRARY techmap; USE techmap.gencomp.ALL; ---USE lpp.ALL; + +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; +USE GRLIB.DMA2AHB_Package.ALL; ENTITY Top_Data_Acquisition IS - generic( - tech : integer := 0 + GENERIC( + hindex : INTEGER := 2; + nb_burst_available_size : INTEGER := 11; + nb_snapshot_param_size : INTEGER := 11; + delta_snapshot_size : INTEGER := 16; + delta_f2_f0_size : INTEGER := 10; + delta_f2_f1_size : INTEGER := 10; + tech : INTEGER := 0 ); PORT ( -- ADS7886 - cnv_run : IN STD_LOGIC; - cnv : OUT STD_LOGIC; - sck : OUT STD_LOGIC; - sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + cnv_run : IN STD_LOGIC; + cnv : OUT STD_LOGIC; + sck : OUT STD_LOGIC; + sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + -- + cnv_clk : IN STD_LOGIC; + cnv_rstn : IN STD_LOGIC; -- - cnv_clk : IN STD_LOGIC; - cnv_rstn : IN STD_LOGIC; + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + -- + sample_f0_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); + sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); -- - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; + sample_f1_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); + sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + -- + sample_f2_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); + sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); -- - sample_f0_0_ren : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f0_0_rdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); - sample_f0_0_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f0_0_empty : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - -- - sample_f0_1_ren : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f0_1_rdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); - sample_f0_1_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f0_1_empty : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - -- - sample_f1_ren : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f1_rdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); - sample_f1_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f1_empty : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - -- - sample_f3_ren : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f3_rdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); - sample_f3_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f3_empty : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) + sample_f3_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); + sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + + -- AMBA AHB Master Interface + AHB_Master_In : IN AHB_Mst_In_Type; + AHB_Master_Out : OUT AHB_Mst_Out_Type; + + coarse_time_0 : IN STD_LOGIC; + + --config + data_shaping_SP0 : IN STD_LOGIC; + data_shaping_SP1 : IN STD_LOGIC; + data_shaping_R0 : IN STD_LOGIC; + data_shaping_R1 : IN STD_LOGIC; + + delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); + delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); + delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); + + enable_f0 : IN STD_LOGIC; + enable_f1 : IN STD_LOGIC; + enable_f2 : IN STD_LOGIC; + enable_f3 : IN STD_LOGIC; + + burst_f0 : IN STD_LOGIC; + burst_f1 : IN STD_LOGIC; + burst_f2 : IN STD_LOGIC; + + nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); + nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); + status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma + + addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) ); END Top_Data_Acquisition; @@ -79,49 +123,55 @@ ARCHITECTURE tb OF Top_Data_Acquisition CONSTANT CoefPerCel : INTEGER := 5; CONSTANT Cels_count : INTEGER := 5; - SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0); - SIGNAL coefs_JC : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0); - SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); - SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); - -- - SIGNAL sample_filter_JC_out_val : STD_LOGIC; - SIGNAL sample_filter_JC_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); - -- - SIGNAL sample_filter_JC_out_r_val : STD_LOGIC; - SIGNAL sample_filter_JC_out_r : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); - ----------------------------------------------------------------------------- - SIGNAL downsampling_cnt : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL sample_downsampling_out_val : STD_LOGIC; - SIGNAL sample_downsampling_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); + SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0); + SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0); + SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); + SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); -- - SIGNAL sample_f0_val : STD_LOGIC; - SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); - SIGNAL sample_f0_0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f0_1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); - -- - SIGNAL sample_f0_0_val : STD_LOGIC; - SIGNAL sample_f0_1_val : STD_LOGIC; - SIGNAL counter_f0 : INTEGER; + SIGNAL sample_filter_v2_out_val : STD_LOGIC; + SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); + ----------------------------------------------------------------------------- + SIGNAL sample_data_shaping_out_val : STD_LOGIC; + SIGNAL sample_data_shaping_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); + SIGNAL sample_data_shaping_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0); + SIGNAL sample_data_shaping_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0); + SIGNAL sample_data_shaping_f2_s : STD_LOGIC_VECTOR(17 DOWNTO 0); + SIGNAL sample_data_shaping_f1_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0); + SIGNAL sample_data_shaping_f2_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0); + ----------------------------------------------------------------------------- + SIGNAL sample_filter_v2_out_val_s : STD_LOGIC; + SIGNAL sample_filter_v2_out_s : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0); ----------------------------------------------------------------------------- - SIGNAL sample_f1_val : STD_LOGIC; - SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); - SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); + SIGNAL sample_f0_val : STD_LOGIC; + SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0); + SIGNAL sample_f0_s : samplT(5 DOWNTO 0, 15 DOWNTO 0); + -- + SIGNAL sample_f1_val : STD_LOGIC; + SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0); + SIGNAL sample_f1_s : samplT(5 DOWNTO 0, 15 DOWNTO 0); + -- + SIGNAL sample_f2_val : STD_LOGIC; + SIGNAL sample_f2 : samplT(5 DOWNTO 0, 15 DOWNTO 0); -- - SIGNAL sample_f2_val : STD_LOGIC; - SIGNAL sample_f2 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); - -- - SIGNAL sample_f3_val : STD_LOGIC; - SIGNAL sample_f3 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); - SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); + SIGNAL sample_f3_val : STD_LOGIC; + SIGNAL sample_f3 : samplT(5 DOWNTO 0, 15 DOWNTO 0); + + ----------------------------------------------------------------------------- + SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); + SIGNAL data_f1_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); + SIGNAL data_f2_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); + SIGNAL data_f3_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); + ----------------------------------------------------------------------------- + SIGNAL sample_f0_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + SIGNAL sample_f1_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + SIGNAL sample_f2_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + SIGNAL sample_f3_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); BEGIN -- component instantiation ----------------------------------------------------------------------------- - DIGITAL_acquisition : ADS7886_drvr + DIGITAL_acquisition : AD7688_drvr GENERIC MAP ( ChanelCount => ChanelCount, ncycle_cnv_high => ncycle_cnv_high, @@ -159,166 +209,126 @@ BEGIN sample_filter_in(i, 17) <= sample(i)(15); END GENERATE; - --coefs <= CoefsInitValCst; - coefs_JC <= CoefsInitValCst_v2; - - --FILTER : IIR_CEL_CTRLR - -- GENERIC MAP ( - -- tech => 0, - -- Sample_SZ => 18, - -- ChanelsCount => ChanelCount, - -- Coef_SZ => Coef_SZ, - -- CoefCntPerCel => CoefCntPerCel, - -- Cels_count => Cels_count, - -- Mem_use => use_CEL) -- use_CEL for SIMU, use_RAM for synthesis - -- PORT MAP ( - -- reset => rstn, - -- clk => clk, - -- sample_clk => sample_val_delay, - -- sample_in => sample_filter_in, - -- sample_out => sample_filter_out, - -- virg_pos => 7, - -- GOtest => OPEN, - -- coefs => coefs); + coefs_v2 <= CoefsInitValCst_v2; IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 GENERIC MAP ( tech => 0, - Mem_use => use_RAM, + Mem_use => use_CEL, -- use_RAM Sample_SZ => 18, Coef_SZ => Coef_SZ, - Coef_Nb => 25, -- TODO - Coef_sel_SZ => 5, -- TODO + Coef_Nb => 25, + Coef_sel_SZ => 5, Cels_count => Cels_count, ChanelsCount => ChanelCount) PORT MAP ( rstn => rstn, clk => clk, virg_pos => 7, - coefs => coefs_JC, + coefs => coefs_v2, sample_in_val => sample_val_delay, sample_in => sample_filter_in, - sample_out_val => sample_filter_JC_out_val, - sample_out => sample_filter_JC_out); + sample_out_val => sample_filter_v2_out_val, + sample_out => sample_filter_v2_out); ----------------------------------------------------------------------------- + -- DATA_SHAPING + ----------------------------------------------------------------------------- + all_data_shaping_in_loop: FOR I IN 17 DOWNTO 0 GENERATE + sample_data_shaping_f0_s(I) <= sample_filter_v2_out(0,I); + sample_data_shaping_f1_s(I) <= sample_filter_v2_out(1,I); + sample_data_shaping_f2_s(I) <= sample_filter_v2_out(2,I); + END GENERATE all_data_shaping_in_loop; + + sample_data_shaping_f1_f0_s <= sample_data_shaping_f1_s - sample_data_shaping_f0_s; + sample_data_shaping_f2_f1_s <= sample_data_shaping_f2_s - sample_data_shaping_f1_s; + PROCESS (clk, rstn) BEGIN -- PROCESS IF rstn = '0' THEN -- asynchronous reset (active low) - sample_filter_JC_out_r_val <= '0'; - rst_all_chanel : FOR I IN ChanelCount-1 DOWNTO 0 LOOP - rst_all_bits : FOR J IN 17 DOWNTO 0 LOOP - sample_filter_JC_out_r(I, J) <= '0'; - END LOOP rst_all_bits; - END LOOP rst_all_chanel; - ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge - sample_filter_JC_out_r_val <= sample_filter_JC_out_val; - IF sample_filter_JC_out_val = '1' THEN - sample_filter_JC_out_r <= sample_filter_JC_out; - END IF; + sample_data_shaping_out_val <= '0'; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + sample_data_shaping_out_val <= sample_filter_v2_out_val; END IF; END PROCESS; - + + SampleLoop_data_shaping: FOR j IN 0 TO 17 GENERATE + PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + sample_data_shaping_out(0,j) <= '0'; + sample_data_shaping_out(1,j) <= '0'; + sample_data_shaping_out(2,j) <= '0'; + sample_data_shaping_out(3,j) <= '0'; + sample_data_shaping_out(4,j) <= '0'; + sample_data_shaping_out(5,j) <= '0'; + sample_data_shaping_out(6,j) <= '0'; + sample_data_shaping_out(7,j) <= '0'; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + sample_data_shaping_out(0,j) <= sample_filter_v2_out(0,j); + IF data_shaping_SP0 = '1' THEN + sample_data_shaping_out(1,j) <= sample_data_shaping_f1_f0_s(j); + ELSE + sample_data_shaping_out(1,j) <= sample_filter_v2_out(1,j); + END IF; + IF data_shaping_SP1 = '1' THEN + sample_data_shaping_out(2,j) <= sample_data_shaping_f2_f1_s(j); + ELSE + sample_data_shaping_out(2,j) <= sample_filter_v2_out(2,j); + END IF; + sample_data_shaping_out(4,j) <= sample_filter_v2_out(4,j); + sample_data_shaping_out(5,j) <= sample_filter_v2_out(5,j); + sample_data_shaping_out(6,j) <= sample_filter_v2_out(6,j); + sample_data_shaping_out(7,j) <= sample_filter_v2_out(7,j); + END IF; + END PROCESS; + END GENERATE; + + sample_filter_v2_out_val_s <= sample_data_shaping_out_val; + ChanelLoopOut : FOR i IN 0 TO 7 GENERATE + SampleLoopOut : FOR j IN 0 TO 15 GENERATE + sample_filter_v2_out_s(i,j) <= sample_data_shaping_out(i,j); + END GENERATE; + END GENERATE; ----------------------------------------------------------------------------- -- F0 -- @24.576 kHz ----------------------------------------------------------------------------- Downsampling_f0 : Downsampling GENERIC MAP ( - ChanelCount => ChanelCount, - SampleSize => 18, + ChanelCount => 8, + SampleSize => 16, DivideParam => 4) PORT MAP ( clk => clk, rstn => rstn, - sample_in_val => sample_filter_JC_out_val , - sample_in => sample_filter_JC_out, + sample_in_val => sample_filter_v2_out_val_s, + sample_in => sample_filter_v2_out_s, sample_out_val => sample_f0_val, sample_out => sample_f0); - all_bit_sample_f0: FOR I IN 17 DOWNTO 0 GENERATE - sample_f0_wdata( I) <= sample_f0(0,I); - sample_f0_wdata(18*1+I) <= sample_f0(1,I); - sample_f0_wdata(18*2+I) <= sample_f0(2,I); - sample_f0_wdata(18*3+I) <= sample_f0(6,I); - sample_f0_wdata(18*4+I) <= sample_f0(7,I); + all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE + sample_f0_wdata_s(I) <= sample_f0(0, I); -- V + sample_f0_wdata_s(16*1+I) <= sample_f0(1, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(3, I); -- E1 + sample_f0_wdata_s(16*2+I) <= sample_f0(2, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(4, I); -- E2 + sample_f0_wdata_s(16*3+I) <= sample_f0(5, I); -- B1 + sample_f0_wdata_s(16*4+I) <= sample_f0(6, I); -- B2 + sample_f0_wdata_s(16*5+I) <= sample_f0(7, I); -- B3 END GENERATE all_bit_sample_f0; - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - counter_f0 <= 0; - ELSIF clk'event AND clk = '1' THEN -- rising clock edge - IF sample_f0_val = '1' THEN - IF counter_f0 = 511 THEN - counter_f0 <= 0; - ELSE - counter_f0 <= counter_f0 + 1; - END IF; - END IF; - END IF; - END PROCESS; - - sample_f0_0_val <= sample_f0_val WHEN counter_f0 < 256 ELSE '0'; - sample_f0_0_wen <= NOT(sample_f0_0_val) & - NOT(sample_f0_0_val) & - NOT(sample_f0_0_val) & - NOT(sample_f0_0_val) & - NOT(sample_f0_0_val); - - lppFIFO_f0_0: lppFIFOxN - GENERIC MAP ( - tech => tech, - Data_sz => 18, - FifoCnt => 5, - Enable_ReUse => '0') - PORT MAP ( - rst => rstn, - wclk => clk, - rclk => clk, - ReUse => (OTHERS => '0'), - - wen => sample_f0_0_wen, - ren => sample_f0_0_ren, - wdata => sample_f0_wdata, - rdata => sample_f0_0_rdata, - full => sample_f0_0_full, - empty => sample_f0_0_empty); - - sample_f0_1_val <= sample_f0_val WHEN counter_f0 > 255 ELSE '0'; - sample_f0_1_wen <= NOT(sample_f0_1_val) & - NOT(sample_f0_1_val) & - NOT(sample_f0_1_val) & - NOT(sample_f0_1_val) & - NOT(sample_f0_1_val); - - lppFIFO_f0_1: lppFIFOxN - GENERIC MAP ( - tech => tech, - Data_sz => 18, - FifoCnt => 5, - Enable_ReUse => '0') - PORT MAP ( - rst => rstn, - wclk => clk, - rclk => clk, - ReUse => (OTHERS => '0'), - - wen => sample_f0_1_wen, - ren => sample_f0_1_ren, - wdata => sample_f0_wdata, - rdata => sample_f0_1_rdata, - full => sample_f0_1_full, - empty => sample_f0_1_empty); + sample_f0_wen <= NOT(sample_f0_val) & + NOT(sample_f0_val) & + NOT(sample_f0_val) & + NOT(sample_f0_val) & + NOT(sample_f0_val) & + NOT(sample_f0_val); - - ----------------------------------------------------------------------------- -- F1 -- @4096 Hz ----------------------------------------------------------------------------- Downsampling_f1 : Downsampling GENERIC MAP ( - ChanelCount => ChanelCount, - SampleSize => 18, + ChanelCount => 8, + SampleSize => 16, DivideParam => 6) PORT MAP ( clk => clk, @@ -327,105 +337,162 @@ BEGIN sample_in => sample_f0, sample_out_val => sample_f1_val, sample_out => sample_f1); - - sample_f1_wen <= NOT(sample_f1_val) & - NOT(sample_f1_val) & - NOT(sample_f1_val) & - NOT(sample_f1_val) & - NOT(sample_f1_val); - - all_bit_sample_f1: FOR I IN 17 DOWNTO 0 GENERATE - sample_f1_wdata( I) <= sample_f1(0,I); - sample_f1_wdata(18*1+I) <= sample_f1(1,I); - sample_f1_wdata(18*2+I) <= sample_f1(2,I); - sample_f1_wdata(18*3+I) <= sample_f1(6,I); - sample_f1_wdata(18*4+I) <= sample_f1(7,I); + + all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE + sample_f1_wdata_s(I) <= sample_f1(0, I); -- V + sample_f1_wdata_s(16*1+I) <= sample_f1(1, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(3, I); -- E1 + sample_f1_wdata_s(16*2+I) <= sample_f1(2, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(4, I); -- E2 + sample_f1_wdata_s(16*3+I) <= sample_f1(5, I); -- B1 + sample_f1_wdata_s(16*4+I) <= sample_f1(6, I); -- B2 + sample_f1_wdata_s(16*5+I) <= sample_f1(7, I); -- B3 END GENERATE all_bit_sample_f1; - - lppFIFO_f1: lppFIFOxN - GENERIC MAP ( - tech => tech, - Data_sz => 18, - FifoCnt => 5, - Enable_ReUse => '0') - PORT MAP ( - rst => rstn, - wclk => clk, - rclk => clk, - ReUse => (OTHERS => '0'), - - wen => sample_f1_wen, - ren => sample_f1_ren, - wdata => sample_f1_wdata, - rdata => sample_f1_rdata, - full => sample_f1_full, - empty => sample_f1_empty); + + sample_f1_wen <= NOT(sample_f1_val) & + NOT(sample_f1_val) & + NOT(sample_f1_val) & + NOT(sample_f1_val) & + NOT(sample_f1_val) & + NOT(sample_f1_val); ----------------------------------------------------------------------------- - -- F2 -- @16 Hz + -- F2 -- @256 Hz ----------------------------------------------------------------------------- + all_bit_sample_f0_s : FOR I IN 15 DOWNTO 0 GENERATE + sample_f0_s(0, I) <= sample_f0(0, I); -- V + sample_f0_s(1, I) <= sample_f0(1, I); -- E1 + sample_f0_s(2, I) <= sample_f0(2, I); -- E2 + sample_f0_s(3, I) <= sample_f0(5, I); -- B1 + sample_f0_s(4, I) <= sample_f0(6, I); -- B2 + sample_f0_s(5, I) <= sample_f0(7, I); -- B3 + END GENERATE all_bit_sample_f0_s; + Downsampling_f2 : Downsampling GENERIC MAP ( - ChanelCount => ChanelCount, - SampleSize => 18, + ChanelCount => 6, + SampleSize => 16, + DivideParam => 96) + PORT MAP ( + clk => clk, + rstn => rstn, + sample_in_val => sample_f0_val , + sample_in => sample_f0_s, + sample_out_val => sample_f2_val, + sample_out => sample_f2); + + sample_f2_wen <= NOT(sample_f2_val) & + NOT(sample_f2_val) & + NOT(sample_f2_val) & + NOT(sample_f2_val) & + NOT(sample_f2_val) & + NOT(sample_f2_val); + + all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE + sample_f2_wdata_s(I) <= sample_f2(0, I); + sample_f2_wdata_s(16*1+I) <= sample_f2(1, I); + sample_f2_wdata_s(16*2+I) <= sample_f2(2, I); + sample_f2_wdata_s(16*3+I) <= sample_f2(3, I); + sample_f2_wdata_s(16*4+I) <= sample_f2(4, I); + sample_f2_wdata_s(16*5+I) <= sample_f2(5, I); + END GENERATE all_bit_sample_f2; + + ----------------------------------------------------------------------------- + -- F3 -- @16 Hz + ----------------------------------------------------------------------------- + all_bit_sample_f1_s : FOR I IN 15 DOWNTO 0 GENERATE + sample_f1_s(0, I) <= sample_f1(0, I); -- V + sample_f1_s(1, I) <= sample_f1(1, I); -- E1 + sample_f1_s(2, I) <= sample_f1(2, I); -- E2 + sample_f1_s(3, I) <= sample_f1(5, I); -- B1 + sample_f1_s(4, I) <= sample_f1(6, I); -- B2 + sample_f1_s(5, I) <= sample_f1(7, I); -- B3 + END GENERATE all_bit_sample_f1_s; + + Downsampling_f3 : Downsampling + GENERIC MAP ( + ChanelCount => 6, + SampleSize => 16, DivideParam => 256) PORT MAP ( clk => clk, rstn => rstn, sample_in_val => sample_f1_val , - sample_in => sample_f1, - sample_out_val => sample_f2_val, - sample_out => sample_f2); - - ----------------------------------------------------------------------------- - -- F3 -- @256 Hz - ----------------------------------------------------------------------------- - Downsampling_f3 : Downsampling - GENERIC MAP ( - ChanelCount => ChanelCount, - SampleSize => 18, - DivideParam => 96) - PORT MAP ( - clk => clk, - rstn => rstn, - sample_in_val => sample_f0_val , - sample_in => sample_f0, + sample_in => sample_f1_s, sample_out_val => sample_f3_val, sample_out => sample_f3); - sample_f3_wen <= (NOT sample_f3_val) & - (NOT sample_f3_val) & - (NOT sample_f3_val) & - (NOT sample_f3_val) & - (NOT sample_f3_val); + sample_f3_wen <= (NOT sample_f3_val) & + (NOT sample_f3_val) & + (NOT sample_f3_val) & + (NOT sample_f3_val) & + (NOT sample_f3_val) & + (NOT sample_f3_val); - all_bit_sample_f3: FOR I IN 17 DOWNTO 0 GENERATE - sample_f3_wdata( I) <= sample_f3(0,I); - sample_f3_wdata(18*1+I) <= sample_f3(1,I); - sample_f3_wdata(18*2+I) <= sample_f3(2,I); - sample_f3_wdata(18*3+I) <= sample_f3(6,I); - sample_f3_wdata(18*4+I) <= sample_f3(7,I); + all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE + sample_f3_wdata_s(I) <= sample_f3(0, I); + sample_f3_wdata_s(16*1+I) <= sample_f3(1, I); + sample_f3_wdata_s(16*2+I) <= sample_f3(2, I); + sample_f3_wdata_s(16*3+I) <= sample_f3(3, I); + sample_f3_wdata_s(16*4+I) <= sample_f3(4, I); + sample_f3_wdata_s(16*5+I) <= sample_f3(5, I); END GENERATE all_bit_sample_f3; - - lppFIFO_f3: lppFIFOxN + + lpp_waveform_1 : lpp_waveform GENERIC MAP ( - tech => tech, - Data_sz => 18, - FifoCnt => 5, - Enable_ReUse => '0') + hindex => hindex, + tech => tech, + data_size => 160, + nb_burst_available_size => nb_burst_available_size, + nb_snapshot_param_size => nb_snapshot_param_size, + delta_snapshot_size => delta_snapshot_size, + delta_f2_f0_size => delta_f2_f0_size, + delta_f2_f1_size => delta_f2_f1_size) PORT MAP ( - rst => rstn, - wclk => clk, - rclk => clk, - ReUse => (OTHERS => '0'), - - wen => sample_f3_wen, - ren => sample_f3_ren, - wdata => sample_f3_wdata, - rdata => sample_f3_rdata, - full => sample_f3_full, - empty => sample_f3_empty); + clk => clk, + rstn => rstn, + + AHB_Master_In => AHB_Master_In, + AHB_Master_Out => AHB_Master_Out, + + coarse_time_0 => coarse_time_0, -- IN + delta_snapshot => delta_snapshot, -- IN + delta_f2_f1 => delta_f2_f1, -- IN + delta_f2_f0 => delta_f2_f0, -- IN + enable_f0 => enable_f0, -- IN + enable_f1 => enable_f1, -- IN + enable_f2 => enable_f2, -- IN + enable_f3 => enable_f3, -- IN + burst_f0 => burst_f0, -- IN + burst_f1 => burst_f1, -- IN + burst_f2 => burst_f2, -- IN + nb_burst_available => nb_burst_available, + nb_snapshot_param => nb_snapshot_param, + status_full => status_full, + status_full_ack => status_full_ack, -- IN + status_full_err => status_full_err, + status_new_err => status_new_err, - + addr_data_f0 => addr_data_f0, -- IN + addr_data_f1 => addr_data_f1, -- IN + addr_data_f2 => addr_data_f2, -- IN + addr_data_f3 => addr_data_f3, -- IN + + data_f0_in => data_f0_in_valid, + data_f1_in => data_f1_in_valid, + data_f2_in => data_f2_in_valid, + data_f3_in => data_f3_in_valid, + data_f0_in_valid => sample_f0_val, + data_f1_in_valid => sample_f1_val, + data_f2_in_valid => sample_f2_val, + data_f3_in_valid => sample_f3_val); + + data_f0_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f0_wdata_s; + data_f1_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f1_wdata_s; + data_f2_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f2_wdata_s; + data_f3_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f3_wdata_s; + + sample_f0_wdata <= sample_f0_wdata_s; + sample_f1_wdata <= sample_f1_wdata_s; + sample_f2_wdata <= sample_f2_wdata_s; + sample_f3_wdata <= sample_f3_wdata_s; END tb; diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/run_sim_data_acquisition.do b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/run_sim_data_acquisition.do --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/run_sim_data_acquisition.do +++ b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/run_sim_data_acquisition.do @@ -1,49 +1,72 @@ - -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/general_purpose.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/SYNC_FF.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MUXN.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MUX2.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/REG.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_CONTROLER.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_REG.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_MUX.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_MUX2.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/Shifter.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MULTIPLIER.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ADDER.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ALU.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ADDRcntr.vhd - -vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/iir_filter.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/FILTERcfg.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CEL.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR2.vhd -#vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR.vhd - -vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd - -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lpp_memory.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lpp_FIFO.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lppFIFOxN.vhd - -vcom -quiet -93 -work lpp ../../lib/lpp/dsp/lpp_downsampling/Downsampling.vhd - -vcom -quiet -93 -work lpp e:/opt/tortoiseHG_vhdlib/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd -vcom -quiet -93 -work lpp e:/opt/tortoiseHG_vhdlib/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd - -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/lpp_ad_conv.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/ADS7886_drvr.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/TestModule_ADS7886.vhd - -vcom -quiet -93 -work work Top_Data_Acquisition.vhd -vcom -quiet -93 -work work TB_Data_Acquisition.vhd - -#vsim work.TB_Data_Acquisition - -#log -r * -#do wave_data_acquisition.do + +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/general_purpose.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/SYNC_FF.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MUXN.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MUX2.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/REG.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_CONTROLER.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_REG.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_MUX.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_MUX2.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/Shifter.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MULTIPLIER.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ADDER.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ALU.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ADDRcntr.vhd + +vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/iir_filter.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/FILTERcfg.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CEL.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CEL_N.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR2.vhd +#vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR.vhd + +vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd + +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lpp_memory.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lpp_FIFO.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lppFIFOxN.vhd + +vcom -quiet -93 -work lpp ../../lib/lpp/dsp/lpp_downsampling/Downsampling.vhd + +vcom -quiet -93 -work lpp e:/opt/tortoiseHG_vhdlib/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd +vcom -quiet -93 -work lpp e:/opt/tortoiseHG_vhdlib/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd + +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/lpp_ad_conv.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/AD7688_drvr.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/TestModule_ADS7886.vhd + + +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_acq.vhd +#vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_lfr.vhd + +vcom -quiet -93 -work lpp ../../lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lfr_time_management/apb_lfr_time_management.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lfr_time_management/lfr_time_management.vhd + +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/lpp_dma_pkg.vhd + +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_snapshot_controler.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_snapshot.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_burst.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_dma.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_dma_send_Nword.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_dma_selectaddress.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_dma_genvalid.vhd + +vcom -quiet -93 -work work Top_Data_Acquisition.vhd + +vcom -quiet -93 -work work TB_Data_Acquisition.vhd + +#vsim work.TB_Data_Acquisition + +#log -r * +#do wave_data_acquisition.do #run 5 ms \ No newline at end of file diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/run_sim_waveform_picker.do b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/run_sim_waveform_picker.do new file mode 100644 --- /dev/null +++ b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/run_sim_waveform_picker.do @@ -0,0 +1,83 @@ + +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/general_purpose.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/SYNC_FF.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MUXN.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MUX2.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/REG.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_CONTROLER.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_REG.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_MUX.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_MUX2.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/Shifter.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MULTIPLIER.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ADDER.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ALU.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ADDRcntr.vhd + +vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/iir_filter.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/FILTERcfg.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CEL.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CEL_N.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR2.vhd +#vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR.vhd + +vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd + +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lpp_memory.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lpp_FIFO.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lppFIFOxN.vhd + +vcom -quiet -93 -work lpp ../../lib/lpp/dsp/lpp_downsampling/Downsampling.vhd + +vcom -quiet -93 -work lpp e:/opt/tortoiseHG_vhdlib/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd +vcom -quiet -93 -work lpp e:/opt/tortoiseHG_vhdlib/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd + +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/lpp_ad_conv.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/AD7688_drvr.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/TestModule_ADS7886.vhd + + +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_apbreg.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_lfr_wf_picker_ip.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_lfr_wf_picker.vhd +#vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_acq.vhd +#vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_lfr.vhd + +vcom -quiet -93 -work lpp ../../lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lfr_time_management/apb_lfr_time_management.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lfr_time_management/lfr_time_management.vhd + +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/lpp_dma_pkg.vhd + +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_snapshot_controler.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_snapshot.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_burst.vhd + +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_fifo_ctrl.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_fifo.vhd + +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_dma.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/lpp_dma_pkg.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/lpp_dma_send_1word.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/lpp_dma_send_16word.vhd +#vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_dma_send_Nword.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_dma_selectaddress.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_dma_genvalid.vhd + +vcom -quiet -93 -work work Top_Data_Acquisition.vhd + +vcom -quiet -93 -work work TB_Data_Acquisition.vhd + +vsim work.TB_Data_Acquisition + +log -r * +do wave_waveform_picker.do +run 5 ms diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/wave_data_acquisition.do b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/wave_data_acquisition.do --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/wave_data_acquisition.do +++ b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/wave_data_acquisition.do @@ -1,231 +1,38 @@ onerror {resume} quietly WaveActivateNextPane {} 0 -add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/chanelcount -add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/ncycle_cnv_high -add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/ncycle_cnv -add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/cnv_clk -add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/cnv_rstn -add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/cnv_run -add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/cnv -add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/clk -add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/rstn -add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/sck -add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/sdo -add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/sample -add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/sample_val -add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/cnv_cycle_counter -add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/cnv_s -add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/cnv_sync -add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/cnv_sync_r -add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/cnv_done -add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/sample_bit_counter -add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/shift_reg -add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/cnv_run_sync -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/tech -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/sample_sz -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/chanelscount -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/coef_sz -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/coefcntpercel -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/cels_count -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/mem_use -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/reset -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/clk -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/sample_clk -add wave -noupdate -group FILTER -radix decimal -subitemconfig {/tb_data_acquisition/top_data_acquisition_1/filter/sample_in(7) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in(6) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in(5) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in(4) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in(3) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in(2) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in(1) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in(0) {-height 15 -radix decimal}} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in -add wave -noupdate -group FILTER -subitemconfig {/tb_data_acquisition/top_data_acquisition_1/filter/sample_out(7) {-height 15 -radix unsigned} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out(6) {-height 15 -radix unsigned} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out(5) {-height 15 -radix unsigned} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out(4) {-height 15 -radix unsigned} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out(3) {-height 15 -radix unsigned} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out(2) {-height 15 -radix unsigned} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out(1) {-height 15 -radix unsigned} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out(0) {-height 15 -radix unsigned}} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/virg_pos -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/gotest -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/coefs -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/smpl_clk_old -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/wd_sel -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/read -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/svg_addr -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/count -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/write -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/waddr_sel -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/go_0 -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/ram_sample_in -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/ram_sample_in_bk -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/ram_sample_out -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/alu_ctrl -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/alu_sample_in -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/alu_coef_in -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/alu_out -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/curentcel -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/curentchan -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/sample_in_buff -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/sample_out_buff -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/coefsreg -add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/iir_cel_state -add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/cnv_run -add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/cnv -add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/sck -add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/sdo -add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/cnv_clk -add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/cnv_rstn -add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/clk -add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/rstn -add wave -noupdate -expand -subitemconfig {/tb_data_acquisition/top_data_acquisition_1/sample(7) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/sample(6) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/sample(5) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/sample(4) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/sample(3) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/sample(2) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/sample(1) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/sample(0) {-height 15 -radix decimal}} /tb_data_acquisition/top_data_acquisition_1/sample -add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/sample_val -add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/coefs -add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/sample_filter_in -add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/sample_filter_out -add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/iir_cel_state -add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/alu_selected_coeff -add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/chanel_ongoing -add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/cel_ongoing -add wave -noupdate -expand -group ALU /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/clk -add wave -noupdate -expand -group ALU /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/reset -add wave -noupdate -expand -group ALU /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/ctrl -add wave -noupdate -expand -group ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/op1 -add wave -noupdate -expand -group ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/op2 -add wave -noupdate -expand -group ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/res -add wave -noupdate -group ALU_MUX_INPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_sel_input -add wave -noupdate -group ALU_MUX_INPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/reg_sample_in -add wave -noupdate -group ALU_MUX_INPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_output -add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/rstn -add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/clk -add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/virg_pos -add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/coefs -add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/in_sel_src -add wave -noupdate -group DATA_FLOW -radix hexadecimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_sel_wdata -add wave -noupdate -group DATA_FLOW -radix unsigned /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_input -add wave -noupdate -group DATA_FLOW -radix hexadecimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_write -add wave -noupdate -group DATA_FLOW -radix hexadecimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_read -add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/raddr_rst -add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/raddr_add1 -add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/waddr_previous -add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_sel_input -add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_sel_coeff -add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_ctrl -add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/sample_in -add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/sample_out -add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/reg_sample_in -add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_output -add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_output -add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_sample -add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_output_s -add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/arraycoeff -add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_coef_s -add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_coef -add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/rstn -add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/clk -add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/virg_pos -add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/coefs -add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in_val -add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in -add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_val -add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out -add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/in_sel_src -add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/ram_sel_wdata -add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/ram_write -add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/ram_read -add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/raddr_rst -add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/raddr_add1 -add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/waddr_previous -add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/alu_sel_input -add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/alu_sel_coeff -add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/alu_ctrl -add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in_buf -add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in_rotate -add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in_s -add wave -noupdate -group IIR_CEL_FILTER_v2 -radix unsigned /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_val_s -add wave -noupdate -group IIR_CEL_FILTER_v2 -radix unsigned /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_val_s2 -add wave -noupdate -group IIR_CEL_FILTER_v2 -radix unsigned /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_rot_s -add wave -noupdate -group IIR_CEL_FILTER_v2 -radix unsigned -subitemconfig {/tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(17) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(16) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(15) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(14) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(13) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(12) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(11) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(10) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(9) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(8) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(7) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(6) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(5) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(4) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(3) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(2) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(1) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(0) {-radix unsigned}} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s -add wave -noupdate -group IIR_CEL_FILTER_v2 -radix unsigned -expand -subitemconfig {/tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(7) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(6) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(5) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(4) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(3) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(2) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(1) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(0) {-radix unsigned}} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2 -add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_INPUT_MUX -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/in_sel_src -add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_INPUT_MUX -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_output -add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_INPUT_MUX -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_output -add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_INPUT_MUX -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/sample_in -add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_INPUT_MUX -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/reg_sample_in -add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/waddr_previous -add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_write -add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_RAM -radix hexadecimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_sel_wdata -add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_RAM -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/reg_sample_in -add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_RAM -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_output -add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_RAM -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_output -add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_RAM -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_input -add wave -noupdate -group DATAFLOW -group DATAFLOW_OUTPUT_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_read -add wave -noupdate -group DATAFLOW -group DATAFLOW_OUTPUT_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/raddr_rst -add wave -noupdate -group DATAFLOW -group DATAFLOW_OUTPUT_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/raddr_add1 -add wave -noupdate -group DATAFLOW -group DATAFLOW_OUTPUT_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_output -add wave -noupdate -group DATAFLOW -group DATAFLOW_SELECT_COEFF /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/arraycoeff -add wave -noupdate -group DATAFLOW -group DATAFLOW_SELECT_COEFF /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_coef_s -add wave -noupdate -group DATAFLOW -group DATAFLOW_SELECT_COEFF -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_coef -add wave -noupdate -group DATAFLOW -group DATAFLOW_SELECT_COEFF -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_sel_coeff -add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_ALU_MUX /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_sel_input -add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_ALU_MUX -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/reg_sample_in -add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_ALU_MUX -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_output -add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_ctrl -add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_coef -add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_sample -add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_output_s -add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_output -add wave -noupdate -group DATAFLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/iir_cel_state -add wave -noupdate -group DATAFLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/chanel_ongoing -add wave -noupdate -group DATAFLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/cel_ongoing -add wave -noupdate -group DATAFLOW -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/sample_out -add wave -noupdate -group DATAFLOW_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/rstn -add wave -noupdate -group DATAFLOW_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/clk -add wave -noupdate -group DATAFLOW_RAM -subitemconfig {/tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(0) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(1) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(2) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(3) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(4) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(5) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(6) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(7) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(8) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(9) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(10) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(11) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(12) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(13) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(14) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(15) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(16) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(17) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(18) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(19) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(20) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(21) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(22) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(23) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(24) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(25) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(26) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(27) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(28) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(29) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(30) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(31) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(32) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(33) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(34) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(35) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(36) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(37) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(38) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(39) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(40) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(41) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(42) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(43) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(44) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(45) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(46) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(47) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(48) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(49) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(50) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(51) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(52) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(53) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(54) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(55) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(56) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(57) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(58) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(59) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(60) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(61) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(62) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(63) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(64) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(65) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(66) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(67) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(68) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(69) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(70) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(71) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(72) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(73) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(74) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(75) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(76) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(77) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(78) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(79) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(80) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(81) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(82) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(83) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(84) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(85) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(86) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(87) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(88) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(89) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(90) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(91) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(92) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(93) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(94) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(95) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(96) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(97) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(98) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(99) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(100) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(101) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(102) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(103) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(104) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(105) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(106) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(107) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(108) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(109) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(110) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(111) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(112) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(113) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(114) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(115) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(116) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(117) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(118) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(119) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(120) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(121) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(122) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(123) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(124) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(125) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(126) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(127) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(128) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(129) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(130) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(131) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(132) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(133) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(134) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(135) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(136) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(137) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(138) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(139) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(140) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(141) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(142) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(143) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(144) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(145) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(146) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(147) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(148) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(149) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(150) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(151) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(152) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(153) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(154) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(155) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(156) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(157) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(158) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(159) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(160) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(161) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(162) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(163) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(164) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(165) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(166) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(167) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(168) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(169) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(170) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(171) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(172) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(173) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(174) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(175) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(176) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(177) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(178) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(179) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(180) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(181) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(182) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(183) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(184) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(185) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(186) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(187) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(188) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(189) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(190) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(191) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(192) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(193) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(194) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(195) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(196) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(197) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(198) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(199) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(200) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(201) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(202) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(203) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(204) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(205) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(206) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(207) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(208) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(209) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(210) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(211) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(212) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(213) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(214) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(215) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(216) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(217) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(218) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(219) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(220) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(221) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(222) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(223) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(224) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(225) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(226) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(227) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(228) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(229) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(230) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(231) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(232) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(233) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(234) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(235) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(236) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(237) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(238) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(239) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(240) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(241) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(242) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(243) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(244) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(245) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(246) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(247) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(248) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(249) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(250) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(251) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(252) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(253) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(254) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(255) {-height 15 -radix decimal}} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray -add wave -noupdate -group DATAFLOW_RAM -group COUNTER -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/counter -add wave -noupdate -group DATAFLOW_RAM -group COUNTER /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/raddr_rst -add wave -noupdate -group DATAFLOW_RAM -group COUNTER /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/raddr_add1 -add wave -noupdate -group DATAFLOW_RAM -group COUNTER /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/waddr_previous -add wave -noupdate -group DATAFLOW_RAM -group WRITE /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/ram_write -add wave -noupdate -group DATAFLOW_RAM -group WRITE /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/wen -add wave -noupdate -group DATAFLOW_RAM -group WRITE -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/waddr -add wave -noupdate -group DATAFLOW_RAM -group WRITE -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/wd -add wave -noupdate -group DATAFLOW_RAM -group WRITE -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/sample_in -add wave -noupdate -group DATAFLOW_RAM -group READ /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/ram_read -add wave -noupdate -group DATAFLOW_RAM -group READ /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/ren -add wave -noupdate -group DATAFLOW_RAM -group READ -radix unsigned /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/raddr -add wave -noupdate -group DATAFLOW_RAM -group READ /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/rd -add wave -noupdate -group DATAFLOW_RAM -group READ /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/sample_out -add wave -noupdate -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in_val -add wave -noupdate -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in -add wave -noupdate -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_val -add wave -noupdate -radix decimal -subitemconfig {/tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(7) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(6) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(5) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(4) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(3) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(2) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(1) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(0) {-height 15 -radix decimal}} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out -add wave -noupdate -height 15 -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(4) -add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/clk -add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/reset -add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/clr_mac -add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/mac_mul_add -add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/op1 -add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/op2 -add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/res -add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/add -add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/mult -add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/multout -add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/adderina -add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/adderinb -add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/adderout -add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/macmuxsel -add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/op1_d_resz -add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/op2_d_resz -add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/macmux2sel -add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/add_d -add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/op1_d -add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/op2_d -add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/multout_d -add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/macmuxsel_d -add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/macmux2sel_d -add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/macmux2sel_d_d -add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/clr_mac_d -add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/clr_mac_d_d -add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/sample_out_val -add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/sample_out_rot -add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/iir_cel_state -add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/sample_out -add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_val_s -add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_val_s2 -add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_rot_s -add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s -add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2 +add wave -noupdate -expand -group {Data Acq & Filter} -expand -group DIGITAL_ACQ /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/sample +add wave -noupdate -expand -group {Data Acq & Filter} -expand -group DIGITAL_ACQ /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/sample_val +add wave -noupdate -expand -group {Data Acq & Filter} -group FILTER /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in_val +add wave -noupdate -expand -group {Data Acq & Filter} -group FILTER /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in +add wave -noupdate -expand -group {Data Acq & Filter} -group FILTER /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_val +add wave -noupdate -expand -group {Data Acq & Filter} -group FILTER /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out +add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f0} /tb_data_acquisition/top_data_acquisition_1/downsampling_f0/sample_in_val +add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f0} /tb_data_acquisition/top_data_acquisition_1/downsampling_f0/sample_in +add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f0} /tb_data_acquisition/top_data_acquisition_1/downsampling_f0/sample_out_val +add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f0} /tb_data_acquisition/top_data_acquisition_1/downsampling_f0/sample_out +add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f1} /tb_data_acquisition/top_data_acquisition_1/downsampling_f1/sample_in_val +add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f1} /tb_data_acquisition/top_data_acquisition_1/downsampling_f1/sample_in +add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f1} /tb_data_acquisition/top_data_acquisition_1/downsampling_f1/sample_out_val +add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f1} /tb_data_acquisition/top_data_acquisition_1/downsampling_f1/sample_out +add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f2} /tb_data_acquisition/top_data_acquisition_1/downsampling_f2/sample_in_val +add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f2} /tb_data_acquisition/top_data_acquisition_1/downsampling_f2/sample_in +add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f2} /tb_data_acquisition/top_data_acquisition_1/downsampling_f2/sample_out_val +add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f2} /tb_data_acquisition/top_data_acquisition_1/downsampling_f2/sample_out +add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f3} /tb_data_acquisition/top_data_acquisition_1/downsampling_f3/sample_in_val +add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f3} /tb_data_acquisition/top_data_acquisition_1/downsampling_f3/sample_in +add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f3} /tb_data_acquisition/top_data_acquisition_1/downsampling_f3/sample_out_val +add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f3} /tb_data_acquisition/top_data_acquisition_1/downsampling_f3/sample_out +add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f0_wen +add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f0_wdata +add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f1_wen +add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f1_wdata +add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f2_wen +add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f2_wdata +add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f3_wen +add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f3_wdata TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {4520000 ps} 0} -configure wave -namecolwidth 677 +WaveRestoreCursors {{Cursor 1} {0 ps} 0} +configure wave -namecolwidth 430 configure wave -valuecolwidth 100 configure wave -justifyvalue left configure wave -signalnamewidth 0 @@ -239,4 +46,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {2722930 ps} {6210191 ps} +WaveRestoreZoom {0 ps} {754717 ps} diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/wave_waveform_picker.do b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/wave_waveform_picker.do new file mode 100644 --- /dev/null +++ b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/wave_waveform_picker.do @@ -0,0 +1,364 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /tb_data_acquisition/sample_f0_wen +add wave -noupdate /tb_data_acquisition/sample_f0_wdata +add wave -noupdate /tb_data_acquisition/sample_f1_wen +add wave -noupdate /tb_data_acquisition/sample_f1_wdata +add wave -noupdate /tb_data_acquisition/sample_f2_wen +add wave -noupdate /tb_data_acquisition/sample_f2_wdata +add wave -noupdate /tb_data_acquisition/sample_f3_wen +add wave -noupdate /tb_data_acquisition/sample_f3_wdata +add wave -noupdate -group TOP /tb_data_acquisition/ahb_master_in +add wave -noupdate -group TOP /tb_data_acquisition/ahb_master_out +add wave -noupdate -group TOP /tb_data_acquisition/coarse_time_0 +add wave -noupdate -group TOP /tb_data_acquisition/coarse_time_0_t +add wave -noupdate -group TOP /tb_data_acquisition/coarse_time_0_t2 +add wave -noupdate -group TOP /tb_data_acquisition/delta_snapshot +add wave -noupdate -group TOP /tb_data_acquisition/delta_f2_f1 +add wave -noupdate -group TOP /tb_data_acquisition/delta_f2_f0 +add wave -noupdate -group TOP /tb_data_acquisition/enable_f0 +add wave -noupdate -group TOP /tb_data_acquisition/enable_f1 +add wave -noupdate -group TOP /tb_data_acquisition/enable_f2 +add wave -noupdate -group TOP /tb_data_acquisition/enable_f3 +add wave -noupdate -group TOP /tb_data_acquisition/burst_f0 +add wave -noupdate -group TOP /tb_data_acquisition/burst_f1 +add wave -noupdate -group TOP /tb_data_acquisition/burst_f2 +add wave -noupdate -group TOP /tb_data_acquisition/nb_snapshot_param +add wave -noupdate -group TOP /tb_data_acquisition/status_full +add wave -noupdate -group TOP /tb_data_acquisition/status_full_ack +add wave -noupdate -group TOP /tb_data_acquisition/status_full_err +add wave -noupdate -group TOP /tb_data_acquisition/status_new_err +add wave -noupdate -group TOP /tb_data_acquisition/addr_data_f0 +add wave -noupdate -group TOP /tb_data_acquisition/addr_data_f1 +add wave -noupdate -group TOP /tb_data_acquisition/addr_data_f2 +add wave -noupdate -group TOP /tb_data_acquisition/addr_data_f3 +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_size +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/nb_snapshot_param_size +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/delta_snapshot_size +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/delta_f2_f0_size +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/delta_f2_f1_size +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/clk +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/rstn +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/ahb_master_in +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/ahb_master_out +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/coarse_time_0 +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/delta_snapshot +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/delta_f2_f1 +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/delta_f2_f0 +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/enable_f0 +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/enable_f1 +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/enable_f2 +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/enable_f3 +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/burst_f0 +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/burst_f1 +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/burst_f2 +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/nb_snapshot_param +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/status_full +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/status_full_ack +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/status_full_err +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/status_new_err +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/addr_data_f0 +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/addr_data_f1 +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/addr_data_f2 +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/addr_data_f3 +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f0_in +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f1_in +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f2_in +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f3_in +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f0_in_valid +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f1_in_valid +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f2_in_valid +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f3_in_valid +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/start_snapshot_f0 +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/start_snapshot_f1 +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/start_snapshot_f2 +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f0_out +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f1_out +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f2_out +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f3_out +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f0_out_valid +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f1_out_valid +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f2_out_valid +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f3_out_valid +add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/clk +add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/rstn +add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/delta_snapshot +add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/delta_f2_f1 +add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/delta_f2_f0 +add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/coarse_time_0 +add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/data_f2_in_valid +add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/start_snapshot_f0 +add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/start_snapshot_f1 +add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/start_snapshot_f2 +add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/counter_delta_snapshot +add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/coarse_time_0_r +add wave -noupdate -group waveform_snapshot_f0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f0/clk +add wave -noupdate -group waveform_snapshot_f0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f0/rstn +add wave -noupdate -group waveform_snapshot_f0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f0/enable +add wave -noupdate -group waveform_snapshot_f0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f0/burst_enable +add wave -noupdate -group waveform_snapshot_f0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f0/nb_snapshot_param +add wave -noupdate -group waveform_snapshot_f0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f0/start_snapshot +add wave -noupdate -group waveform_snapshot_f0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f0/data_in +add wave -noupdate -group waveform_snapshot_f0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f0/data_in_valid +add wave -noupdate -group waveform_snapshot_f0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f0/data_out +add wave -noupdate -group waveform_snapshot_f0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f0/data_out_valid +add wave -noupdate -group waveform_snapshot_f0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f0/counter_points_snapshot +add wave -noupdate -group waveform_snapshot_f1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f1/clk +add wave -noupdate -group waveform_snapshot_f1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f1/rstn +add wave -noupdate -group waveform_snapshot_f1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f1/enable +add wave -noupdate -group waveform_snapshot_f1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f1/burst_enable +add wave -noupdate -group waveform_snapshot_f1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f1/nb_snapshot_param +add wave -noupdate -group waveform_snapshot_f1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f1/start_snapshot +add wave -noupdate -group waveform_snapshot_f1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f1/data_in +add wave -noupdate -group waveform_snapshot_f1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f1/data_in_valid +add wave -noupdate -group waveform_snapshot_f1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f1/data_out +add wave -noupdate -group waveform_snapshot_f1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f1/data_out_valid +add wave -noupdate -group waveform_snapshot_f1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f1/counter_points_snapshot +add wave -noupdate -group waveform_snapshot_f2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f2/clk +add wave -noupdate -group waveform_snapshot_f2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f2/rstn +add wave -noupdate -group waveform_snapshot_f2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f2/enable +add wave -noupdate -group waveform_snapshot_f2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f2/burst_enable +add wave -noupdate -group waveform_snapshot_f2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f2/nb_snapshot_param +add wave -noupdate -group waveform_snapshot_f2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f2/start_snapshot +add wave -noupdate -group waveform_snapshot_f2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f2/data_in +add wave -noupdate -group waveform_snapshot_f2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f2/data_in_valid +add wave -noupdate -group waveform_snapshot_f2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f2/data_out +add wave -noupdate -group waveform_snapshot_f2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f2/data_out_valid +add wave -noupdate -group waveform_snapshot_f2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f2/counter_points_snapshot +add wave -noupdate -group waveform_burst____f3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_burst_f3/clk +add wave -noupdate -group waveform_burst____f3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_burst_f3/rstn +add wave -noupdate -group waveform_burst____f3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_burst_f3/enable +add wave -noupdate -group waveform_burst____f3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_burst_f3/data_in +add wave -noupdate -group waveform_burst____f3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_burst_f3/data_in_valid +add wave -noupdate -group waveform_burst____f3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_burst_f3/data_out +add wave -noupdate -group waveform_burst____f3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_burst_f3/data_out_valid +add wave -noupdate -group GEN_VALID_F0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(0)/lpp_waveform_dma_gen_valid_i/hclk +add wave -noupdate -group GEN_VALID_F0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(0)/lpp_waveform_dma_gen_valid_i/hresetn +add wave -noupdate -group GEN_VALID_F0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(0)/lpp_waveform_dma_gen_valid_i/valid_in +add wave -noupdate -group GEN_VALID_F0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(0)/lpp_waveform_dma_gen_valid_i/ack_in +add wave -noupdate -group GEN_VALID_F0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(0)/lpp_waveform_dma_gen_valid_i/valid_out +add wave -noupdate -group GEN_VALID_F0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(0)/lpp_waveform_dma_gen_valid_i/error +add wave -noupdate -group GEN_VALID_F1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(1)/lpp_waveform_dma_gen_valid_i/hclk +add wave -noupdate -group GEN_VALID_F1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(1)/lpp_waveform_dma_gen_valid_i/hresetn +add wave -noupdate -group GEN_VALID_F1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(1)/lpp_waveform_dma_gen_valid_i/valid_in +add wave -noupdate -group GEN_VALID_F1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(1)/lpp_waveform_dma_gen_valid_i/ack_in +add wave -noupdate -group GEN_VALID_F1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(1)/lpp_waveform_dma_gen_valid_i/valid_out +add wave -noupdate -group GEN_VALID_F1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(1)/lpp_waveform_dma_gen_valid_i/error +add wave -noupdate -group GEN_VALID_F1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(1)/lpp_waveform_dma_gen_valid_i/state +add wave -noupdate -group GEN_VALID_F2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(2)/lpp_waveform_dma_gen_valid_i/hclk +add wave -noupdate -group GEN_VALID_F2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(2)/lpp_waveform_dma_gen_valid_i/hresetn +add wave -noupdate -group GEN_VALID_F2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(2)/lpp_waveform_dma_gen_valid_i/valid_in +add wave -noupdate -group GEN_VALID_F2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(2)/lpp_waveform_dma_gen_valid_i/ack_in +add wave -noupdate -group GEN_VALID_F2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(2)/lpp_waveform_dma_gen_valid_i/valid_out +add wave -noupdate -group GEN_VALID_F2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(2)/lpp_waveform_dma_gen_valid_i/error +add wave -noupdate -group GEN_VALID_F2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(2)/lpp_waveform_dma_gen_valid_i/state +add wave -noupdate -group GEN_VALID_F3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(3)/lpp_waveform_dma_gen_valid_i/hclk +add wave -noupdate -group GEN_VALID_F3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(3)/lpp_waveform_dma_gen_valid_i/hresetn +add wave -noupdate -group GEN_VALID_F3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(3)/lpp_waveform_dma_gen_valid_i/valid_in +add wave -noupdate -group GEN_VALID_F3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(3)/lpp_waveform_dma_gen_valid_i/ack_in +add wave -noupdate -group GEN_VALID_F3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(3)/lpp_waveform_dma_gen_valid_i/valid_out +add wave -noupdate -group GEN_VALID_F3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(3)/lpp_waveform_dma_gen_valid_i/error +add wave -noupdate -group GEN_VALID_F3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(3)/lpp_waveform_dma_gen_valid_i/state +add wave -noupdate /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/valid_in +add wave -noupdate /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/valid_out +add wave -noupdate /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/valid_ack +add wave -noupdate /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/status_new_err +add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/clk +add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/rstn +add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/state +add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_f0_valid +add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_f1_valid +add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_f2_valid +add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_f3_valid +add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_valid_ack +add wave -noupdate -group FIFO_ARB -radix hexadecimal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_f0 +add wave -noupdate -group FIFO_ARB -radix hexadecimal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_f1 +add wave -noupdate -group FIFO_ARB -radix hexadecimal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_f2 +add wave -noupdate -group FIFO_ARB -radix hexadecimal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_f3 +add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/ready +add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/time_wen +add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_wen +add wave -noupdate -group FIFO_ARB -radix hexadecimal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data +add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_valid_and_ready +add wave -noupdate -group FIFO_ARB -radix hexadecimal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_selected +add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_valid_selected +add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_ready_to_go +add wave -noupdate -group FIFO_ARB -radix hexadecimal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_temp +add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/time_en_temp +add wave -noupdate -expand -group FIFO -expand -group {IN - OUT} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/rstn +add wave -noupdate -expand -group FIFO -expand -group {IN - OUT} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/ready +add wave -noupdate -expand -group FIFO -expand -group {IN - OUT} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/time_ren +add wave -noupdate -expand -group FIFO -expand -group {IN - OUT} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/data_ren +add wave -noupdate -expand -group FIFO -expand -group {IN - OUT} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/rdata +add wave -noupdate -expand -group FIFO -expand -group {IN - OUT} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/time_wen +add wave -noupdate -expand -group FIFO -expand -group {IN - OUT} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/data_wen +add wave -noupdate -expand -group FIFO -expand -group {IN - OUT} -radix hexadecimal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/wdata +add wave -noupdate -expand -group FIFO -expand -group read -radix hexadecimal -subitemconfig {/tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/time_mem_addr_r(3) {-radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/time_mem_addr_r(2) {-radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/time_mem_addr_r(1) {-radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/time_mem_addr_r(0) {-radix hexadecimal}} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/time_mem_addr_r +add wave -noupdate -expand -group FIFO -expand -group read /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/data_mem_addr_r +add wave -noupdate -expand -group FIFO -expand -group read /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/time_mem_ren +add wave -noupdate -expand -group FIFO -expand -group read /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/data_mem_ren +add wave -noupdate -expand -group FIFO -expand -group read /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/data_addr_r +add wave -noupdate -expand -group FIFO -expand -group read /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/ren +add wave -noupdate -expand -group FIFO -group write /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/data_mem_addr_w +add wave -noupdate -expand -group FIFO -group write /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/time_mem_addr_w +add wave -noupdate -expand -group FIFO -group write /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/data_mem_wen +add wave -noupdate -expand -group FIFO -group write /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/time_mem_wen +add wave -noupdate -expand -group FIFO -group write -radix unsigned /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/data_addr_w +add wave -noupdate -expand -group FIFO -group write /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/wen +add wave -noupdate -radix hexadecimal -subitemconfig {/tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(0) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(1) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(2) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(3) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(4) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(5) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(6) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(7) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(8) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(9) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(10) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(11) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(12) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(13) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(14) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(15) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(16) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(17) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(18) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(19) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(20) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(21) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(22) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(23) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(24) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(25) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(26) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(27) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(28) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(29) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(30) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(31) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(32) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(33) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(34) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(35) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(36) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(37) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(38) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(39) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(40) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(41) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(42) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(43) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(44) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(45) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(46) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(47) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(48) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(49) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(50) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(51) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(52) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(53) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(54) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(55) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(56) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(57) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(58) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(59) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(60) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(61) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(62) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(63) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(64) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(65) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(66) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(67) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(68) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(69) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(70) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(71) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(72) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(73) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(74) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(75) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(76) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(77) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(78) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(79) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(80) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(81) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(82) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(83) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(84) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(85) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(86) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(87) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(88) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(89) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(90) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(91) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(92) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(93) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(94) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(95) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(96) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(97) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(98) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(99) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(100) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(101) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(102) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(103) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(104) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(105) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(106) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(107) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(108) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(109) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(110) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(111) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(112) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(113) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(114) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(115) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(116) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(117) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(118) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(119) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(120) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(121) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(122) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(123) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(124) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(125) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(126) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(127) {-height 15 -radix hexadecimal}} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd +add wave -noupdate -expand -group DMA -expand -group INOUT /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/hclk +add wave -noupdate -expand -group DMA -expand -group INOUT /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/hresetn +add wave -noupdate -expand -group DMA -expand -group INOUT /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/ahb_master_in +add wave -noupdate -expand -group DMA -expand -group INOUT -subitemconfig {/tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/ahb_master_out.haddr {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/ahb_master_out.hwdata {-height 15 -radix hexadecimal}} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/ahb_master_out +add wave -noupdate -expand -group DMA -expand -group INOUT -expand -group FIFO_interface /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/data_ready +add wave -noupdate -expand -group DMA -expand -group INOUT -expand -group FIFO_interface /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/data +add wave -noupdate -expand -group DMA -expand -group INOUT -expand -group FIFO_interface /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/data_data_ren +add wave -noupdate -expand -group DMA -expand -group INOUT -expand -group FIFO_interface /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/data_time_ren +add wave -noupdate -expand -group DMA -expand -group INOUT -expand -group REG_CONFIG -radix unsigned /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/nb_burst_available +add wave -noupdate -expand -group DMA -expand -group INOUT -expand -group REG_CONFIG /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/addr_data_f0 +add wave -noupdate -expand -group DMA -expand -group INOUT -expand -group REG_CONFIG /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/addr_data_f1 +add wave -noupdate -expand -group DMA -expand -group INOUT -expand -group REG_CONFIG /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/addr_data_f2 +add wave -noupdate -expand -group DMA -expand -group INOUT -expand -group REG_CONFIG /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/addr_data_f3 +add wave -noupdate -expand -group DMA -expand -group INOUT /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/status_full +add wave -noupdate -expand -group DMA -expand -group INOUT /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/status_full_ack +add wave -noupdate -expand -group DMA -expand -group INOUT /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/status_full_err +add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/dmain +add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/dmaout +add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/state +add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/sel_data_s +add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/sel_data +add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/update +add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/time_select +add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/time_write +add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/time_already_send +add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/time_already_send_s +add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/time_dmai +add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/time_send +add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/time_send_ok +add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/time_send_ko +add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/time_fifo_ren +add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/time_ren +add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/data_dmai +add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/data_send +add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/data_send_ok +add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/data_send_ko +add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/data_fifo_ren +add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/data_ren +add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/data_address +add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/update_and_sel +add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/addr_data_reg_vector +add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/addr_data_vector +add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/send_16_3_time +add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/count_send_time +add wave -noupdate /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/ren +add wave -noupdate /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/wen +add wave -noupdate -group fifo_ctrl_time_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(3)/lpp_waveform_fifo_ctrl_time/clk +add wave -noupdate -group fifo_ctrl_time_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(3)/lpp_waveform_fifo_ctrl_time/rstn +add wave -noupdate -group fifo_ctrl_time_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(3)/lpp_waveform_fifo_ctrl_time/ren +add wave -noupdate -group fifo_ctrl_time_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(3)/lpp_waveform_fifo_ctrl_time/wen +add wave -noupdate -group fifo_ctrl_time_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(3)/lpp_waveform_fifo_ctrl_time/mem_re +add wave -noupdate -group fifo_ctrl_time_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(3)/lpp_waveform_fifo_ctrl_time/mem_we +add wave -noupdate -group fifo_ctrl_time_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(3)/lpp_waveform_fifo_ctrl_time/mem_addr_ren +add wave -noupdate -group fifo_ctrl_time_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(3)/lpp_waveform_fifo_ctrl_time/mem_addr_wen +add wave -noupdate -group fifo_ctrl_time_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(3)/lpp_waveform_fifo_ctrl_time/ready +add wave -noupdate -expand -group fifo_ctrl_time_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(2)/lpp_waveform_fifo_ctrl_time/clk +add wave -noupdate -expand -group fifo_ctrl_time_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(2)/lpp_waveform_fifo_ctrl_time/rstn +add wave -noupdate -expand -group fifo_ctrl_time_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(2)/lpp_waveform_fifo_ctrl_time/ren +add wave -noupdate -expand -group fifo_ctrl_time_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(2)/lpp_waveform_fifo_ctrl_time/wen +add wave -noupdate -expand -group fifo_ctrl_time_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(2)/lpp_waveform_fifo_ctrl_time/mem_re +add wave -noupdate -expand -group fifo_ctrl_time_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(2)/lpp_waveform_fifo_ctrl_time/mem_we +add wave -noupdate -expand -group fifo_ctrl_time_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(2)/lpp_waveform_fifo_ctrl_time/mem_addr_ren +add wave -noupdate -expand -group fifo_ctrl_time_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(2)/lpp_waveform_fifo_ctrl_time/mem_addr_wen +add wave -noupdate -expand -group fifo_ctrl_time_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(2)/lpp_waveform_fifo_ctrl_time/ready +add wave -noupdate -expand -group fifo_ctrl_time_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(1)/lpp_waveform_fifo_ctrl_time/clk +add wave -noupdate -expand -group fifo_ctrl_time_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(1)/lpp_waveform_fifo_ctrl_time/rstn +add wave -noupdate -expand -group fifo_ctrl_time_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(1)/lpp_waveform_fifo_ctrl_time/ren +add wave -noupdate -expand -group fifo_ctrl_time_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(1)/lpp_waveform_fifo_ctrl_time/wen +add wave -noupdate -expand -group fifo_ctrl_time_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(1)/lpp_waveform_fifo_ctrl_time/mem_re +add wave -noupdate -expand -group fifo_ctrl_time_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(1)/lpp_waveform_fifo_ctrl_time/mem_we +add wave -noupdate -expand -group fifo_ctrl_time_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(1)/lpp_waveform_fifo_ctrl_time/mem_addr_ren +add wave -noupdate -expand -group fifo_ctrl_time_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(1)/lpp_waveform_fifo_ctrl_time/mem_addr_wen +add wave -noupdate -expand -group fifo_ctrl_time_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(1)/lpp_waveform_fifo_ctrl_time/ready +add wave -noupdate -group fifo_ctrl_time_0 -group IN /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/clk +add wave -noupdate -group fifo_ctrl_time_0 -group IN /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/rstn +add wave -noupdate -group fifo_ctrl_time_0 -group IN /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/ren +add wave -noupdate -group fifo_ctrl_time_0 -group IN /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/wen +add wave -noupdate -group fifo_ctrl_time_0 -group OUT /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/mem_re +add wave -noupdate -group fifo_ctrl_time_0 -group OUT /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/mem_we +add wave -noupdate -group fifo_ctrl_time_0 -group OUT /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/mem_addr_ren +add wave -noupdate -group fifo_ctrl_time_0 -group OUT /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/mem_addr_wen +add wave -noupdate -group fifo_ctrl_time_0 -group OUT /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/ready +add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/sfull +add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/sfull_s +add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/sempty_s +add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/sempty +add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/sren +add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/swen +add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/sre +add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/swe +add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/waddr_vect +add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/raddr_vect +add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/waddr_vect_s +add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/raddr_vect_s +add wave -noupdate -group fifo_ctrl_time_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/clk +add wave -noupdate -group fifo_ctrl_time_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/rstn +add wave -noupdate -group fifo_ctrl_time_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/ren +add wave -noupdate -group fifo_ctrl_time_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/wen +add wave -noupdate -group fifo_ctrl_time_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/mem_re +add wave -noupdate -group fifo_ctrl_time_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/mem_we +add wave -noupdate -group fifo_ctrl_time_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/mem_addr_ren +add wave -noupdate -group fifo_ctrl_time_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/mem_addr_wen +add wave -noupdate -group fifo_ctrl_time_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/ready +add wave -noupdate -group fifo_ctrl_data_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(3)/lpp_waveform_fifo_ctrl_data/clk +add wave -noupdate -group fifo_ctrl_data_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(3)/lpp_waveform_fifo_ctrl_data/rstn +add wave -noupdate -group fifo_ctrl_data_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(3)/lpp_waveform_fifo_ctrl_data/ren +add wave -noupdate -group fifo_ctrl_data_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(3)/lpp_waveform_fifo_ctrl_data/wen +add wave -noupdate -group fifo_ctrl_data_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(3)/lpp_waveform_fifo_ctrl_data/mem_re +add wave -noupdate -group fifo_ctrl_data_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(3)/lpp_waveform_fifo_ctrl_data/mem_we +add wave -noupdate -group fifo_ctrl_data_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(3)/lpp_waveform_fifo_ctrl_data/mem_addr_ren +add wave -noupdate -group fifo_ctrl_data_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(3)/lpp_waveform_fifo_ctrl_data/mem_addr_wen +add wave -noupdate -group fifo_ctrl_data_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(3)/lpp_waveform_fifo_ctrl_data/ready +add wave -noupdate -expand -group fifo_ctrl_data_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(2)/lpp_waveform_fifo_ctrl_data/clk +add wave -noupdate -expand -group fifo_ctrl_data_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(2)/lpp_waveform_fifo_ctrl_data/rstn +add wave -noupdate -expand -group fifo_ctrl_data_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(2)/lpp_waveform_fifo_ctrl_data/ren +add wave -noupdate -expand -group fifo_ctrl_data_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(2)/lpp_waveform_fifo_ctrl_data/wen +add wave -noupdate -expand -group fifo_ctrl_data_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(2)/lpp_waveform_fifo_ctrl_data/mem_re +add wave -noupdate -expand -group fifo_ctrl_data_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(2)/lpp_waveform_fifo_ctrl_data/mem_we +add wave -noupdate -expand -group fifo_ctrl_data_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(2)/lpp_waveform_fifo_ctrl_data/mem_addr_ren +add wave -noupdate -expand -group fifo_ctrl_data_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(2)/lpp_waveform_fifo_ctrl_data/mem_addr_wen +add wave -noupdate -expand -group fifo_ctrl_data_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(2)/lpp_waveform_fifo_ctrl_data/ready +add wave -noupdate -group fifo_ctrl_data_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(1)/lpp_waveform_fifo_ctrl_data/clk +add wave -noupdate -group fifo_ctrl_data_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(1)/lpp_waveform_fifo_ctrl_data/rstn +add wave -noupdate -group fifo_ctrl_data_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(1)/lpp_waveform_fifo_ctrl_data/ren +add wave -noupdate -group fifo_ctrl_data_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(1)/lpp_waveform_fifo_ctrl_data/wen +add wave -noupdate -group fifo_ctrl_data_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(1)/lpp_waveform_fifo_ctrl_data/mem_re +add wave -noupdate -group fifo_ctrl_data_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(1)/lpp_waveform_fifo_ctrl_data/mem_we +add wave -noupdate -group fifo_ctrl_data_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(1)/lpp_waveform_fifo_ctrl_data/mem_addr_ren +add wave -noupdate -group fifo_ctrl_data_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(1)/lpp_waveform_fifo_ctrl_data/mem_addr_wen +add wave -noupdate -group fifo_ctrl_data_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(1)/lpp_waveform_fifo_ctrl_data/ready +add wave -noupdate -group fifo_ctrl_data_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(0)/lpp_waveform_fifo_ctrl_data/clk +add wave -noupdate -group fifo_ctrl_data_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(0)/lpp_waveform_fifo_ctrl_data/rstn +add wave -noupdate -group fifo_ctrl_data_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(0)/lpp_waveform_fifo_ctrl_data/ren +add wave -noupdate -group fifo_ctrl_data_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(0)/lpp_waveform_fifo_ctrl_data/wen +add wave -noupdate -group fifo_ctrl_data_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(0)/lpp_waveform_fifo_ctrl_data/mem_re +add wave -noupdate -group fifo_ctrl_data_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(0)/lpp_waveform_fifo_ctrl_data/mem_we +add wave -noupdate -group fifo_ctrl_data_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(0)/lpp_waveform_fifo_ctrl_data/mem_addr_ren +add wave -noupdate -group fifo_ctrl_data_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(0)/lpp_waveform_fifo_ctrl_data/mem_addr_wen +add wave -noupdate -group fifo_ctrl_data_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(0)/lpp_waveform_fifo_ctrl_data/ready +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {70458134452 ps} 0} +configure wave -namecolwidth 842 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {70455153866 ps} {70464281299 ps} diff --git a/lib/lpp/dsp/iir_filter/APB_IIR_CEL.vhd b/lib/lpp/dsp/iir_filter/APB_IIR_CEL.vhd --- a/lib/lpp/dsp/iir_filter/APB_IIR_CEL.vhd +++ b/lib/lpp/dsp/iir_filter/APB_IIR_CEL.vhd @@ -1,212 +1,213 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Alexis Jeandet --- Mail : alexis.jeandet@lpp.polytechnique.fr -------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -library grlib; -use grlib.amba.all; -use grlib.stdlib.all; -use grlib.devices.all; -library lpp; -use lpp.iir_filter.all; -use lpp.general_purpose.all; -use lpp.lpp_amba.all; -use lpp.apb_devices_list.all; - -entity APB_IIR_CEL is - generic ( - tech : integer := 0; - pindex : integer := 0; - paddr : integer := 0; - pmask : integer := 16#fff#; - pirq : integer := 0; - abits : integer := 8; - Sample_SZ : integer := 16; - ChanelsCount : integer := 1; - Coef_SZ : integer := 9; - CoefCntPerCel: integer := 6; - Cels_count : integer := 5; - virgPos : integer := 3; - Mem_use : integer := use_RAM - ); - port ( - rst : in std_logic; - clk : in std_logic; - apbi : in apb_slv_in_type; - apbo : out apb_slv_out_type; - sample_clk : in std_logic; - sample_clk_out : out std_logic; - sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0); - sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0); - CoefsInitVal : in std_logic_vector((Cels_count*CoefCntPerCel*Coef_SZ)-1 downto 0) := (others => '1') - ); -end; - - -architecture AR_APB_IIR_CEL of APB_IIR_CEL is - -constant REVISION : integer := 1; - -constant pconfig : apb_config_type := ( - 0 => ahb_device_reg (VENDOR_LPP, LPP_IIR_CEL_FILTER, 0, REVISION, 0), - 1 => apb_iobar(paddr, pmask)); - - - -type FILTERreg is record - regin : in_IIR_CEL_reg; - regout : out_IIR_CEL_reg; -end record; - -signal Rdata : std_logic_vector(31 downto 0); -signal r : FILTERreg; -signal filter_reset : std_logic:='0'; -signal smp_cnt : integer :=0; -signal sample_clk_out_R : std_logic; -signal RawCoefs : std_logic_vector(((Coef_SZ*CoefCntPerCel*Cels_count)-1) downto 0); - -type CoefCelT is array(0 to (CoefCntPerCel/2)-1) of std_logic_vector(Coef_SZ-1 downto 0); -type CoefTblT is array(0 to Cels_count-1) of CoefCelT; - -type CoefsRegT is record - numCoefs : CoefTblT; - denCoefs : CoefTblT; -end record; - -signal CoefsReg : CoefsRegT; -signal CoefsReg_d : CoefsRegT; - - -begin - -filter_reset <= rst and r.regin.config(0); -sample_clk_out <= sample_clk_out_R; --- -filter : IIR_CEL_FILTER -generic map(tech,Sample_SZ,ChanelsCount,Coef_SZ,CoefCntPerCel,Cels_count,Mem_use) -port map( - reset => filter_reset, - clk => clk, - sample_clk => sample_clk, - regs_in => r.regin, - regs_out => r.regout, - sample_in => sample_in, - sample_out => sample_out, - coefs => RawCoefs - ); - -process(rst,sample_clk) -begin -if rst = '0' then - smp_cnt <= 0; - sample_clk_out_R <= '0'; -elsif sample_clk'event and sample_clk = '1' then - if smp_cnt = 1 then - smp_cnt <= 0; - sample_clk_out_R <= not sample_clk_out_R; - else - smp_cnt <= smp_cnt +1; - end if; -end if; -end process; - - -coefsConnectL0: for z in 0 to Cels_count-1 generate - coefsConnectL1: for y in 0 to (CoefCntPerCel/2)-1 generate - RawCoefs(((((z*CoefCntPerCel+y)+1)*Coef_SZ)-1) downto (((z*CoefCntPerCel+y))*Coef_SZ) ) <= CoefsReg_d.numCoefs(z)(y)(Coef_SZ-1 downto 0); - RawCoefs(((((z*CoefCntPerCel+y+(CoefCntPerCel/2))+1)*Coef_SZ)-1) downto ((z*CoefCntPerCel+y+(CoefCntPerCel/2))*Coef_SZ)) <= CoefsReg_d.denCoefs(z)(y)(Coef_SZ-1 downto 0); - end generate; -end generate; - - -process(rst,clk) -begin - if rst = '0' then - r.regin.virgPos <= std_logic_vector(to_unsigned(virgPos,5)); -coefsRstL0: for z in 0 to Cels_count-1 loop - coefsRstL1: for y in 0 to (CoefCntPerCel/2)-1 loop - CoefsReg.numCoefs(z)(y) <= CoefsInitVal(((((z*CoefCntPerCel+y)+1)*Coef_SZ)-1) downto (((z*CoefCntPerCel+y))*Coef_SZ) ); - CoefsReg.denCoefs(z)(y) <= CoefsInitVal(((((z*CoefCntPerCel+y+(CoefCntPerCel/2))+1)*Coef_SZ)-1) downto ((z*CoefCntPerCel+y+(CoefCntPerCel/2))*Coef_SZ)); - end loop; -end loop; - elsif clk'event and clk = '1' then - CoefsReg_d <= CoefsReg; - ---APB Write OP - if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then - if apbi.paddr(7 downto 2) = "000000" then - r.regin.config(0) <= apbi.pwdata(0); - elsif apbi.paddr(7 downto 2) = "000001" then - r.regin.virgPos <= apbi.pwdata(4 downto 0); - else - for i in 0 to Cels_count-1 loop - for j in 0 to (CoefCntPerCel/2) - 1 loop - if apbi.paddr(9 downto 2) = std_logic_vector(TO_UNSIGNED((2+ (i*(CoefCntPerCel/2))+j),8)) then - CoefsReg.numCoefs(i)(j) <= apbi.pwdata(Coef_SZ-1 downto 0); - CoefsReg.denCoefs(i)(j) <= apbi.pwdata((Coef_SZ+15) downto 16); - end if; - end loop; - end loop; - end if; - end if; - ---APB READ OP - if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then - if apbi.paddr(7 downto 2) = "000000" then - Rdata(7 downto 0) <= std_logic_vector(TO_UNSIGNED(ChanelsCount,8)); - Rdata(15 downto 8) <= std_logic_vector(TO_UNSIGNED(Sample_SZ,8)); - Rdata(23 downto 16) <= std_logic_vector(TO_UNSIGNED(CoefCntPerCel,8)); - Rdata(31 downto 24) <= std_logic_vector(TO_UNSIGNED(Cels_count,8)); - elsif apbi.paddr(7 downto 2) = "000001" then - Rdata(4 downto 0) <= r.regin.virgPos; - Rdata(15 downto 8) <= std_logic_vector(TO_UNSIGNED(Coef_SZ,8)); - Rdata(7 downto 5) <= (others => '0'); - Rdata(31 downto 16) <= (others => '0'); - else - for i in 0 to Cels_count-1 loop - for j in 0 to (CoefCntPerCel/2) - 1 loop - if apbi.paddr(9 downto 2) = std_logic_vector(TO_UNSIGNED((2+ (i*(CoefCntPerCel/2))+j),8)) then - Rdata(Coef_SZ-1 downto 0) <= CoefsReg_d.numCoefs(i)(j); - Rdata((Coef_SZ+15) downto 16) <= CoefsReg_d.denCoefs(i)(j); - end if; - end loop; - end loop; - end if; - end if; - end if; - apbo.pconfig <= pconfig; -end process; - -apbo.prdata <= Rdata when apbi.penable = '1' ; - --- pragma translate_off - bootmsg : report_version - generic map ("apb IIR filter" & tost(pindex) & - ": IIR filter rev " & tost(REVISION) & ", fifo " & tost(fifosize) & - ", irq " & tost(pirq)); --- pragma translate_on - - - - -end ar_APB_IIR_CEL; - +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Alexis Jeandet +-- Mail : alexis.jeandet@lpp.polytechnique.fr +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library grlib; +use grlib.amba.all; +use grlib.stdlib.all; +use grlib.devices.all; +library lpp; +use lpp.iir_filter.all; +use lpp.general_purpose.all; +use lpp.lpp_amba.all; +use lpp.apb_devices_list.all; + +entity APB_IIR_CEL is + generic ( + tech : integer := 0; + pindex : integer := 0; + paddr : integer := 0; + pmask : integer := 16#fff#; + pirq : integer := 0; + abits : integer := 8; + Sample_SZ : integer := 16; + ChanelsCount : integer := 1; + Coef_SZ : integer := 9; + CoefCntPerCel: integer := 6; + Cels_count : integer := 5; + virgPos : integer := 3; + Mem_use : integer := use_RAM + ); + port ( + rst : in std_logic; + clk : in std_logic; + apbi : in apb_slv_in_type; + apbo : out apb_slv_out_type; + sample_clk : in std_logic; + sample_clk_out : out std_logic; + sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0); + sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0); + CoefsInitVal : in std_logic_vector((Cels_count*CoefCntPerCel*Coef_SZ)-1 downto 0) := (others => '1') + ); +end; + + +architecture AR_APB_IIR_CEL of APB_IIR_CEL is + +constant REVISION : integer := 1; + +constant pconfig : apb_config_type := ( + 0 => ahb_device_reg (VENDOR_LPP, LPP_IIR_CEL_FILTER, 0, REVISION, 0), + 1 => apb_iobar(paddr, pmask)); + + + +type FILTERreg is record + regin : in_IIR_CEL_reg; + regout : out_IIR_CEL_reg; +end record; + +signal Rdata : std_logic_vector(31 downto 0); +signal r : FILTERreg; +signal filter_reset : std_logic:='0'; +signal smp_cnt : integer :=0; +signal sample_clk_out_R : std_logic; +signal RawCoefs : std_logic_vector(((Coef_SZ*CoefCntPerCel*Cels_count)-1) downto 0); + +type CoefCelT is array(0 to (CoefCntPerCel/2)-1) of std_logic_vector(Coef_SZ-1 downto 0); +type CoefTblT is array(0 to Cels_count-1) of CoefCelT; + +type CoefsRegT is record + numCoefs : CoefTblT; + denCoefs : CoefTblT; +end record; + +signal CoefsReg : CoefsRegT; +signal CoefsReg_d : CoefsRegT; + + +begin + +filter_reset <= rst and r.regin.config(0); +sample_clk_out <= sample_clk_out_R; +-- +filter : IIR_CEL_FILTER +generic map(tech,Sample_SZ,ChanelsCount,Coef_SZ,CoefCntPerCel,Cels_count,Mem_use) +port map( + reset => filter_reset, + clk => clk, + sample_clk => sample_clk, + regs_in => r.regin, + regs_out => r.regout, + sample_in => sample_in, + sample_out => sample_out, + coefs => RawCoefs + ); + +process(rst,sample_clk) +begin +if rst = '0' then + smp_cnt <= 0; + sample_clk_out_R <= '0'; +elsif sample_clk'event and sample_clk = '1' then + if smp_cnt = 1 then + smp_cnt <= 0; + sample_clk_out_R <= not sample_clk_out_R; + else + smp_cnt <= smp_cnt +1; + end if; +end if; +end process; + + +coefsConnectL0: for z in 0 to Cels_count-1 generate + coefsConnectL1: for y in 0 to (CoefCntPerCel/2)-1 generate + RawCoefs(((((z*CoefCntPerCel+y)+1)*Coef_SZ)-1) downto (((z*CoefCntPerCel+y))*Coef_SZ) ) <= CoefsReg_d.numCoefs(z)(y)(Coef_SZ-1 downto 0); + RawCoefs(((((z*CoefCntPerCel+y+(CoefCntPerCel/2))+1)*Coef_SZ)-1) downto ((z*CoefCntPerCel+y+(CoefCntPerCel/2))*Coef_SZ)) <= CoefsReg_d.denCoefs(z)(y)(Coef_SZ-1 downto 0); + end generate; +end generate; + + +process(rst,clk) +begin + if rst = '0' then + r.regin.virgPos <= std_logic_vector(to_unsigned(virgPos,5)); +coefsRstL0: for z in 0 to Cels_count-1 loop + coefsRstL1: for y in 0 to (CoefCntPerCel/2)-1 loop + CoefsReg.numCoefs(z)(y) <= CoefsInitVal(((((z*CoefCntPerCel+y)+1)*Coef_SZ)-1) downto (((z*CoefCntPerCel+y))*Coef_SZ) ); + CoefsReg.denCoefs(z)(y) <= CoefsInitVal(((((z*CoefCntPerCel+y+(CoefCntPerCel/2))+1)*Coef_SZ)-1) downto ((z*CoefCntPerCel+y+(CoefCntPerCel/2))*Coef_SZ)); + end loop; +end loop; + elsif clk'event and clk = '1' then + CoefsReg_d <= CoefsReg; + +--APB Write OP + if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then + if apbi.paddr(7 downto 2) = "000000" then + r.regin.config(0) <= apbi.pwdata(0); + elsif apbi.paddr(7 downto 2) = "000001" then + r.regin.virgPos <= apbi.pwdata(4 downto 0); + else + for i in 0 to Cels_count-1 loop + for j in 0 to (CoefCntPerCel/2) - 1 loop + if apbi.paddr(9 downto 2) = std_logic_vector(TO_UNSIGNED((2+ (i*(CoefCntPerCel/2))+j),8)) then + CoefsReg.numCoefs(i)(j) <= apbi.pwdata(Coef_SZ-1 downto 0); + CoefsReg.denCoefs(i)(j) <= apbi.pwdata((Coef_SZ+15) downto 16); + end if; + end loop; + end loop; + end if; + end if; + +--APB READ OP + if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then + if apbi.paddr(7 downto 2) = "000000" then + Rdata(7 downto 0) <= std_logic_vector(TO_UNSIGNED(ChanelsCount,8)); + Rdata(15 downto 8) <= std_logic_vector(TO_UNSIGNED(Sample_SZ,8)); + Rdata(23 downto 16) <= std_logic_vector(TO_UNSIGNED(CoefCntPerCel,8)); + Rdata(31 downto 24) <= std_logic_vector(TO_UNSIGNED(Cels_count,8)); + elsif apbi.paddr(7 downto 2) = "000001" then + Rdata(4 downto 0) <= r.regin.virgPos; + Rdata(15 downto 8) <= std_logic_vector(TO_UNSIGNED(Coef_SZ,8)); + Rdata(7 downto 5) <= (others => '0'); + Rdata(31 downto 16) <= (others => '0'); + else + for i in 0 to Cels_count-1 loop + for j in 0 to (CoefCntPerCel/2) - 1 loop + if apbi.paddr(9 downto 2) = std_logic_vector(TO_UNSIGNED((2+ (i*(CoefCntPerCel/2))+j),8)) then + Rdata(Coef_SZ-1 downto 0) <= CoefsReg_d.numCoefs(i)(j); + Rdata((Coef_SZ+15) downto 16) <= CoefsReg_d.denCoefs(i)(j); + end if; + end loop; + end loop; + end if; + end if; + end if; + apbo.pconfig <= pconfig; +end process; + +apbo.prdata <= Rdata when apbi.penable = '1' ; + +-- pragma translate_off + bootmsg : report_version + generic map ("apb IIR filter" & tost(pindex) & + ": IIR filter rev " & tost(REVISION)& + --", fifo " & tost(fifosize) & + ", irq " & tost(pirq)); +-- pragma translate_on + + + + +end ar_APB_IIR_CEL; + diff --git a/lib/lpp/dsp/iir_filter/FILTER.vhd b/lib/lpp/dsp/iir_filter/FILTER.vhd --- a/lib/lpp/dsp/iir_filter/FILTER.vhd +++ b/lib/lpp/dsp/iir_filter/FILTER.vhd @@ -63,7 +63,7 @@ begin --============================================================== --=========================A L U================================ --============================================================== -ALU1 : entity ALU +ALU1 : ALU generic map( Arith_en => 1, Logic_en => 0, diff --git a/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd b/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd --- a/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd +++ b/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd @@ -196,7 +196,8 @@ BEGIN GENERIC MAP ( Arith_en => 1, Input_SZ_1 => Sample_SZ, - Input_SZ_2 => Coef_SZ) + Input_SZ_2 => Coef_SZ, + COMP_EN => 1) PORT MAP ( clk => clk, reset => rstn, diff --git a/lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd b/lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd --- a/lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd +++ b/lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd @@ -72,7 +72,7 @@ BEGIN memCEL : IF Mem_use = use_CEL GENERATE WEN <= NOT ram_write; REN <= NOT ram_read; - RAMblk : RAM_CEL + RAMblk : RAM_CEL_N GENERIC MAP(Input_SZ_1) PORT MAP( WD => WD, diff --git a/lib/lpp/dsp/iir_filter/iir_filter.vhd b/lib/lpp/dsp/iir_filter/iir_filter.vhd --- a/lib/lpp/dsp/iir_filter/iir_filter.vhd +++ b/lib/lpp/dsp/iir_filter/iir_filter.vhd @@ -216,6 +216,18 @@ PACKAGE iir_filter IS RWCLK, RESET : IN STD_LOGIC); END COMPONENT; + COMPONENT RAM_CEL_N + GENERIC ( + size : INTEGER); + PORT ( + WD : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0); + RD : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0); + WEN, REN : IN STD_LOGIC; + WADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + RADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + RWCLK, RESET : IN STD_LOGIC); + END COMPONENT; + COMPONENT IIR_CEL_FILTER IS GENERIC( tech : INTEGER := 0; diff --git a/lib/lpp/dsp/lpp_fft/FFT.vhd b/lib/lpp/dsp/lpp_fft/FFT.vhd --- a/lib/lpp/dsp/lpp_fft/FFT.vhd +++ b/lib/lpp/dsp/lpp_fft/FFT.vhd @@ -22,9 +22,10 @@ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -library lpp; +use work.fft_components.all; use lpp.lpp_fft.all; -use work.fft_components.all; + +-- Update possible lecture (ren) de fifo en continu, pendant un Load, au lieu d'une lecture "cr�neau" entity FFT is generic( @@ -36,6 +37,7 @@ entity FFT is FifoIN_Empty : in std_logic_vector(4 downto 0); FifoIN_Data : in std_logic_vector(79 downto 0); FifoOUT_Full : in std_logic_vector(4 downto 0); + Load : out std_logic; Read : out std_logic_vector(4 downto 0); Write : out std_logic_vector(4 downto 0); ReUse : out std_logic_vector(4 downto 0); @@ -62,6 +64,7 @@ signal Link_Read : std_logic; begin Start <= '0'; +Load <= FFT_Load; DRIVE : Driver_FFT generic map(Data_sz,NbData) diff --git a/lib/lpp/dsp/lpp_fft/lpp_fft.vhd b/lib/lpp/dsp/lpp_fft/lpp_fft.vhd --- a/lib/lpp/dsp/lpp_fft/lpp_fft.vhd +++ b/lib/lpp/dsp/lpp_fft/lpp_fft.vhd @@ -84,6 +84,7 @@ component FFT is FifoIN_Empty : in std_logic_vector(4 downto 0); FifoIN_Data : in std_logic_vector(79 downto 0); FifoOUT_Full : in std_logic_vector(4 downto 0); + Load : out std_logic; Read : out std_logic_vector(4 downto 0); Write : out std_logic_vector(4 downto 0); ReUse : out std_logic_vector(4 downto 0); diff --git a/lib/lpp/general_purpose/ALU.vhd b/lib/lpp/general_purpose/ALU.vhd --- a/lib/lpp/general_purpose/ALU.vhd +++ b/lib/lpp/general_purpose/ALU.vhd @@ -32,7 +32,9 @@ generic( Arith_en : integer := 1; Logic_en : integer := 1; Input_SZ_1 : integer := 16; - Input_SZ_2 : integer := 16); + Input_SZ_2 : integer := 16; + COMP_EN : INTEGER := 0 -- 1 => No Comp + ); port( clk : in std_logic; --! Horloge du composant reset : in std_logic; --! Reset general du composant @@ -56,8 +58,8 @@ begin arith : if Arith_en = 1 generate MACinst : MAC -generic map(Input_SZ_1,Input_SZ_2) +generic map(Input_SZ_1,Input_SZ_2,COMP_EN) port map(clk,reset,ctrl(2),ctrl(1 downto 0),comp,OP1,OP2,RES); end generate; -end architecture; \ No newline at end of file +end architecture; diff --git a/lib/lpp/general_purpose/Adder.vhd b/lib/lpp/general_purpose/Adder.vhd --- a/lib/lpp/general_purpose/Adder.vhd +++ b/lib/lpp/general_purpose/Adder.vhd @@ -22,10 +22,6 @@ LIBRARY IEEE; USE IEEE.numeric_std.ALL; USE IEEE.std_logic_1164.ALL; -LIBRARY lpp; -USE lpp.general_purpose.ALL; - - ENTITY Adder IS GENERIC( diff --git a/lib/lpp/general_purpose/MAC.vhd b/lib/lpp/general_purpose/MAC.vhd --- a/lib/lpp/general_purpose/MAC.vhd +++ b/lib/lpp/general_purpose/MAC.vhd @@ -32,7 +32,8 @@ USE lpp.general_purpose.ALL; ENTITY MAC IS GENERIC( Input_SZ_A : INTEGER := 8; - Input_SZ_B : INTEGER := 8 + Input_SZ_B : INTEGER := 8; + COMP_EN : INTEGER := 0 -- 1 => No Comp ); PORT( @@ -52,35 +53,35 @@ END MAC; ARCHITECTURE ar_MAC OF MAC IS -signal add,mult : std_logic; -signal MULTout : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); + SIGNAL add, mult : STD_LOGIC; + SIGNAL MULTout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); -signal ADDERinA : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); -signal ADDERinB : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); -signal ADDERout : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); + SIGNAL ADDERinA : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); + SIGNAL ADDERinB : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); + SIGNAL ADDERout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); -signal MACMUXsel : std_logic; -signal OP1_2C_D_Resz : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); -signal OP2_2C_D_Resz : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); + SIGNAL MACMUXsel : STD_LOGIC; + SIGNAL OP1_2C_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); + SIGNAL OP2_2C_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); -signal OP1_2C : std_logic_vector(Input_SZ_A-1 downto 0); -signal OP2_2C : std_logic_vector(Input_SZ_B-1 downto 0); + SIGNAL OP1_2C : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); + SIGNAL OP2_2C : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); -signal MACMUX2sel : std_logic; + SIGNAL MACMUX2sel : STD_LOGIC; -signal add_D : std_logic; -signal OP1_2C_D : std_logic_vector(Input_SZ_A-1 downto 0); -signal OP2_2C_D : std_logic_vector(Input_SZ_B-1 downto 0); -signal MULTout_D : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); -signal MACMUXsel_D : std_logic; -signal MACMUX2sel_D : std_logic; -signal MACMUX2sel_D_D : std_logic; -signal clr_MAC_D : std_logic; -signal clr_MAC_D_D : std_logic; -signal MAC_MUL_ADD_2C_D : std_logic_vector(1 downto 0); + SIGNAL add_D : STD_LOGIC; + SIGNAL OP1_2C_D : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); + SIGNAL OP2_2C_D : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); + SIGNAL MULTout_D : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); + SIGNAL MACMUXsel_D : STD_LOGIC; + SIGNAL MACMUX2sel_D : STD_LOGIC; + SIGNAL MACMUX2sel_D_D : STD_LOGIC; + SIGNAL clr_MAC_D : STD_LOGIC; + SIGNAL clr_MAC_D_D : STD_LOGIC; + SIGNAL MAC_MUL_ADD_2C_D : STD_LOGIC_VECTOR(1 DOWNTO 0); -SIGNAL load_mult_result : STD_LOGIC; -SIGNAL load_mult_result_D : STD_LOGIC; + SIGNAL load_mult_result : STD_LOGIC; + SIGNAL load_mult_result_D : STD_LOGIC; BEGIN @@ -113,25 +114,25 @@ BEGIN Input_SZ_A => Input_SZ_A, Input_SZ_B => Input_SZ_B ) -port map( - clk => clk, - reset => reset, - mult => mult, - OP1 => OP1_2C, - OP2 => OP2_2C, - RES => MULTout -); + PORT MAP( + clk => clk, + reset => reset, + mult => mult, + OP1 => OP1_2C, + OP2 => OP2_2C, + RES => MULTout + ); --============================================================== PROCESS (clk, reset) BEGIN -- PROCESS IF reset = '0' THEN -- asynchronous reset (active low) load_mult_result_D <= '0'; - ELSIF clk'event AND clk = '1' THEN -- rising clock edge + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge load_mult_result_D <= load_mult_result; END IF; END PROCESS; - + --============================================================== --======================A D D E R ============================== --============================================================== @@ -154,32 +155,38 @@ port map( --============================================================== --===================TWO COMPLEMENTERS========================== --============================================================== -TWO_COMPLEMENTER1 : TwoComplementer -generic map( - Input_SZ => Input_SZ_A -) -port map( - clk => clk, - reset => reset, - clr => clr_MAC, - TwoComp => Comp_2C(0), - OP => OP1, - RES => OP1_2C -); + gen_comp : IF COMP_EN = 0 GENERATE + TWO_COMPLEMENTER1 : TwoComplementer + GENERIC MAP( + Input_SZ => Input_SZ_A + ) + PORT MAP( + clk => clk, + reset => reset, + clr => clr_MAC, + TwoComp => Comp_2C(0), + OP => OP1, + RES => OP1_2C + ); - -TWO_COMPLEMENTER2 : TwoComplementer -generic map( - Input_SZ => Input_SZ_B -) -port map( - clk => clk, - reset => reset, - clr => clr_MAC, - TwoComp => Comp_2C(1), - OP => OP2, - RES => OP2_2C -); + TWO_COMPLEMENTER2 : TwoComplementer + GENERIC MAP( + Input_SZ => Input_SZ_B + ) + PORT MAP( + clk => clk, + reset => reset, + clr => clr_MAC, + TwoComp => Comp_2C(1), + OP => OP2, + RES => OP2_2C + ); + END GENERATE gen_comp; + + no_gen_comp : IF COMP_EN = 1 GENERATE + OP2_2C <= OP2; + OP1_2C <= OP1; + END GENERATE no_gen_comp; --============================================================== clr_MACREG1 : MAC_REG @@ -200,24 +207,24 @@ port map( Q(0) => add_D ); -OP1REG : MAC_REG -generic map(size => Input_SZ_A) -port map( - reset => reset, - clk => clk, - D => OP1_2C, - Q => OP1_2C_D -); + OP1REG : MAC_REG + GENERIC MAP(size => Input_SZ_A) + PORT MAP( + reset => reset, + clk => clk, + D => OP1_2C, + Q => OP1_2C_D + ); -OP2REG : MAC_REG -generic map(size => Input_SZ_B) -port map( - reset => reset, - clk => clk, - D => OP2_2C, - Q => OP2_2C_D -); + OP2REG : MAC_REG + GENERIC MAP(size => Input_SZ_B) + PORT MAP( + reset => reset, + clk => clk, + D => OP2_2C, + Q => OP2_2C_D + ); MULToutREG : MAC_REG GENERIC MAP(size => Input_SZ_A+Input_SZ_B) diff --git a/lib/lpp/general_purpose/MAC_CONTROLER.vhd b/lib/lpp/general_purpose/MAC_CONTROLER.vhd --- a/lib/lpp/general_purpose/MAC_CONTROLER.vhd +++ b/lib/lpp/general_purpose/MAC_CONTROLER.vhd @@ -22,9 +22,6 @@ library IEEE; use IEEE.numeric_std.all; use IEEE.std_logic_1164.all; -library lpp; -use lpp.general_purpose.all; - --IDLE =00 MAC =01 MULT =10 ADD =11 diff --git a/lib/lpp/general_purpose/MAC_MUX.vhd b/lib/lpp/general_purpose/MAC_MUX.vhd --- a/lib/lpp/general_purpose/MAC_MUX.vhd +++ b/lib/lpp/general_purpose/MAC_MUX.vhd @@ -22,10 +22,6 @@ library IEEE; use IEEE.numeric_std.all; use IEEE.std_logic_1164.all; -library lpp; -use lpp.general_purpose.all; - - entity MAC_MUX is generic( diff --git a/lib/lpp/general_purpose/MAC_MUX2.vhd b/lib/lpp/general_purpose/MAC_MUX2.vhd --- a/lib/lpp/general_purpose/MAC_MUX2.vhd +++ b/lib/lpp/general_purpose/MAC_MUX2.vhd @@ -22,9 +22,6 @@ library IEEE; use IEEE.numeric_std.all; use IEEE.std_logic_1164.all; -library lpp; -use lpp.general_purpose.all; - entity MAC_MUX2 is diff --git a/lib/lpp/general_purpose/MAC_REG.vhd b/lib/lpp/general_purpose/MAC_REG.vhd --- a/lib/lpp/general_purpose/MAC_REG.vhd +++ b/lib/lpp/general_purpose/MAC_REG.vhd @@ -22,10 +22,6 @@ library IEEE; use IEEE.numeric_std.all; use IEEE.std_logic_1164.all; -library lpp; -use lpp.general_purpose.all; - - entity MAC_REG is generic(size : integer := 16); diff --git a/lib/lpp/general_purpose/Multiplier.vhd b/lib/lpp/general_purpose/Multiplier.vhd --- a/lib/lpp/general_purpose/Multiplier.vhd +++ b/lib/lpp/general_purpose/Multiplier.vhd @@ -23,11 +23,6 @@ library IEEE; use IEEE.numeric_std.all; use IEEE.std_logic_1164.all; -library lpp; -use lpp.general_purpose.all; - - - entity Multiplier is generic( Input_SZ_A : integer := 16; diff --git a/lib/lpp/general_purpose/general_purpose.vhd b/lib/lpp/general_purpose/general_purpose.vhd --- a/lib/lpp/general_purpose/general_purpose.vhd +++ b/lib/lpp/general_purpose/general_purpose.vhd @@ -83,7 +83,8 @@ PACKAGE general_purpose IS Arith_en : INTEGER := 1; Logic_en : INTEGER := 1; Input_SZ_1 : INTEGER := 16; - Input_SZ_2 : INTEGER := 9 + Input_SZ_2 : INTEGER := 9; + COMP_EN : INTEGER := 0 -- 1 => No Comp ); PORT( @@ -110,8 +111,8 @@ Constant ctrl_CLRMAC : std_logic_vector( COMPONENT MAC IS GENERIC( Input_SZ_A : INTEGER := 8; - Input_SZ_B : INTEGER := 8 - + Input_SZ_B : INTEGER := 8; + COMP_EN : INTEGER := 0 -- 1 => No Comp ); PORT( clk : IN STD_LOGIC; diff --git a/lib/lpp/general_purpose/vhdlsyn.txt b/lib/lpp/general_purpose/vhdlsyn.txt --- a/lib/lpp/general_purpose/vhdlsyn.txt +++ b/lib/lpp/general_purpose/vhdlsyn.txt @@ -15,3 +15,4 @@ REG.vhd SYNC_FF.vhd Shifter.vhd general_purpose.vhd +TwoComplementer.vhd diff --git a/lib/lpp/leon3mp.vhd b/lib/lpp/leon3mp.vhd --- a/lib/lpp/leon3mp.vhd +++ b/lib/lpp/leon3mp.vhd @@ -98,14 +98,14 @@ entity leon3mp is UART_RXD : in std_logic; UART_TXD : out std_logic; -- ACQ - Clk_49Mhz : IN STD_LOGIC; CNV_CH1 : OUT STD_LOGIC; SCK_CH1 : OUT STD_LOGIC; SDO_CH1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + Bias_Fails : out std_logic; -- ADC -- ADC_in : in AD7688_in(4 downto 0); -- ADC_out : out AD7688_out; --- Bias_Fails : out std_logic; + -- CNA -- DAC_SYNC : out std_logic; -- DAC_SCLK : out std_logic; @@ -177,25 +177,17 @@ signal dsuo : dsu_out_type; --- AJOUT TEST ------------------------Signaux---------------------- --------------------------------------------------------------------- -- FIFOs -signal FifoF0a_Full : std_logic_vector(4 downto 0); -signal FifoF0a_Empty : std_logic_vector(4 downto 0); -signal FifoF0a_Data : std_logic_vector(79 downto 0); -signal FifoF0b_Full : std_logic_vector(4 downto 0); -signal FifoF0b_Empty : std_logic_vector(4 downto 0); -signal FifoF0b_Data : std_logic_vector(79 downto 0); -signal FifoF1_Full : std_logic_vector(4 downto 0); +signal FifoF0_Empty : std_logic_vector(4 downto 0); +signal FifoF0_Data : std_logic_vector(79 downto 0); signal FifoF1_Empty : std_logic_vector(4 downto 0); signal FifoF1_Data : std_logic_vector(79 downto 0); -signal FifoF3_Full : std_logic_vector(4 downto 0); signal FifoF3_Empty : std_logic_vector(4 downto 0); signal FifoF3_Data : std_logic_vector(79 downto 0); signal FifoINT_Full : std_logic_vector(4 downto 0); signal FifoINT_Data : std_logic_vector(79 downto 0); ---signal FifoOUT_FullV : std_logic; signal FifoOUT_Full : std_logic_vector(1 downto 0); ---signal Matrix_WriteV : std_logic_vector(0 downto 0); -- MATRICE SPECTRALE signal SM_FlagError : std_logic; @@ -207,19 +199,23 @@ signal SM_Data : std_logic_vector(6 signal Dma_acq : std_logic; -- FFT +signal FFT_Load : std_logic; signal FFT_Read : std_logic_vector(4 downto 0); signal FFT_Write : std_logic_vector(4 downto 0); signal FFT_ReUse : std_logic_vector(4 downto 0); signal FFT_Data : std_logic_vector(79 downto 0); -- DEMUX -signal DEMU_Read : std_logic_vector(19 downto 0); +signal DEMU_Read : std_logic_vector(14 downto 0); signal DEMU_Empty : std_logic_vector(4 downto 0); signal DEMU_Data : std_logic_vector(79 downto 0); -- ACQ -signal TopACQ_WenF0a : STD_LOGIC_VECTOR(4 DOWNTO 0); -signal TopACQ_WenF0b : STD_LOGIC_VECTOR(4 DOWNTO 0); + +signal sample_val : STD_LOGIC; +signal sample : Samples(8-1 DOWNTO 0); + +signal TopACQ_WenF0 : STD_LOGIC_VECTOR(4 DOWNTO 0); signal TopACQ_DataF0 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); signal TopACQ_WenF1 : STD_LOGIC_VECTOR(4 DOWNTO 0); signal TopACQ_DataF1 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); @@ -311,7 +307,7 @@ led(1 downto 0) <= gpio(1 downto 0); -- port map (clkm,rstn,SmplClk,ADC_DataReady,Fuller,WG_ReUse,WG_Write); -- --enableADC <= gpio(0); ---Bias_Fails <= '0'; + --WG_DATA <= ADC_SmplOut(4) & ADC_SmplOut(3) & ADC_SmplOut(2) & ADC_SmplOut(1) & ADC_SmplOut(0); -- -- @@ -319,32 +315,68 @@ led(1 downto 0) <= gpio(1 downto 0); -- generic map (pindex => 6, paddr => 6, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) -- port map (clkm,rstn,clkm,clkm,WG_ReUse,(others => '1'),WG_Write,open,Fuller,open,WG_DATA,open,open,apbi,apbo(6)); - TopACQ : lpp_top_acq - port map('1',CNV_CH1,SCK_CH1,SDO_CH1,Clk_49Mhz,rstn,clkm,rstn,TopACQ_WenF0a,TopACQ_WenF0b,TopACQ_DataF0,TopACQ_WenF1,TopACQ_DataF1,open,open,TopACQ_WenF3,TopACQ_DataF3); + DIGITAL_acquisition : ADS7886_drvr + GENERIC MAP ( + ChanelCount => 8, + ncycle_cnv_high => 79, + ncycle_cnv => 500) + PORT MAP ( + cnv_clk => clk50MHz, -- + cnv_rstn => rstn, -- + cnv_run => '1', -- + cnv => CNV_CH1, -- + clk => clkm, -- + rstn => rstn, -- + sck => SCK_CH1, -- + sdo => SDO_CH1, -- + sample => sample, + sample_val => sample_val); +-- +TopACQ_WenF0 <= not sample_val & not sample_val & not sample_val & not sample_val & not sample_val; +TopACQ_DataF0 <= sample(4) & sample(3) & sample(2) & sample(1) & sample(0); +-- +TEST(0) <= TopACQ_WenF0(1); +TEST(1) <= SDO_CH1(1); +-- +-- +-- +--process(clkm,rstn) +--begin +-- if(rstn='0')then +-- TopACQ_WenF0a <= (others => '1'); +-- +-- elsif(clkm'event and clkm='1')then +-- TopACQ_WenF0a <= not sample_val & not sample_val & not sample_val & not sample_val & not sample_val; +-- +-- end if; +--end process; +-- TopACQ : lpp_top_acq +-- port map('1',CNV_CH1,SCK_CH1,SDO_CH1,clk50MHz,rstn,clkm,rstn,TopACQ_WenF0,TopACQ_DataF0,TopACQ_WenF1,TopACQ_DataF1,open,open,TopACQ_WenF3,TopACQ_DataF3); + +Bias_Fails <= '0'; --- FIFO IN ------------------------------------------------------------- - Memf0a : lppFIFOxN - generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '0') - port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF0a,DEMU_Read(4 downto 0),TopACQ_DataF0,FifoF0a_Data,FifoF0a_Full,FifoF0a_Empty); + MemOut : APB_FIFO + generic map (pindex => 9, paddr => 9, FifoCnt => 5, Data_sz => 16, Addr_sz => 9, Enable_ReUse => '0', R => 1, W => 0) + port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),TopACQ_WenF0,FifoF0_Empty,open,open,TopACQ_DataF0,open,open,apbi,apbo(9)); +-- Memf0 : lppFIFOxN +-- generic map(Data_sz => 16, Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0') +-- port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF0,DEMU_Read(4 downto 0),TopACQ_DataF0,FifoF0_Data,open,FifoF0_Empty); - Memf0b : lppFIFOxN - generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '0') - port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF0b,DEMU_Read(9 downto 5),TopACQ_DataF0,FifoF0b_Data,FifoF0b_Full,FifoF0b_Empty); - Memf1 : lppFIFOxN - generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '0') - port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF1,DEMU_Read(14 downto 10),TopACQ_DataF1,FifoF1_Data,FifoF1_Full,FifoF1_Empty); + generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') + port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF1,DEMU_Read(9 downto 5),TopACQ_DataF1,FifoF1_Data,open,FifoF1_Empty); Memf3 : lppFIFOxN - generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '0') - port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF3,DEMU_Read(19 downto 15),TopACQ_DataF3,FifoF3_Data,FifoF3_Full,FifoF3_Empty); + generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') + port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF3,DEMU_Read(14 downto 10),TopACQ_DataF3,FifoF3_Data,open,FifoF3_Empty); --- DEMUX ------------------------------------------------------------- - DEMUX0 : Demultiplex + DEMU0 : DEMUX generic map(Data_sz => 16) - port map(clkm,rstn,FFT_Read,FifoF0a_Empty,FifoF0b_Empty,FifoF1_Empty,FifoF3_Empty,FifoF0a_Data,FifoF0b_Data,FifoF1_Data,FifoF3_Data,DEMU_Read,DEMU_Empty,DEMU_Data); + port map(clkm,rstn,FFT_Read,FFT_Load,FifoF0_Empty,FifoF1_Empty,FifoF3_Empty,FifoF0_Data,FifoF1_Data,FifoF3_Data,DEMU_Read,DEMU_Empty,DEMU_Data); --- FFT ------------------------------------------------------------- @@ -354,18 +386,18 @@ led(1 downto 0) <= gpio(1 downto 0); FFT0 : FFT generic map(Data_sz => 16,NbData => 256) - port map(clkm,rstn,DEMU_Empty,DEMU_Data,FifoINT_Full,FFT_Read,FFT_Write,FFT_ReUse,FFT_Data); + port map(clkm,rstn,DEMU_Empty,DEMU_Data,FifoINT_Full,FFT_Load,FFT_Read,FFT_Write,FFT_ReUse,FFT_Data); ----- LINK MEMORY ------------------------------------------------------- -- MemOut : APB_FIFO -- generic map (pindex => 9, paddr => 9, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 0) --- port map (clkm,rstn,clkm,clkm,Link_ReUse,(others =>'1'),Link_Write,Ept,FifoOUT_Full,open,Link_Data,open,open,apbi,apbo(9)); +-- port map (clkm,rstn,clkm,clkm,FFT_ReUse,(others =>'1'),FFT_Write,open,FifoINT_Full,open,FFT_Data,open,open,apbi,apbo(9)); MemInt : lppFIFOxN generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '1') port map(rstn,clkm,clkm,FFT_ReUse,FFT_Write,SM_Read,FFT_Data,FifoINT_Data,FifoINT_Full,open); - +-- -- MemIn : APB_FIFO -- generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 0, W => 1) -- port map (clkm,rstn,clkm,clkm,(others => '0'),TopSM_Read,(others => '1'),open,FifoINT_Full,FifoINT_Data,(others => '0'),open,open,apbi,apbo(8)); @@ -378,9 +410,9 @@ led(1 downto 0) <= gpio(1 downto 0); Dma_acq <= '1'; - MemOut : APB_FIFO - generic map (pindex => 9, paddr => 9, FifoCnt => 2, Data_sz => 32, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) - port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),SM_Write,open,FifoOUT_Full,open,SM_Data,open,open,apbi,apbo(9)); +-- MemOut : APB_FIFO +-- generic map (pindex => 9, paddr => 9, FifoCnt => 2, Data_sz => 32, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) +-- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),SM_Write,open,FifoOUT_Full,open,SM_Data,open,open,apbi,apbo(9)); ----- FIFO ------------------------------------------------------------- diff --git a/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd b/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd --- a/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd +++ b/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd @@ -17,158 +17,158 @@ -- Additional Comments: -- ---------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; -library grlib; -use grlib.amba.all; -use grlib.stdlib.all; -use grlib.devices.all; -library lpp; -use lpp.apb_devices_list.all; -use lpp.lpp_lfr_time_management.all; +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; +LIBRARY lpp; +USE lpp.apb_devices_list.ALL; +USE lpp.lpp_lfr_time_management.ALL; -entity apb_lfr_time_management is +ENTITY apb_lfr_time_management IS -generic( - pindex : integer := 0; --! APB slave index - paddr : integer := 0; --! ADDR field of the APB BAR - pmask : integer := 16#fff#; --! MASK field of the APB BAR - pirq : integer := 0; --! 2 consecutive IRQ lines are used - masterclk : integer := 25000000; --! master clock in Hz - otherclk : integer := 49152000; --! other clock in Hz - finetimeclk : integer := 65536 --! divided clock used for the fine time counter - ); + GENERIC( + pindex : INTEGER := 0; --! APB slave index + paddr : INTEGER := 0; --! ADDR field of the APB BAR + pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR + pirq : INTEGER := 0; --! 2 consecutive IRQ lines are used + masterclk : INTEGER := 25000000; --! master clock in Hz + otherclk : INTEGER := 49152000; --! other clock in Hz + finetimeclk : INTEGER := 65536 --! divided clock used for the fine time counter + ); -Port ( - clk25MHz : in STD_LOGIC; --! Clock - clk49_152MHz : in STD_LOGIC; --! secondary clock - resetn : in STD_LOGIC; --! Reset - grspw_tick : in STD_LOGIC; --! grspw signal asserted when a valid time-code is received - apbi : in apb_slv_in_type; --! APB slave input signals - apbo : out apb_slv_out_type; --! APB slave output signals - coarse_time : out std_logic_vector(31 downto 0); --! coarse time - fine_time : out std_logic_vector(31 downto 0) --! fine time - ); - -end apb_lfr_time_management; + PORT ( + clk25MHz : IN STD_LOGIC; --! Clock + clk49_152MHz : IN STD_LOGIC; --! secondary clock + resetn : IN STD_LOGIC; --! Reset + grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received + apbi : IN apb_slv_in_type; --! APB slave input signals + apbo : OUT apb_slv_out_type; --! APB slave output signals + coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time + fine_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) --! fine time + ); -architecture Behavioral of apb_lfr_time_management is +END apb_lfr_time_management; -constant REVISION : integer := 1; +ARCHITECTURE Behavioral OF apb_lfr_time_management IS + + CONSTANT REVISION : INTEGER := 1; --! the following types are defined in the grlib amba package --! subtype amba_config_word is std_logic_vector(31 downto 0); --! type apb_config_type is array (0 to NAPBCFG-1) of amba_config_word; -constant pconfig : apb_config_type := ( + CONSTANT pconfig : apb_config_type := ( --! 0 => ahb_device_reg (VENDOR_LPP, LPP_ROTARY, 0, REVISION, 0), - 0 => ahb_device_reg (19, 14, 0, REVISION, pirq), - 1 => apb_iobar(paddr, pmask)); + 0 => ahb_device_reg (19, 14, 0, REVISION, pirq), + 1 => apb_iobar(paddr, pmask)); -type apb_lfr_time_management_Reg is record - ctrl : std_logic_vector(31 downto 0); - coarse_time_load : std_logic_vector(31 downto 0); - coarse_time : std_logic_vector(31 downto 0); - fine_time : std_logic_vector(31 downto 0); - next_commutation : std_logic_vector(31 downto 0); -end record; + TYPE apb_lfr_time_management_Reg IS RECORD + ctrl : STD_LOGIC_VECTOR(31 DOWNTO 0); + coarse_time_load : STD_LOGIC_VECTOR(31 DOWNTO 0); + coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); + fine_time : STD_LOGIC_VECTOR(31 DOWNTO 0); + next_commutation : STD_LOGIC_VECTOR(31 DOWNTO 0); + END RECORD; -signal r : apb_lfr_time_management_Reg; -signal Rdata : std_logic_vector(31 downto 0); -signal force_tick : std_logic; -signal previous_force_tick : std_logic; -signal soft_tick : std_logic; -signal reset_next_commutation : std_logic; + SIGNAL r : apb_lfr_time_management_Reg; + SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL force_tick : STD_LOGIC; + SIGNAL previous_force_tick : STD_LOGIC; + SIGNAL soft_tick : STD_LOGIC; + SIGNAL reset_next_commutation : STD_LOGIC; -begin +BEGIN -lfrtimemanagement0: lfr_time_management -generic map(masterclk => masterclk, timeclk => otherclk, finetimeclk => finetimeclk) -Port map( master_clock => clk25MHz, time_clock => clk49_152MHz, resetn => resetn, - grspw_tick => grspw_tick, soft_tick => soft_tick, - coarse_time_load => r.coarse_time_load, coarse_time => r.coarse_time, fine_time => r.fine_time, - next_commutation => r.next_commutation, reset_next_commutation => reset_next_commutation, - irq1 => apbo.pirq(pirq), irq2 => apbo.pirq(pirq+1) ); + lfrtimemanagement0 : lfr_time_management + GENERIC MAP(masterclk => masterclk, timeclk => otherclk, finetimeclk => finetimeclk) + PORT MAP(master_clock => clk25MHz, time_clock => clk49_152MHz, resetn => resetn, + grspw_tick => grspw_tick, soft_tick => soft_tick, + coarse_time_load => r.coarse_time_load, coarse_time => r.coarse_time, fine_time => r.fine_time, + next_commutation => r.next_commutation, reset_next_commutation => reset_next_commutation, + irq1 => apbo.pirq(pirq), irq2 => apbo.pirq(pirq+1)); -process(resetn,clk25MHz, reset_next_commutation) -begin + PROCESS(resetn, clk25MHz, reset_next_commutation) + BEGIN - if resetn = '0' then - r.coarse_time_load <= x"80000000"; - r.ctrl <= x"00000000"; - r.next_commutation <= x"ffffffff"; - force_tick <= '0'; - previous_force_tick <= '0'; - soft_tick <= '0'; + IF resetn = '0' THEN + r.coarse_time_load <= x"80000000"; + r.ctrl <= x"00000000"; + r.next_commutation <= x"ffffffff"; + force_tick <= '0'; + previous_force_tick <= '0'; + soft_tick <= '0'; - elsif reset_next_commutation = '1' then - r.next_commutation <= x"ffffffff"; + ELSIF reset_next_commutation = '1' THEN + r.next_commutation <= x"ffffffff"; - elsif clk25MHz'event and clk25MHz = '1' then + ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN - previous_force_tick <= force_tick; - force_tick <= r.ctrl(0); - if (previous_force_tick = '0') and (force_tick = '1') then - soft_tick <= '1'; - else - soft_tick <= '0'; - end if; - + previous_force_tick <= force_tick; + force_tick <= r.ctrl(0); + IF (previous_force_tick = '0') AND (force_tick = '1') THEN + soft_tick <= '1'; + ELSE + soft_tick <= '0'; + END IF; + --APB Write OP - if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then - case apbi.paddr(7 downto 2) is - when "000000" => - r.ctrl <= apbi.pwdata(31 downto 0); - when "000001" => - r.coarse_time_load <= apbi.pwdata(31 downto 0); - when "000100" => - r.next_commutation <= apbi.pwdata(31 downto 0); - when others => - r.coarse_time_load <= x"00000000"; - end case; - elsif r.ctrl(0) = '1' then - r.ctrl(0) <= '0'; - end if; + IF (apbi.psel(pindex) AND apbi.penable AND apbi.pwrite) = '1' THEN + CASE apbi.paddr(7 DOWNTO 2) IS + WHEN "000000" => + r.ctrl <= apbi.pwdata(31 DOWNTO 0); + WHEN "000001" => + r.coarse_time_load <= apbi.pwdata(31 DOWNTO 0); + WHEN "000100" => + r.next_commutation <= apbi.pwdata(31 DOWNTO 0); + WHEN OTHERS => + r.coarse_time_load <= x"00000000"; + END CASE; + ELSIF r.ctrl(0) = '1' THEN + r.ctrl(0) <= '0'; + END IF; --APB READ OP - if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then - case apbi.paddr(7 downto 2) is - when "000000" => - Rdata(31 downto 24) <= r.ctrl(31 downto 24); - Rdata(23 downto 16) <= r.ctrl(23 downto 16); - Rdata(15 downto 8) <= r.ctrl(15 downto 8); - Rdata(7 downto 0) <= r.ctrl(7 downto 0); - when "000001" => - Rdata(31 downto 24) <= r.coarse_time_load(31 downto 24); - Rdata(23 downto 16) <= r.coarse_time_load(23 downto 16); - Rdata(15 downto 8) <= r.coarse_time_load(15 downto 8); - Rdata(7 downto 0) <= r.coarse_time_load(7 downto 0); - when "000010" => - Rdata(31 downto 24) <= r.coarse_time(31 downto 24); - Rdata(23 downto 16) <= r.coarse_time(23 downto 16); - Rdata(15 downto 8) <= r.coarse_time(15 downto 8); - Rdata(7 downto 0) <= r.coarse_time(7 downto 0); - when "000011" => - Rdata(31 downto 24) <= r.fine_time(31 downto 24); - Rdata(23 downto 16) <= r.fine_time(23 downto 16); - Rdata(15 downto 8) <= r.fine_time(15 downto 8); - Rdata(7 downto 0) <= r.fine_time(7 downto 0); - when "000100" => - Rdata(31 downto 24) <= r.next_commutation(31 downto 24); - Rdata(23 downto 16) <= r.next_commutation(23 downto 16); - Rdata(15 downto 8) <= r.next_commutation(15 downto 8); - Rdata(7 downto 0) <= r.next_commutation(7 downto 0); - when others => - Rdata(31 downto 0) <= x"00000000"; - end case; - end if; + IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN + CASE apbi.paddr(7 DOWNTO 2) IS + WHEN "000000" => + Rdata(31 DOWNTO 24) <= r.ctrl(31 DOWNTO 24); + Rdata(23 DOWNTO 16) <= r.ctrl(23 DOWNTO 16); + Rdata(15 DOWNTO 8) <= r.ctrl(15 DOWNTO 8); + Rdata(7 DOWNTO 0) <= r.ctrl(7 DOWNTO 0); + WHEN "000001" => + Rdata(31 DOWNTO 24) <= r.coarse_time_load(31 DOWNTO 24); + Rdata(23 DOWNTO 16) <= r.coarse_time_load(23 DOWNTO 16); + Rdata(15 DOWNTO 8) <= r.coarse_time_load(15 DOWNTO 8); + Rdata(7 DOWNTO 0) <= r.coarse_time_load(7 DOWNTO 0); + WHEN "000010" => + Rdata(31 DOWNTO 24) <= r.coarse_time(31 DOWNTO 24); + Rdata(23 DOWNTO 16) <= r.coarse_time(23 DOWNTO 16); + Rdata(15 DOWNTO 8) <= r.coarse_time(15 DOWNTO 8); + Rdata(7 DOWNTO 0) <= r.coarse_time(7 DOWNTO 0); + WHEN "000011" => + Rdata(31 DOWNTO 24) <= r.fine_time(31 DOWNTO 24); + Rdata(23 DOWNTO 16) <= r.fine_time(23 DOWNTO 16); + Rdata(15 DOWNTO 8) <= r.fine_time(15 DOWNTO 8); + Rdata(7 DOWNTO 0) <= r.fine_time(7 DOWNTO 0); + WHEN "000100" => + Rdata(31 DOWNTO 24) <= r.next_commutation(31 DOWNTO 24); + Rdata(23 DOWNTO 16) <= r.next_commutation(23 DOWNTO 16); + Rdata(15 DOWNTO 8) <= r.next_commutation(15 DOWNTO 8); + Rdata(7 DOWNTO 0) <= r.next_commutation(7 DOWNTO 0); + WHEN OTHERS => + Rdata(31 DOWNTO 0) <= x"00000000"; + END CASE; + END IF; - end if; - apbo.pconfig <= pconfig; -end process; + END IF; + apbo.pconfig <= pconfig; + END PROCESS; -apbo.prdata <= Rdata when apbi.penable = '1' ; -coarse_time <= r.coarse_time; -fine_time <= r.fine_time; + apbo.prdata <= Rdata WHEN apbi.penable = '1'; + coarse_time <= r.coarse_time; + fine_time <= r.fine_time; -end Behavioral; \ No newline at end of file +END Behavioral; diff --git a/lib/lpp/lpp_ad_Conv/AD7688_drvr.vhd b/lib/lpp/lpp_ad_Conv/AD7688_drvr.vhd --- a/lib/lpp/lpp_ad_Conv/AD7688_drvr.vhd +++ b/lib/lpp/lpp_ad_Conv/AD7688_drvr.vhd @@ -18,97 +18,180 @@ ------------------------------------------------------------------------------- -- Author : Alexis Jeandet -- Mail : alexis.jeandet@lpp.polytechnique.fr ----------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library lpp; -use lpp.lpp_ad_conv.all; -use lpp.general_purpose.Clk_divider; - ---! \brief AD7688 driver, generates all needed signal to drive this ADC. ---! ---! \author Alexis Jeandet alexis.jeandet@lpp.polytechnique.fr +------------------------------------------------------------------------------- +-- MODIFIED by Jean-christophe PELLION +-- jean-christophe.pellion@lpp.polytechnique.fr +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +LIBRARY lpp; +USE lpp.lpp_ad_conv.ALL; +USE lpp.general_purpose.SYNC_FF; -entity AD7688_drvr is -generic( - ChanelCount :integer; --! Number of ADC you whant to drive - clkkHz :integer --! System clock frequency in kHz usefull to generate some pulses with good width. - ); -Port( - clk : in STD_LOGIC; --! System clock - rstn : in STD_LOGIC; --! System reset - enable : in std_logic; --! Negative enable - smplClk : in STD_LOGIC; --! Sampling clock - DataReady : out std_logic; --! New sample available - smpout : out Samples_out(ChanelCount-1 downto 0); --! Samples - AD_in : in AD7688_in(ChanelCount-1 downto 0); --! Input signals for ADC see lpp.lpp_ad_conv - AD_out : out AD7688_out --! Output signals for ADC see lpp.lpp_ad_conv -); -end AD7688_drvr; - -architecture ar_AD7688_drvr of AD7688_drvr is - -constant convTrigger : integer:= clkkHz*16/10000; --tconv = 1.6µs - -signal i : integer range 0 to convTrigger :=0; -signal clk_int : std_logic; -signal clk_int_inv : std_logic; -signal smplClk_reg : std_logic; -signal cnv_int : std_logic; -signal reset : std_logic; +ENTITY AD7688_drvr IS + GENERIC( + ChanelCount : INTEGER; + ncycle_cnv_high : INTEGER := 79; + ncycle_cnv : INTEGER := 500); + PORT ( + -- CONV -- + cnv_clk : IN STD_LOGIC; + cnv_rstn : IN STD_LOGIC; + cnv_run : IN STD_LOGIC; + cnv : OUT STD_LOGIC; -begin - -clkdiv: if clkkHz>=66000 generate - clkdivider: entity work.Clk_divider - generic map(clkkHz*1000,60000000) - Port map( clk ,reset,clk_int); -end generate; + -- DATA -- + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + sck : OUT STD_LOGIC; + sdo : IN STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0); -clknodiv: if clkkHz<66000 generate -nodiv: clk_int <= clk; -end generate; - -clk_int_inv <= not clk_int; - -AD_out.CNV <= cnv_int; -AD_out.SCK <= clk_int; -reset <= rstn and enable; + sample : OUT Samples(ChanelCount-1 DOWNTO 0); + sample_val : OUT STD_LOGIC + ); +END AD7688_drvr; -sckgen: process(clk,reset) -begin - if reset = '0' then - i <= 0; - cnv_int <= '0'; - smplClk_reg <= '0'; - elsif clk'event and clk = '1' then - if smplClk = '1' and smplClk_reg = '0' then - if i = convTrigger then - smplClk_reg <= '1'; - i <= 0; - cnv_int <= '0'; - else - i <= i+1; - cnv_int <= '1'; - end if; - elsif smplClk = '0' and smplClk_reg = '1' then - smplClk_reg <= '0'; - end if; - end if; -end process; +ARCHITECTURE ar_AD7688_drvr OF AD7688_drvr IS + + COMPONENT SYNC_FF + GENERIC ( + NB_FF_OF_SYNC : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + A : IN STD_LOGIC; + A_sync : OUT STD_LOGIC); + END COMPONENT; + SIGNAL cnv_cycle_counter : INTEGER; + SIGNAL cnv_s : STD_LOGIC; + SIGNAL cnv_sync : STD_LOGIC; + SIGNAL cnv_sync_r : STD_LOGIC; + SIGNAL cnv_done : STD_LOGIC; + SIGNAL sample_bit_counter : INTEGER; + SIGNAL shift_reg : Samples(ChanelCount-1 DOWNTO 0); -spidrvr: entity work.AD7688_spi_if - generic map(ChanelCount) - Port map(clk_int_inv,reset,cnv_int,DataReady,AD_in,smpout); + SIGNAL cnv_run_sync : STD_LOGIC; + +BEGIN + ----------------------------------------------------------------------------- + -- CONV + ----------------------------------------------------------------------------- + PROCESS (cnv_clk, cnv_rstn) + BEGIN -- PROCESS + IF cnv_rstn = '0' THEN -- asynchronous reset (active low) + cnv_cycle_counter <= 0; + cnv_s <= '0'; + ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge + IF cnv_run = '1' THEN + IF cnv_cycle_counter < ncycle_cnv THEN + cnv_cycle_counter <= cnv_cycle_counter +1; + IF cnv_cycle_counter < ncycle_cnv_high THEN + cnv_s <= '1'; + ELSE + cnv_s <= '0'; + END IF; + ELSE + cnv_s <= '1'; + cnv_cycle_counter <= 0; + END IF; + ELSE + cnv_s <= '0'; + cnv_cycle_counter <= 0; + END IF; + END IF; + END PROCESS; + cnv <= cnv_s; + + ----------------------------------------------------------------------------- -end ar_AD7688_drvr; + ----------------------------------------------------------------------------- + -- SYNC CNV + ----------------------------------------------------------------------------- + + SYNC_FF_cnv : SYNC_FF + GENERIC MAP ( + NB_FF_OF_SYNC => 2) + PORT MAP ( + clk => clk, + rstn => rstn, + A => cnv_s, + A_sync => cnv_sync); + PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + cnv_sync_r <= '0'; + cnv_done <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN + cnv_sync_r <= cnv_sync; + cnv_done <= (NOT cnv_sync) AND cnv_sync_r; + END IF; + END PROCESS; + + ----------------------------------------------------------------------------- + + SYNC_FF_run : SYNC_FF + GENERIC MAP ( + NB_FF_OF_SYNC => 2) + PORT MAP ( + clk => clk, + rstn => rstn, + A => cnv_run, + A_sync => cnv_run_sync); - + + ----------------------------------------------------------------------------- + -- DATA + ----------------------------------------------------------------------------- + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN + FOR l IN 0 TO ChanelCount-1 LOOP + shift_reg(l) <= (OTHERS => '0'); + END LOOP; + sample_bit_counter <= 0; + sample_val <= '0'; + SCK <= '1'; + ELSIF clk'EVENT AND clk = '1' THEN + + IF cnv_run_sync = '0' THEN + sample_bit_counter <= 0; + ELSIF cnv_done = '1' THEN + sample_bit_counter <= 1; + ELSIF sample_bit_counter > 0 AND sample_bit_counter < 32 THEN + sample_bit_counter <= sample_bit_counter + 1; + END IF; + IF (sample_bit_counter MOD 2) = 1 THEN + FOR l IN 0 TO ChanelCount-1 LOOP + --shift_reg(l)(15) <= sdo(l); + --shift_reg(l)(14 DOWNTO 0) <= shift_reg(l)(15 DOWNTO 1); + shift_reg(l)(0) <= sdo(l); + shift_reg(l)(15 DOWNTO 1) <= shift_reg(l)(14 DOWNTO 0); + END LOOP; + SCK <= '0'; + ELSE + SCK <= '1'; + END IF; + IF sample_bit_counter = 31 THEN + sample_val <= '1'; + FOR l IN 0 TO ChanelCount-1 LOOP + --sample(l)(15) <= sdo(l); + --sample(l)(14 DOWNTO 0) <= shift_reg(l)(15 DOWNTO 1); + sample(l)(0) <= sdo(l); + sample(l)(15 DOWNTO 1) <= shift_reg(l)(14 DOWNTO 0); + END LOOP; + ELSE + sample_val <= '0'; + END IF; + END IF; + END PROCESS; + +END ar_AD7688_drvr; + diff --git a/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd b/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd --- a/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd +++ b/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd @@ -50,7 +50,7 @@ PACKAGE lpp_ad_conv IS TYPE Samples IS ARRAY(NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0); - COMPONENT ADS7886_drvr + COMPONENT AD7688_drvr GENERIC ( ChanelCount : INTEGER; ncycle_cnv_high : INTEGER := 79; @@ -162,26 +162,26 @@ Type ADS127X_config is MODE : ADS127X_MODE_Type; end record; -COMPONENT ADS1274_DRIVER is -generic(modeCfg : ADS127X_MODE_Type := ADS127X_MODE_low_power; formatCfg : ADS127X_FORMAT_Type := ADS127X_FSYNC_FORMAT); -port( - Clk : in std_logic; - reset : in std_logic; - SpiClk : out std_logic; - DIN : in std_logic_vector(3 downto 0); - Ready : in std_logic; - Format : out std_logic_vector(2 downto 0); - Mode : out std_logic_vector(1 downto 0); - ClkDiv : out std_logic; - PWDOWN : out std_logic_vector(3 downto 0); - SmplClk : in std_logic; - OUT0 : out std_logic_vector(23 downto 0); - OUT1 : out std_logic_vector(23 downto 0); - OUT2 : out std_logic_vector(23 downto 0); - OUT3 : out std_logic_vector(23 downto 0); - FSynch : out std_logic; - test : out std_logic -); +COMPONENT ADS1274_DRIVER is +generic(modeCfg : ADS127X_MODE_Type := ADS127X_MODE_low_power; formatCfg : ADS127X_FORMAT_Type := ADS127X_FSYNC_FORMAT); +port( + Clk : in std_logic; + reset : in std_logic; + SpiClk : out std_logic; + DIN : in std_logic_vector(3 downto 0); + Ready : in std_logic; + Format : out std_logic_vector(2 downto 0); + Mode : out std_logic_vector(1 downto 0); + ClkDiv : out std_logic; + PWDOWN : out std_logic_vector(3 downto 0); + SmplClk : in std_logic; + OUT0 : out std_logic_vector(23 downto 0); + OUT1 : out std_logic_vector(23 downto 0); + OUT2 : out std_logic_vector(23 downto 0); + OUT3 : out std_logic_vector(23 downto 0); + FSynch : out std_logic; + test : out std_logic +); end COMPONENT; diff --git a/lib/lpp/lpp_amba/apb_devices_list.vhd b/lib/lpp/lpp_amba/apb_devices_list.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_amba/apb_devices_list.vhd @@ -0,0 +1,41 @@ + +--================================================================================= +--THIS FILE IS GENERATED BY A SCRIPT, DON'T TRY TO EDIT +-- +--TAKE A LOOK AT VHD_LIB/APB_DEVICES FOLDER TO ADD A DEVICE ID OR VENDOR ID +--================================================================================= + + +library ieee; +use ieee.std_logic_1164.all; +library grlib; +use grlib.amba.all; +use std.textio.all; + + +package apb_devices_list is + + +constant VENDOR_LPP : amba_vendor_type := 16#19#; + +constant ROCKET_TM : amba_device_type := 16#1#; +constant otherCore : amba_device_type := 16#2#; +constant LPP_SIMPLE_DIODE : amba_device_type := 16#3#; +constant LPP_MULTI_DIODE : amba_device_type := 16#4#; +constant LPP_LCD_CTRLR : amba_device_type := 16#5#; +constant LPP_UART : amba_device_type := 16#6#; +constant LPP_CNA : amba_device_type := 16#7#; +constant LPP_APB_ADC : amba_device_type := 16#8#; +constant LPP_CHENILLARD : amba_device_type := 16#9#; +constant LPP_IIR_CEL_FILTER : amba_device_type := 16#10#; +constant LPP_FIFO_PID : amba_device_type := 16#11#; +constant LPP_FFT : amba_device_type := 16#12#; +constant LPP_MATRIX : amba_device_type := 16#13#; +constant LPP_BALISE : amba_device_type := 16#14#; +constant LPP_USB : amba_device_type := 16#15#; +constant LPP_DELAY : amba_device_type := 16#16#; +constant LPP_DMA_TYPE : amba_device_type := 16#17#; +constant LPP_BOOTLOADER_TYPE : amba_device_type := 16#18#; + + +end; diff --git a/lib/lpp/lpp_demux/DEMUX.vhd b/lib/lpp/lpp_demux/DEMUX.vhd --- a/lib/lpp/lpp_demux/DEMUX.vhd +++ b/lib/lpp/lpp_demux/DEMUX.vhd @@ -31,19 +31,17 @@ port( rstn : in std_logic; Read : in std_logic_vector(4 downto 0); - DataCpt : in std_logic_vector(3 downto 0); -- f2 f1 f0b f0a + Load : in std_logic; - EmptyF0a : in std_logic_vector(4 downto 0); - EmptyF0b : in std_logic_vector(4 downto 0); + EmptyF0 : in std_logic_vector(4 downto 0); EmptyF1 : in std_logic_vector(4 downto 0); EmptyF2 : in std_logic_vector(4 downto 0); - DataF0a : in std_logic_vector((5*Data_sz)-1 downto 0); - DataF0b : in std_logic_vector((5*Data_sz)-1 downto 0); + DataF0 : in std_logic_vector((5*Data_sz)-1 downto 0); DataF1 : in std_logic_vector((5*Data_sz)-1 downto 0); DataF2 : in std_logic_vector((5*Data_sz)-1 downto 0); - Read_DEMUX : out std_logic_vector(19 downto 0); + Read_DEMUX : out std_logic_vector(14 downto 0); Empty : out std_logic_vector(4 downto 0); Data : out std_logic_vector((5*Data_sz)-1 downto 0) ); @@ -55,9 +53,8 @@ architecture ar_DEMUX of DEMUX is type etat is (eX,e0,e1,e2,e3); signal ect : etat; -signal pong : std_logic; -signal DataCpt_reg : std_logic_vector(3 downto 0); +signal load_reg : std_logic; constant Dummy_Read : std_logic_vector(4 downto 0) := (others => '1'); signal Countf0 : integer; @@ -68,61 +65,40 @@ begin begin if(rstn='0')then ect <= e0; - pong <= '0'; - Countf0 <= 1; + load_reg <= '0'; + Countf0 <= 5; Countf1 <= 0; elsif(clk'event and clk='1')then - DataCpt_reg <= DataCpt; + load_reg <= Load; case ect is when e0 => - if(DataCpt_reg(0) = '1' and DataCpt(0) = '0')then - pong <= not pong; - if(Countf0 = 5)then + if(load_reg = '1' and Load = '0')then + if(Countf0 = 24)then Countf0 <= 0; - ect <= e2; + ect <= e1; else Countf0 <= Countf0 + 1; - ect <= e1; + ect <= e0; end if; end if; when e1 => - if(DataCpt_reg(1) = '1' and DataCpt(1) = '0')then - pong <= not pong; - if(Countf0 = 5)then - Countf0 <= 0; + if(load_reg = '1' and Load = '0')then + if(Countf1 = 74)then + Countf1 <= 0; ect <= e2; else - Countf0 <= Countf0 + 1; + Countf1 <= Countf1 + 1; ect <= e0; end if; end if; when e2 => - if(DataCpt_reg(2) = '1' and DataCpt(2) = '0')then - if(Countf1 = 15)then - Countf1 <= 0; - ect <= e3; - else - Countf1 <= Countf1 + 1; - if(pong = '0')then - ect <= e0; - else - ect <= e1; - end if; - end if; - end if; - - when e3 => - if(DataCpt_reg(3) = '1' and DataCpt(3) = '0')then - if(pong = '0')then - ect <= e0; - else - ect <= e1; - end if; + if(load_reg = '1' and Load = '0')then + ect <= e0; end if; when others => @@ -133,29 +109,23 @@ begin end process; with ect select - Empty <= EmptyF0a when e0, - EmptyF0b when e1, - EmptyF1 when e2, - EmptyF2 when e3, + Empty <= EmptyF0 when e0, + EmptyF1 when e1, + EmptyF2 when e2, (others => '1') when others; with ect select - Data <= DataF0a when e0, - DataF0b when e1, - DataF1 when e2, - DataF2 when e3, + Data <= DataF0 when e0, + DataF1 when e1, + DataF2 when e2, (others => '0') when others; with ect select - Read_DEMUX <= Dummy_Read & Dummy_Read & Dummy_Read & Read when e0, - Dummy_Read & Dummy_Read & Read & Dummy_Read when e1, - Dummy_Read & Read & Dummy_Read & Dummy_Read when e2, - Read & Dummy_Read & Dummy_Read & Dummy_Read when e3, + Read_DEMUX <= Dummy_Read & Dummy_Read & Read when e0, + Dummy_Read & Read & Dummy_Read when e1, + Read & Dummy_Read & Dummy_Read when e2, (others => '1') when others; - - - end architecture; diff --git a/lib/lpp/lpp_demux/Demultiplex.vhd b/lib/lpp/lpp_demux/Demultiplex.vhd deleted file mode 100644 --- a/lib/lpp/lpp_demux/Demultiplex.vhd +++ /dev/null @@ -1,87 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- --- Author : Martin Morlot --- Mail : martin.morlot@lpp.polytechnique.fr ------------------------------------------------------------------------------- -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -library lpp; -use lpp.lpp_demux.all; - -entity Demultiplex is -generic( - Data_sz : integer range 1 to 32 := 16); -port( - clk : in std_logic; - rstn : in std_logic; - - Read : in std_logic_vector(4 downto 0); - - EmptyF0a : in std_logic_vector(4 downto 0); - EmptyF0b : in std_logic_vector(4 downto 0); - EmptyF1 : in std_logic_vector(4 downto 0); - EmptyF2 : in std_logic_vector(4 downto 0); - - DataF0a : in std_logic_vector((5*Data_sz)-1 downto 0); - DataF0b : in std_logic_vector((5*Data_sz)-1 downto 0); - DataF1 : in std_logic_vector((5*Data_sz)-1 downto 0); - DataF2 : in std_logic_vector((5*Data_sz)-1 downto 0); - - Read_DEMUX : out std_logic_vector(19 downto 0); - Empty : out std_logic_vector(4 downto 0); - Data : out std_logic_vector((5*Data_sz)-1 downto 0) -); -end entity; - - -architecture ar_Demultiplex of Demultiplex is - -signal DataCpt : std_logic_vector(3 downto 0); - -begin - - FLG0 : WatchFlag - port map(clk,rstn,EmptyF0a,EmptyF0b,EmptyF1,EmptyF2,DataCpt); - - DEM : DEMUX - generic map(Data_sz) - port map(clk,rstn,Read,DataCpt,EmptyF0a,EmptyF0b,EmptyF1,EmptyF2,DataF0a,DataF0b,DataF1,DataF2,Read_DEMUX,Empty,Data); - -end architecture; - - - - - - - - - - - - - - - - - - - - diff --git a/lib/lpp/lpp_demux/WatchFlag.vhd b/lib/lpp/lpp_demux/WatchFlag.vhd deleted file mode 100644 --- a/lib/lpp/lpp_demux/WatchFlag.vhd +++ /dev/null @@ -1,81 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- --- Author : Martin Morlot --- Mail : martin.morlot@lpp.polytechnique.fr ------------------------------------------------------------------------------- -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity WatchFlag is -port( - clk : in std_logic; - rstn : in std_logic; - - EmptyF0a : in std_logic_vector(4 downto 0); - EmptyF0b : in std_logic_vector(4 downto 0); - EmptyF1 : in std_logic_vector(4 downto 0); - EmptyF2 : in std_logic_vector(4 downto 0); - - DataCpt : out std_logic_vector(3 downto 0) -- f2 f1 f0b f0a -); -end entity; - - -architecture ar_WatchFlag of WatchFlag is - -constant FlagSet : std_logic_vector(4 downto 0) := (others =>'1'); -constant OneToSet : std_logic_vector(4 downto 0) := "01111"; - -begin - process(clk,rstn) - begin - if(rstn='0')then - DataCpt <= (others => '0'); - - elsif(clk'event and clk='1')then - - if(EmptyF0a = OneToSet)then - DataCpt(0) <= '1'; - elsif(EmptyF0a = FlagSet)then - DataCpt(0) <= '0'; - end if; - - if(EmptyF0b = OneToSet)then - DataCpt(1) <= '1'; - elsif(EmptyF0b = FlagSet)then - DataCpt(1) <= '0'; - end if; - - if(EmptyF1 = OneToSet)then - DataCpt(2) <= '1'; - elsif(EmptyF1 = FlagSet)then - DataCpt(2) <= '0'; - end if; - - if(EmptyF2 = OneToSet)then - DataCpt(3) <= '1'; - elsif(EmptyF2 = FlagSet)then - DataCpt(3) <= '0'; - end if; - - end if; - end process; - -end architecture; \ No newline at end of file diff --git a/lib/lpp/lpp_demux/lpp_demux.vhd b/lib/lpp/lpp_demux/lpp_demux.vhd --- a/lib/lpp/lpp_demux/lpp_demux.vhd +++ b/lib/lpp/lpp_demux/lpp_demux.vhd @@ -29,34 +29,7 @@ use lpp.lpp_amba.all; --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on -package lpp_demux is - - -component Demultiplex is -generic( - Data_sz : integer range 1 to 32 := 16); -port( - clk : in std_logic; - rstn : in std_logic; - - Read : in std_logic_vector(4 downto 0); - - EmptyF0a : in std_logic_vector(4 downto 0); - EmptyF0b : in std_logic_vector(4 downto 0); - EmptyF1 : in std_logic_vector(4 downto 0); - EmptyF2 : in std_logic_vector(4 downto 0); - - DataF0a : in std_logic_vector((5*Data_sz)-1 downto 0); - DataF0b : in std_logic_vector((5*Data_sz)-1 downto 0); - DataF1 : in std_logic_vector((5*Data_sz)-1 downto 0); - DataF2 : in std_logic_vector((5*Data_sz)-1 downto 0); - - Read_DEMUX : out std_logic_vector(19 downto 0); - Empty : out std_logic_vector(4 downto 0); - Data : out std_logic_vector((5*Data_sz)-1 downto 0) -); -end component; - +package lpp_demux is component DEMUX is generic( @@ -66,38 +39,20 @@ port( rstn : in std_logic; Read : in std_logic_vector(4 downto 0); - DataCpt : in std_logic_vector(3 downto 0); -- f2 f1 f0b f0a + Load : in std_logic; - EmptyF0a : in std_logic_vector(4 downto 0); - EmptyF0b : in std_logic_vector(4 downto 0); + EmptyF0 : in std_logic_vector(4 downto 0); EmptyF1 : in std_logic_vector(4 downto 0); EmptyF2 : in std_logic_vector(4 downto 0); - DataF0a : in std_logic_vector((5*Data_sz)-1 downto 0); - DataF0b : in std_logic_vector((5*Data_sz)-1 downto 0); + DataF0 : in std_logic_vector((5*Data_sz)-1 downto 0); DataF1 : in std_logic_vector((5*Data_sz)-1 downto 0); DataF2 : in std_logic_vector((5*Data_sz)-1 downto 0); - Read_DEMUX : out std_logic_vector(19 downto 0); + Read_DEMUX : out std_logic_vector(14 downto 0); Empty : out std_logic_vector(4 downto 0); Data : out std_logic_vector((5*Data_sz)-1 downto 0) ); end component; - -component WatchFlag is -port( - clk : in std_logic; - rstn : in std_logic; - - EmptyF0a : in std_logic_vector(4 downto 0); - EmptyF0b : in std_logic_vector(4 downto 0); - EmptyF1 : in std_logic_vector(4 downto 0); - EmptyF2 : in std_logic_vector(4 downto 0); - - DataCpt : out std_logic_vector(3 downto 0) -- f2 f1 f0b f0a -); -end component; - - end; \ No newline at end of file diff --git a/lib/lpp/lpp_dma/vhdlsyn.txt b/lib/lpp/lpp_dma/vhdlsyn.txt --- a/lib/lpp/lpp_dma/vhdlsyn.txt +++ b/lib/lpp/lpp_dma/vhdlsyn.txt @@ -1,7 +1,6 @@ fifo_latency_correction.vhd lpp_dma.vhd lpp_dma_apbreg.vhd -lpp_dma_fsm.vhd lpp_dma_ip.vhd lpp_dma_pkg.vhd lpp_dma_send_16word.vhd diff --git a/lib/lpp/lpp_matrix/ALU_Driver.vhd b/lib/lpp/lpp_matrix/ALU_Driver.vhd --- a/lib/lpp/lpp_matrix/ALU_Driver.vhd +++ b/lib/lpp/lpp_matrix/ALU_Driver.vhd @@ -22,7 +22,6 @@ library IEEE; use IEEE.numeric_std.all; use IEEE.std_logic_1164.all; -library lpp; use lpp.general_purpose.all; --! Driver de l'ALU diff --git a/lib/lpp/lpp_matrix/MatriceSpectrale.vhd b/lib/lpp/lpp_matrix/MatriceSpectrale.vhd --- a/lib/lpp/lpp_matrix/MatriceSpectrale.vhd +++ b/lib/lpp/lpp_matrix/MatriceSpectrale.vhd @@ -22,8 +22,8 @@ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -library lpp; -use lpp.lpp_matrix.all; +--library lpp; +--use lpp.lpp_matrix.all; entity MatriceSpectrale is generic( @@ -34,14 +34,17 @@ entity MatriceSpectrale is rstn : in std_logic; FifoIN_Full : in std_logic_vector(4 downto 0); + SetReUse : in std_logic_vector(4 downto 0); FifoOUT_Full : in std_logic_vector(1 downto 0); - Data_IN : in std_logic_vector(79 downto 0); + Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0); ACQ : in std_logic; FlagError : out std_logic; Pong : out std_logic; + Statu : out std_logic_vector(3 downto 0); Write : out std_logic_vector(1 downto 0); Read : out std_logic_vector(4 downto 0); - Data_OUT : out std_logic_vector(63 downto 0) + ReUse : out std_logic_vector(4 downto 0); + Data_OUT : out std_logic_vector((2*Result_SZ)-1 downto 0) ); end entity; @@ -59,18 +62,23 @@ signal TopSM_Data2 : std_logic_vect begin - TopSM : TopSpecMatrix + CTRL0 : entity work.ReUse_CTRLR + port map(clkm,rstn,SetReUse,TopSM_Statu,ReUse); + + + TopSM : entity work.TopSpecMatrix generic map (Input_SZ) port map(clkm,rstn,Matrix_Write,Matrix_Read,FifoIN_Full,Data_IN,TopSM_Start,Read,TopSM_Statu,TopSM_Data1,TopSM_Data2); - SM : SpectralMatrix + SM : entity work.SpectralMatrix generic map (Input_SZ,Result_SZ) port map(clkm,rstn,TopSM_Start,TopSM_Data1,TopSM_Data2,TopSM_Statu,Matrix_Read,Matrix_Write,Matrix_Result); - DISP : Dispatch + DISP : entity work.Dispatch generic map(Result_SZ) port map(clkm,rstn,ACQ,Matrix_Result,Matrix_Write,FifoOUT_Full,Data_OUT,Write,Pong,FlagError); +Statu <= TopSM_Statu; end architecture; diff --git a/lib/lpp/lpp_matrix/ReUse_CTRLR.vhd b/lib/lpp/lpp_matrix/ReUse_CTRLR.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_matrix/ReUse_CTRLR.vhd @@ -0,0 +1,80 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------- +library IEEE; +use IEEE.numeric_std.all; +use IEEE.std_logic_1164.all; + +entity ReUse_CTRLR is + port( + clk : in std_logic; + reset : in std_logic; + + SetReUse : in std_logic_vector(4 downto 0); + Statu : in std_logic_vector(3 downto 0); + + ReUse : out std_logic_vector(4 downto 0) + ); +end entity; + + +architecture ar_ReUse_CTRLR of ReUse_CTRLR is + +signal ResetReUse : std_logic_vector(4 downto 0); +signal MatrixParam : integer; +signal MatrixParam_Reg : integer; + +begin + + + + process (clk,reset) +-- variable MatrixParam : integer; + begin +-- MatrixParam := to_integer(unsigned(Statu)); + + if(reset='0')then + ResetReUse <= (others => '1'); + MatrixParam_Reg <= 0; + + + elsif(clk' event and clk='1')then + MatrixParam_Reg <= MatrixParam; + + if(MatrixParam_Reg = 7 and MatrixParam = 8)then -- On videra FIFO(B1) a sa derni�re utilisation PARAM = 11 + ResetReUse(0) <= '0'; + elsif(MatrixParam_Reg = 8 and MatrixParam = 9)then -- On videra FIFO(B2) a sa derni�re utilisation PARAM = 12 + ResetReUse(1) <= '0'; + elsif(MatrixParam_Reg = 9 and MatrixParam = 10)then -- On videra FIFO(B3) a sa derni�re utilisation PARAM = 13 + ResetReUse(2) <= '0'; + elsif(MatrixParam_Reg = 10 and MatrixParam = 11)then -- On videra FIFO(E1) a sa derni�re utilisation PARAM = 14 + ResetReUse(3) <= '0'; + elsif(MatrixParam_Reg = 14 and MatrixParam = 15)then -- On videra FIFO(E2) a sa derni�re utilisation PARAM = 15 + ResetReUse(4) <= '0'; + end if; + + end if; + end process; + + MatrixParam <= to_integer(unsigned(Statu)); + ReUse <= SetReUse and ResetReUse; + +end architecture; \ No newline at end of file diff --git a/lib/lpp/lpp_matrix/lpp_matrix.vhd b/lib/lpp/lpp_matrix/lpp_matrix.vhd --- a/lib/lpp/lpp_matrix/lpp_matrix.vhd +++ b/lib/lpp/lpp_matrix/lpp_matrix.vhd @@ -65,14 +65,17 @@ component MatriceSpectrale is rstn : in std_logic; FifoIN_Full : in std_logic_vector(4 downto 0); + SetReUse : in std_logic_vector(4 downto 0); FifoOUT_Full : in std_logic_vector(1 downto 0); - Data_IN : in std_logic_vector(79 downto 0); + Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0); ACQ : in std_logic; FlagError : out std_logic; Pong : out std_logic; + Statu : out std_logic_vector(3 downto 0); Write : out std_logic_vector(1 downto 0); Read : out std_logic_vector(4 downto 0); - Data_OUT : out std_logic_vector(63 downto 0) + ReUse : out std_logic_vector(4 downto 0); + Data_OUT : out std_logic_vector((2*Result_SZ)-1 downto 0) ); end component; @@ -250,4 +253,14 @@ component ALU_Driver is ); end component; +component ReUse_CTRLR is + port( + clk : in std_logic; + reset : in std_logic; + SetReUse : in std_logic_vector(4 downto 0); + Statu : in std_logic_vector(3 downto 0); + ReUse : out std_logic_vector(4 downto 0) + ); +end component; + end; \ No newline at end of file diff --git a/lib/lpp/lpp_memory/lppFIFOxN.vhd b/lib/lpp/lpp_memory/lppFIFOxN.vhd --- a/lib/lpp/lpp_memory/lppFIFOxN.vhd +++ b/lib/lpp/lpp_memory/lppFIFOxN.vhd @@ -31,6 +31,7 @@ entity lppFIFOxN is generic( tech : integer := 0; Data_sz : integer range 1 to 32 := 8; + Addr_sz : integer range 1 to 32 := 8; FifoCnt : integer := 1; Enable_ReUse : std_logic := '0' ); @@ -55,32 +56,9 @@ begin fifos: for i in 0 to FifoCnt-1 generate FIFO0 : lpp_fifo - generic map (tech,Enable_ReUse,Data_sz,8) + generic map (tech,Enable_ReUse,Data_sz,Addr_sz) port map(rst,ReUse(i),rclk,ren(i),rdata((i+1)*Data_sz-1 downto i*Data_sz),empty(i),open,wclk,wen(i),wdata((i+1)*Data_sz-1 downto i*Data_sz),full(i),open); end generate; - - --- fifoB1 : entity work.lpp_fifo --- generic map (tech,Enable_ReUse,Data_sz,8) --- port map(rst,ReUse(0),rclk,ren(0),rdata(Data_sz-1 downto 0),empty(0),open,wclk,wen(0),wdata(Data_sz-1 downto 0),full(0),open); --- --- fifoB2 : entity work.lpp_fifo --- generic map (tech,Enable_ReUse,Data_sz,8) --- port map(rst,ReUse(1),rclk,ren(1),rdata((2*Data_sz)-1 downto Data_sz),empty(1),open,wclk,wen(1),wdata((2*Data_sz)-1 downto Data_sz),full(1),open); --- --- fifoB3 : entity work.lpp_fifo --- generic map (tech,Enable_ReUse,Data_sz,8) --- port map(rst,ReUse(2),rclk,ren(2),rdata((3*Data_sz)-1 downto 2*Data_sz),empty(2),open,wclk,wen(2),wdata((3*Data_sz)-1 downto 2*Data_sz),full(2),open); --- --- fifoE1 : entity work.lpp_fifo --- generic map (tech,Enable_ReUse,Data_sz,8) --- port map(rst,ReUse(3),rclk,ren(3),rdata((4*Data_sz)-1 downto 3*Data_sz),empty(3),open,wclk,wen(3),wdata((4*Data_sz)-1 downto 3*Data_sz),full(3),open); --- --- fifoE2 : entity work.lpp_fifo --- generic map (tech,Enable_ReUse,Data_sz,8) --- port map(rst,ReUse(4),rclk,ren(4),rdata((5*Data_sz)-1 downto 4*Data_sz),empty(4),open,wclk,wen(4),wdata((5*Data_sz)-1 downto 4*Data_sz),full(4),open); - - end architecture; diff --git a/lib/lpp/lpp_memory/lpp_memory.vhd b/lib/lpp/lpp_memory/lpp_memory.vhd --- a/lib/lpp/lpp_memory/lpp_memory.vhd +++ b/lib/lpp/lpp_memory/lpp_memory.vhd @@ -99,6 +99,7 @@ component lppFIFOxN is generic( tech : integer := 0; Data_sz : integer range 1 to 32 := 8; + Addr_sz : integer range 1 to 32 := 8; FifoCnt : integer := 1; Enable_ReUse : std_logic := '0' ); diff --git a/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd b/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd --- a/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd @@ -1,332 +1,303 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -LIBRARY lpp; -USE lpp.lpp_ad_conv.ALL; -USE lpp.iir_filter.ALL; -USE lpp.FILTERcfg.ALL; -USE lpp.lpp_memory.ALL; -USE lpp.lpp_top_lfr_pkg.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; - -ENTITY lpp_top_acq IS - GENERIC( - tech : INTEGER := 0 - ); - PORT ( - -- ADS7886 - cnv_run : IN STD_LOGIC; - cnv : OUT STD_LOGIC; - sck : OUT STD_LOGIC; - sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - -- - cnv_clk : IN STD_LOGIC; -- 49 MHz - cnv_rstn : IN STD_LOGIC; - -- - clk : IN STD_LOGIC; -- 25 MHz - rstn : IN STD_LOGIC; - -- - sample_f0_0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f0_1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - -- - sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - -- - sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - -- - sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0) - ); -END lpp_top_acq; - -ARCHITECTURE tb OF lpp_top_acq IS - - COMPONENT Downsampling - GENERIC ( - ChanelCount : INTEGER; - SampleSize : INTEGER; - DivideParam : INTEGER); - PORT ( - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; - sample_in_val : IN STD_LOGIC; - sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0); - sample_out_val : OUT STD_LOGIC; - sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0)); - END COMPONENT; - - ----------------------------------------------------------------------------- - CONSTANT ChanelCount : INTEGER := 8; - CONSTANT ncycle_cnv_high : INTEGER := 79; - CONSTANT ncycle_cnv : INTEGER := 500; - - ----------------------------------------------------------------------------- - SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0); - SIGNAL sample_val : STD_LOGIC; - SIGNAL sample_val_delay : STD_LOGIC; - ----------------------------------------------------------------------------- - CONSTANT Coef_SZ : INTEGER := 9; - CONSTANT CoefCntPerCel : INTEGER := 6; - CONSTANT CoefPerCel : INTEGER := 5; - CONSTANT Cels_count : INTEGER := 5; - - SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0); - SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); - -- - SIGNAL sample_filter_v2_out_val : STD_LOGIC; - SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); - -- - SIGNAL sample_filter_v2_out_r_val : STD_LOGIC; - SIGNAL sample_filter_v2_out_r : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); - ----------------------------------------------------------------------------- - SIGNAL downsampling_cnt : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL sample_downsampling_out_val : STD_LOGIC; - SIGNAL sample_downsampling_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); - -- - SIGNAL sample_f0_val : STD_LOGIC; - SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); - -- - SIGNAL sample_f0_0_val : STD_LOGIC; - SIGNAL sample_f0_1_val : STD_LOGIC; - SIGNAL counter_f0 : INTEGER; - ----------------------------------------------------------------------------- - SIGNAL sample_f1_val : STD_LOGIC; - SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); - -- - SIGNAL sample_f2_val : STD_LOGIC; - SIGNAL sample_f2 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); - -- - SIGNAL sample_f3_val : STD_LOGIC; - SIGNAL sample_f3 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); - -BEGIN - - -- component instantiation - ----------------------------------------------------------------------------- - DIGITAL_acquisition : ADS7886_drvr - GENERIC MAP ( - ChanelCount => ChanelCount, - ncycle_cnv_high => ncycle_cnv_high, - ncycle_cnv => ncycle_cnv) - PORT MAP ( - cnv_clk => cnv_clk, -- - cnv_rstn => cnv_rstn, -- - cnv_run => cnv_run, -- - cnv => cnv, -- - clk => clk, -- - rstn => rstn, -- - sck => sck, -- - sdo => sdo(ChanelCount-1 DOWNTO 0), -- - sample => sample, - sample_val => sample_val); - - ----------------------------------------------------------------------------- - - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - sample_val_delay <= '0'; - ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge - sample_val_delay <= sample_val; - END IF; - END PROCESS; - - ----------------------------------------------------------------------------- - ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE - SampleLoop : FOR j IN 0 TO 15 GENERATE - sample_filter_in(i, j) <= sample(i)(j); - END GENERATE; - - sample_filter_in(i, 16) <= sample(i)(15); - sample_filter_in(i, 17) <= sample(i)(15); - END GENERATE; - - coefs_v2 <= CoefsInitValCst_v2; - - IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 - GENERIC MAP ( - tech => 0, - Mem_use => use_RAM, - Sample_SZ => 18, - Coef_SZ => Coef_SZ, - Coef_Nb => 25, -- TODO - Coef_sel_SZ => 5, -- TODO - Cels_count => Cels_count, - ChanelsCount => ChanelCount) - PORT MAP ( - rstn => rstn, - clk => clk, - virg_pos => 7, - coefs => coefs_v2, - sample_in_val => sample_val_delay, - sample_in => sample_filter_in, - sample_out_val => sample_filter_v2_out_val, - sample_out => sample_filter_v2_out); - - ----------------------------------------------------------------------------- - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - sample_filter_v2_out_r_val <= '0'; - rst_all_chanel : FOR I IN ChanelCount-1 DOWNTO 0 LOOP - rst_all_bits : FOR J IN 17 DOWNTO 0 LOOP - sample_filter_v2_out_r(I, J) <= '0'; - END LOOP rst_all_bits; - END LOOP rst_all_chanel; - ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge - sample_filter_v2_out_r_val <= sample_filter_v2_out_val; - IF sample_filter_v2_out_val = '1' THEN - sample_filter_v2_out_r <= sample_filter_v2_out; - END IF; - END IF; - END PROCESS; - - ----------------------------------------------------------------------------- - -- F0 -- @24.576 kHz - ----------------------------------------------------------------------------- - Downsampling_f0 : Downsampling - GENERIC MAP ( - ChanelCount => ChanelCount, - SampleSize => 18, - DivideParam => 4) - PORT MAP ( - clk => clk, - rstn => rstn, - sample_in_val => sample_filter_v2_out_val , - sample_in => sample_filter_v2_out, - sample_out_val => sample_f0_val, - sample_out => sample_f0); - - all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE - sample_f0_wdata(I) <= sample_f0(0, I); - sample_f0_wdata(16*1+I) <= sample_f0(1, I); - sample_f0_wdata(16*2+I) <= sample_f0(2, I); - sample_f0_wdata(16*3+I) <= sample_f0(6, I); - sample_f0_wdata(16*4+I) <= sample_f0(7, I); - END GENERATE all_bit_sample_f0; - - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - counter_f0 <= 0; - ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge - IF sample_f0_val = '1' THEN - IF counter_f0 = 511 THEN - counter_f0 <= 0; - ELSE - counter_f0 <= counter_f0 + 1; - END IF; - END IF; - END IF; - END PROCESS; - - sample_f0_0_val <= sample_f0_val WHEN counter_f0 < 256 ELSE '0'; - sample_f0_0_wen <= NOT(sample_f0_0_val) & - NOT(sample_f0_0_val) & - NOT(sample_f0_0_val) & - NOT(sample_f0_0_val) & - NOT(sample_f0_0_val); - - sample_f0_1_val <= sample_f0_val WHEN counter_f0 > 255 ELSE '0'; - sample_f0_1_wen <= NOT(sample_f0_1_val) & - NOT(sample_f0_1_val) & - NOT(sample_f0_1_val) & - NOT(sample_f0_1_val) & - NOT(sample_f0_1_val); - - - ----------------------------------------------------------------------------- - -- F1 -- @4096 Hz - ----------------------------------------------------------------------------- - Downsampling_f1 : Downsampling - GENERIC MAP ( - ChanelCount => ChanelCount, - SampleSize => 18, - DivideParam => 6) - PORT MAP ( - clk => clk, - rstn => rstn, - sample_in_val => sample_f0_val , - sample_in => sample_f0, - sample_out_val => sample_f1_val, - sample_out => sample_f1); - - sample_f1_wen <= NOT(sample_f1_val) & - NOT(sample_f1_val) & - NOT(sample_f1_val) & - NOT(sample_f1_val) & - NOT(sample_f1_val); - - all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE - sample_f1_wdata(I) <= sample_f1(0, I); - sample_f1_wdata(16*1+I) <= sample_f1(1, I); - sample_f1_wdata(16*2+I) <= sample_f1(2, I); - sample_f1_wdata(16*3+I) <= sample_f1(6, I); - sample_f1_wdata(16*4+I) <= sample_f1(7, I); - END GENERATE all_bit_sample_f1; - - ----------------------------------------------------------------------------- - -- F2 -- @16 Hz - ----------------------------------------------------------------------------- - Downsampling_f2 : Downsampling - GENERIC MAP ( - ChanelCount => ChanelCount, - SampleSize => 18, - DivideParam => 256) - PORT MAP ( - clk => clk, - rstn => rstn, - sample_in_val => sample_f1_val , - sample_in => sample_f1, - sample_out_val => sample_f2_val, - sample_out => sample_f2); - - sample_f2_wen <= NOT(sample_f2_val) & - NOT(sample_f2_val) & - NOT(sample_f2_val) & - NOT(sample_f2_val) & - NOT(sample_f2_val); - - all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE - sample_f2_wdata(I) <= sample_f2(0, I); - sample_f2_wdata(16*1+I) <= sample_f2(1, I); - sample_f2_wdata(16*2+I) <= sample_f2(2, I); - sample_f2_wdata(16*3+I) <= sample_f2(6, I); - sample_f2_wdata(16*4+I) <= sample_f2(7, I); - END GENERATE all_bit_sample_f2; - - ----------------------------------------------------------------------------- - -- F3 -- @256 Hz - ----------------------------------------------------------------------------- - Downsampling_f3 : Downsampling - GENERIC MAP ( - ChanelCount => ChanelCount, - SampleSize => 18, - DivideParam => 96) - PORT MAP ( - clk => clk, - rstn => rstn, - sample_in_val => sample_f0_val , - sample_in => sample_f0, - sample_out_val => sample_f3_val, - sample_out => sample_f3); - - sample_f3_wen <= (NOT sample_f3_val) & - (NOT sample_f3_val) & - (NOT sample_f3_val) & - (NOT sample_f3_val) & - (NOT sample_f3_val); - - all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE - sample_f3_wdata(I) <= sample_f3(0, I); - sample_f3_wdata(16*1+I) <= sample_f3(1, I); - sample_f3_wdata(16*2+I) <= sample_f3(2, I); - sample_f3_wdata(16*3+I) <= sample_f3(6, I); - sample_f3_wdata(16*4+I) <= sample_f3(7, I); - END GENERATE all_bit_sample_f3; - - - -END tb; +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +LIBRARY lpp; +USE lpp.lpp_ad_conv.ALL; +USE lpp.iir_filter.ALL; +USE lpp.FILTERcfg.ALL; +USE lpp.lpp_memory.ALL; +USE lpp.lpp_top_lfr_pkg.ALL; +LIBRARY techmap; +USE techmap.gencomp.ALL; + +ENTITY lpp_top_acq IS + GENERIC( + tech : INTEGER := 0 + ); + PORT ( + -- ADS7886 + cnv_run : IN STD_LOGIC; + cnv : OUT STD_LOGIC; + sck : OUT STD_LOGIC; + sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + -- + cnv_clk : IN STD_LOGIC; -- 49 MHz + cnv_rstn : IN STD_LOGIC; + -- + clk : IN STD_LOGIC; -- 25 MHz + rstn : IN STD_LOGIC; + -- + sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + -- + sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + -- + sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + -- + sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0) + ); +END lpp_top_acq; + +ARCHITECTURE tb OF lpp_top_acq IS + + COMPONENT Downsampling + GENERIC ( + ChanelCount : INTEGER; + SampleSize : INTEGER; + DivideParam : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + sample_in_val : IN STD_LOGIC; + sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0); + sample_out_val : OUT STD_LOGIC; + sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0)); + END COMPONENT; + + ----------------------------------------------------------------------------- + CONSTANT ChanelCount : INTEGER := 8; + CONSTANT ncycle_cnv_high : INTEGER := 79; + CONSTANT ncycle_cnv : INTEGER := 500; + + ----------------------------------------------------------------------------- + SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0); + SIGNAL sample_val : STD_LOGIC; + SIGNAL sample_val_delay : STD_LOGIC; + ----------------------------------------------------------------------------- + CONSTANT Coef_SZ : INTEGER := 9; + CONSTANT CoefCntPerCel : INTEGER := 6; + CONSTANT CoefPerCel : INTEGER := 5; + CONSTANT Cels_count : INTEGER := 5; + + SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0); + SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); + -- + SIGNAL sample_filter_v2_out_val : STD_LOGIC; + SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); + -- + SIGNAL sample_filter_v2_out_r_val : STD_LOGIC; + SIGNAL sample_filter_v2_out_r : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); + ----------------------------------------------------------------------------- + SIGNAL downsampling_cnt : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL sample_downsampling_out_val : STD_LOGIC; + SIGNAL sample_downsampling_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); + -- + SIGNAL sample_f0_val : STD_LOGIC; + SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); + ----------------------------------------------------------------------------- + SIGNAL sample_f1_val : STD_LOGIC; + SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); + -- + SIGNAL sample_f2_val : STD_LOGIC; + SIGNAL sample_f2 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); + -- + SIGNAL sample_f3_val : STD_LOGIC; + SIGNAL sample_f3 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); + +BEGIN + + -- component instantiation + ----------------------------------------------------------------------------- + DIGITAL_acquisition : AD7688_drvr + GENERIC MAP ( + ChanelCount => ChanelCount, + ncycle_cnv_high => ncycle_cnv_high, + ncycle_cnv => ncycle_cnv) + PORT MAP ( + cnv_clk => cnv_clk, -- + cnv_rstn => cnv_rstn, -- + cnv_run => cnv_run, -- + cnv => cnv, -- + clk => clk, -- + rstn => rstn, -- + sck => sck, -- + sdo => sdo(ChanelCount-1 DOWNTO 0), -- + sample => sample, + sample_val => sample_val); + + ----------------------------------------------------------------------------- + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + sample_val_delay <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + sample_val_delay <= sample_val; + END IF; + END PROCESS; + + ----------------------------------------------------------------------------- + ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE + SampleLoop : FOR j IN 0 TO 15 GENERATE + sample_filter_in(i, j) <= sample(i)(j); + END GENERATE; + + sample_filter_in(i, 16) <= sample(i)(15); + sample_filter_in(i, 17) <= sample(i)(15); + END GENERATE; + + coefs_v2 <= CoefsInitValCst_v2; + + IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 + GENERIC MAP ( + tech => 0, + Mem_use => use_RAM, + Sample_SZ => 18, + Coef_SZ => Coef_SZ, + Coef_Nb => 25, -- TODO + Coef_sel_SZ => 5, -- TODO + Cels_count => Cels_count, + ChanelsCount => ChanelCount) + PORT MAP ( + rstn => rstn, + clk => clk, + virg_pos => 7, + coefs => coefs_v2, + sample_in_val => sample_val_delay, + sample_in => sample_filter_in, + sample_out_val => sample_filter_v2_out_val, + sample_out => sample_filter_v2_out); + + ----------------------------------------------------------------------------- + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + sample_filter_v2_out_r_val <= '0'; + rst_all_chanel : FOR I IN ChanelCount-1 DOWNTO 0 LOOP + rst_all_bits : FOR J IN 17 DOWNTO 0 LOOP + sample_filter_v2_out_r(I, J) <= '0'; + END LOOP rst_all_bits; + END LOOP rst_all_chanel; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + sample_filter_v2_out_r_val <= sample_filter_v2_out_val; + IF sample_filter_v2_out_val = '1' THEN + sample_filter_v2_out_r <= sample_filter_v2_out; + END IF; + END IF; + END PROCESS; + + ----------------------------------------------------------------------------- + -- F0 -- @24.576 kHz + ----------------------------------------------------------------------------- + Downsampling_f0 : Downsampling + GENERIC MAP ( + ChanelCount => ChanelCount, + SampleSize => 18, + DivideParam => 4) + PORT MAP ( + clk => clk, + rstn => rstn, + sample_in_val => sample_filter_v2_out_val , + sample_in => sample_filter_v2_out, + sample_out_val => sample_f0_val, + sample_out => sample_f0); + + all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE + sample_f0_wdata(I) <= sample_f0(0, I); + sample_f0_wdata(16*1+I) <= sample_f0(1, I); + sample_f0_wdata(16*2+I) <= sample_f0(2, I); + sample_f0_wdata(16*3+I) <= sample_f0(6, I); + sample_f0_wdata(16*4+I) <= sample_f0(7, I); + END GENERATE all_bit_sample_f0; + + sample_f0_wen <= NOT(sample_f0_val) & + NOT(sample_f0_val) & + NOT(sample_f0_val) & + NOT(sample_f0_val) & + NOT(sample_f0_val); + + ----------------------------------------------------------------------------- + -- F1 -- @4096 Hz + ----------------------------------------------------------------------------- + Downsampling_f1 : Downsampling + GENERIC MAP ( + ChanelCount => ChanelCount, + SampleSize => 18, + DivideParam => 6) + PORT MAP ( + clk => clk, + rstn => rstn, + sample_in_val => sample_f0_val , + sample_in => sample_f0, + sample_out_val => sample_f1_val, + sample_out => sample_f1); + + sample_f1_wen <= NOT(sample_f1_val) & + NOT(sample_f1_val) & + NOT(sample_f1_val) & + NOT(sample_f1_val) & + NOT(sample_f1_val); + + all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE + sample_f1_wdata(I) <= sample_f1(0, I); + sample_f1_wdata(16*1+I) <= sample_f1(1, I); + sample_f1_wdata(16*2+I) <= sample_f1(2, I); + sample_f1_wdata(16*3+I) <= sample_f1(6, I); + sample_f1_wdata(16*4+I) <= sample_f1(7, I); + END GENERATE all_bit_sample_f1; + + ----------------------------------------------------------------------------- + -- F2 -- @16 Hz + ----------------------------------------------------------------------------- + Downsampling_f2 : Downsampling + GENERIC MAP ( + ChanelCount => ChanelCount, + SampleSize => 18, + DivideParam => 96) + PORT MAP ( + clk => clk, + rstn => rstn, + sample_in_val => sample_f1_val , + sample_in => sample_f1, + sample_out_val => sample_f2_val, + sample_out => sample_f2); + + sample_f2_wen <= NOT(sample_f2_val) & + NOT(sample_f2_val) & + NOT(sample_f2_val) & + NOT(sample_f2_val) & + NOT(sample_f2_val); + + all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE + sample_f2_wdata(I) <= sample_f2(0, I); + sample_f2_wdata(16*1+I) <= sample_f2(1, I); + sample_f2_wdata(16*2+I) <= sample_f2(2, I); + sample_f2_wdata(16*3+I) <= sample_f2(6, I); + sample_f2_wdata(16*4+I) <= sample_f2(7, I); + END GENERATE all_bit_sample_f2; + + ----------------------------------------------------------------------------- + -- F3 -- @256 Hz + ----------------------------------------------------------------------------- + Downsampling_f3 : Downsampling + GENERIC MAP ( + ChanelCount => ChanelCount, + SampleSize => 18, + DivideParam => 256) + PORT MAP ( + clk => clk, + rstn => rstn, + sample_in_val => sample_f0_val , + sample_in => sample_f0, + sample_out_val => sample_f3_val, + sample_out => sample_f3); + + sample_f3_wen <= (NOT sample_f3_val) & + (NOT sample_f3_val) & + (NOT sample_f3_val) & + (NOT sample_f3_val) & + (NOT sample_f3_val); + + all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE + sample_f3_wdata(I) <= sample_f3(0, I); + sample_f3_wdata(16*1+I) <= sample_f3(1, I); + sample_f3_wdata(16*2+I) <= sample_f3(2, I); + sample_f3_wdata(16*3+I) <= sample_f3(6, I); + sample_f3_wdata(16*4+I) <= sample_f3(7, I); + END GENERATE all_bit_sample_f3; + + + +END tb; diff --git a/lib/lpp/lpp_top_lfr/lpp_top_apbreg.vhd b/lib/lpp/lpp_top_lfr/lpp_top_apbreg.vhd --- a/lib/lpp/lpp_top_lfr/lpp_top_apbreg.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_top_apbreg.vhd @@ -36,6 +36,12 @@ USE techmap.gencomp.ALL; ENTITY lpp_top_apbreg IS GENERIC ( + nb_burst_available_size : INTEGER := 11; + nb_snapshot_param_size : INTEGER := 11; + delta_snapshot_size : INTEGER := 16; + delta_f2_f0_size : INTEGER := 10; + delta_f2_f1_size : INTEGER := 10; + pindex : INTEGER := 4; paddr : INTEGER := 4; pmask : INTEGER := 16#fff#; @@ -49,6 +55,8 @@ ENTITY lpp_top_apbreg IS apbi : IN apb_slv_in_type; apbo : OUT apb_slv_out_type; + --------------------------------------------------------------------------- + -- Spectral Matrix Reg -- IN ready_matrix_f0_0 : IN STD_LOGIC; ready_matrix_f0_1 : IN STD_LOGIC; @@ -71,7 +79,43 @@ ENTITY lpp_top_apbreg IS addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + --------------------------------------------------------------------------- + --------------------------------------------------------------------------- + -- WaveForm picker Reg + status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + + -- OUT + data_shaping_BW : OUT STD_LOGIC; + data_shaping_SP0 : OUT STD_LOGIC; + data_shaping_SP1 : OUT STD_LOGIC; + data_shaping_R0 : OUT STD_LOGIC; + data_shaping_R1 : OUT STD_LOGIC; + + delta_snapshot : OUT STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); + delta_f2_f1 : OUT STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); + delta_f2_f0 : OUT STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); + nb_burst_available : OUT STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); + nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); + + enable_f0 : OUT STD_LOGIC; + enable_f1 : OUT STD_LOGIC; + enable_f2 : OUT STD_LOGIC; + enable_f3 : OUT STD_LOGIC; + + burst_f0 : OUT STD_LOGIC; + burst_f1 : OUT STD_LOGIC; + burst_f2 : OUT STD_LOGIC; + + addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + + --------------------------------------------------------------------------- ); END lpp_top_apbreg; @@ -84,7 +128,7 @@ ARCHITECTURE beh OF lpp_top_apbreg IS 0 => ahb_device_reg (VENDOR_LPP, LPP_DMA_TYPE, 0, REVISION, pirq), 1 => apb_iobar(paddr, pmask)); - TYPE lpp_dma_regs IS RECORD + TYPE lpp_SpectralMatrix_regs IS RECORD config_active_interruption_onNewMatrix : STD_LOGIC; config_active_interruption_onError : STD_LOGIC; status_ready_matrix_f0_0 : STD_LOGIC; @@ -98,53 +142,144 @@ ARCHITECTURE beh OF lpp_top_apbreg IS addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); END RECORD; + SIGNAL reg_sp : lpp_SpectralMatrix_regs; - SIGNAL reg : lpp_dma_regs; + TYPE lpp_WaveformPicker_regs IS RECORD + status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); + status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); + data_shaping_BW : STD_LOGIC; + data_shaping_SP0 : STD_LOGIC; + data_shaping_SP1 : STD_LOGIC; + data_shaping_R0 : STD_LOGIC; + data_shaping_R1 : STD_LOGIC; + delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); + delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); + delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); + nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); + nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); + enable_f0 : STD_LOGIC; + enable_f1 : STD_LOGIC; + enable_f2 : STD_LOGIC; + enable_f3 : STD_LOGIC; + burst_f0 : STD_LOGIC; + burst_f1 : STD_LOGIC; + burst_f2 : STD_LOGIC; + addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); + END RECORD; + SIGNAL reg_wp : lpp_WaveformPicker_regs; SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0); BEGIN -- beh - status_ready_matrix_f0_0 <= reg.status_ready_matrix_f0_0; - status_ready_matrix_f0_1 <= reg.status_ready_matrix_f0_1; - status_ready_matrix_f1 <= reg.status_ready_matrix_f1; - status_ready_matrix_f2 <= reg.status_ready_matrix_f2; - status_error_anticipating_empty_fifo <= reg.status_error_anticipating_empty_fifo; - status_error_bad_component_error <= reg.status_error_bad_component_error; + status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0; + status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1; + status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1; + status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2; + status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo; + status_error_bad_component_error <= reg_sp.status_error_bad_component_error; + + config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix; + config_active_interruption_onError <= reg_sp.config_active_interruption_onError; + addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0; + addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1; + addr_matrix_f1 <= reg_sp.addr_matrix_f1; + addr_matrix_f2 <= reg_sp.addr_matrix_f2; + - config_active_interruption_onNewMatrix <= reg.config_active_interruption_onNewMatrix; - config_active_interruption_onError <= reg.config_active_interruption_onError; - addr_matrix_f0_0 <= reg.addr_matrix_f0_0; - addr_matrix_f0_1 <= reg.addr_matrix_f0_1; - addr_matrix_f1 <= reg.addr_matrix_f1; - addr_matrix_f2 <= reg.addr_matrix_f2; + + + data_shaping_BW <= reg_wp.data_shaping_BW; + data_shaping_SP0 <= reg_wp.data_shaping_SP0; + data_shaping_SP1 <= reg_wp.data_shaping_SP1; + data_shaping_R0 <= reg_wp.data_shaping_R0; + data_shaping_R1 <= reg_wp.data_shaping_R1; + + delta_snapshot <= reg_wp.delta_snapshot; + delta_f2_f1 <= reg_wp.delta_f2_f1; + delta_f2_f0 <= reg_wp.delta_f2_f0; + nb_burst_available <= reg_wp.nb_burst_available; + nb_snapshot_param <= reg_wp.nb_snapshot_param; + + enable_f0 <= reg_wp.enable_f0; + enable_f1 <= reg_wp.enable_f1; + enable_f2 <= reg_wp.enable_f2; + enable_f3 <= reg_wp.enable_f3; + + burst_f0 <= reg_wp.burst_f0; + burst_f1 <= reg_wp.burst_f1; + burst_f2 <= reg_wp.burst_f2; + + addr_data_f0 <= reg_wp.addr_data_f0; + addr_data_f1 <= reg_wp.addr_data_f1; + addr_data_f2 <= reg_wp.addr_data_f2; + addr_data_f3 <= reg_wp.addr_data_f3; lpp_top_apbreg : PROCESS (HCLK, HRESETn) VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2); BEGIN -- PROCESS lpp_dma_top - IF HRESETn = '0' THEN -- asynchronous reset (active low) - reg.config_active_interruption_onNewMatrix <= '0'; - reg.config_active_interruption_onError <= '0'; - reg.status_ready_matrix_f0_0 <= '0'; - reg.status_ready_matrix_f0_1 <= '0'; - reg.status_ready_matrix_f1 <= '0'; - reg.status_ready_matrix_f2 <= '0'; - reg.status_error_anticipating_empty_fifo <= '0'; - reg.status_error_bad_component_error <= '0'; - reg.addr_matrix_f0_0 <= (OTHERS => '0'); - reg.addr_matrix_f0_1 <= (OTHERS => '0'); - reg.addr_matrix_f1 <= (OTHERS => '0'); - reg.addr_matrix_f2 <= (OTHERS => '0'); - prdata <= (OTHERS => '0'); + IF HRESETn = '0' THEN -- asynchronous reset (active low) + reg_sp.config_active_interruption_onNewMatrix <= '0'; + reg_sp.config_active_interruption_onError <= '0'; + reg_sp.status_ready_matrix_f0_0 <= '0'; + reg_sp.status_ready_matrix_f0_1 <= '0'; + reg_sp.status_ready_matrix_f1 <= '0'; + reg_sp.status_ready_matrix_f2 <= '0'; + reg_sp.status_error_anticipating_empty_fifo <= '0'; + reg_sp.status_error_bad_component_error <= '0'; + reg_sp.addr_matrix_f0_0 <= (OTHERS => '0'); + reg_sp.addr_matrix_f0_1 <= (OTHERS => '0'); + reg_sp.addr_matrix_f1 <= (OTHERS => '0'); + reg_sp.addr_matrix_f2 <= (OTHERS => '0'); + prdata <= (OTHERS => '0'); + + apbo.pirq <= (OTHERS => '0'); + + status_full_ack <= (OTHERS => '0'); + + reg_wp.data_shaping_BW <= '0'; + reg_wp.data_shaping_SP0 <= '0'; + reg_wp.data_shaping_SP1 <= '0'; + reg_wp.data_shaping_R0 <= '0'; + reg_wp.data_shaping_R1 <= '0'; + reg_wp.enable_f0 <= '0'; + reg_wp.enable_f1 <= '0'; + reg_wp.enable_f2 <= '0'; + reg_wp.enable_f3 <= '0'; + reg_wp.burst_f0 <= '0'; + reg_wp.burst_f1 <= '0'; + reg_wp.burst_f2 <= '0'; + reg_wp.addr_data_f0 <= (OTHERS => '0'); + reg_wp.addr_data_f1 <= (OTHERS => '0'); + reg_wp.addr_data_f2 <= (OTHERS => '0'); + reg_wp.addr_data_f3 <= (OTHERS => '0'); + reg_wp.status_full <= (OTHERS => '0'); + reg_wp.status_full_err <= (OTHERS => '0'); + reg_wp.status_new_err <= (OTHERS => '0'); + reg_wp.delta_snapshot <= (OTHERS => '0'); + reg_wp.delta_f2_f1 <= (OTHERS => '0'); + reg_wp.delta_f2_f0 <= (OTHERS => '0'); + reg_wp.nb_burst_available <= (OTHERS => '0'); + reg_wp.nb_snapshot_param <= (OTHERS => '0'); + ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge + status_full_ack <= (OTHERS => '0'); - reg.status_ready_matrix_f0_0 <= reg.status_ready_matrix_f0_0 OR ready_matrix_f0_0; - reg.status_ready_matrix_f0_1 <= reg.status_ready_matrix_f0_1 OR ready_matrix_f0_1; - reg.status_ready_matrix_f1 <= reg.status_ready_matrix_f1 OR ready_matrix_f1; - reg.status_ready_matrix_f2 <= reg.status_ready_matrix_f2 OR ready_matrix_f2; + reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0; + reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1; + reg_sp.status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1 OR ready_matrix_f1; + reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2; - reg.status_error_anticipating_empty_fifo <= reg.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo; - reg.status_error_bad_component_error <= reg.status_error_bad_component_error OR error_bad_component_error; + reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo; + reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error; + + reg_wp.status_full <= reg_wp.status_full OR status_full; + reg_wp.status_full_err <= reg_wp.status_full_err OR status_full_err; + reg_wp.status_new_err <= reg_wp.status_new_err OR status_new_err; paddr := "000000"; paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2); @@ -152,44 +287,119 @@ BEGIN -- beh IF apbi.psel(pindex) = '1' THEN -- APB DMA READ -- CASE paddr(7 DOWNTO 2) IS - WHEN "000000" => prdata(0) <= reg.config_active_interruption_onNewMatrix; - prdata(1) <= reg.config_active_interruption_onError; - WHEN "000001" => prdata(0) <= reg.status_ready_matrix_f0_0; - prdata(1) <= reg.status_ready_matrix_f0_1; - prdata(2) <= reg.status_ready_matrix_f1; - prdata(3) <= reg.status_ready_matrix_f2; - prdata(4) <= reg.status_error_anticipating_empty_fifo; - prdata(5) <= reg.status_error_bad_component_error; - WHEN "000010" => prdata <= reg.addr_matrix_f0_0; - WHEN "000011" => prdata <= reg.addr_matrix_f0_1; - WHEN "000100" => prdata <= reg.addr_matrix_f1; - WHEN "000101" => prdata <= reg.addr_matrix_f2; - WHEN "000110" => prdata <= debug_reg; + -- + WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix; + prdata(1) <= reg_sp.config_active_interruption_onError; + WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0; + prdata(1) <= reg_sp.status_ready_matrix_f0_1; + prdata(2) <= reg_sp.status_ready_matrix_f1; + prdata(3) <= reg_sp.status_ready_matrix_f2; + prdata(4) <= reg_sp.status_error_anticipating_empty_fifo; + prdata(5) <= reg_sp.status_error_bad_component_error; + WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0; + WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1; + WHEN "000100" => prdata <= reg_sp.addr_matrix_f1; + WHEN "000101" => prdata <= reg_sp.addr_matrix_f2; + WHEN "000110" => prdata <= debug_reg; + -- + WHEN "001000" => prdata(0) <= reg_wp.data_shaping_BW; + prdata(1) <= reg_wp.data_shaping_SP0; + prdata(2) <= reg_wp.data_shaping_SP1; + prdata(3) <= reg_wp.data_shaping_R0; + prdata(4) <= reg_wp.data_shaping_R1; + WHEN "001001" => prdata(0) <= reg_wp.enable_f0; + prdata(1) <= reg_wp.enable_f1; + prdata(2) <= reg_wp.enable_f2; + prdata(3) <= reg_wp.enable_f3; + prdata(4) <= reg_wp.burst_f0; + prdata(5) <= reg_wp.burst_f1; + prdata(6) <= reg_wp.burst_f2; + WHEN "001010" => prdata <= reg_wp.addr_data_f0; + WHEN "001011" => prdata <= reg_wp.addr_data_f1; + WHEN "001100" => prdata <= reg_wp.addr_data_f2; + WHEN "001101" => prdata <= reg_wp.addr_data_f3; + WHEN "001110" => prdata(3 DOWNTO 0) <= reg_wp.status_full; + prdata(7 DOWNTO 4) <= reg_wp.status_full_err; + prdata(11 DOWNTO 8) <= reg_wp.status_new_err; + WHEN "001111" => prdata(delta_snapshot_size-1 DOWNTO 0) <= reg_wp.delta_snapshot; + WHEN "010000" => prdata(delta_f2_f1_size-1 DOWNTO 0) <= reg_wp.delta_f2_f1; + WHEN "010001" => prdata(delta_f2_f0_size-1 DOWNTO 0) <= reg_wp.delta_f2_f0; + WHEN "010010" => prdata(nb_burst_available_size-1 DOWNTO 0) <= reg_wp.nb_burst_available; + WHEN "010011" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param; + -- WHEN OTHERS => NULL; END CASE; IF (apbi.pwrite AND apbi.penable) = '1' THEN -- APB DMA WRITE -- CASE paddr(7 DOWNTO 2) IS - WHEN "000000" => reg.config_active_interruption_onNewMatrix <= apbi.pwdata(0); - reg.config_active_interruption_onError <= apbi.pwdata(1); - WHEN "000001" => reg.status_ready_matrix_f0_0 <= apbi.pwdata(0); - reg.status_ready_matrix_f0_1 <= apbi.pwdata(1); - reg.status_ready_matrix_f1 <= apbi.pwdata(2); - reg.status_ready_matrix_f2 <= apbi.pwdata(3); - reg.status_error_anticipating_empty_fifo <= apbi.pwdata(4); - reg.status_error_bad_component_error <= apbi.pwdata(5); - WHEN "000010" => reg.addr_matrix_f0_0 <= apbi.pwdata; - WHEN "000011" => reg.addr_matrix_f0_1 <= apbi.pwdata; - WHEN "000100" => reg.addr_matrix_f1 <= apbi.pwdata; - WHEN "000101" => reg.addr_matrix_f2 <= apbi.pwdata; + -- + WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0); + reg_sp.config_active_interruption_onError <= apbi.pwdata(1); + WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0); + reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1); + reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2); + reg_sp.status_ready_matrix_f2 <= apbi.pwdata(3); + reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4); + reg_sp.status_error_bad_component_error <= apbi.pwdata(5); + WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata; + WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata; + WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata; + WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata; + -- + WHEN "001000" => reg_wp.data_shaping_BW <= apbi.pwdata(0); + reg_wp.data_shaping_SP0 <= apbi.pwdata(1); + reg_wp.data_shaping_SP1 <= apbi.pwdata(2); + reg_wp.data_shaping_R0 <= apbi.pwdata(3); + reg_wp.data_shaping_R1 <= apbi.pwdata(4); + WHEN "001001" => reg_wp.enable_f0 <= apbi.pwdata(0); + reg_wp.enable_f1 <= apbi.pwdata(1); + reg_wp.enable_f2 <= apbi.pwdata(2); + reg_wp.enable_f3 <= apbi.pwdata(3); + reg_wp.burst_f0 <= apbi.pwdata(4); + reg_wp.burst_f1 <= apbi.pwdata(5); + reg_wp.burst_f2 <= apbi.pwdata(6); + WHEN "001010" => reg_wp.addr_data_f0 <= apbi.pwdata; + WHEN "001011" => reg_wp.addr_data_f1 <= apbi.pwdata; + WHEN "001100" => reg_wp.addr_data_f2 <= apbi.pwdata; + WHEN "001101" => reg_wp.addr_data_f3 <= apbi.pwdata; + WHEN "001110" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0); + reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4); + reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8); + status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0); + status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1); + status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2); + status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3); + WHEN "001111" => reg_wp.delta_snapshot <= apbi.pwdata(delta_snapshot_size-1 DOWNTO 0); + WHEN "010000" => reg_wp.delta_f2_f1 <= apbi.pwdata(delta_f2_f1_size-1 DOWNTO 0); + WHEN "010001" => reg_wp.delta_f2_f0 <= apbi.pwdata(delta_f2_f0_size-1 DOWNTO 0); + WHEN "010010" => reg_wp.nb_burst_available <= apbi.pwdata(nb_burst_available_size-1 DOWNTO 0); + WHEN "010011" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0); + -- WHEN OTHERS => NULL; END CASE; END IF; END IF; + + apbo.pirq(pirq) <= (reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR + ready_matrix_f0_1 OR + ready_matrix_f1 OR + ready_matrix_f2) + ) + OR + (reg_sp.config_active_interruption_onError AND (error_anticipating_empty_fifo OR + error_bad_component_error) + ) + OR + (status_full(0) OR status_full_err(0) OR status_new_err(0) OR + status_full(1) OR status_full_err(1) OR status_new_err(1) OR + status_full(2) OR status_full_err(2) OR status_new_err(2) OR + status_full(3) OR status_full_err(3) OR status_new_err(3) + ); + + END IF; END PROCESS lpp_top_apbreg; - apbo.pirq <= (OTHERS => '0'); apbo.pindex <= pindex; apbo.pconfig <= pconfig; apbo.prdata <= prdata; diff --git a/lib/lpp/lpp_top_lfr/lpp_top_lfr.vhd b/lib/lpp/lpp_top_lfr/lpp_top_lfr.vhd --- a/lib/lpp/lpp_top_lfr/lpp_top_lfr.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_top_lfr.vhd @@ -14,7 +14,8 @@ USE lpp.lpp_top_lfr_pkg.ALL; USE lpp.lpp_dma_pkg.ALL; USE lpp.lpp_demux.ALL; USE lpp.lpp_fft.ALL; -use lpp.lpp_matrix.all; +USE lpp.lpp_matrix.ALL; +USE lpp.lpp_waveform_pkg.ALL; LIBRARY techmap; USE techmap.gencomp.ALL; @@ -46,6 +47,10 @@ ENTITY lpp_top_lfr IS -- AMBA AHB Master Interface AHB_DMA_SpectralMatrix_In : IN AHB_Mst_In_Type; AHB_DMA_SpectralMatrix_Out : OUT AHB_Mst_Out_Type + + -- Time + coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time + fine_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) --! fine time ); END lpp_top_lfr; @@ -53,8 +58,7 @@ ARCHITECTURE tb OF lpp_top_lfr IS ----------------------------------------------------------------------------- -- f0 - SIGNAL sample_f0_0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f0_1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); -- SIGNAL sample_f0_0_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); @@ -104,9 +108,9 @@ ARCHITECTURE tb OF lpp_top_lfr IS SIGNAL fft_fifo_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); SIGNAL fft_fifo_reuse : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL SP_fifo_data : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - SIGNAL SP_fifo_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); - + SIGNAL SP_fifo_data : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + SIGNAL SP_fifo_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL fifo_empty : STD_LOGIC; SIGNAL fifo_ren : STD_LOGIC; @@ -136,6 +140,35 @@ ARCHITECTURE tb OF lpp_top_lfr IS SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); + + ----------------------------------------------------------------------------- + -- + ----------------------------------------------------------------------------- + + CONSTANT nb_snapshot_param_size : INTEGER := 11; + CONSTANT delta_snapshot_size : INTEGER := 16; + CONSTANT delta_f2_f0_size : INTEGER := 10; + CONSTANT delta_f2_f1_size : INTEGER := 10; + + SIGNAL waveform_enable_f0 : STD_LOGIC; + SIGNAL waveform_enable_f1 : STD_LOGIC; + SIGNAL waveform_enable_f2 : STD_LOGIC; + SIGNAL waveform_enable_f3 : STD_LOGIC; + + SIGNAL waveform_burst_f0 : STD_LOGIC; + SIGNAL waveform_burst_f1 : STD_LOGIC; + SIGNAL waveform_burst_f2 : STD_LOGIC; + + SIGNAL waveform_nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); + SIGNAL waveform_delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); + SIGNAL waveform_delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); + SIGNAL waveform_delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); + + SIGNAL data_f0_in_valid : STD_LOGIC; + SIGNAL data_f0_in_valid_r : STD_LOGIC; + SIGNAL data_f1_in_valid : STD_LOGIC; + SIGNAL data_f2_in_valid : STD_LOGIC; + SIGNAL data_f3_in_valid : STD_LOGIC; BEGIN @@ -155,8 +188,7 @@ BEGIN clk => clk, rstn => rstn, - sample_f0_0_wen => sample_f0_0_wen, - sample_f0_1_wen => sample_f0_1_wen, + sample_f0_wen => sample_f0_wen, sample_f0_wdata => sample_f0_wdata, sample_f1_wen => sample_f1_wen, sample_f1_wdata => sample_f1_wdata, @@ -169,7 +201,7 @@ BEGIN -- FIFO ----------------------------------------------------------------------------- - lppFIFO_f0_0 : lppFIFOxN + lppFIFO_f0 : lppFIFOxN GENERIC MAP ( tech => tech, Data_sz => 16, @@ -181,31 +213,12 @@ BEGIN rclk => clk, ReUse => (OTHERS => '0'), - wen => sample_f0_0_wen, - ren => sample_f0_0_ren, + wen => sample_f0_wen, + ren => sample_f0_ren, wdata => sample_f0_wdata, - rdata => sample_f0_0_rdata, - full => sample_f0_0_full, - empty => sample_f0_0_empty); - - lppFIFO_f0_1 : lppFIFOxN - GENERIC MAP ( - tech => tech, - Data_sz => 16, - FifoCnt => 5, - Enable_ReUse => '0') - PORT MAP ( - rst => rstn, - wclk => clk, - rclk => clk, - ReUse => (OTHERS => '0'), - - wen => sample_f0_1_wen, - ren => sample_f0_1_ren, - wdata => sample_f0_wdata, - rdata => sample_f0_1_rdata, - full => sample_f0_1_full, - empty => sample_f0_1_empty); + rdata => sample_f0_rdata, + full => sample_f0_full, + empty => sample_f0_empty); lppFIFO_f1 : lppFIFOxN GENERIC MAP ( @@ -226,7 +239,7 @@ BEGIN full => sample_f1_full, empty => sample_f1_empty); - lppFIFO_f3 : lppFIFOxN + lppFIFO_f2 : lppFIFOxN GENERIC MAP ( tech => tech, Data_sz => 16, @@ -238,92 +251,91 @@ BEGIN rclk => clk, ReUse => (OTHERS => '0'), - wen => sample_f3_wen, - ren => sample_f3_ren, - wdata => sample_f3_wdata, - rdata => sample_f3_rdata, - full => sample_f3_full, - empty => sample_f3_empty); + wen => sample_f2_wen, + ren => sample_f2_ren, + wdata => sample_f2_wdata, + rdata => sample_f2_rdata, + full => sample_f2_full, + empty => sample_f2_empty); ----------------------------------------------------------------------------- -- SPECTRAL MATRIX ----------------------------------------------------------------------------- - sample_f0_0_ren <= sample_ren(4 DOWNTO 0); - sample_f0_1_ren <= sample_ren(9 DOWNTO 5); - sample_f1_ren <= sample_ren(14 DOWNTO 10); - sample_f3_ren <= sample_ren(19 DOWNTO 15); + --sample_f0_ren <= sample_ren(4 DOWNTO 0); + --sample_f1_ren <= sample_ren(14 DOWNTO 10); + --sample_f2_ren <= sample_ren(19 DOWNTO 15); - Demultiplex_1 : Demultiplex - GENERIC MAP ( - Data_sz => 16) - PORT MAP ( - clk => clk, - rstn => rstn, + --Demultiplex_1 : Demultiplex + -- GENERIC MAP ( + -- Data_sz => 16) + -- PORT MAP ( + -- clk => clk, + -- rstn => rstn, - Read => demux_ren, - EmptyF0a => sample_f0_0_empty, - EmptyF0b => sample_f0_0_empty, - EmptyF1 => sample_f1_empty, - EmptyF2 => sample_f3_empty, - DataF0a => sample_f0_0_rdata, - DataF0b => sample_f0_1_rdata, - DataF1 => sample_f1_rdata, - DataF2 => sample_f3_rdata, - Read_DEMUX => sample_ren, - Empty => demux_empty, - Data => demux_data); + -- Read => demux_ren, + -- EmptyF0a => sample_f0_0_empty, + -- EmptyF0b => sample_f0_0_empty, + -- EmptyF1 => sample_f1_empty, + -- EmptyF2 => sample_f3_empty, + -- DataF0a => sample_f0_0_rdata, + -- DataF0b => sample_f0_1_rdata, + -- DataF1 => sample_f1_rdata, + -- DataF2 => sample_f3_rdata, + -- Read_DEMUX => sample_ren, + -- Empty => demux_empty, + -- Data => demux_data); - FFT_1 : FFT - GENERIC MAP ( - Data_sz => 16, - NbData => 256) - PORT MAP ( - clkm => clk, - rstn => rstn, - FifoIN_Empty => demux_empty, - FifoIN_Data => demux_data, - FifoOUT_Full => fft_fifo_full, - Read => demux_ren, - Write => fft_fifo_wen, - ReUse => fft_fifo_reuse, - Data => fft_fifo_data); + --FFT_1 : FFT + -- GENERIC MAP ( + -- Data_sz => 16, + -- NbData => 256) + -- PORT MAP ( + -- clkm => clk, + -- rstn => rstn, + -- FifoIN_Empty => demux_empty, + -- FifoIN_Data => demux_data, + -- FifoOUT_Full => fft_fifo_full, + -- Read => demux_ren, + -- Write => fft_fifo_wen, + -- ReUse => fft_fifo_reuse, + -- Data => fft_fifo_data); - lppFIFO_fft : lppFIFOxN - GENERIC MAP ( - tech => tech, - Data_sz => 16, - FifoCnt => 5, - Enable_ReUse => '1') - PORT MAP ( - rst => rstn, - wclk => clk, - rclk => clk, - ReUse => fft_fifo_reuse, - wen => fft_fifo_wen, - ren => SP_fifo_ren, - wdata => fft_fifo_data, - rdata => SP_fifo_data, - full => fft_fifo_full, - empty => OPEN); + --lppFIFO_fft : lppFIFOxN + -- GENERIC MAP ( + -- tech => tech, + -- Data_sz => 16, + -- FifoCnt => 5, + -- Enable_ReUse => '1') + -- PORT MAP ( + -- rst => rstn, + -- wclk => clk, + -- rclk => clk, + -- ReUse => fft_fifo_reuse, + -- wen => fft_fifo_wen, + -- ren => SP_fifo_ren, + -- wdata => fft_fifo_data, + -- rdata => SP_fifo_data, + -- full => fft_fifo_full, + -- empty => OPEN); - MatriceSpectrale_1: MatriceSpectrale - GENERIC MAP ( - Input_SZ => 16, - Result_SZ => 32) - PORT MAP ( - clkm => clk, - rstn => rstn, - - FifoIN_Full => fft_fifo_full, - FifoOUT_Full => , -- TODO - Data_IN => SP_fifo_data, - ACQ => , -- TODO - FlagError => , -- TODO - Pong => , -- TODO - Write => , -- TODO - Read => SP_fifo_ren, - Data_OUT => ); -- TODO - + --MatriceSpectrale_1 : MatriceSpectrale + -- GENERIC MAP ( + -- Input_SZ => 16, + -- Result_SZ => 32) + -- PORT MAP ( + -- clkm => clk, + -- rstn => rstn, + + -- FifoIN_Full => fft_fifo_full, + -- FifoOUT_Full => , -- TODO + -- Data_IN => SP_fifo_data, + -- ACQ => , -- TODO + -- FlagError => , -- TODO + -- Pong => , -- TODO + -- Write => , -- TODO + -- Read => SP_fifo_ren, + -- Data_OUT => ); -- TODO + ----------------------------------------------------------------------------- -- DMA SPECTRAL MATRIX @@ -401,8 +413,73 @@ BEGIN addr_matrix_f2 => addr_matrix_f2); - --TODO : add the irq alert for DMA matrix transfert ending + ----------------------------------------------------------------------------- + -- WAVEFORM + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + delay_valid_waveform : PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + data_f0_in_valid <= '0'; + data_f1_in_valid <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN + data_f0_in_valid_r <= NOT sample_f0_wen; + data_f0_in_valid <= NOT data_f0_in_valid_r; + data_f1_in_valid <= NOT sample_f1_wen; + END IF; + END PROCESS delay_valid_waveform; + + data_f2_in_valid <= NOT sample_f2_wen; + data_f3_in_valid <= NOT sample_f3_wen; + + ----------------------------------------------------------------------------- + lpp_waveform_1 : lpp_waveform + GENERIC MAP ( + data_size => 16, + nb_snapshot_param_size => nb_snapshot_param_size, + delta_snapshot_size => delta_snapshot_size, + delta_f2_f0_size => delta_f2_f0_size, + delta_f2_f1_size => delta_f2_f1_size) + PORT MAP ( + clk => clk, + rstn => rstn, + + coarse_time_0 => coarse_time(0), + delta_snapshot => waveform_delta_snapshot, + delta_f2_f1 => waveform_delta_f2_f1, + delta_f2_f0 => waveform_delta_f2_f0, + + enable_f0 => waveform_enable_f0, + enable_f1 => waveform_enable_f1, + enable_f2 => waveform_enable_f2, + enable_f3 => waveform_enable_f3, + + burst_f0 => waveform_burst_f0, + burst_f1 => waveform_burst_f1, + burst_f2 => waveform_burst_f2, + + nb_snapshot_param => waveform_nb_snapshot_param, + + data_f0_in => sample_f0_wdata, + data_f1_in => sample_f1_wdata, + data_f2_in => sample_f2_wdata, + data_f3_in => sample_f3_wdata, + + data_f0_in_valid => data_f0_in_valid, + data_f1_in_valid => data_f1_in_valid, + data_f2_in_valid => data_f2_in_valid, + data_f3_in_valid => data_f3_in_valid); + + ----------------------------------------------------------------------------- + -- + ----------------------------------------------------------------------------- + + --DONE : add the irq alert for DMA matrix transfert ending + --TODO : add 5 bit register into APB to control the DATA SHIPING + --TODO : data shiping + --TODO : add Spectral Matrix (FFT + SP) --TODO : add DMA for WaveForms Picker --TODO : add APB Reg to control WaveForms Picker diff --git a/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd b/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd --- a/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd @@ -15,34 +15,47 @@ USE techmap.gencomp.ALL; PACKAGE lpp_top_lfr_pkg IS COMPONENT lpp_top_acq - GENERIC ( - tech : integer); - PORT ( - cnv_run : IN STD_LOGIC; - cnv : OUT STD_LOGIC; - sck : OUT STD_LOGIC; - sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - cnv_clk : IN STD_LOGIC; - cnv_rstn : IN STD_LOGIC; - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; - sample_f0_0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f0_1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0)); + GENERIC( + tech : INTEGER := 0 + ); + PORT ( + -- ADS7886 + cnv_run : IN STD_LOGIC; + cnv : OUT STD_LOGIC; + sck : OUT STD_LOGIC; + sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + -- + cnv_clk : IN STD_LOGIC; -- 49 MHz + cnv_rstn : IN STD_LOGIC; + -- + clk : IN STD_LOGIC; -- 25 MHz + rstn : IN STD_LOGIC; + -- + sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + -- + sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + -- + sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + -- + sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0) + ); END COMPONENT; COMPONENT lpp_top_apbreg GENERIC ( - pindex : INTEGER; - paddr : INTEGER; - pmask : INTEGER; - pirq : INTEGER); + nb_burst_available_size : INTEGER; + nb_snapshot_param_size : INTEGER; + delta_snapshot_size : INTEGER; + delta_f2_f0_size : INTEGER; + delta_f2_f1_size : INTEGER; + pindex : INTEGER; + paddr : INTEGER; + pmask : INTEGER; + pirq : INTEGER); PORT ( HCLK : IN STD_ULOGIC; HRESETn : IN STD_ULOGIC; @@ -66,7 +79,120 @@ PACKAGE lpp_top_lfr_pkg IS addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); + addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + data_shaping_BW : OUT STD_LOGIC; + data_shaping_SP0 : OUT STD_LOGIC; + data_shaping_SP1 : OUT STD_LOGIC; + data_shaping_R0 : OUT STD_LOGIC; + data_shaping_R1 : OUT STD_LOGIC; + delta_snapshot : OUT STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); + delta_f2_f1 : OUT STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); + delta_f2_f0 : OUT STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); + nb_burst_available : OUT STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); + nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); + enable_f0 : OUT STD_LOGIC; + enable_f1 : OUT STD_LOGIC; + enable_f2 : OUT STD_LOGIC; + enable_f3 : OUT STD_LOGIC; + burst_f0 : OUT STD_LOGIC; + burst_f1 : OUT STD_LOGIC; + burst_f2 : OUT STD_LOGIC; + addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); + END COMPONENT; + + COMPONENT lpp_top_lfr_wf_picker + GENERIC ( + hindex : INTEGER; + pindex : INTEGER; + paddr : INTEGER; + pmask : INTEGER; + pirq : INTEGER; + tech : INTEGER; + nb_burst_available_size : INTEGER; + nb_snapshot_param_size : INTEGER; + delta_snapshot_size : INTEGER; + delta_f2_f0_size : INTEGER; + delta_f2_f1_size : INTEGER); + PORT ( + cnv_run : IN STD_LOGIC; + cnv : OUT STD_LOGIC; + sck : OUT STD_LOGIC; + sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + cnv_clk : IN STD_LOGIC; + cnv_rstn : IN STD_LOGIC; + HCLK : IN STD_ULOGIC; + HRESETn : IN STD_ULOGIC; + apbi : IN apb_slv_in_type; + apbo : OUT apb_slv_out_type; + AHB_Master_In : IN AHB_Mst_In_Type; + AHB_Master_Out : OUT AHB_Mst_Out_Type; + coarse_time_0 : IN STD_LOGIC; + data_shaping_BW : OUT STD_LOGIC); END COMPONENT; -END lpp_top_lfr_pkg; \ No newline at end of file + + COMPONENT lpp_top_lfr_wf_picker_ip + GENERIC ( + hindex : INTEGER; + nb_burst_available_size : INTEGER; + nb_snapshot_param_size : INTEGER; + delta_snapshot_size : INTEGER; + delta_f2_f0_size : INTEGER; + delta_f2_f1_size : INTEGER; + tech : INTEGER); + PORT ( + cnv_run : IN STD_LOGIC; + cnv : OUT STD_LOGIC; + sck : OUT STD_LOGIC; + sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + cnv_clk : IN STD_LOGIC; + cnv_rstn : IN STD_LOGIC; + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + sample_f0_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); + sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + sample_f1_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); + sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + sample_f2_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); + sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + sample_f3_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); + sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + AHB_Master_In : IN AHB_Mst_In_Type; + AHB_Master_Out : OUT AHB_Mst_Out_Type; + coarse_time_0 : IN STD_LOGIC; + data_shaping_SP0 : IN STD_LOGIC; + data_shaping_SP1 : IN STD_LOGIC; + data_shaping_R0 : IN STD_LOGIC; + data_shaping_R1 : IN STD_LOGIC; + delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); + delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); + delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); + enable_f0 : IN STD_LOGIC; + enable_f1 : IN STD_LOGIC; + enable_f2 : IN STD_LOGIC; + enable_f3 : IN STD_LOGIC; + burst_f0 : IN STD_LOGIC; + burst_f1 : IN STD_LOGIC; + burst_f2 : IN STD_LOGIC; + nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); + nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); + status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); + END COMPONENT; + + + +END lpp_top_lfr_pkg; diff --git a/lib/lpp/lpp_top_lfr/lpp_top_lfr_wf_picker.vhd b/lib/lpp/lpp_top_lfr/lpp_top_lfr_wf_picker.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_top_lfr/lpp_top_lfr_wf_picker.vhd @@ -0,0 +1,243 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY lpp; +USE lpp.lpp_ad_conv.ALL; +USE lpp.iir_filter.ALL; +USE lpp.FILTERcfg.ALL; +USE lpp.lpp_memory.ALL; +USE lpp.lpp_waveform_pkg.ALL; +USE lpp.lpp_top_lfr_pkg.ALL; + +LIBRARY techmap; +USE techmap.gencomp.ALL; + +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; +USE GRLIB.DMA2AHB_Package.ALL; + +ENTITY lpp_top_lfr_wf_picker IS + GENERIC ( + hindex : INTEGER := 2; + pindex : INTEGER := 4; + paddr : INTEGER := 4; + pmask : INTEGER := 16#fff#; + pirq : INTEGER := 0; + tech : INTEGER := 0; + nb_burst_available_size : INTEGER := 11; + nb_snapshot_param_size : INTEGER := 11; + delta_snapshot_size : INTEGER := 16; + delta_f2_f0_size : INTEGER := 10; + delta_f2_f1_size : INTEGER := 10 + ); + PORT ( + -- ADS7886 + cnv_run : IN STD_LOGIC; + cnv : OUT STD_LOGIC; + sck : OUT STD_LOGIC; + sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + -- + cnv_clk : IN STD_LOGIC; + cnv_rstn : IN STD_LOGIC; + + -- AMBA AHB system signals + HCLK : IN STD_ULOGIC; + HRESETn : IN STD_ULOGIC; + + -- AMBA APB Slave Interface + apbi : IN apb_slv_in_type; + apbo : OUT apb_slv_out_type; + + -- AMBA AHB Master Interface + AHB_Master_In : IN AHB_Mst_In_Type; + AHB_Master_Out : OUT AHB_Mst_Out_Type; + + -- + coarse_time_0 : IN STD_LOGIC; + + -- + data_shaping_BW : OUT STD_LOGIC + ); +END lpp_top_lfr_wf_picker; + +ARCHITECTURE tb OF lpp_top_lfr_wf_picker IS + + SIGNAL ready_matrix_f0_0 : STD_LOGIC; + SIGNAL ready_matrix_f0_1 : STD_LOGIC; + SIGNAL ready_matrix_f1 : STD_LOGIC; + SIGNAL ready_matrix_f2 : STD_LOGIC; + SIGNAL error_anticipating_empty_fifo : STD_LOGIC; + SIGNAL error_bad_component_error : STD_LOGIC; + SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL status_ready_matrix_f0_0 : STD_LOGIC; + SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; + SIGNAL status_ready_matrix_f1 : STD_LOGIC; + SIGNAL status_ready_matrix_f2 : STD_LOGIC; + SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC; + SIGNAL status_error_bad_component_error : STD_LOGIC; + SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC; + SIGNAL config_active_interruption_onError : STD_LOGIC; + SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); + + SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL data_shaping_SP0 : STD_LOGIC; + SIGNAL data_shaping_SP1 : STD_LOGIC; + SIGNAL data_shaping_R0 : STD_LOGIC; + SIGNAL data_shaping_R1 : STD_LOGIC; + SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); + SIGNAL delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); + SIGNAL delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); + SIGNAL nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); + SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); + SIGNAL enable_f0 : STD_LOGIC; + SIGNAL enable_f1 : STD_LOGIC; + SIGNAL enable_f2 : STD_LOGIC; + SIGNAL enable_f3 : STD_LOGIC; + SIGNAL burst_f0 : STD_LOGIC; + SIGNAL burst_f1 : STD_LOGIC; + SIGNAL burst_f2 : STD_LOGIC; + SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); + + SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); + SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); + SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); + SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); + SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + + +BEGIN + + lpp_top_apbreg_1: lpp_top_apbreg + GENERIC MAP ( + nb_burst_available_size => nb_burst_available_size, + nb_snapshot_param_size => nb_snapshot_param_size, + delta_snapshot_size => delta_snapshot_size, + delta_f2_f0_size => delta_f2_f0_size, + delta_f2_f1_size => delta_f2_f1_size, + pindex => pindex, + paddr => paddr, + pmask => pmask, + pirq => pirq) + PORT MAP ( + HCLK => HCLK, + HRESETn => HRESETn, + apbi => apbi, + apbo => apbo, + + ready_matrix_f0_0 => ready_matrix_f0_0, + ready_matrix_f0_1 => ready_matrix_f0_1, + ready_matrix_f1 => ready_matrix_f1, + ready_matrix_f2 => ready_matrix_f2, + error_anticipating_empty_fifo => error_anticipating_empty_fifo, + error_bad_component_error => error_bad_component_error, + debug_reg => debug_reg, + status_ready_matrix_f0_0 => status_ready_matrix_f0_0, + status_ready_matrix_f0_1 => status_ready_matrix_f0_1, + status_ready_matrix_f1 => status_ready_matrix_f1, + status_ready_matrix_f2 => status_ready_matrix_f2, + status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, + status_error_bad_component_error => status_error_bad_component_error, + config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, + config_active_interruption_onError => config_active_interruption_onError, + addr_matrix_f0_0 => addr_matrix_f0_0, + addr_matrix_f0_1 => addr_matrix_f0_1, + addr_matrix_f1 => addr_matrix_f1, + addr_matrix_f2 => addr_matrix_f2, + + status_full => status_full, + status_full_ack => status_full_ack, + status_full_err => status_full_err, + status_new_err => status_new_err, + data_shaping_BW => data_shaping_BW, + data_shaping_SP0 => data_shaping_SP0, + data_shaping_SP1 => data_shaping_SP1, + data_shaping_R0 => data_shaping_R0, + data_shaping_R1 => data_shaping_R1, + delta_snapshot => delta_snapshot, + delta_f2_f1 => delta_f2_f1, + delta_f2_f0 => delta_f2_f0, + nb_burst_available => nb_burst_available, + nb_snapshot_param => nb_snapshot_param, + enable_f0 => enable_f0, + enable_f1 => enable_f1, + enable_f2 => enable_f2, + enable_f3 => enable_f3, + burst_f0 => burst_f0, + burst_f1 => burst_f1, + burst_f2 => burst_f2, + addr_data_f0 => addr_data_f0, + addr_data_f1 => addr_data_f1, + addr_data_f2 => addr_data_f2, + addr_data_f3 => addr_data_f3); + + lpp_top_lfr_wf_picker_ip_1: lpp_top_lfr_wf_picker_ip + GENERIC MAP ( + hindex => hindex, + nb_burst_available_size => nb_burst_available_size, + nb_snapshot_param_size => nb_snapshot_param_size, + delta_snapshot_size => delta_snapshot_size, + delta_f2_f0_size => delta_f2_f0_size, + delta_f2_f1_size => delta_f2_f1_size, + tech => tech) + PORT MAP ( + cnv_run => cnv_run, + cnv => cnv, + sck => sck, + sdo => sdo, + cnv_clk => cnv_clk, + cnv_rstn => cnv_rstn, + + clk => HCLK, + rstn => HRESETn, + + sample_f0_wen => sample_f0_wen, + sample_f0_wdata => sample_f0_wdata, + sample_f1_wen => sample_f1_wen, + sample_f1_wdata => sample_f1_wdata, + sample_f2_wen => sample_f2_wen, + sample_f2_wdata => sample_f2_wdata, + sample_f3_wen => sample_f3_wen, + sample_f3_wdata => sample_f3_wdata, + AHB_Master_In => AHB_Master_In, + AHB_Master_Out => AHB_Master_Out, + coarse_time_0 => coarse_time_0, + data_shaping_SP0 => data_shaping_SP0, + data_shaping_SP1 => data_shaping_SP1, + data_shaping_R0 => data_shaping_R0, + data_shaping_R1 => data_shaping_R1, + delta_snapshot => delta_snapshot, + delta_f2_f1 => delta_f2_f1, + delta_f2_f0 => delta_f2_f0, + enable_f0 => enable_f0, + enable_f1 => enable_f1, + enable_f2 => enable_f2, + enable_f3 => enable_f3, + burst_f0 => burst_f0, + burst_f1 => burst_f1, + burst_f2 => burst_f2, + nb_burst_available => nb_burst_available, + nb_snapshot_param => nb_snapshot_param, + status_full => status_full, + status_full_ack => status_full_ack, + status_full_err => status_full_err, + status_new_err => status_new_err, + addr_data_f0 => addr_data_f0, + addr_data_f1 => addr_data_f1, + addr_data_f2 => addr_data_f2, + addr_data_f3 => addr_data_f3); +END tb; diff --git a/lib/lpp/lpp_top_lfr/lpp_top_lfr_wf_picker_ip.vhd b/lib/lpp/lpp_top_lfr/lpp_top_lfr_wf_picker_ip.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_top_lfr/lpp_top_lfr_wf_picker_ip.vhd @@ -0,0 +1,498 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY lpp; +USE lpp.lpp_ad_conv.ALL; +USE lpp.iir_filter.ALL; +USE lpp.FILTERcfg.ALL; +USE lpp.lpp_memory.ALL; +USE lpp.lpp_waveform_pkg.ALL; + +LIBRARY techmap; +USE techmap.gencomp.ALL; + +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; +USE GRLIB.DMA2AHB_Package.ALL; + +ENTITY lpp_top_lfr_wf_picker_ip IS + GENERIC( + hindex : INTEGER := 2; + nb_burst_available_size : INTEGER := 11; + nb_snapshot_param_size : INTEGER := 11; + delta_snapshot_size : INTEGER := 16; + delta_f2_f0_size : INTEGER := 10; + delta_f2_f1_size : INTEGER := 10; + tech : INTEGER := 0 + ); + PORT ( + -- ADS7886 + cnv_run : IN STD_LOGIC; + cnv : OUT STD_LOGIC; + sck : OUT STD_LOGIC; + sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + -- + cnv_clk : IN STD_LOGIC; + cnv_rstn : IN STD_LOGIC; + -- + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + -- + sample_f0_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); + sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + -- + sample_f1_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); + sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + -- + sample_f2_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); + sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + -- + sample_f3_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); + sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + + -- AMBA AHB Master Interface + AHB_Master_In : IN AHB_Mst_In_Type; + AHB_Master_Out : OUT AHB_Mst_Out_Type; + + coarse_time_0 : IN STD_LOGIC; + + --config + data_shaping_SP0 : IN STD_LOGIC; + data_shaping_SP1 : IN STD_LOGIC; + data_shaping_R0 : IN STD_LOGIC; + data_shaping_R1 : IN STD_LOGIC; + + delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); + delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); + delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); + + enable_f0 : IN STD_LOGIC; + enable_f1 : IN STD_LOGIC; + enable_f2 : IN STD_LOGIC; + enable_f3 : IN STD_LOGIC; + + burst_f0 : IN STD_LOGIC; + burst_f1 : IN STD_LOGIC; + burst_f2 : IN STD_LOGIC; + + nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); + nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); + status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma + + addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END lpp_top_lfr_wf_picker_ip; + +ARCHITECTURE tb OF lpp_top_lfr_wf_picker_ip IS + + COMPONENT Downsampling + GENERIC ( + ChanelCount : INTEGER; + SampleSize : INTEGER; + DivideParam : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + sample_in_val : IN STD_LOGIC; + sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0); + sample_out_val : OUT STD_LOGIC; + sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0)); + END COMPONENT; + + ----------------------------------------------------------------------------- + CONSTANT ChanelCount : INTEGER := 8; + CONSTANT ncycle_cnv_high : INTEGER := 79; + CONSTANT ncycle_cnv : INTEGER := 500; + + ----------------------------------------------------------------------------- + SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0); + SIGNAL sample_val : STD_LOGIC; + SIGNAL sample_val_delay : STD_LOGIC; + ----------------------------------------------------------------------------- + CONSTANT Coef_SZ : INTEGER := 9; + CONSTANT CoefCntPerCel : INTEGER := 6; + CONSTANT CoefPerCel : INTEGER := 5; + CONSTANT Cels_count : INTEGER := 5; + + SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0); + SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0); + SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); + SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); + -- + SIGNAL sample_filter_v2_out_val : STD_LOGIC; + SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); + ----------------------------------------------------------------------------- + SIGNAL sample_data_shaping_out_val : STD_LOGIC; + SIGNAL sample_data_shaping_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); + SIGNAL sample_data_shaping_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0); + SIGNAL sample_data_shaping_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0); + SIGNAL sample_data_shaping_f2_s : STD_LOGIC_VECTOR(17 DOWNTO 0); + SIGNAL sample_data_shaping_f1_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0); + SIGNAL sample_data_shaping_f2_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0); + ----------------------------------------------------------------------------- + SIGNAL sample_filter_v2_out_val_s : STD_LOGIC; + SIGNAL sample_filter_v2_out_s : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0); + ----------------------------------------------------------------------------- + SIGNAL sample_f0_val : STD_LOGIC; + SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0); + SIGNAL sample_f0_s : samplT(5 DOWNTO 0, 15 DOWNTO 0); + -- + SIGNAL sample_f1_val : STD_LOGIC; + SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0); + SIGNAL sample_f1_s : samplT(5 DOWNTO 0, 15 DOWNTO 0); + -- + SIGNAL sample_f2_val : STD_LOGIC; + SIGNAL sample_f2 : samplT(5 DOWNTO 0, 15 DOWNTO 0); + -- + SIGNAL sample_f3_val : STD_LOGIC; + SIGNAL sample_f3 : samplT(5 DOWNTO 0, 15 DOWNTO 0); + + ----------------------------------------------------------------------------- + SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); + SIGNAL data_f1_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); + SIGNAL data_f2_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); + SIGNAL data_f3_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); + ----------------------------------------------------------------------------- + + SIGNAL sample_f0_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + SIGNAL sample_f1_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + SIGNAL sample_f2_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + SIGNAL sample_f3_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); +BEGIN + + -- component instantiation + ----------------------------------------------------------------------------- + DIGITAL_acquisition : AD7688_drvr + GENERIC MAP ( + ChanelCount => ChanelCount, + ncycle_cnv_high => ncycle_cnv_high, + ncycle_cnv => ncycle_cnv) + PORT MAP ( + cnv_clk => cnv_clk, -- + cnv_rstn => cnv_rstn, -- + cnv_run => cnv_run, -- + cnv => cnv, -- + clk => clk, -- + rstn => rstn, -- + sck => sck, -- + sdo => sdo(ChanelCount-1 DOWNTO 0), -- + sample => sample, + sample_val => sample_val); + + ----------------------------------------------------------------------------- + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + sample_val_delay <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + sample_val_delay <= sample_val; + END IF; + END PROCESS; + + ----------------------------------------------------------------------------- + ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE + SampleLoop : FOR j IN 0 TO 15 GENERATE + sample_filter_in(i, j) <= sample(i)(j); + END GENERATE; + + sample_filter_in(i, 16) <= sample(i)(15); + sample_filter_in(i, 17) <= sample(i)(15); + END GENERATE; + + coefs_v2 <= CoefsInitValCst_v2; + + IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 + GENERIC MAP ( + tech => 0, + Mem_use => use_CEL, -- use_RAM + Sample_SZ => 18, + Coef_SZ => Coef_SZ, + Coef_Nb => 25, + Coef_sel_SZ => 5, + Cels_count => Cels_count, + ChanelsCount => ChanelCount) + PORT MAP ( + rstn => rstn, + clk => clk, + virg_pos => 7, + coefs => coefs_v2, + sample_in_val => sample_val_delay, + sample_in => sample_filter_in, + sample_out_val => sample_filter_v2_out_val, + sample_out => sample_filter_v2_out); + + ----------------------------------------------------------------------------- + -- DATA_SHAPING + ----------------------------------------------------------------------------- + all_data_shaping_in_loop: FOR I IN 17 DOWNTO 0 GENERATE + sample_data_shaping_f0_s(I) <= sample_filter_v2_out(0,I); + sample_data_shaping_f1_s(I) <= sample_filter_v2_out(1,I); + sample_data_shaping_f2_s(I) <= sample_filter_v2_out(2,I); + END GENERATE all_data_shaping_in_loop; + + sample_data_shaping_f1_f0_s <= sample_data_shaping_f1_s - sample_data_shaping_f0_s; + sample_data_shaping_f2_f1_s <= sample_data_shaping_f2_s - sample_data_shaping_f1_s; + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + sample_data_shaping_out_val <= '0'; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + sample_data_shaping_out_val <= sample_filter_v2_out_val; + END IF; + END PROCESS; + + SampleLoop_data_shaping: FOR j IN 0 TO 17 GENERATE + PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + sample_data_shaping_out(0,j) <= '0'; + sample_data_shaping_out(1,j) <= '0'; + sample_data_shaping_out(2,j) <= '0'; + sample_data_shaping_out(3,j) <= '0'; + sample_data_shaping_out(4,j) <= '0'; + sample_data_shaping_out(5,j) <= '0'; + sample_data_shaping_out(6,j) <= '0'; + sample_data_shaping_out(7,j) <= '0'; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + sample_data_shaping_out(0,j) <= sample_filter_v2_out(0,j); + IF data_shaping_SP0 = '1' THEN + sample_data_shaping_out(1,j) <= sample_data_shaping_f1_f0_s(j); + ELSE + sample_data_shaping_out(1,j) <= sample_filter_v2_out(1,j); + END IF; + IF data_shaping_SP1 = '1' THEN + sample_data_shaping_out(2,j) <= sample_data_shaping_f2_f1_s(j); + ELSE + sample_data_shaping_out(2,j) <= sample_filter_v2_out(2,j); + END IF; + sample_data_shaping_out(4,j) <= sample_filter_v2_out(4,j); + sample_data_shaping_out(5,j) <= sample_filter_v2_out(5,j); + sample_data_shaping_out(6,j) <= sample_filter_v2_out(6,j); + sample_data_shaping_out(7,j) <= sample_filter_v2_out(7,j); + END IF; + END PROCESS; + END GENERATE; + + sample_filter_v2_out_val_s <= sample_data_shaping_out_val; + ChanelLoopOut : FOR i IN 0 TO 7 GENERATE + SampleLoopOut : FOR j IN 0 TO 15 GENERATE + sample_filter_v2_out_s(i,j) <= sample_data_shaping_out(i,j); + END GENERATE; + END GENERATE; + ----------------------------------------------------------------------------- + -- F0 -- @24.576 kHz + ----------------------------------------------------------------------------- + Downsampling_f0 : Downsampling + GENERIC MAP ( + ChanelCount => 8, + SampleSize => 16, + DivideParam => 4) + PORT MAP ( + clk => clk, + rstn => rstn, + sample_in_val => sample_filter_v2_out_val_s, + sample_in => sample_filter_v2_out_s, + sample_out_val => sample_f0_val, + sample_out => sample_f0); + + all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE + sample_f0_wdata_s(I) <= sample_f0(0, I); -- V + sample_f0_wdata_s(16*1+I) <= sample_f0(1, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(3, I); -- E1 + sample_f0_wdata_s(16*2+I) <= sample_f0(2, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(4, I); -- E2 + sample_f0_wdata_s(16*3+I) <= sample_f0(5, I); -- B1 + sample_f0_wdata_s(16*4+I) <= sample_f0(6, I); -- B2 + sample_f0_wdata_s(16*5+I) <= sample_f0(7, I); -- B3 + END GENERATE all_bit_sample_f0; + + sample_f0_wen <= NOT(sample_f0_val) & + NOT(sample_f0_val) & + NOT(sample_f0_val) & + NOT(sample_f0_val) & + NOT(sample_f0_val) & + NOT(sample_f0_val); + + ----------------------------------------------------------------------------- + -- F1 -- @4096 Hz + ----------------------------------------------------------------------------- + Downsampling_f1 : Downsampling + GENERIC MAP ( + ChanelCount => 8, + SampleSize => 16, + DivideParam => 6) + PORT MAP ( + clk => clk, + rstn => rstn, + sample_in_val => sample_f0_val , + sample_in => sample_f0, + sample_out_val => sample_f1_val, + sample_out => sample_f1); + + all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE + sample_f1_wdata_s(I) <= sample_f1(0, I); -- V + sample_f1_wdata_s(16*1+I) <= sample_f1(1, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(3, I); -- E1 + sample_f1_wdata_s(16*2+I) <= sample_f1(2, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(4, I); -- E2 + sample_f1_wdata_s(16*3+I) <= sample_f1(5, I); -- B1 + sample_f1_wdata_s(16*4+I) <= sample_f1(6, I); -- B2 + sample_f1_wdata_s(16*5+I) <= sample_f1(7, I); -- B3 + END GENERATE all_bit_sample_f1; + + sample_f1_wen <= NOT(sample_f1_val) & + NOT(sample_f1_val) & + NOT(sample_f1_val) & + NOT(sample_f1_val) & + NOT(sample_f1_val) & + NOT(sample_f1_val); + + ----------------------------------------------------------------------------- + -- F2 -- @256 Hz + ----------------------------------------------------------------------------- + all_bit_sample_f0_s : FOR I IN 15 DOWNTO 0 GENERATE + sample_f0_s(0, I) <= sample_f0(0, I); -- V + sample_f0_s(1, I) <= sample_f0(1, I); -- E1 + sample_f0_s(2, I) <= sample_f0(2, I); -- E2 + sample_f0_s(3, I) <= sample_f0(5, I); -- B1 + sample_f0_s(4, I) <= sample_f0(6, I); -- B2 + sample_f0_s(5, I) <= sample_f0(7, I); -- B3 + END GENERATE all_bit_sample_f0_s; + + Downsampling_f2 : Downsampling + GENERIC MAP ( + ChanelCount => 6, + SampleSize => 16, + DivideParam => 96) + PORT MAP ( + clk => clk, + rstn => rstn, + sample_in_val => sample_f0_val , + sample_in => sample_f0_s, + sample_out_val => sample_f2_val, + sample_out => sample_f2); + + sample_f2_wen <= NOT(sample_f2_val) & + NOT(sample_f2_val) & + NOT(sample_f2_val) & + NOT(sample_f2_val) & + NOT(sample_f2_val) & + NOT(sample_f2_val); + + all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE + sample_f2_wdata_s(I) <= sample_f2(0, I); + sample_f2_wdata_s(16*1+I) <= sample_f2(1, I); + sample_f2_wdata_s(16*2+I) <= sample_f2(2, I); + sample_f2_wdata_s(16*3+I) <= sample_f2(3, I); + sample_f2_wdata_s(16*4+I) <= sample_f2(4, I); + sample_f2_wdata_s(16*5+I) <= sample_f2(5, I); + END GENERATE all_bit_sample_f2; + + ----------------------------------------------------------------------------- + -- F3 -- @16 Hz + ----------------------------------------------------------------------------- + all_bit_sample_f1_s : FOR I IN 15 DOWNTO 0 GENERATE + sample_f1_s(0, I) <= sample_f1(0, I); -- V + sample_f1_s(1, I) <= sample_f1(1, I); -- E1 + sample_f1_s(2, I) <= sample_f1(2, I); -- E2 + sample_f1_s(3, I) <= sample_f1(5, I); -- B1 + sample_f1_s(4, I) <= sample_f1(6, I); -- B2 + sample_f1_s(5, I) <= sample_f1(7, I); -- B3 + END GENERATE all_bit_sample_f1_s; + + Downsampling_f3 : Downsampling + GENERIC MAP ( + ChanelCount => 6, + SampleSize => 16, + DivideParam => 256) + PORT MAP ( + clk => clk, + rstn => rstn, + sample_in_val => sample_f1_val , + sample_in => sample_f1_s, + sample_out_val => sample_f3_val, + sample_out => sample_f3); + + sample_f3_wen <= (NOT sample_f3_val) & + (NOT sample_f3_val) & + (NOT sample_f3_val) & + (NOT sample_f3_val) & + (NOT sample_f3_val) & + (NOT sample_f3_val); + + all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE + sample_f3_wdata_s(I) <= sample_f3(0, I); + sample_f3_wdata_s(16*1+I) <= sample_f3(1, I); + sample_f3_wdata_s(16*2+I) <= sample_f3(2, I); + sample_f3_wdata_s(16*3+I) <= sample_f3(3, I); + sample_f3_wdata_s(16*4+I) <= sample_f3(4, I); + sample_f3_wdata_s(16*5+I) <= sample_f3(5, I); + END GENERATE all_bit_sample_f3; + + lpp_waveform_1 : lpp_waveform + GENERIC MAP ( + hindex => hindex, + tech => tech, + data_size => 160, + nb_burst_available_size => nb_burst_available_size, + nb_snapshot_param_size => nb_snapshot_param_size, + delta_snapshot_size => delta_snapshot_size, + delta_f2_f0_size => delta_f2_f0_size, + delta_f2_f1_size => delta_f2_f1_size) + PORT MAP ( + clk => clk, + rstn => rstn, + + AHB_Master_In => AHB_Master_In, + AHB_Master_Out => AHB_Master_Out, + + coarse_time_0 => coarse_time_0, -- IN + delta_snapshot => delta_snapshot, -- IN + delta_f2_f1 => delta_f2_f1, -- IN + delta_f2_f0 => delta_f2_f0, -- IN + enable_f0 => enable_f0, -- IN + enable_f1 => enable_f1, -- IN + enable_f2 => enable_f2, -- IN + enable_f3 => enable_f3, -- IN + burst_f0 => burst_f0, -- IN + burst_f1 => burst_f1, -- IN + burst_f2 => burst_f2, -- IN + nb_burst_available => nb_burst_available, + nb_snapshot_param => nb_snapshot_param, + status_full => status_full, + status_full_ack => status_full_ack, -- IN + status_full_err => status_full_err, + status_new_err => status_new_err, + + addr_data_f0 => addr_data_f0, -- IN + addr_data_f1 => addr_data_f1, -- IN + addr_data_f2 => addr_data_f2, -- IN + addr_data_f3 => addr_data_f3, -- IN + + data_f0_in => data_f0_in_valid, + data_f1_in => data_f1_in_valid, + data_f2_in => data_f2_in_valid, + data_f3_in => data_f3_in_valid, + data_f0_in_valid => sample_f0_val, + data_f1_in_valid => sample_f1_val, + data_f2_in_valid => sample_f2_val, + data_f3_in_valid => sample_f3_val); + + data_f0_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f0_wdata_s; + data_f1_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f1_wdata_s; + data_f2_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f2_wdata_s; + data_f3_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f3_wdata_s; + + sample_f0_wdata <= sample_f0_wdata_s; + sample_f1_wdata <= sample_f1_wdata_s; + sample_f2_wdata <= sample_f2_wdata_s; + sample_f3_wdata <= sample_f3_wdata_s; + +END tb; diff --git a/lib/lpp/lpp_waveform/lpp_waveform.vhd b/lib/lpp/lpp_waveform/lpp_waveform.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_waveform/lpp_waveform.vhd @@ -0,0 +1,277 @@ +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; +USE GRLIB.DMA2AHB_Package.ALL; + +LIBRARY lpp; +USE lpp.lpp_waveform_pkg.ALL; + +LIBRARY techmap; +USE techmap.gencomp.ALL; + +ENTITY lpp_waveform IS + + GENERIC ( + hindex : INTEGER := 2; + tech : INTEGER := inferred; + data_size : INTEGER := 160; + nb_burst_available_size : INTEGER := 11; + nb_snapshot_param_size : INTEGER := 11; + delta_snapshot_size : INTEGER := 16; + delta_f2_f0_size : INTEGER := 10; + delta_f2_f1_size : INTEGER := 10); + + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + + -- AMBA AHB Master Interface + AHB_Master_In : IN AHB_Mst_In_Type; + AHB_Master_Out : OUT AHB_Mst_Out_Type; + + coarse_time_0 : IN STD_LOGIC; + + --config + delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); + delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); + delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); + + enable_f0 : IN STD_LOGIC; + enable_f1 : IN STD_LOGIC; + enable_f2 : IN STD_LOGIC; + enable_f3 : IN STD_LOGIC; + + burst_f0 : IN STD_LOGIC; + burst_f1 : IN STD_LOGIC; + burst_f2 : IN STD_LOGIC; + + nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); + nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); + status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma + addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + + data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + + data_f0_in_valid : IN STD_LOGIC; + data_f1_in_valid : IN STD_LOGIC; + data_f2_in_valid : IN STD_LOGIC; + data_f3_in_valid : IN STD_LOGIC + ); + +END lpp_waveform; + +ARCHITECTURE beh OF lpp_waveform IS + SIGNAL start_snapshot_f0 : STD_LOGIC; + SIGNAL start_snapshot_f1 : STD_LOGIC; + SIGNAL start_snapshot_f2 : STD_LOGIC; + + SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + + SIGNAL data_f0_out_valid : STD_LOGIC; + SIGNAL data_f1_out_valid : STD_LOGIC; + SIGNAL data_f2_out_valid : STD_LOGIC; + SIGNAL data_f3_out_valid : STD_LOGIC; + SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0); + + -- + SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL ready : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0); + -- + SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0); + +BEGIN -- beh + + lpp_waveform_snapshot_controler_1: lpp_waveform_snapshot_controler + GENERIC MAP ( + delta_snapshot_size => delta_snapshot_size, + delta_f2_f0_size => delta_f2_f0_size, + delta_f2_f1_size => delta_f2_f1_size) + PORT MAP ( + clk => clk, + rstn => rstn, + delta_snapshot => delta_snapshot, + delta_f2_f1 => delta_f2_f1, + delta_f2_f0 => delta_f2_f0, + coarse_time_0 => coarse_time_0, + data_f0_in_valid => data_f0_in_valid, + data_f2_in_valid => data_f2_in_valid, + start_snapshot_f0 => start_snapshot_f0, + start_snapshot_f1 => start_snapshot_f1, + start_snapshot_f2 => start_snapshot_f2); + + lpp_waveform_snapshot_f0 : lpp_waveform_snapshot + GENERIC MAP ( + data_size => data_size, + nb_snapshot_param_size => nb_snapshot_param_size) + PORT MAP ( + clk => clk, + rstn => rstn, + enable => enable_f0, + burst_enable => burst_f0, + nb_snapshot_param => nb_snapshot_param, + start_snapshot => start_snapshot_f0, + data_in => data_f0_in, + data_in_valid => data_f0_in_valid, + data_out => data_f0_out, + data_out_valid => data_f0_out_valid); + + nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) + 1; + + lpp_waveform_snapshot_f1 : lpp_waveform_snapshot + GENERIC MAP ( + data_size => data_size, + nb_snapshot_param_size => nb_snapshot_param_size+1) + PORT MAP ( + clk => clk, + rstn => rstn, + enable => enable_f1, + burst_enable => burst_f1, + nb_snapshot_param => nb_snapshot_param_more_one, + start_snapshot => start_snapshot_f1, + data_in => data_f1_in, + data_in_valid => data_f1_in_valid, + data_out => data_f1_out, + data_out_valid => data_f1_out_valid); + + lpp_waveform_snapshot_f2 : lpp_waveform_snapshot + GENERIC MAP ( + data_size => data_size, + nb_snapshot_param_size => nb_snapshot_param_size+1) + PORT MAP ( + clk => clk, + rstn => rstn, + enable => enable_f2, + burst_enable => burst_f2, + nb_snapshot_param => nb_snapshot_param_more_one, + start_snapshot => start_snapshot_f2, + data_in => data_f2_in, + data_in_valid => data_f2_in_valid, + data_out => data_f2_out, + data_out_valid => data_f2_out_valid); + + lpp_waveform_burst_f3: lpp_waveform_burst + GENERIC MAP ( + data_size => data_size) + PORT MAP ( + clk => clk, + rstn => rstn, + enable => enable_f3, + data_in => data_f3_in, + data_in_valid => data_f3_in_valid, + data_out => data_f3_out, + data_out_valid => data_f3_out_valid); + + + valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid; + + all_input_valid: FOR i IN 3 DOWNTO 0 GENERATE + lpp_waveform_dma_gen_valid_I: lpp_waveform_dma_gen_valid + PORT MAP ( + HCLK => clk, + HRESETn => rstn, + valid_in => valid_in(I), + ack_in => valid_ack(I), + valid_out => valid_out(I), + error => status_new_err(I)); + END GENERATE all_input_valid; + + lpp_waveform_fifo_arbiter_1: lpp_waveform_fifo_arbiter + GENERIC MAP (tech => tech) + PORT MAP ( + clk => clk, + rstn => rstn, + data_f0_valid => valid_out(0), + data_f1_valid => valid_out(1), + data_f2_valid => valid_out(2), + data_f3_valid => valid_out(3), + + data_valid_ack => valid_ack, + + data_f0 => data_f0_out, + data_f1 => data_f1_out, + data_f2 => data_f2_out, + data_f3 => data_f3_out, + + ready => ready_arb, + time_wen => time_wen, + data_wen => data_wen, + data => wdata); + + ready_arb <= NOT ready; + + lpp_waveform_fifo_1: lpp_waveform_fifo + GENERIC MAP (tech => tech) + PORT MAP ( + clk => clk, + rstn => rstn, + ready => ready, + time_ren => time_ren, -- todo + data_ren => data_ren, -- todo + rdata => rdata, -- todo + + time_wen => time_wen, + data_wen => data_wen, + wdata => wdata); + + --time_ren <= (OTHERS => '1'); + --data_ren <= (OTHERS => '1'); + + pp_waveform_dma_1: lpp_waveform_dma + GENERIC MAP ( + data_size => data_size, + tech => tech, + hindex => hindex, + nb_burst_available_size => nb_burst_available_size) + PORT MAP ( + HCLK => clk, + HRESETn => rstn, + AHB_Master_In => AHB_Master_In, + AHB_Master_Out => AHB_Master_Out, + data_ready => ready, + data => rdata, + data_data_ren => data_ren, + data_time_ren => time_ren, + --data_f0_in => data_f0_out, + --data_f1_in => data_f1_out, + --data_f2_in => data_f2_out, + --data_f3_in => data_f3_out, + --data_f0_in_valid => data_f0_out_valid, + --data_f1_in_valid => data_f1_out_valid, + --data_f2_in_valid => data_f2_out_valid, + --data_f3_in_valid => data_f3_out_valid, + nb_burst_available => nb_burst_available, + status_full => status_full, + status_full_ack => status_full_ack, + status_full_err => status_full_err, +-- status_new_err => status_new_err, + addr_data_f0 => addr_data_f0, + addr_data_f1 => addr_data_f1, + addr_data_f2 => addr_data_f2, + addr_data_f3 => addr_data_f3); + +END beh; diff --git a/lib/lpp/lpp_waveform/lpp_waveform_burst.vhd b/lib/lpp/lpp_waveform/lpp_waveform_burst.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_waveform/lpp_waveform_burst.vhd @@ -0,0 +1,42 @@ +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; + +ENTITY lpp_waveform_burst IS + + GENERIC ( + data_size : INTEGER := 16); + + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + + enable : IN STD_LOGIC; + + data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + data_in_valid : IN STD_LOGIC; + + data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + data_out_valid : OUT STD_LOGIC + ); + +END lpp_waveform_burst; + +ARCHITECTURE beh OF lpp_waveform_burst IS +BEGIN -- beh + + PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + data_out <= (OTHERS => '0'); + data_out_valid <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN + data_out <= data_in; + IF enable = '0' THEN + data_out_valid <= '0'; + ELSE + data_out_valid <= data_in_valid; + END IF; + END IF; + END PROCESS; + +END beh; diff --git a/lib/lpp/lpp_waveform/lpp_waveform_dma.vhd b/lib/lpp/lpp_waveform/lpp_waveform_dma.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_waveform/lpp_waveform_dma.vhd @@ -0,0 +1,363 @@ + +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +-- jean-christophe.pellion@easii-ic.com +------------------------------------------------------------------------------- +-- 1.0 - initial version +-- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS) +------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; +USE GRLIB.DMA2AHB_Package.ALL; +LIBRARY lpp; +USE lpp.lpp_amba.ALL; +USE lpp.apb_devices_list.ALL; +USE lpp.lpp_memory.ALL; +USE lpp.lpp_dma_pkg.ALL; +USE lpp.lpp_waveform_pkg.ALL; +LIBRARY techmap; +USE techmap.gencomp.ALL; + + +ENTITY lpp_waveform_dma IS + GENERIC ( + data_size : INTEGER := 160; + tech : INTEGER := inferred; + hindex : INTEGER := 2; + nb_burst_available_size : INTEGER := 11 + ); + PORT ( + -- AMBA AHB system signals + HCLK : IN STD_ULOGIC; + HRESETn : IN STD_ULOGIC; + -- AMBA AHB Master Interface + AHB_Master_In : IN AHB_Mst_In_Type; + AHB_Master_Out : OUT AHB_Mst_Out_Type; + -- + data_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo + data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo + data_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo + data_time_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo + -- Reg + nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); + status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); +-- status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma + addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END; + +ARCHITECTURE Behavioral OF lpp_waveform_dma IS + ----------------------------------------------------------------------------- + SIGNAL DMAIn : DMA_In_Type; + SIGNAL DMAOut : DMA_OUt_Type; + ----------------------------------------------------------------------------- + TYPE state_DMAWriteBurst IS (IDLE, + SEND_TIME_0, WAIT_TIME_0, + SEND_TIME_1, WAIT_TIME_1, + SEND_5_TIME, + SEND_DATA, WAIT_DATA); + SIGNAL state : state_DMAWriteBurst := IDLE; + ----------------------------------------------------------------------------- + -- CONTROL + SIGNAL sel_data_s : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL sel_data : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL update : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL time_select : STD_LOGIC; + SIGNAL time_write : STD_LOGIC; + SIGNAL time_already_send : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL time_already_send_s : STD_LOGIC; + ----------------------------------------------------------------------------- + -- SEND TIME MODULE + SIGNAL time_dmai : DMA_In_Type; + SIGNAL time_send : STD_LOGIC; + SIGNAL time_send_ok : STD_LOGIC; + SIGNAL time_send_ko : STD_LOGIC; + SIGNAL time_fifo_ren : STD_LOGIC; + SIGNAL time_ren : STD_LOGIC; + ----------------------------------------------------------------------------- + -- SEND DATA MODULE + SIGNAL data_dmai : DMA_In_Type; + SIGNAL data_send : STD_LOGIC; + SIGNAL data_send_ok : STD_LOGIC; + SIGNAL data_send_ko : STD_LOGIC; + SIGNAL data_fifo_ren : STD_LOGIC; + SIGNAL data_ren : STD_LOGIC; + ----------------------------------------------------------------------------- + -- SELECT ADDRESS + SIGNAL data_address : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL update_and_sel : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL addr_data_reg_vector : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); + SIGNAL addr_data_vector : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); + ----------------------------------------------------------------------------- + SIGNAL send_16_3_time : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL count_send_time : INTEGER; +BEGIN + + ----------------------------------------------------------------------------- + -- DMA to AHB interface + DMA2AHB_1 : DMA2AHB + GENERIC MAP ( + hindex => hindex, + vendorid => VENDOR_LPP, + deviceid => 0, + version => 0, + syncrst => 1, + boundary => 1) -- FIX 11/01/2013 + PORT MAP ( + HCLK => HCLK, + HRESETn => HRESETn, + DMAIn => DMAIn, + DMAOut => DMAOut, + AHBIn => AHB_Master_In, + AHBOut => AHB_Master_Out); + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- This module memorises when the Times info are write. When FSM send + -- the Times info, the "reg" is set and when a full_ack is received the "reg" is reset. + all_time_write: FOR I IN 3 DOWNTO 0 GENERATE + PROCESS (HCLK, HRESETn) + BEGIN -- PROCESS + IF HRESETn = '0' THEN -- asynchronous reset (active low) + time_already_send(I) <= '0'; + ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge + IF time_write = '1' AND UNSIGNED(sel_data) = I THEN + time_already_send(I) <= '1'; + ELSIF status_full_ack(I) = '1' THEN + time_already_send(I) <= '0'; + END IF; + END IF; + END PROCESS; + END GENERATE all_time_write; + + ----------------------------------------------------------------------------- + sel_data_s <= "00" WHEN data_ready(0) = '1' ELSE + "01" WHEN data_ready(1) = '1' ELSE + "10" WHEN data_ready(2) = '1' ELSE + "11"; + + time_already_send_s <= time_already_send(0) WHEN data_ready(0) = '1' ELSE + time_already_send(1) WHEN data_ready(1) = '1' ELSE + time_already_send(2) WHEN data_ready(2) = '1' ELSE + time_already_send(3); + + -- DMA control + DMAWriteFSM_p : PROCESS (HCLK, HRESETn) + BEGIN -- PROCESS DMAWriteBurst_p + IF HRESETn = '0' THEN + state <= IDLE; + + sel_data <= "00"; + update <= "00"; + time_select <= '0'; + time_fifo_ren <= '1'; + data_send <= '0'; + time_send <= '0'; + time_write <= '0'; + send_16_3_time <= "001"; + + ELSIF HCLK'EVENT AND HCLK = '1' THEN + + CASE state IS + WHEN IDLE => + count_send_time <= 0; + sel_data <= "00"; + update <= "00"; + time_select <= '0'; + time_fifo_ren <= '1'; + data_send <= '0'; + time_send <= '0'; + time_write <= '0'; + + IF data_ready = "0000" THEN + state <= IDLE; + ELSE + sel_data <= sel_data_s; + send_16_3_time <= send_16_3_time(1 DOWNTO 0) & send_16_3_time(2); + IF send_16_3_time(0) = '1' THEN + state <= SEND_TIME_0; + ELSE + state <= SEND_5_TIME; + END IF; + END IF; + + WHEN SEND_TIME_0 => + time_select <= '1'; + IF time_already_send_s = '0' THEN + time_send <= '1'; + state <= WAIT_TIME_0; + ELSE + time_send <= '0'; + state <= SEND_TIME_1; + END IF; + time_fifo_ren <= '0'; + + WHEN WAIT_TIME_0 => + time_fifo_ren <= '1'; + update <= "00"; + time_send <= '0'; + IF time_send_ok = '1' OR time_send_ko = '1' THEN + update <= "01"; + state <= SEND_TIME_1; + END IF; + + WHEN SEND_TIME_1 => + time_select <= '1'; + IF time_already_send_s = '0' THEN + time_send <= '1'; + state <= WAIT_TIME_1; + ELSE + time_send <= '0'; + state <= SEND_5_TIME; + END IF; + time_fifo_ren <= '0'; + + WHEN WAIT_TIME_1 => + time_fifo_ren <= '1'; + update <= "00"; + time_send <= '0'; + IF time_send_ok = '1' OR time_send_ko = '1' THEN + time_write <= '1'; + update <= "01"; + state <= SEND_5_TIME; + END IF; + + WHEN SEND_5_TIME => + update <= "00"; + time_select <= '1'; + time_fifo_ren <= '0'; + count_send_time <= count_send_time + 1; + IF count_send_time = 10 THEN + state <= SEND_DATA; + END IF; + + WHEN SEND_DATA => + time_fifo_ren <= '1'; + time_write <= '0'; + time_send <= '0'; + + time_select <= '0'; + data_send <= '1'; + update <= "00"; + state <= WAIT_DATA; + + WHEN WAIT_DATA => + data_send <= '0'; + + IF data_send_ok = '1' OR data_send_ko = '1' THEN + state <= IDLE; + update <= "10"; + END IF; + + WHEN OTHERS => NULL; + END CASE; + + END IF; + END PROCESS DMAWriteFSM_p; + ----------------------------------------------------------------------------- + + + + ----------------------------------------------------------------------------- + -- SEND 1 word by DMA + ----------------------------------------------------------------------------- + lpp_dma_send_1word_1 : lpp_dma_send_1word + PORT MAP ( + HCLK => HCLK, + HRESETn => HRESETn, + DMAIn => time_dmai, + DMAOut => DMAOut, + + send => time_send, + address => data_address, + data => data, + send_ok => time_send_ok, + send_ko => time_send_ko + ); + + ----------------------------------------------------------------------------- + -- SEND 16 word by DMA (in burst mode) + ----------------------------------------------------------------------------- + lpp_dma_send_16word_1 : lpp_dma_send_16word + PORT MAP ( + HCLK => HCLK, + HRESETn => HRESETn, + DMAIn => data_dmai, + DMAOut => DMAOut, + + send => data_send, + address => data_address, + data => data, + ren => data_fifo_ren, + send_ok => data_send_ok, + send_ko => data_send_ko); + + DMAIn <= time_dmai WHEN time_select = '1' ELSE data_dmai; + data_ren <= '1' WHEN time_select = '1' ELSE data_fifo_ren; + time_ren <= time_fifo_ren WHEN time_select = '1' ELSE '1'; + + all_data_ren : FOR I IN 3 DOWNTO 0 GENERATE + data_data_ren(I) <= data_ren WHEN UNSIGNED(sel_data) = I ELSE '1'; + data_time_ren(I) <= time_ren WHEN UNSIGNED(sel_data) = I ELSE '1'; + END GENERATE all_data_ren; + + ----------------------------------------------------------------------------- + -- SELECT ADDRESS + addr_data_reg_vector <= addr_data_f3 & addr_data_f2 & addr_data_f1 & addr_data_f0; + + gen_select_address : FOR I IN 3 DOWNTO 0 GENERATE + + update_and_sel((2*I)+1 DOWNTO 2*I) <= update WHEN UNSIGNED(sel_data) = I ELSE "00"; + + lpp_waveform_dma_selectaddress_I : lpp_waveform_dma_selectaddress + GENERIC MAP ( + nb_burst_available_size => nb_burst_available_size) + PORT MAP ( + HCLK => HCLK, + HRESETn => HRESETn, + update => update_and_sel((2*I)+1 DOWNTO 2*I), + nb_burst_available => nb_burst_available, + addr_data_reg => addr_data_reg_vector(32*I+31 DOWNTO 32*I), + addr_data => addr_data_vector(32*I+31 DOWNTO 32*I), + status_full => status_full(I), + status_full_ack => status_full_ack(I), + status_full_err => status_full_err(I)); + + END GENERATE gen_select_address; + + data_address <= addr_data_vector(31 DOWNTO 0) WHEN UNSIGNED(sel_data) = 0 ELSE + addr_data_vector(32*1+31 DOWNTO 32*1) WHEN UNSIGNED(sel_data) = 1 ELSE + addr_data_vector(32*2+31 DOWNTO 32*2) WHEN UNSIGNED(sel_data) = 2 ELSE + addr_data_vector(32*3+31 DOWNTO 32*3); + ----------------------------------------------------------------------------- + + +END Behavioral; diff --git a/lib/lpp/lpp_waveform/lpp_waveform_dma_genvalid.vhd b/lib/lpp/lpp_waveform/lpp_waveform_dma_genvalid.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_waveform/lpp_waveform_dma_genvalid.vhd @@ -0,0 +1,88 @@ + +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +-- jean-christophe.pellion@easii-ic.com +------------------------------------------------------------------------------- +-- 1.0 - initial version +------------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + + +ENTITY lpp_waveform_dma_gen_valid IS + PORT ( + HCLK : IN STD_LOGIC; + HRESETn : IN STD_LOGIC; + + valid_in : IN STD_LOGIC; + ack_in : IN STD_LOGIC; + + valid_out : OUT STD_LOGIC; + error : OUT STD_LOGIC + ); +END; + +ARCHITECTURE Behavioral OF lpp_waveform_dma_gen_valid IS + TYPE state_fsm IS (IDLE, VALID); + SIGNAL state : state_fsm; +BEGIN + + FSM_SELECT_ADDRESS : PROCESS (HCLK, HRESETn) + BEGIN + IF HRESETn = '0' THEN + state <= IDLE; + valid_out <= '0'; + error <= '0'; + ELSIF HCLK'EVENT AND HCLK = '1' THEN + CASE state IS + WHEN IDLE => + valid_out <= '0'; + error <= '0'; + IF valid_in = '1' THEN + state <= VALID; + valid_out <= '1'; + END IF; + + WHEN VALID => + valid_out <= '1'; + error <= '0'; + IF valid_in = '1' THEN + IF ack_in = '1' THEN + state <= VALID; + valid_out <= '1'; + ELSE + state <= IDLE; + error <= '1'; + valid_out <= '0'; + END IF; + ELSIF ack_in = '1' THEN + state <= IDLE; + valid_out <= '0'; + END IF; + + WHEN OTHERS => NULL; + END CASE; + END IF; + END PROCESS FSM_SELECT_ADDRESS; + +END Behavioral; diff --git a/lib/lpp/lpp_waveform/lpp_waveform_dma_selectaddress.vhd b/lib/lpp/lpp_waveform/lpp_waveform_dma_selectaddress.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_waveform/lpp_waveform_dma_selectaddress.vhd @@ -0,0 +1,132 @@ + +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +-- jean-christophe.pellion@easii-ic.com +------------------------------------------------------------------------------- +-- 1.0 - initial version +------------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + + +ENTITY lpp_waveform_dma_selectaddress IS + GENERIC ( + nb_burst_available_size : INTEGER := 11 + ); + PORT ( + HCLK : IN STD_ULOGIC; + HRESETn : IN STD_ULOGIC; + + update : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + + nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); + addr_data_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + + addr_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + + status_full : OUT STD_LOGIC; + status_full_ack : IN STD_LOGIC; + status_full_err : OUT STD_LOGIC + ); +END; + +ARCHITECTURE Behavioral OF lpp_waveform_dma_selectaddress IS + TYPE state_fsm_select_data IS (IDLE, ADD, FULL, ERR, UPDATED); + SIGNAL state : state_fsm_select_data; + + SIGNAL address : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL nb_send : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); + SIGNAL nb_send_next : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); + + SIGNAL update_s : STD_LOGIC; + SIGNAL update_r : STD_LOGIC_VECTOR(1 DOWNTO 0); +BEGIN + + update_s <= update(0) OR update(1); + + addr_data <= address; + nb_send_next <= STD_LOGIC_VECTOR(UNSIGNED(nb_send) + 1); + + FSM_SELECT_ADDRESS : PROCESS (HCLK, HRESETn) + BEGIN + IF HRESETn = '0' THEN + state <= IDLE; + address <= (OTHERS => '0'); + nb_send <= (OTHERS => '0'); + status_full <= '0'; + status_full_err <= '0'; + update_r <= "00"; + ELSIF HCLK'EVENT AND HCLK = '1' THEN + update_r <= update; + CASE state IS + WHEN IDLE => + IF update_s = '1' THEN + state <= ADD; + END IF; + + WHEN ADD => + IF UNSIGNED(nb_send_next) < UNSIGNED(nb_burst_available) THEN + state <= IDLE; + IF update_r = "10" THEN + address <= STD_LOGIC_VECTOR(UNSIGNED(address) + 64); + nb_send <= nb_send_next; + ELSIF update_r = "01" THEN + address <= STD_LOGIC_VECTOR(UNSIGNED(address) + 4); + END IF; + ELSE + state <= FULL; + nb_send <= (OTHERS => '0'); + status_full <= '1'; + END IF; + + WHEN FULL => + status_full <= '0'; + IF status_full_ack = '1' THEN + IF update_s = '1' THEN + status_full_err <= '1'; + END IF; + state <= UPDATED; + ELSE + IF update_s = '1' THEN + status_full_err <= '1'; + state <= ERR; + END IF; + END IF; + + WHEN ERR => + status_full_err <= '0'; + IF status_full_ack = '1' THEN + state <= UPDATED; + END IF; + + WHEN UPDATED => + status_full_err <= '0'; + state <= IDLE; + address <= addr_data_reg; + + WHEN OTHERS => NULL; + END CASE; + END IF; + END PROCESS FSM_SELECT_ADDRESS; + +END Behavioral; diff --git a/lib/lpp/lpp_waveform/lpp_waveform_dma_send_Nword.vhd b/lib/lpp/lpp_waveform/lpp_waveform_dma_send_Nword.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_waveform/lpp_waveform_dma_send_Nword.vhd @@ -0,0 +1,173 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +-- jean-christophe.pellion@easii-ic.com +---------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; +USE GRLIB.DMA2AHB_Package.ALL; +LIBRARY lpp; +USE lpp.lpp_amba.ALL; +USE lpp.apb_devices_list.ALL; +USE lpp.lpp_memory.ALL; +LIBRARY techmap; +USE techmap.gencomp.ALL; + +ENTITY lpp_waveform_dma_send_Nword IS + PORT ( + -- AMBA AHB system signals + HCLK : IN STD_ULOGIC; + HRESETn : IN STD_ULOGIC; + + -- DMA + DMAIn : OUT DMA_In_Type; + DMAOut : IN DMA_OUt_Type; + + -- + Nb_word_less1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + -- + send : IN STD_LOGIC; + address : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + ren : OUT STD_LOGIC; + -- + send_ok : OUT STD_LOGIC; + send_ko : OUT STD_LOGIC + ); +END lpp_waveform_dma_send_Nword; + +ARCHITECTURE beh OF lpp_waveform_dma_send_Nword IS + + TYPE state_fsm_send_Nword IS (IDLE, REQUEST_BUS, SEND_DATA, ERROR0, ERROR1, WAIT_LAST_READY); + SIGNAL state : state_fsm_send_Nword; + + SIGNAL data_counter : INTEGER; + SIGNAL grant_counter : INTEGER; + +BEGIN -- beh + + DMAIn.Beat <= HINCR16; + DMAIn.Size <= HSIZE32; + + PROCESS (HCLK, HRESETn) + BEGIN -- PROCESS + IF HRESETn = '0' THEN -- asynchronous reset (active low) + state <= IDLE; + send_ok <= '0'; + send_ko <= '0'; + + DMAIn.Reset <= '0'; + DMAIn.Address <= (OTHERS => '0'); + DMAIn.Request <= '0'; + DMAIn.Store <= '0'; + DMAIn.Burst <= '1'; + DMAIn.Lock <= '0'; + data_counter <= 0; + ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge + + CASE state IS + WHEN IDLE => + DMAIn.Store <= '1'; + DMAIn.Request <= '0'; + send_ok <= '0'; + send_ko <= '0'; + DMAIn.Address <= address; + data_counter <= 0; + DMAIn.Lock <= '0'; -- FIX test + IF send = '1' THEN + state <= REQUEST_BUS; + DMAIn.Request <= '1'; + DMAIn.Lock <= '1'; -- FIX test + DMAIn.Store <= '1'; + END IF; + WHEN REQUEST_BUS => + IF DMAOut.Grant = '1' THEN + data_counter <= 1; + grant_counter <= 1; + state <= SEND_DATA; + END IF; + WHEN SEND_DATA => + + IF DMAOut.Fault = '1' THEN + DMAIn.Reset <= '0'; + DMAIn.Address <= (OTHERS => '0'); + DMAIn.Request <= '0'; + DMAIn.Store <= '0'; + DMAIn.Burst <= '0'; + state <= ERROR0; + ELSE + + IF DMAOut.Grant = '1' THEN + IF grant_counter = UNSIGNED(Nb_word_less1) THEN -- + DMAIn.Reset <= '0'; + DMAIn.Request <= '0'; + DMAIn.Store <= '0'; + DMAIn.Burst <= '0'; + ELSE + grant_counter <= grant_counter+1; + END IF; + END IF; + + IF DMAOut.OKAY = '1' THEN + IF data_counter = UNSIGNED(Nb_word_less1) THEN + DMAIn.Address <= (OTHERS => '0'); + state <= WAIT_LAST_READY; + ELSE + data_counter <= data_counter + 1; + END IF; + END IF; + END IF; + + + WHEN WAIT_LAST_READY => + IF DMAOut.Ready = '1' THEN + IF grant_counter = UNSIGNED(Nb_word_less1) THEN + state <= IDLE; + send_ok <= '1'; + send_ko <= '0'; + ELSE + state <= ERROR0; + END IF; + END IF; + + WHEN ERROR0 => + state <= ERROR1; + WHEN ERROR1 => + send_ok <= '0'; + send_ko <= '1'; + state <= IDLE; + WHEN OTHERS => NULL; + END CASE; + END IF; + END PROCESS; + + DMAIn.Data <= data; + + ren <= '0' WHEN DMAOut.OKAY = '1' AND state = SEND_DATA ELSE + '0' WHEN state = REQUEST_BUS AND DMAOut.Grant = '1' ELSE + '1'; + +END beh; diff --git a/lib/lpp/lpp_waveform/lpp_waveform_fifo.vhd b/lib/lpp/lpp_waveform/lpp_waveform_fifo.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_waveform/lpp_waveform_fifo.vhd @@ -0,0 +1,176 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Jean-christophe PELLION +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +------------------------------------------------------------------------------ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +LIBRARY lpp; +USE lpp.lpp_memory.ALL; +USE lpp.iir_filter.ALL; +USE lpp.lpp_waveform_pkg.ALL; + +LIBRARY techmap; +USE techmap.gencomp.ALL; + +ENTITY lpp_waveform_fifo IS + GENERIC( + tech : INTEGER := 0 + ); + PORT( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + + --------------------------------------------------------------------------- + ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- FIFO_DATA occupancy is greater than 16 * 32b + + --------------------------------------------------------------------------- + time_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + + rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + + --------------------------------------------------------------------------- + time_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + + wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END ENTITY; + + +ARCHITECTURE ar_lpp_waveform_fifo OF lpp_waveform_fifo IS + + + SIGNAL time_mem_addr_r : LPP_TYPE_ADDR_FIFO_WAVEFORM(3 DOWNTO 0); + SIGNAL time_mem_addr_w : LPP_TYPE_ADDR_FIFO_WAVEFORM(3 DOWNTO 0); + SIGNAL time_mem_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL time_mem_wen : STD_LOGIC_VECTOR(3 DOWNTO 0); + + SIGNAL data_mem_addr_r : LPP_TYPE_ADDR_FIFO_WAVEFORM(3 DOWNTO 0); + SIGNAL data_mem_addr_w : LPP_TYPE_ADDR_FIFO_WAVEFORM(3 DOWNTO 0); + SIGNAL data_mem_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL data_mem_wen : STD_LOGIC_VECTOR(3 DOWNTO 0); + + SIGNAL data_addr_r : STD_LOGIC_VECTOR(6 DOWNTO 0); + SIGNAL data_addr_w : STD_LOGIC_VECTOR(6 DOWNTO 0); + SIGNAL ren : STD_LOGIC; + SIGNAL wen : STD_LOGIC; + +BEGIN + + SRAM : syncram_2p + GENERIC MAP(tech, 7, 32) + PORT MAP(clk, ren, data_addr_r, rdata, + clk, wen, data_addr_w, wdata); + + + ren <= time_mem_ren(3) OR data_mem_ren(3) OR + time_mem_ren(2) OR data_mem_ren(2) OR + time_mem_ren(1) OR data_mem_ren(1) OR + time_mem_ren(0) OR data_mem_ren(0); + + wen <= time_mem_wen(3) OR data_mem_wen(3) OR + time_mem_wen(2) OR data_mem_wen(2) OR + time_mem_wen(1) OR data_mem_wen(1) OR + time_mem_wen(0) OR data_mem_wen(0); + + data_addr_r <= time_mem_addr_r(0) WHEN time_mem_ren(0) = '1' ELSE + time_mem_addr_r(1) WHEN time_mem_ren(1) = '1' ELSE + time_mem_addr_r(2) WHEN time_mem_ren(2) = '1' ELSE + time_mem_addr_r(3) WHEN time_mem_ren(3) = '1' ELSE + data_mem_addr_r(0) WHEN data_mem_ren(0) = '1' ELSE + data_mem_addr_r(1) WHEN data_mem_ren(1) = '1' ELSE + data_mem_addr_r(2) WHEN data_mem_ren(2) = '1' ELSE + data_mem_addr_r(3); + + data_addr_w <= time_mem_addr_w(0) WHEN time_mem_wen(0) = '1' ELSE + time_mem_addr_w(1) WHEN time_mem_wen(1) = '1' ELSE + time_mem_addr_w(2) WHEN time_mem_wen(2) = '1' ELSE + time_mem_addr_w(3) WHEN time_mem_wen(3) = '1' ELSE + data_mem_addr_w(0) WHEN data_mem_wen(0) = '1' ELSE + data_mem_addr_w(1) WHEN data_mem_wen(1) = '1' ELSE + data_mem_addr_w(2) WHEN data_mem_wen(2) = '1' ELSE + data_mem_addr_w(3); + + gen_fifo_ctrl_time: FOR I IN 3 DOWNTO 0 GENERATE + lpp_waveform_fifo_ctrl_time: lpp_waveform_fifo_ctrl + GENERIC MAP ( + offset => 32*I + 20, + length => 10, + enable_ready => '0') + PORT MAP ( + clk => clk, + rstn => rstn, + ren => time_ren(I), + wen => time_wen(I), + mem_re => time_mem_ren(I), + mem_we => time_mem_wen(I), + mem_addr_ren => time_mem_addr_r(I), + mem_addr_wen => time_mem_addr_w(I), + ready => OPEN); + END GENERATE gen_fifo_ctrl_time; + + gen_fifo_ctrl_data: FOR I IN 3 DOWNTO 0 GENERATE + lpp_waveform_fifo_ctrl_data: lpp_waveform_fifo_ctrl + GENERIC MAP ( + offset => 32*I, + length => 20, + enable_ready => '1') + PORT MAP ( + clk => clk, + rstn => rstn, + ren => data_ren(I), + wen => data_wen(I), + mem_re => data_mem_ren(I), + mem_we => data_mem_wen(I), + mem_addr_ren => data_mem_addr_r(I), + mem_addr_wen => data_mem_addr_w(I), + ready => ready(I)); + END GENERATE gen_fifo_ctrl_data; + + +END ARCHITECTURE; + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter.vhd b/lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter.vhd @@ -0,0 +1,177 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Jean-christophe PELLION +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +------------------------------------------------------------------------------ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +LIBRARY lpp; +USE lpp.lpp_waveform_pkg.ALL; + +ENTITY lpp_waveform_fifo_arbiter IS + GENERIC( + tech : INTEGER := 0 + ); + PORT( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + + --------------------------------------------------------------------------- + data_f0_valid : IN STD_LOGIC; + data_f1_valid : IN STD_LOGIC; + data_f2_valid : IN STD_LOGIC; + data_f3_valid : IN STD_LOGIC; + + data_valid_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + + data_f0 : IN STD_LOGIC_VECTOR(159 DOWNTO 0); + data_f1 : IN STD_LOGIC_VECTOR(159 DOWNTO 0); + data_f2 : IN STD_LOGIC_VECTOR(159 DOWNTO 0); + data_f3 : IN STD_LOGIC_VECTOR(159 DOWNTO 0); + + --------------------------------------------------------------------------- + ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + + --------------------------------------------------------------------------- + time_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + data_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + + ); +END ENTITY; + + +ARCHITECTURE ar_lpp_waveform_fifo_arbiter OF lpp_waveform_fifo_arbiter IS + TYPE state_fsm IS (IDLE, T1, T2, D1, D2); + SIGNAL state : state_fsm; + + SIGNAL data_valid_and_ready : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL data_selected : STD_LOGIC_VECTOR(159 DOWNTO 0); + SIGNAL data_valid_selected : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL data_ready_to_go : STD_LOGIC; + + SIGNAL data_temp : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); + SIGNAL time_en_temp : STD_LOGIC_VECTOR(3 DOWNTO 0); +BEGIN + + data_valid_and_ready(0) <= ready(0) AND data_f0_valid; + data_valid_and_ready(1) <= ready(1) AND data_f1_valid; + data_valid_and_ready(2) <= ready(2) AND data_f2_valid; + data_valid_and_ready(3) <= ready(3) AND data_f3_valid; + + data_selected <= data_f0 WHEN data_valid_and_ready(0) = '1' ELSE + data_f1 WHEN data_valid_and_ready(1) = '1' ELSE + data_f2 WHEN data_valid_and_ready(2) = '1' ELSE + data_f3; + + data_valid_selected <= "0001" WHEN data_valid_and_ready(0) = '1' ELSE + "0010" WHEN data_valid_and_ready(1) = '1' ELSE + "0100" WHEN data_valid_and_ready(2) = '1' ELSE + "1000" WHEN data_valid_and_ready(3) = '1' ELSE + "0000"; + + data_ready_to_go <= data_valid_and_ready(0) OR + data_valid_and_ready(1) OR + data_valid_and_ready(2) OR + data_valid_and_ready(3); + + PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + state <= IDLE; + data_valid_ack <= (OTHERS => '0'); + data_wen <= (OTHERS => '1'); + time_wen <= (OTHERS => '1'); + data <= (OTHERS => '0'); + data_temp <= (OTHERS => '0'); + time_en_temp <= (OTHERS => '0'); + ELSIF clk'EVENT AND clk = '1' THEN + CASE state IS + WHEN IDLE => + data_valid_ack <= (OTHERS => '0'); + time_wen <= (OTHERS => '1'); + data_wen <= (OTHERS => '1'); + data <= (OTHERS => '0'); + data_temp <= (OTHERS => '0'); + IF data_ready_to_go = '1' THEN + state <= T1; + data_valid_ack <= data_valid_selected; + time_wen <= NOT data_valid_selected; + time_en_temp <= NOT data_valid_selected; + data <= data_selected(31 DOWNTO 0); + data_temp <= data_selected(159 DOWNTO 32); + END IF; + WHEN T1 => + state <= T2; + data_valid_ack <= (OTHERS => '0'); + data <= data_temp(31 DOWNTO 0); + data_temp(32*3-1 DOWNTO 0) <= data_temp(32*4-1 DOWNTO 32); + + WHEN T2 => + state <= D1; + time_wen <= (OTHERS => '1'); + data_wen <= time_en_temp; + data <= data_temp(31 DOWNTO 0); + data_temp(32*3-1 DOWNTO 0) <= data_temp(32*4-1 DOWNTO 32); + + WHEN D1 => + state <= D2; + data <= data_temp(31 DOWNTO 0); + data_temp(32*3-1 DOWNTO 0) <= data_temp(32*4-1 DOWNTO 32); + + WHEN D2 => + state <= IDLE; + data <= data_temp(31 DOWNTO 0); + data_temp(32*3-1 DOWNTO 0) <= data_temp(32*4-1 DOWNTO 32); + + WHEN OTHERS => NULL; + END CASE; + + END IF; + END PROCESS; + +END ARCHITECTURE; + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/lib/lpp/lpp_waveform/lpp_waveform_fifo_ctrl.vhd b/lib/lpp/lpp_waveform/lpp_waveform_fifo_ctrl.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_waveform/lpp_waveform_fifo_ctrl.vhd @@ -0,0 +1,171 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Jean-christophe PELLION +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +------------------------------------------------------------------------------ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +LIBRARY lpp; +USE lpp.lpp_memory.ALL; +USE lpp.iir_filter.ALL; +USE lpp.lpp_waveform_pkg.ALL; + +LIBRARY techmap; +USE techmap.gencomp.ALL; + +ENTITY lpp_waveform_fifo_ctrl IS + generic( + offset : INTEGER := 0; + length : INTEGER := 20; + enable_ready : STD_LOGIC := '1' + ); + PORT( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + + ren : IN STD_LOGIC; + wen : IN STD_LOGIC; + + mem_re : OUT STD_LOGIC; + mem_we : OUT STD_LOGIC; + + mem_addr_ren : out STD_LOGIC_VECTOR(6 DOWNTO 0); + mem_addr_wen : out STD_LOGIC_VECTOR(6 DOWNTO 0); + + ready : OUT STD_LOGIC + ); +END ENTITY; + + +ARCHITECTURE ar_lpp_waveform_fifo_ctrl OF lpp_waveform_fifo_ctrl IS + + SIGNAL sFull : STD_LOGIC; + SIGNAL sFull_s : STD_LOGIC; + SIGNAL sEmpty_s : STD_LOGIC; + + SIGNAL sEmpty : STD_LOGIC; + SIGNAL sREN : STD_LOGIC; + SIGNAL sWEN : STD_LOGIC; + SIGNAL sRE : STD_LOGIC; + SIGNAL sWE : STD_LOGIC; + + SIGNAL Waddr_vect : INTEGER RANGE 0 TO length := 0; + SIGNAL Raddr_vect : INTEGER RANGE 0 TO length := 0; + SIGNAL Waddr_vect_s : INTEGER RANGE 0 TO length := 0; + SIGNAL Raddr_vect_s : INTEGER RANGE 0 TO length := 0; + +BEGIN + mem_re <= sRE; + mem_we <= sWE; +--============================= +-- Read section +--============================= + sREN <= REN OR sEmpty; + sRE <= NOT sREN; + + sEmpty_s <= '1' WHEN sEmpty = '1' AND Wen = '1' ELSE + '1' WHEN sEmpty = '0' AND (Wen = '1' AND Ren = '0' AND Raddr_vect_s = Waddr_vect) ELSE + '0'; + + Raddr_vect_s <= Raddr_vect +1 WHEN Raddr_vect < length -1 ELSE 0 ; + + PROCESS (clk, rstn) + BEGIN + IF(rstn = '0')then + Raddr_vect <= 0; + sempty <= '1'; + ELSIF(clk'EVENT AND clk = '1')then + sEmpty <= sempty_s; + + IF(sREN = '0' and sempty = '0')then + Raddr_vect <= Raddr_vect_s; + END IF; + + END IF; + END PROCESS; + +--============================= +-- Write section +--============================= + sWEN <= WEN OR sFull; + sWE <= NOT sWEN; + + sFull_s <= '1' WHEN Waddr_vect_s = Raddr_vect AND REN = '1' AND WEN = '0' ELSE + '1' WHEN sFull = '1' AND REN = '1' ELSE + '0'; + + Waddr_vect_s <= Waddr_vect +1 WHEN Waddr_vect < length -1 ELSE 0 ; + + PROCESS (clk, rstn) + BEGIN + IF(rstn = '0')then + Waddr_vect <= 0; + sfull <= '0'; + ELSIF(clk'EVENT AND clk = '1')then + sfull <= sfull_s; + + IF(sWEN = '0' and sfull = '0')THEN + Waddr_vect <= Waddr_vect_s; + END IF; + + END IF; + END PROCESS; + + + mem_addr_wen <= std_logic_vector(to_unsigned((Waddr_vect + offset), mem_addr_wen'length)); + mem_addr_ren <= std_logic_vector(to_unsigned((Raddr_vect + offset), mem_addr_ren'length)); + + ready_gen: IF enable_ready = '1' GENERATE + ready <= '1' WHEN Waddr_vect > Raddr_vect AND (Waddr_vect - Raddr_vect) > 15 ELSE + '1' WHEN Waddr_vect < Raddr_vect AND (length + Waddr_vect - Raddr_vect) > 15 ELSE + '0'; + END GENERATE ready_gen; + + ready_not_gen: IF enable_ready = '0' GENERATE + ready <= '0'; + END GENERATE ready_not_gen; + +END ARCHITECTURE; + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd b/lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd @@ -0,0 +1,243 @@ +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; + +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; +USE GRLIB.DMA2AHB_Package.ALL; + +LIBRARY techmap; +USE techmap.gencomp.ALL; + +PACKAGE lpp_waveform_pkg IS + + TYPE LPP_TYPE_ADDR_FIFO_WAVEFORM IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(6 DOWNTO 0); + + COMPONENT lpp_waveform_snapshot + GENERIC ( + data_size : INTEGER; + nb_snapshot_param_size : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + enable : IN STD_LOGIC; + burst_enable : IN STD_LOGIC; + nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); + start_snapshot : IN STD_LOGIC; + data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + data_in_valid : IN STD_LOGIC; + data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + data_out_valid : OUT STD_LOGIC); + END COMPONENT; + + COMPONENT lpp_waveform_burst + GENERIC ( + data_size : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + enable : IN STD_LOGIC; + data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + data_in_valid : IN STD_LOGIC; + data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + data_out_valid : OUT STD_LOGIC); + END COMPONENT; + + COMPONENT lpp_waveform_snapshot_controler + GENERIC ( + delta_snapshot_size : INTEGER; + delta_f2_f0_size : INTEGER; + delta_f2_f1_size : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); + delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); + delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); + coarse_time_0 : IN STD_LOGIC; + data_f0_in_valid : IN STD_LOGIC; + data_f2_in_valid : IN STD_LOGIC; + start_snapshot_f0 : OUT STD_LOGIC; + start_snapshot_f1 : OUT STD_LOGIC; + start_snapshot_f2 : OUT STD_LOGIC); + END COMPONENT; + + + + COMPONENT lpp_waveform + GENERIC ( + hindex : INTEGER; + tech : INTEGER; + data_size : INTEGER; + nb_burst_available_size : INTEGER; + nb_snapshot_param_size : INTEGER; + delta_snapshot_size : INTEGER; + delta_f2_f0_size : INTEGER; + delta_f2_f1_size : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + AHB_Master_In : IN AHB_Mst_In_Type; + AHB_Master_Out : OUT AHB_Mst_Out_Type; + coarse_time_0 : IN STD_LOGIC; + delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); + delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); + delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); + enable_f0 : IN STD_LOGIC; + enable_f1 : IN STD_LOGIC; + enable_f2 : IN STD_LOGIC; + enable_f3 : IN STD_LOGIC; + burst_f0 : IN STD_LOGIC; + burst_f1 : IN STD_LOGIC; + burst_f2 : IN STD_LOGIC; + nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); + nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); + status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + data_f0_in_valid : IN STD_LOGIC; + data_f1_in_valid : IN STD_LOGIC; + data_f2_in_valid : IN STD_LOGIC; + data_f3_in_valid : IN STD_LOGIC); + END COMPONENT; + + COMPONENT lpp_waveform_dma_send_Nword + PORT ( + HCLK : IN STD_ULOGIC; + HRESETn : IN STD_ULOGIC; + DMAIn : OUT DMA_In_Type; + DMAOut : IN DMA_OUt_Type; + Nb_word_less1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + send : IN STD_LOGIC; + address : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + ren : OUT STD_LOGIC; + send_ok : OUT STD_LOGIC; + send_ko : OUT STD_LOGIC); + END COMPONENT; + + COMPONENT lpp_waveform_dma_selectaddress + GENERIC ( + nb_burst_available_size : INTEGER); + PORT ( + HCLK : IN STD_ULOGIC; + HRESETn : IN STD_ULOGIC; + update : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); + addr_data_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + status_full : OUT STD_LOGIC; + status_full_ack : IN STD_LOGIC; + status_full_err : OUT STD_LOGIC); + END COMPONENT; + + COMPONENT lpp_waveform_dma_gen_valid + PORT ( + HCLK : IN STD_LOGIC; + HRESETn : IN STD_LOGIC; + valid_in : IN STD_LOGIC; + ack_in : IN STD_LOGIC; + valid_out : OUT STD_LOGIC; + error : OUT STD_LOGIC); + END COMPONENT; + + COMPONENT lpp_waveform_dma + GENERIC ( + data_size : INTEGER; + tech : INTEGER; + hindex : INTEGER; + nb_burst_available_size : INTEGER); + PORT ( + HCLK : IN STD_ULOGIC; + HRESETn : IN STD_ULOGIC; + AHB_Master_In : IN AHB_Mst_In_Type; + AHB_Master_Out : OUT AHB_Mst_Out_Type; + data_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + data_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + data_time_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + --data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + --data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + --data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + --data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + --data_f0_in_valid : IN STD_LOGIC; + --data_f1_in_valid : IN STD_LOGIC; + --data_f2_in_valid : IN STD_LOGIC; + --data_f3_in_valid : IN STD_LOGIC; + nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); + status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); +-- status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); + END COMPONENT; + + COMPONENT lpp_waveform_fifo_ctrl + GENERIC ( + offset : INTEGER; + length : INTEGER; + enable_ready : STD_LOGIC); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + ren : IN STD_LOGIC; + wen : IN STD_LOGIC; + mem_re : OUT STD_LOGIC; + mem_we : OUT STD_LOGIC; + mem_addr_ren : out STD_LOGIC_VECTOR(6 DOWNTO 0); + mem_addr_wen : out STD_LOGIC_VECTOR(6 DOWNTO 0); + ready : OUT STD_LOGIC); + END COMPONENT; + + COMPONENT lpp_waveform_fifo_arbiter + GENERIC ( + tech : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + data_f0_valid : IN STD_LOGIC; + data_f1_valid : IN STD_LOGIC; + data_f2_valid : IN STD_LOGIC; + data_f3_valid : IN STD_LOGIC; + data_valid_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + data_f0 : IN STD_LOGIC_VECTOR(159 DOWNTO 0); + data_f1 : IN STD_LOGIC_VECTOR(159 DOWNTO 0); + data_f2 : IN STD_LOGIC_VECTOR(159 DOWNTO 0); + data_f3 : IN STD_LOGIC_VECTOR(159 DOWNTO 0); + ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + time_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + data_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); + END COMPONENT; + + COMPONENT lpp_waveform_fifo + GENERIC ( + tech : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + time_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + time_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); + END COMPONENT; + + + +END lpp_waveform_pkg; diff --git a/lib/lpp/lpp_waveform/lpp_waveform_snapshot.vhd b/lib/lpp/lpp_waveform/lpp_waveform_snapshot.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_waveform/lpp_waveform_snapshot.vhd @@ -0,0 +1,80 @@ +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY lpp_waveform_snapshot IS + + GENERIC ( + data_size : INTEGER := 16; + nb_snapshot_param_size : INTEGER := 11); + + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + + enable : IN STD_LOGIC; + burst_enable : IN STD_LOGIC; + nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); + + start_snapshot : IN STD_LOGIC; + + data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + data_in_valid : IN STD_LOGIC; + + data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + data_out_valid : OUT STD_LOGIC + ); + +END lpp_waveform_snapshot; + +ARCHITECTURE beh OF lpp_waveform_snapshot IS + SIGNAL counter_points_snapshot : INTEGER; +BEGIN -- beh + + PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + data_out <= (OTHERS => '0'); + data_out_valid <= '0'; + counter_points_snapshot <= 0; + ELSIF clk'EVENT AND clk = '1' THEN + data_out <= data_in; + IF enable = '0' THEN + data_out_valid <= '0'; + counter_points_snapshot <= 0; + ELSE + IF burst_enable = '1' THEN + -- BURST ModE -- + data_out_valid <= data_in_valid; + counter_points_snapshot <= 0; + ELSE + -- SNAPShOT MODE -- + IF start_snapshot = '1' THEN + IF data_in_valid = '1' THEN + counter_points_snapshot <= to_integer(unsigned(nb_snapshot_param)) - 1; + data_out_valid <= '1'; + ELSE + counter_points_snapshot <= to_integer(unsigned(nb_snapshot_param)); + data_out_valid <= '0'; + END IF; + ELSE + IF data_in_valid = '1' THEN + IF counter_points_snapshot > 0 THEN + counter_points_snapshot <= counter_points_snapshot - 1; + data_out_valid <= '1'; + ELSE + counter_points_snapshot <= counter_points_snapshot; + data_out_valid <= '0'; + END IF; + ELSE + counter_points_snapshot <= counter_points_snapshot; + data_out_valid <= '0'; + END IF; + END IF; + + END IF; + END IF; + END IF; + END PROCESS; + +END beh; diff --git a/lib/lpp/lpp_waveform/lpp_waveform_snapshot_controler.vhd b/lib/lpp/lpp_waveform/lpp_waveform_snapshot_controler.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_waveform/lpp_waveform_snapshot_controler.vhd @@ -0,0 +1,116 @@ +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY lpp_waveform_snapshot_controler IS + + GENERIC ( + delta_snapshot_size : INTEGER := 16; + delta_f2_f0_size : INTEGER := 10; + delta_f2_f1_size : INTEGER := 10); + + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + --config + delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); + delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); + delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); + + --input + coarse_time_0 : IN STD_LOGIC; + data_f0_in_valid : IN STD_LOGIC; + data_f2_in_valid : IN STD_LOGIC; + --output + start_snapshot_f0 : OUT STD_LOGIC; + start_snapshot_f1 : OUT STD_LOGIC; + start_snapshot_f2 : OUT STD_LOGIC + ); + +END lpp_waveform_snapshot_controler; + +ARCHITECTURE beh OF lpp_waveform_snapshot_controler IS + SIGNAL counter_delta_snapshot : INTEGER; + SIGNAL counter_delta_f0 : INTEGER; + + SIGNAL coarse_time_0_r : STD_LOGIC; + SIGNAL start_snapshot_f2_temp : STD_LOGIC; + SIGNAL start_snapshot_fothers_temp : STD_LOGIC; + SIGNAL start_snapshot_fothers_temp2 : STD_LOGIC; +BEGIN -- beh + + PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + start_snapshot_f0 <= '0'; + start_snapshot_f1 <= '0'; + start_snapshot_f2 <= '0'; + counter_delta_snapshot <= 0; + counter_delta_f0 <= 0; + coarse_time_0_r <= '0'; + start_snapshot_f2_temp <= '0'; + start_snapshot_fothers_temp <= '0'; + start_snapshot_fothers_temp2 <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN + IF counter_delta_snapshot = UNSIGNED(delta_snapshot) THEN + start_snapshot_f2_temp <= '1'; + ELSE + start_snapshot_f2_temp <= '0'; + END IF; + ------------------------------------------------------------------------- + IF counter_delta_snapshot = UNSIGNED(delta_snapshot) AND start_snapshot_f2_temp = '0' THEN + start_snapshot_f2 <= '1'; + ELSE + start_snapshot_f2 <= '0'; + END IF; + ------------------------------------------------------------------------- + coarse_time_0_r <= coarse_time_0; + IF coarse_time_0 = NOT coarse_time_0_r AND coarse_time_0 = '1' THEN + IF counter_delta_snapshot = 0 THEN + counter_delta_snapshot <= to_integer(UNSIGNED(delta_snapshot)); + ELSE + counter_delta_snapshot <= counter_delta_snapshot - 1; + END IF; + END IF; + + + ------------------------------------------------------------------------- + + + + IF counter_delta_f0 = UNSIGNED(delta_f2_f1) THEN + start_snapshot_f1 <= '1'; + ELSE + start_snapshot_f1 <= '0'; + END IF; + + IF counter_delta_f0 = 1 THEN --UNSIGNED(delta_f2_f0) THEN + start_snapshot_f0 <= '1'; + ELSE + start_snapshot_f0 <= '0'; + END IF; + + IF counter_delta_snapshot = UNSIGNED(delta_snapshot) + AND start_snapshot_f2_temp = '0' + THEN -- + start_snapshot_fothers_temp <= '1'; + ELSIF counter_delta_f0 > 0 THEN + start_snapshot_fothers_temp <= '0'; + END IF; + + + ------------------------------------------------------------------------- + IF (start_snapshot_fothers_temp = '1' OR (counter_delta_snapshot = UNSIGNED(delta_snapshot) AND start_snapshot_f2_temp = '0')) AND data_f2_in_valid = '1' THEN + --counter_delta_snapshot = UNSIGNED(delta_snapshot) AND start_snapshot_f2_temp = '0' THEN -- + --counter_delta_snapshot = UNSIGNED(delta_snapshot) THEN + counter_delta_f0 <= to_integer(UNSIGNED(delta_f2_f0)); --0; + ELSE + IF (( counter_delta_f0 > 0 ) AND ( data_f0_in_valid = '1' )) THEN --<= UNSIGNED(delta_f2_f0) THEN + counter_delta_f0 <= counter_delta_f0 - 1;--counter_delta_f0 + 1; + END IF; + END IF; + ------------------------------------------------------------------------- + END IF; + END PROCESS; + +END beh; diff --git a/lib/lpp/lpp_waveform/lpp_waveform_valid_ack.vhd b/lib/lpp/lpp_waveform/lpp_waveform_valid_ack.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_waveform/lpp_waveform_valid_ack.vhd @@ -0,0 +1,88 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Jean-christophe PELLION +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +------------------------------------------------------------------------------ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +LIBRARY lpp; +USE lpp.lpp_waveform_pkg.ALL; + +ENTITY lpp_waveform_valid_ack IS + PORT( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + + data_valid_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + data_valid_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + error_valid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) + ); +END ENTITY; + + +ARCHITECTURE ar_lpp_waveform_valid_ack OF lpp_waveform_valid_ack IS + + SIGNAL data_valid_temp : STD_LOGIC_VECTOR(3 DOWNTO 0); + +BEGIN + + all_input: FOR I IN 3 DOWNTO 0 GENERATE + + PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + data_valid_temp(I) <= '0'; + ELSIF clk'event AND clk = '1' THEN + data_valid_temp(I) <= data_valid_in(I); + data_valid_out(I) <= data_valid_in(I) AND ; + + END IF; + END PROCESS; + + END GENERATE all_input; + +END ARCHITECTURE; + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/lib/lpp/lpp_waveform/vhdlsyn.txt b/lib/lpp/lpp_waveform/vhdlsyn.txt new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_waveform/vhdlsyn.txt @@ -0,0 +1,9 @@ +lpp_waveform_pkg.vhd +lpp_waveform.vhd +lpp_waveform_snapshot_controler.vhd +lpp_waveform_snapshot.vhd +lpp_waveform_burst.vhd +lpp_waveform_dma.vhd +lpp_waveform_dma_send_Nword.vhd +lpp_waveform_dma_selectaddress.vhd +lpp_waveform_dma_genvalid.vhd