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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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-- Author : Martin Morlot
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-- Mail : martin.morlot@lpp.polytechnique.fr
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------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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--library lpp;
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--use lpp.lpp_matrix.all;
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entity MatriceSpectrale is
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generic(
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Input_SZ : integer := 16;
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Result_SZ : integer := 32);
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port(
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clkm : in std_logic;
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rstn : in std_logic;
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FifoIN_Full : in std_logic_vector(4 downto 0);
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SetReUse : in std_logic_vector(4 downto 0);
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FifoOUT_Full : in std_logic_vector(1 downto 0);
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Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0);
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ACQ : in std_logic;
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FlagError : out std_logic;
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Pong : out std_logic;
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Statu : out std_logic_vector(3 downto 0);
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Write : out std_logic_vector(1 downto 0);
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Read : out std_logic_vector(4 downto 0);
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ReUse : out std_logic_vector(4 downto 0);
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Data_OUT : out std_logic_vector((2*Result_SZ)-1 downto 0)
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);
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end entity;
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architecture ar_MatriceSpectrale of MatriceSpectrale is
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signal Matrix_Write : std_logic;
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signal Matrix_Read : std_logic_vector(1 downto 0);
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signal Matrix_Result : std_logic_vector(31 downto 0);
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signal TopSM_Start : std_logic;
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signal TopSM_Statu : std_logic_vector(3 downto 0);
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signal TopSM_Data1 : std_logic_vector(15 downto 0);
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signal TopSM_Data2 : std_logic_vector(15 downto 0);
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begin
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CTRL0 : entity work.ReUse_CTRLR
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port map(clkm,rstn,SetReUse,TopSM_Statu,ReUse);
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TopSM : entity work.TopSpecMatrix
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generic map (Input_SZ)
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port map(clkm,rstn,Matrix_Write,Matrix_Read,FifoIN_Full,Data_IN,TopSM_Start,Read,TopSM_Statu,TopSM_Data1,TopSM_Data2);
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SM : entity work.SpectralMatrix
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generic map (Input_SZ,Result_SZ)
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port map(clkm,rstn,TopSM_Start,TopSM_Data1,TopSM_Data2,TopSM_Statu,Matrix_Read,Matrix_Write,Matrix_Result);
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DISP : entity work.Dispatch
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generic map(Result_SZ)
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port map(clkm,rstn,ACQ,Matrix_Result,Matrix_Write,FifoOUT_Full,Data_OUT,Write,Pong,FlagError);
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Statu <= TopSM_Statu;
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end architecture;
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