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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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-- Author : Martin Morlot
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-- Mail : martin.morlot@lpp.polytechnique.fr
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------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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library lpp;
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use lpp.lpp_demux.all;
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entity Demultiplex is
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generic(
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Data_sz : integer range 1 to 32 := 16);
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port(
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clk : in std_logic;
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rstn : in std_logic;
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Read : in std_logic_vector(4 downto 0);
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EmptyF0a : in std_logic_vector(4 downto 0);
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EmptyF0b : in std_logic_vector(4 downto 0);
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EmptyF1 : in std_logic_vector(4 downto 0);
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EmptyF2 : in std_logic_vector(4 downto 0);
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DataF0a : in std_logic_vector((5*Data_sz)-1 downto 0);
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DataF0b : in std_logic_vector((5*Data_sz)-1 downto 0);
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DataF1 : in std_logic_vector((5*Data_sz)-1 downto 0);
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DataF2 : in std_logic_vector((5*Data_sz)-1 downto 0);
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Read_DEMUX : out std_logic_vector(19 downto 0);
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Empty : out std_logic_vector(4 downto 0);
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Data : out std_logic_vector((5*Data_sz)-1 downto 0)
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);
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end entity;
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architecture ar_Demultiplex of Demultiplex is
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signal DataCpt : std_logic_vector(3 downto 0);
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begin
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FLG0 : WatchFlag
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port map(clk,rstn,EmptyF0a,EmptyF0b,EmptyF1,EmptyF2,DataCpt);
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DEM : DEMUX
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generic map(Data_sz)
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port map(clk,rstn,Read,DataCpt,EmptyF0a,EmptyF0b,EmptyF1,EmptyF2,DataF0a,DataF0b,DataF1,DataF2,Read_DEMUX,Empty,Data);
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end architecture;
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