@@ -1,686 +1,653 | |||||
1 | ----------------------------------------------------------------------------- |
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1 | ----------------------------------------------------------------------------- | |
2 | -- LEON3 Demonstration design |
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2 | -- LEON3 Demonstration design | |
3 | -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research |
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3 | -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research | |
4 | ------------------------------------------------------------------------------ |
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4 | ------------------------------------------------------------------------------ | |
5 | -- This file is a part of the GRLIB VHDL IP LIBRARY |
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5 | -- This file is a part of the GRLIB VHDL IP LIBRARY | |
6 | -- Copyright (C) 2010, Aeroflex Gaisler AB - all rights reserved. |
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6 | -- Copyright (C) 2010, Aeroflex Gaisler AB - all rights reserved. | |
7 | -- |
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7 | -- | |
8 | -- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN |
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8 | -- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN | |
9 | -- ACCORDANCE WITH THE GAISLER LICENSE AGREEMENT AND MUST BE APPROVED |
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9 | -- ACCORDANCE WITH THE GAISLER LICENSE AGREEMENT AND MUST BE APPROVED | |
10 | -- IN ADVANCE IN WRITING. |
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10 | -- IN ADVANCE IN WRITING. | |
11 | ------------------------------------------------------------------------------ |
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11 | ------------------------------------------------------------------------------ | |
12 |
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12 | |||
13 |
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13 | |||
14 | LIBRARY ieee; |
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14 | LIBRARY ieee; | |
15 | USE ieee.std_logic_1164.ALL; |
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15 | USE ieee.std_logic_1164.ALL; | |
16 | LIBRARY grlib; |
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16 | LIBRARY grlib; | |
17 | USE grlib.amba.ALL; |
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17 | USE grlib.amba.ALL; | |
18 | USE grlib.stdlib.ALL; |
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18 | USE grlib.stdlib.ALL; | |
19 | USE GRLIB.DMA2AHB_Package.ALL; |
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19 | USE GRLIB.DMA2AHB_Package.ALL; | |
20 | LIBRARY techmap; |
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20 | LIBRARY techmap; | |
21 | USE techmap.gencomp.ALL; |
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21 | USE techmap.gencomp.ALL; | |
22 | LIBRARY gaisler; |
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22 | LIBRARY gaisler; | |
23 | USE gaisler.memctrl.ALL; |
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23 | USE gaisler.memctrl.ALL; | |
24 | USE gaisler.leon3.ALL; |
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24 | USE gaisler.leon3.ALL; | |
25 | USE gaisler.uart.ALL; |
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25 | USE gaisler.uart.ALL; | |
26 | USE gaisler.misc.ALL; |
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26 | USE gaisler.misc.ALL; | |
27 | USE gaisler.pci.ALL; |
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27 | USE gaisler.pci.ALL; | |
28 | USE gaisler.net.ALL; |
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28 | USE gaisler.net.ALL; | |
29 | USE gaisler.jtag.ALL; |
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29 | USE gaisler.jtag.ALL; | |
30 | USE gaisler.spacewire.ALL; |
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30 | USE gaisler.spacewire.ALL; | |
31 | LIBRARY esa; |
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31 | LIBRARY esa; | |
32 | USE esa.memoryctrl.ALL; |
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32 | USE esa.memoryctrl.ALL; | |
33 | USE esa.pcicomp.ALL; |
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33 | USE esa.pcicomp.ALL; | |
34 | USE work.config.ALL; |
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34 | USE work.config.ALL; | |
35 | LIBRARY lpp; |
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35 | LIBRARY lpp; | |
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36 | USE lpp.lpp_bootloader_pkg.ALL; | |||
36 | USE lpp.lpp_dma_pkg.ALL; |
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37 | USE lpp.lpp_dma_pkg.ALL; | |
37 |
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38 | USE lpp.lpp_memory.ALL; | |
38 |
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39 | |||
39 | ENTITY leon3mp IS |
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40 | ENTITY leon3mp IS | |
40 | GENERIC ( |
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41 | GENERIC ( | |
41 | fabtech : INTEGER := CFG_FABTECH; |
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42 | fabtech : INTEGER := CFG_FABTECH; | |
42 | memtech : INTEGER := CFG_MEMTECH; |
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43 | memtech : INTEGER := CFG_MEMTECH; | |
43 | padtech : INTEGER := CFG_PADTECH; |
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44 | padtech : INTEGER := CFG_PADTECH; | |
44 | clktech : INTEGER := CFG_CLKTECH; |
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45 | clktech : INTEGER := CFG_CLKTECH; | |
45 | ncpu : INTEGER := CFG_NCPU; |
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46 | ncpu : INTEGER := CFG_NCPU; | |
46 | disas : INTEGER := CFG_DISAS; -- Enable disassembly to console |
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47 | disas : INTEGER := CFG_DISAS; -- Enable disassembly to console | |
47 | dbguart : INTEGER := CFG_DUART; -- Print UART on console |
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48 | dbguart : INTEGER := CFG_DUART; -- Print UART on console | |
48 | pclow : INTEGER := CFG_PCLOW |
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49 | pclow : INTEGER := CFG_PCLOW | |
49 | ); |
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50 | ); | |
50 | PORT ( |
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51 | PORT ( | |
51 | resetn : IN STD_ULOGIC; |
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52 | resetn : IN STD_ULOGIC; | |
52 | clk : IN STD_ULOGIC; |
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53 | clk : IN STD_ULOGIC; | |
53 | pllref : IN STD_ULOGIC; |
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54 | pllref : IN STD_ULOGIC; | |
54 | errorn : OUT STD_ULOGIC; |
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55 | errorn : OUT STD_ULOGIC; | |
55 | address : OUT STD_LOGIC_VECTOR(27 DOWNTO 0); |
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56 | address : OUT STD_LOGIC_VECTOR(27 DOWNTO 0); | |
56 | data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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57 | data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
57 |
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58 | |||
58 |
dsutx |
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59 | dsutx : OUT STD_ULOGIC; -- DSU tx data | |
59 |
dsurx |
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60 | dsurx : IN STD_ULOGIC; -- DSU rx data | |
60 |
dsuen |
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61 | dsuen : IN STD_ULOGIC; | |
61 |
dsubre |
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62 | dsubre : IN STD_ULOGIC; | |
62 |
dsuact |
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63 | dsuact : OUT STD_ULOGIC; | |
63 |
txd1 |
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64 | txd1 : OUT STD_ULOGIC; -- UART1 tx data | |
64 |
rxd1 |
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65 | rxd1 : IN STD_ULOGIC; -- UART1 rx data | |
65 |
txd2 |
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66 | txd2 : OUT STD_ULOGIC; -- UART2 tx data | |
66 |
rxd2 |
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67 | rxd2 : IN STD_ULOGIC; -- UART2 rx data | |
67 |
ramsn |
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68 | ramsn : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); | |
68 |
ramoen |
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69 | ramoen : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); | |
69 |
rwen |
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70 | rwen : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); | |
70 |
oen |
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71 | oen : OUT STD_ULOGIC; | |
71 |
writen |
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72 | writen : OUT STD_ULOGIC; | |
72 |
read |
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73 | read : OUT STD_ULOGIC; | |
73 |
iosn |
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74 | iosn : OUT STD_ULOGIC; | |
74 |
romsn |
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75 | romsn : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); | |
75 |
gpio |
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76 | gpio : INOUT STD_LOGIC_VECTOR(CFG_GRGPIO_WIDTH-1 DOWNTO 0); -- I/O port | |
76 |
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77 | |||
77 | emddis : OUT STD_LOGIC; |
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78 | emddis : OUT STD_LOGIC; | |
78 | epwrdwn : OUT STD_ULOGIC; |
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79 | epwrdwn : OUT STD_ULOGIC; | |
79 | ereset : OUT STD_ULOGIC; |
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80 | ereset : OUT STD_ULOGIC; | |
80 | esleep : OUT STD_ULOGIC; |
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81 | esleep : OUT STD_ULOGIC; | |
81 | epause : OUT STD_ULOGIC; |
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82 | epause : OUT STD_ULOGIC; | |
82 |
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83 | |||
83 | pci_rst : INOUT STD_LOGIC; -- PCI bus |
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84 | pci_rst : INOUT STD_LOGIC; -- PCI bus | |
84 | pci_clk : IN STD_ULOGIC; |
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85 | pci_clk : IN STD_ULOGIC; | |
85 | pci_gnt : IN STD_ULOGIC; |
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86 | pci_gnt : IN STD_ULOGIC; | |
86 | pci_idsel : IN STD_ULOGIC; |
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87 | pci_idsel : IN STD_ULOGIC; | |
87 | pci_lock : INOUT STD_ULOGIC; |
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88 | pci_lock : INOUT STD_ULOGIC; | |
88 | pci_ad : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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89 | pci_ad : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
89 | pci_cbe : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
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90 | pci_cbe : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
90 | pci_frame : INOUT STD_ULOGIC; |
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91 | pci_frame : INOUT STD_ULOGIC; | |
91 | pci_irdy : INOUT STD_ULOGIC; |
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92 | pci_irdy : INOUT STD_ULOGIC; | |
92 | pci_trdy : INOUT STD_ULOGIC; |
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93 | pci_trdy : INOUT STD_ULOGIC; | |
93 | pci_devsel : INOUT STD_ULOGIC; |
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94 | pci_devsel : INOUT STD_ULOGIC; | |
94 | pci_stop : INOUT STD_ULOGIC; |
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95 | pci_stop : INOUT STD_ULOGIC; | |
95 | pci_perr : INOUT STD_ULOGIC; |
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96 | pci_perr : INOUT STD_ULOGIC; | |
96 | pci_par : INOUT STD_ULOGIC; |
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97 | pci_par : INOUT STD_ULOGIC; | |
97 | pci_req : INOUT STD_ULOGIC; |
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98 | pci_req : INOUT STD_ULOGIC; | |
98 | pci_serr : INOUT STD_ULOGIC; |
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99 | pci_serr : INOUT STD_ULOGIC; | |
99 | pci_host : IN STD_ULOGIC; |
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100 | pci_host : IN STD_ULOGIC; | |
100 | pci_66 : IN STD_ULOGIC; |
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101 | pci_66 : IN STD_ULOGIC; | |
101 | pci_arb_req : IN STD_LOGIC_VECTOR(0 TO 3); |
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102 | pci_arb_req : IN STD_LOGIC_VECTOR(0 TO 3); | |
102 | pci_arb_gnt : OUT STD_LOGIC_VECTOR(0 TO 3); |
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103 | pci_arb_gnt : OUT STD_LOGIC_VECTOR(0 TO 3); | |
103 |
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104 | |||
104 |
spw_clk |
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105 | spw_clk : IN STD_ULOGIC; | |
105 |
spw_rxd |
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106 | spw_rxd : IN STD_LOGIC_VECTOR(0 TO 2); | |
106 |
spw_rxdn |
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107 | spw_rxdn : IN STD_LOGIC_VECTOR(0 TO 2); | |
107 |
spw_rxs |
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108 | spw_rxs : IN STD_LOGIC_VECTOR(0 TO 2); | |
108 |
spw_rxsn |
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109 | spw_rxsn : IN STD_LOGIC_VECTOR(0 TO 2); | |
109 |
spw_txd |
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110 | spw_txd : OUT STD_LOGIC_VECTOR(0 TO 2); | |
110 |
spw_txdn |
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111 | spw_txdn : OUT STD_LOGIC_VECTOR(0 TO 2); | |
111 |
spw_txs |
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112 | spw_txs : OUT STD_LOGIC_VECTOR(0 TO 2); | |
112 |
spw_txsn |
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113 | spw_txsn : OUT STD_LOGIC_VECTOR(0 TO 2); | |
113 |
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114 | |||
114 |
ramclk : OUT STD_LOGIC; |
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115 | ramclk : OUT STD_LOGIC; | |
115 |
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116 | |||
116 |
nBWa |
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117 | nBWa : OUT STD_LOGIC; | |
117 |
nBWb |
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118 | nBWb : OUT STD_LOGIC; | |
118 |
nBWc |
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119 | nBWc : OUT STD_LOGIC; | |
119 |
nBWd |
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120 | nBWd : OUT STD_LOGIC; | |
120 |
nBWE |
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121 | nBWE : OUT STD_LOGIC; | |
121 |
nADSC |
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122 | nADSC : OUT STD_LOGIC; | |
122 |
nADSP |
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123 | nADSP : OUT STD_LOGIC; | |
123 |
nADV |
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124 | nADV : OUT STD_LOGIC; | |
124 |
nGW |
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125 | nGW : OUT STD_LOGIC; | |
125 |
nCE1 |
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126 | nCE1 : OUT STD_LOGIC; | |
126 |
CE2 |
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127 | CE2 : OUT STD_LOGIC; | |
127 |
nCE3 |
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128 | nCE3 : OUT STD_LOGIC; | |
128 | nOE : out std_logic; |
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129 | nOE : OUT STD_LOGIC; | |
129 | MODE : out std_logic; |
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130 | MODE : OUT STD_LOGIC; | |
130 |
SSRAM_CLK |
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131 | SSRAM_CLK : OUT STD_LOGIC; | |
131 |
ZZ |
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132 | ZZ : OUT STD_LOGIC; | |
132 |
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133 | |||
133 | tck, tms, tdi : IN STD_ULOGIC; |
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134 | tck, tms, tdi : IN STD_ULOGIC; | |
134 | tdo : OUT STD_ULOGIC |
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135 | tdo : OUT STD_ULOGIC | |
135 | ); |
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136 | ); | |
136 | END; |
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137 | END; | |
137 |
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138 | |||
138 | ARCHITECTURE rtl OF leon3mp IS |
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139 | ARCHITECTURE rtl OF leon3mp IS | |
139 |
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140 | |||
140 | CONSTANT blength : INTEGER := 12; |
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141 | CONSTANT blength : INTEGER := 12; | |
141 |
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142 | |||
142 | CONSTANT maxahbmsp : INTEGER := NCPU+CFG_AHB_UART+ |
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143 | CONSTANT maxahbmsp : INTEGER := NCPU+CFG_AHB_UART+ | |
143 | CFG_GRETH+CFG_AHB_JTAG+log2x(CFG_PCI); |
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144 | CFG_GRETH+CFG_AHB_JTAG+log2x(CFG_PCI); | |
144 | CONSTANT maxahbm : INTEGER := (CFG_SPW_NUM*CFG_SPW_EN) + maxahbmsp + 1; -- +LPP_DMA |
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145 | CONSTANT maxahbm : INTEGER := (CFG_SPW_NUM*CFG_SPW_EN) + maxahbmsp + 1; -- +LPP_DMA | |
145 |
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146 | |||
146 |
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147 | |||
147 |
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148 | |||
148 | SIGNAL vcc, gnd : STD_LOGIC_VECTOR(4 DOWNTO 0); |
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149 | SIGNAL vcc, gnd : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
149 | SIGNAL memi : memory_in_type; |
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150 | SIGNAL memi : memory_in_type; | |
150 | SIGNAL memo : memory_out_type; |
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151 | SIGNAL memo : memory_out_type; | |
151 | SIGNAL wpo : wprot_out_type; |
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152 | SIGNAL wpo : wprot_out_type; | |
152 | SIGNAL sdi : sdctrl_in_type; |
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153 | SIGNAL sdi : sdctrl_in_type; | |
153 | SIGNAL sdo : sdram_out_type; |
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154 | SIGNAL sdo : sdram_out_type; | |
154 | SIGNAL sdo2, sdo3 : sdctrl_out_type; |
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155 | SIGNAL sdo2, sdo3 : sdctrl_out_type; | |
155 |
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156 | |||
156 | SIGNAL apbi : apb_slv_in_type; |
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157 | SIGNAL apbi : apb_slv_in_type; | |
157 | SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none); |
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158 | SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none); | |
158 | SIGNAL ahbsi : ahb_slv_in_type; |
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159 | SIGNAL ahbsi : ahb_slv_in_type; | |
159 | SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none); |
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160 | SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none); | |
160 | SIGNAL ahbmi : ahb_mst_in_type; |
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161 | SIGNAL ahbmi : ahb_mst_in_type; | |
161 | SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); |
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162 | SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); | |
162 |
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163 | |||
163 | SIGNAL clkm, rstn, rstraw, pciclk, sdclkl, spw_lclk : STD_ULOGIC; |
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164 | SIGNAL clkm, rstn, rstraw, pciclk, sdclkl, spw_lclk : STD_ULOGIC; | |
164 | SIGNAL cgi : clkgen_in_type; |
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165 | SIGNAL cgi : clkgen_in_type; | |
165 | SIGNAL cgo : clkgen_out_type; |
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166 | SIGNAL cgo : clkgen_out_type; | |
166 | SIGNAL u1i, u2i, dui : uart_in_type; |
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167 | SIGNAL u1i, u2i, dui : uart_in_type; | |
167 | SIGNAL u1o, u2o, duo : uart_out_type; |
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168 | SIGNAL u1o, u2o, duo : uart_out_type; | |
168 |
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169 | |||
169 | SIGNAL irqi : irq_in_vector(0 TO NCPU-1); |
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170 | SIGNAL irqi : irq_in_vector(0 TO NCPU-1); | |
170 | SIGNAL irqo : irq_out_vector(0 TO NCPU-1); |
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171 | SIGNAL irqo : irq_out_vector(0 TO NCPU-1); | |
171 |
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172 | |||
172 | SIGNAL dbgi : l3_debug_in_vector(0 TO NCPU-1); |
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173 | SIGNAL dbgi : l3_debug_in_vector(0 TO NCPU-1); | |
173 | SIGNAL dbgo : l3_debug_out_vector(0 TO NCPU-1); |
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174 | SIGNAL dbgo : l3_debug_out_vector(0 TO NCPU-1); | |
174 |
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175 | |||
175 | SIGNAL dsui : dsu_in_type; |
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176 | SIGNAL dsui : dsu_in_type; | |
176 | SIGNAL dsuo : dsu_out_type; |
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177 | SIGNAL dsuo : dsu_out_type; | |
177 |
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178 | |||
178 | SIGNAL pcii : pci_in_type; |
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179 | SIGNAL pcii : pci_in_type; | |
179 | SIGNAL pcio : pci_out_type; |
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180 | SIGNAL pcio : pci_out_type; | |
180 |
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181 | |||
181 | SIGNAL ethi, ethi1, ethi2 : eth_in_type; |
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182 | SIGNAL ethi, ethi1, ethi2 : eth_in_type; | |
182 | SIGNAL etho, etho1, etho2 : eth_out_type; |
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183 | SIGNAL etho, etho1, etho2 : eth_out_type; | |
183 |
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184 | |||
184 | SIGNAL gpti : gptimer_in_type; |
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185 | SIGNAL gpti : gptimer_in_type; | |
185 |
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186 | |||
186 | SIGNAL gpioi : gpio_in_type; |
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187 | SIGNAL gpioi : gpio_in_type; | |
187 | SIGNAL gpioo : gpio_out_type; |
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188 | SIGNAL gpioo : gpio_out_type; | |
188 |
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189 | |||
189 |
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190 | |||
190 | SIGNAL lclk, pci_lclk : STD_ULOGIC := '0'; |
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191 | SIGNAL lclk, pci_lclk : STD_ULOGIC := '0'; | |
191 | SIGNAL pci_arb_req_n, pci_arb_gnt_n : STD_LOGIC_VECTOR(0 TO 3); |
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192 | SIGNAL pci_arb_req_n, pci_arb_gnt_n : STD_LOGIC_VECTOR(0 TO 3); | |
192 |
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193 | |||
193 | SIGNAL spwi : grspw_in_type_vector(0 TO 2); |
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194 | SIGNAL spwi : grspw_in_type_vector(0 TO 2); | |
194 | SIGNAL spwo : grspw_out_type_vector(0 TO 2); |
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195 | SIGNAL spwo : grspw_out_type_vector(0 TO 2); | |
195 | SIGNAL spw_rx_clk : STD_ULOGIC; |
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196 | SIGNAL spw_rx_clk : STD_ULOGIC; | |
196 |
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197 | |||
197 | ATTRIBUTE sync_set_reset : STRING; |
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198 | ATTRIBUTE sync_set_reset : STRING; | |
198 | ATTRIBUTE sync_set_reset OF rstn : SIGNAL IS "true"; |
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199 | ATTRIBUTE sync_set_reset OF rstn : SIGNAL IS "true"; | |
199 |
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200 | |||
200 | CONSTANT BOARD_FREQ : INTEGER := 40000; -- Board frequency in KHz |
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201 | CONSTANT BOARD_FREQ : INTEGER := 40000; -- Board frequency in KHz | |
201 | CONSTANT CPU_FREQ : INTEGER := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; |
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202 | CONSTANT CPU_FREQ : INTEGER := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; | |
202 | CONSTANT IOAEN : INTEGER := CFG_SDCTRL; |
|
203 | CONSTANT IOAEN : INTEGER := CFG_SDCTRL; | |
203 | CONSTANT CFG_SDEN : INTEGER := CFG_SDCTRL + CFG_MCTRL_SDEN; |
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204 | CONSTANT CFG_SDEN : INTEGER := CFG_SDCTRL + CFG_MCTRL_SDEN; | |
204 |
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205 | |||
205 | CONSTANT sysfreq : INTEGER := (CFG_CLKMUL/CFG_CLKDIV)*40000; |
|
206 | CONSTANT sysfreq : INTEGER := (CFG_CLKMUL/CFG_CLKDIV)*40000; | |
206 |
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207 | |||
207 | ----------------------------------------------------------------------------- |
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208 | ----------------------------------------------------------------------------- | |
208 |
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209 | |||
209 |
SIGNAL fifo_data |
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210 | SIGNAL fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
210 |
SIGNAL fifo_empty |
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211 | SIGNAL fifo_empty : STD_LOGIC; | |
211 |
SIGNAL fifo_ren |
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212 | SIGNAL fifo_ren : STD_LOGIC; | |
212 |
SIGNAL dma_data |
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213 | SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
213 |
SIGNAL dma_empty |
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214 | SIGNAL dma_empty : STD_LOGIC; | |
214 |
SIGNAL dma_ren |
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215 | SIGNAL dma_ren : STD_LOGIC; | |
215 |
SIGNAL header |
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216 | SIGNAL header : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
216 |
SIGNAL header_val |
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217 | SIGNAL header_val : STD_LOGIC; | |
217 |
SIGNAL header_ack |
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218 | SIGNAL header_ack : STD_LOGIC; | |
218 |
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219 | |||
219 | signal lclk2x : std_ulogic; |
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220 | SIGNAL lclk2x : STD_ULOGIC; | |
220 | signal clk2x : std_ulogic; |
|
221 | SIGNAL clk2x : STD_ULOGIC; | |
221 |
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222 | |||
222 |
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223 | CONSTANT boardfreq : INTEGER := 50000; | |
223 |
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224 | |||
224 | BEGIN |
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225 | BEGIN | |
225 |
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226 | |||
226 | ---------------------------------------------------------------------- |
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227 | ---------------------------------------------------------------------- | |
227 | --- Reset and Clock generation ------------------------------------- |
|
228 | --- Reset and Clock generation ------------------------------------- | |
228 | ---------------------------------------------------------------------- |
|
229 | ---------------------------------------------------------------------- | |
229 |
|
230 | |||
230 | vcc <= (OTHERS => '1'); |
|
231 | vcc <= (OTHERS => '1'); | |
231 | gnd <= (OTHERS => '0'); |
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232 | gnd <= (OTHERS => '0'); | |
232 | cgi.pllctrl <= "00"; |
|
233 | cgi.pllctrl <= "00"; | |
233 | cgi.pllrst <= rstraw; |
|
234 | cgi.pllrst <= rstraw; | |
234 |
|
235 | |||
235 |
pllref_pad |
|
236 | pllref_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (pllref, cgi.pllref); | |
|
237 | ||||
|
238 | clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk, lclk2x); | |||
236 |
|
239 | |||
237 | -- clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk, lclk); |
|
240 | PROCESS(lclk2x) | |
238 | clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk, lclk2x); |
|
|||
239 |
|
||||
240 | process(lclk2x) |
|
|||
241 | BEGIN |
|
241 | BEGIN | |
242 |
|
|
242 | IF lclk2x'EVENT AND lclk2x = '1' THEN | |
243 |
lclk <= |
|
243 | lclk <= NOT lclk; | |
244 | end if; |
|
244 | END IF; | |
245 | end process; |
|
245 | END PROCESS; | |
246 |
|
246 | |||
247 | pci_clk_pad : clkpad GENERIC MAP (tech => padtech, level => pci33) PORT MAP (pci_clk, pci_lclk); |
|
247 | pci_clk_pad : clkpad GENERIC MAP (tech => padtech, level => pci33) PORT MAP (pci_clk, pci_lclk); | |
248 |
|
248 | |||
249 |
|
|
249 | clkgen0 : clkgen -- clock generator | |
250 |
|
|
250 | GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV) | |
251 | -- CFG_CLK_NOFB, CFG_PCI, CFG_PCIDLL, CFG_PCISYSCLK) |
|
251 | PORT MAP (lclk, lclk, clkm, OPEN, clk2x, sdclkl, pciclk, cgi, cgo); | |
252 | -- PORT MAP (lclk, pci_lclk, clkm, OPEN, OPEN, sdclkl, pciclk, cgi, cgo); |
|
|||
253 |
|
252 | |||
254 | clkgen0 : clkgen -- clock generator |
|
253 | ramclk <= clkm; | |
255 | generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV) |
|
|||
256 | port map (lclk, lclk, clkm, open, clk2x, sdclkl, pciclk, cgi, cgo); |
|
|||
257 |
|
||||
258 | ramclk <= clkm; |
|
|||
259 |
|
254 | |||
260 | rst0 : rstgen -- reset generator |
|
255 | rst0 : rstgen -- reset generator | |
261 | PORT MAP (resetn, clkm, cgo.clklock, rstn, rstraw); |
|
256 | PORT MAP (resetn, clkm, cgo.clklock, rstn, rstraw); | |
262 |
|
257 | |||
263 | ---------------------------------------------------------------------- |
|
258 | ---------------------------------------------------------------------- | |
264 | --- AHB CONTROLLER -------------------------------------------------- |
|
259 | --- AHB CONTROLLER -------------------------------------------------- | |
265 | ---------------------------------------------------------------------- |
|
260 | ---------------------------------------------------------------------- | |
266 |
|
261 | |||
267 | ahb0 : ahbctrl -- AHB arbiter/multiplexer |
|
262 | ahb0 : ahbctrl -- AHB arbiter/multiplexer | |
268 | GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT, |
|
263 | GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT, | |
269 | rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, |
|
264 | rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, | |
270 | ioen => IOAEN, nahbm => maxahbm, nahbs => 8) |
|
265 | ioen => IOAEN, nahbm => maxahbm, nahbs => 8) | |
271 | PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); |
|
266 | PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); | |
272 |
|
267 | |||
273 | ---------------------------------------------------------------------- |
|
268 | ---------------------------------------------------------------------- | |
274 | --- LEON3 processor and DSU ----------------------------------------- |
|
269 | --- LEON3 processor and DSU ----------------------------------------- | |
275 | ---------------------------------------------------------------------- |
|
270 | ---------------------------------------------------------------------- | |
276 |
|
271 | |||
277 | l3 : IF CFG_LEON3 = 1 GENERATE |
|
272 | l3 : IF CFG_LEON3 = 1 GENERATE | |
278 | cpu : FOR i IN 0 TO NCPU-1 GENERATE |
|
273 | cpu : FOR i IN 0 TO NCPU-1 GENERATE | |
279 | u0 : leon3s -- LEON3 processor |
|
274 | u0 : leon3s -- LEON3 processor | |
280 | GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, |
|
275 | GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, | |
281 | 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, |
|
276 | 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, | |
282 | CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, |
|
277 | CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, | |
283 | CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, |
|
278 | CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, | |
284 | CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, |
|
279 | CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, | |
285 | CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1, CFG_DFIXED) |
|
280 | CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1, CFG_DFIXED) | |
286 | PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, |
|
281 | PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, | |
287 | irqi(i), irqo(i), dbgi(i), dbgo(i)); |
|
282 | irqi(i), irqo(i), dbgi(i), dbgo(i)); | |
288 | END GENERATE; |
|
283 | END GENERATE; | |
289 | errorn_pad : odpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error); |
|
284 | errorn_pad : odpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error); | |
290 |
|
285 | |||
291 |
|
286 | |||
292 | dsugen : IF CFG_DSU = 1 GENERATE |
|
287 | dsugen : IF CFG_DSU = 1 GENERATE | |
293 | dsu0 : dsu3 -- LEON3 Debug Support Unit |
|
288 | dsu0 : dsu3 -- LEON3 Debug Support Unit | |
294 | GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#, |
|
289 | GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#, | |
295 | ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) |
|
290 | ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) | |
296 | PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); |
|
291 | PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); | |
297 | dsuen_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (dsuen, dsui.enable); |
|
292 | dsuen_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (dsuen, dsui.enable); | |
298 | dsubre_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (dsubre, dsui.break); |
|
293 | dsubre_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (dsubre, dsui.break); | |
299 | dsuact_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (dsuact, dsuo.active); |
|
294 | dsuact_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (dsuact, dsuo.active); | |
300 | END GENERATE; |
|
295 | END GENERATE; | |
301 | END GENERATE; |
|
296 | END GENERATE; | |
302 |
|
297 | |||
303 | nodsu : IF CFG_DSU = 0 GENERATE |
|
298 | nodsu : IF CFG_DSU = 0 GENERATE | |
304 | ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; |
|
299 | ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; | |
305 | END GENERATE; |
|
300 | END GENERATE; | |
306 |
|
301 | |||
307 | dcomgen : IF CFG_AHB_UART = 1 GENERATE |
|
302 | dcomgen : IF CFG_AHB_UART = 1 GENERATE | |
308 | dcom0 : ahbuart -- Debug UART |
|
303 | dcom0 : ahbuart -- Debug UART | |
309 | GENERIC MAP (hindex => NCPU, pindex => 7, paddr => 7) |
|
304 | GENERIC MAP (hindex => NCPU, pindex => 7, paddr => 7) | |
310 | PORT MAP (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(NCPU)); |
|
305 | PORT MAP (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(NCPU)); | |
311 | dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (dsurx, dui.rxd); |
|
306 | dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (dsurx, dui.rxd); | |
312 | dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (dsutx, duo.txd); |
|
307 | dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (dsutx, duo.txd); | |
313 | END GENERATE; |
|
308 | END GENERATE; | |
314 | nouah : IF CFG_AHB_UART = 0 GENERATE apbo(7) <= apb_none; END GENERATE; |
|
309 | nouah : IF CFG_AHB_UART = 0 GENERATE apbo(7) <= apb_none; END GENERATE; | |
315 |
|
310 | |||
316 | ahbjtaggen0 : IF CFG_AHB_JTAG = 1 GENERATE |
|
311 | ahbjtaggen0 : IF CFG_AHB_JTAG = 1 GENERATE | |
317 | ahbjtag0 : ahbjtag GENERIC MAP(tech => fabtech, hindex => NCPU+CFG_AHB_UART) |
|
312 | ahbjtag0 : ahbjtag GENERIC MAP(tech => fabtech, hindex => NCPU+CFG_AHB_UART) | |
318 | PORT MAP(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART), |
|
313 | PORT MAP(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART), | |
319 | OPEN, OPEN, OPEN, OPEN, OPEN, OPEN, OPEN, gnd(0)); |
|
314 | OPEN, OPEN, OPEN, OPEN, OPEN, OPEN, OPEN, gnd(0)); | |
320 | END GENERATE; |
|
315 | END GENERATE; | |
321 |
|
316 | |||
322 | ---------------------------------------------------------------------- |
|
317 | ---------------------------------------------------------------------- | |
323 | --- Memory controllers ---------------------------------------------- |
|
318 | --- Memory controllers ---------------------------------------------- | |
324 | ---------------------------------------------------------------------- |
|
319 | ---------------------------------------------------------------------- | |
325 |
|
320 | -- LEON2 memory controller | ||
326 | --src : IF CFG_SRCTRL = 1 GENERATE -- 32-bit PROM/SRAM controller |
|
321 | sr1 : mctrl | |
327 | -- sr0 : srctrl GENERIC MAP (hindex => 0, ramws => CFG_SRCTRL_RAMWS, |
|
322 | GENERIC MAP ( | |
328 | -- romws => CFG_SRCTRL_PROMWS, ramaddr => 16#400#, |
|
323 | hindex => 0, | |
329 | -- prom8en => CFG_SRCTRL_8BIT, rmw => CFG_SRCTRL_RMW) |
|
324 | pindex => 0, | |
330 | -- PORT MAP (rstn, clkm, ahbsi, ahbso(0), memi, memo, sdo3); |
|
325 | romaddr => 16#000#, | |
331 | -- apbo(0) <= apb_none; |
|
326 | rommask => 16#E00#, | |
332 | --END GENERATE; |
|
327 | ioaddr => 16#200#, | |
333 |
|
328 | iomask => 16#E00#, | ||
334 | --sdc : IF CFG_SDCTRL = 1 GENERATE |
|
329 | ramaddr => 16#400#, | |
335 | -- sdc : sdctrl GENERIC MAP (hindex => 3, haddr => 16#600#, hmask => 16#F00#, |
|
330 | rammask => 16#C00#, | |
336 | -- ioaddr => 1, fast => 0, pwron => 0, invclk => CFG_SDCTRL_INVCLK, |
|
331 | paddr => 0, | |
337 | -- sdbits => 32 + 32*CFG_SDCTRL_SD64, pageburst => CFG_SDCTRL_PAGE) |
|
332 | pmask => 16#fff#, | |
338 | -- PORT MAP (rstn, clkm, ahbsi, ahbso(3), sdi, sdo2); |
|
333 | wprot => 0, | |
339 | -- sa_pad : outpadv GENERIC MAP (width => 15, tech => padtech) |
|
334 | invclk => 0, | |
340 | -- PORT MAP (sa, sdo2.address); |
|
335 | fast => 0, | |
341 | -- sd_pad : iopadv GENERIC MAP (width => 32, tech => padtech) |
|
336 | romasel => 28, | |
342 | -- PORT MAP (sd(31 DOWNTO 0), sdo2.data(31 DOWNTO 0), sdo2.bdrive, sdi.data(31 DOWNTO 0)); |
|
337 | sdrasel => 29, | |
343 | -- sd2 : IF CFG_SDCTRL_SD64 = 1 GENERATE |
|
338 | srbanks => 4, | |
344 | -- sd_pad2 : iopadv GENERIC MAP (width => 32) |
|
339 | ram8 => 0, | |
345 | -- PORT MAP (sd(63 DOWNTO 32), sdo2.data, sdo2.bdrive, sdi.data(63 DOWNTO 32)); |
|
340 | ram16 => 0, | |
346 | -- END GENERATE; |
|
341 | sden => 0, | |
347 | -- sdcke_pad : outpadv GENERIC MAP (width => 2, tech => padtech) |
|
342 | sepbus => 0, | |
348 | -- PORT MAP (sdcke, sdo2.sdcke); |
|
343 | sdbits => 32, | |
349 | -- sdwen_pad : outpad GENERIC MAP (tech => padtech) |
|
344 | sdlsb => 2, -- set to 12 for the GE-HPE board | |
350 | -- PORT MAP (sdwen, sdo2.sdwen); |
|
345 | oepol => 0, | |
351 | -- sdcsn_pad : outpadv GENERIC MAP (width => 2, tech => padtech) |
|
346 | syncrst => 0, | |
352 | -- PORT MAP (sdcsn, sdo2.sdcsn); |
|
347 | pageburst => 0, | |
353 | -- sdras_pad : outpad GENERIC MAP (tech => padtech) |
|
348 | scantest => 0, | |
354 | -- PORT MAP (sdrasn, sdo2.rasn); |
|
349 | mobile => 0 | |
355 | -- sdcas_pad : outpad GENERIC MAP (tech => padtech) |
|
350 | ) | |
356 | -- PORT MAP (sdcasn, sdo2.casn); |
|
351 | PORT MAP ( | |
357 | -- sddqm_pad : outpadv GENERIC MAP (width => 8, tech => padtech) |
|
352 | rst => rstn, | |
358 | -- PORT MAP (sddqm, sdo2.dqm(7 DOWNTO 0)); |
|
353 | clk => clkm, | |
359 | --END GENERATE; |
|
354 | memi => memi, | |
360 |
|
355 | memo => memo, | ||
361 | -- mg2 : IF CFG_MCTRL_LEON2 = 1 GENERATE -- LEON2 memory controller |
|
356 | ahbsi => ahbsi, | |
362 | sr1 : mctrl GENERIC MAP ( hindex => 0, |
|
357 | ahbso => ahbso(0), | |
363 | pindex => 0, |
|
358 | apbi => apbi, | |
364 | paddr => 0--, |
|
359 | apbo => apbo(0), | |
365 | --srbanks => 4+CFG_MCTRL_5CS, |
|
360 | wpo => wpo, | |
366 | --sden => CFG_MCTRL_SDEN, |
|
361 | sdo => sdo | |
367 | --ram8 => CFG_MCTRL_RAM8BIT, |
|
362 | ); | |
368 | --ram16 => CFG_MCTRL_RAM16BIT, |
|
|||
369 | --invclk => CFG_MCTRL_INVCLK, |
|
|||
370 | --sepbus => CFG_MCTRL_SEPBUS, |
|
|||
371 | --sdbits => 32 + 32*CFG_MCTRL_SD64, |
|
|||
372 | --pageburst => CFG_MCTRL_PAGE |
|
|||
373 | ) |
|
|||
374 | PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); |
|
|||
375 | --sdpads : IF CFG_MCTRL_SDEN = 1 GENERATE -- SDRAM controller |
|
|||
376 | -- sd2 : IF CFG_MCTRL_SEPBUS = 1 GENERATE |
|
|||
377 | -- sa_pad : outpadv GENERIC MAP (width => 15) PORT MAP (sa, memo.sa); |
|
|||
378 | -- bdr : FOR i IN 0 TO 3 GENERATE |
|
|||
379 | -- sd_pad : iopadv GENERIC MAP (tech => padtech, width => 8) |
|
|||
380 | -- PORT MAP (sd(31-i*8 DOWNTO 24-i*8), memo.data(31-i*8 DOWNTO 24-i*8), |
|
|||
381 | -- memo.bdrive(i), memi.sd(31-i*8 DOWNTO 24-i*8)); |
|
|||
382 | -- sd2 : IF CFG_MCTRL_SD64 = 1 GENERATE |
|
|||
383 | -- sd_pad2 : iopadv GENERIC MAP (tech => padtech, width => 8) |
|
|||
384 | -- PORT MAP (sd(31-i*8+32 DOWNTO 24-i*8+32), memo.data(31-i*8 DOWNTO 24-i*8), |
|
|||
385 | -- memo.bdrive(i), memi.sd(31-i*8+32 DOWNTO 24-i*8+32)); |
|
|||
386 | -- END GENERATE; |
|
|||
387 | -- END GENERATE; |
|
|||
388 | -- END GENERATE; |
|
|||
389 | -- sdwen_pad : outpad GENERIC MAP (tech => padtech) |
|
|||
390 | -- PORT MAP (sdwen, sdo.sdwen); |
|
|||
391 | -- sdras_pad : outpad GENERIC MAP (tech => padtech) |
|
|||
392 | -- PORT MAP (sdrasn, sdo.rasn); |
|
|||
393 | -- sdcas_pad : outpad GENERIC MAP (tech => padtech) |
|
|||
394 | -- PORT MAP (sdcasn, sdo.casn); |
|
|||
395 | -- sddqm_pad : outpadv GENERIC MAP (width => 8, tech => padtech) |
|
|||
396 | -- PORT MAP (sddqm, sdo.dqm); |
|
|||
397 | -- sdcke_pad : outpadv GENERIC MAP (width => 2, tech => padtech) |
|
|||
398 | -- PORT MAP (sdcke, sdo.sdcke); |
|
|||
399 | -- sdcsn_pad : outpadv GENERIC MAP (width => 2, tech => padtech) |
|
|||
400 | -- PORT MAP (sdcsn, sdo.sdcsn); |
|
|||
401 | --END GENERATE; |
|
|||
402 | -- END GENERATE; |
|
|||
403 |
|
||||
404 | --nosd0 : IF (CFG_MCTRL_SDEN = 0) AND (CFG_SDCTRL = 0) GENERATE -- no SDRAM controller |
|
|||
405 | -- sdcke_pad : outpadv GENERIC MAP (width => 2, tech => padtech) |
|
|||
406 | -- PORT MAP (sdcke, sdo3.sdcke); |
|
|||
407 | -- sdcsn_pad : outpadv GENERIC MAP (width => 2, tech => padtech) |
|
|||
408 | -- PORT MAP (sdcsn, sdo3.sdcsn); |
|
|||
409 | --END GENERATE; |
|
|||
410 |
|
363 | |||
411 |
|
364 | |||
412 | memi.brdyn <= '1'; memi.bexcn <= '1'; |
|
365 | memi.brdyn <= '1'; memi.bexcn <= '1'; | |
413 | memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10"; |
|
366 | memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10"; | |
414 |
|
367 | |||
415 | mgpads : IF (CFG_SRCTRL = 1) OR (CFG_MCTRL_LEON2 = 1) GENERATE -- prom/sram pads |
|
368 | mgpads : IF (CFG_SRCTRL = 1) OR (CFG_MCTRL_LEON2 = 1) GENERATE -- prom/sram pads | |
416 | addr_pad : outpadv GENERIC MAP (width => 28, tech => padtech) PORT MAP (address, memo.address(27 DOWNTO 0)); |
|
369 | addr_pad : outpadv GENERIC MAP (width => 28, tech => padtech) PORT MAP (address, memo.address(27 DOWNTO 0)); | |
417 |
rams_pad : outpadv GENERIC MAP (width => 5, |
|
370 | rams_pad : outpadv GENERIC MAP (width => 5, tech => padtech) PORT MAP (ramsn, memo.ramsn(4 DOWNTO 0)); | |
418 |
roms_pad : outpadv GENERIC MAP (width => 2, |
|
371 | roms_pad : outpadv GENERIC MAP (width => 2, tech => padtech) PORT MAP (romsn, memo.romsn(1 DOWNTO 0)); | |
419 |
oen_pad : outpad |
|
372 | oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (oen, memo.oen); | |
420 |
rwen_pad : outpadv GENERIC MAP (width => 4, |
|
373 | rwen_pad : outpadv GENERIC MAP (width => 4, tech => padtech) PORT MAP (rwen, memo.wrn); | |
421 |
roen_pad : outpadv GENERIC MAP (width => 5, |
|
374 | roen_pad : outpadv GENERIC MAP (width => 5, tech => padtech) PORT MAP (ramoen, memo.ramoen(4 DOWNTO 0)); | |
422 |
wri_pad : outpad |
|
375 | wri_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (writen, memo.writen); | |
423 |
read_pad : outpad |
|
376 | read_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (read, memo.read); | |
424 |
iosn_pad : outpad |
|
377 | iosn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (iosn, memo.iosn); | |
425 |
|
378 | |||
426 | bdr : FOR i IN 0 TO 3 GENERATE |
|
379 | bdr : FOR i IN 0 TO 3 GENERATE | |
427 | data_pad : iopadv GENERIC MAP (tech => padtech, width => 8) |
|
380 | data_pad : iopadv GENERIC MAP (tech => padtech, width => 8) | |
428 | PORT MAP (data(31-i*8 DOWNTO 24-i*8), memo.data(31-i*8 DOWNTO 24-i*8), |
|
381 | PORT MAP (data(31-i*8 DOWNTO 24-i*8), memo.data(31-i*8 DOWNTO 24-i*8), | |
429 | memo.bdrive(i), memi.data(31-i*8 DOWNTO 24-i*8)); |
|
382 | memo.bdrive(i), memi.data(31-i*8 DOWNTO 24-i*8)); | |
430 | END GENERATE; |
|
383 | END GENERATE; | |
431 |
|
384 | |||
432 | END GENERATE; |
|
385 | END GENERATE; | |
433 |
|
386 | |||
434 | SSRAM_0: ssram_plugin |
|
387 | SSRAM_0 : ssram_plugin | |
435 |
|
|
388 | GENERIC MAP (tech => padtech) | |
436 | port map (lclk2x,memo,SSRAM_CLK,nBWa,nBWb,nBWc,nBWd,nBWE,nADSC,nADSP,nADV,nGW,nCE1,CE2,nCE3,nOE,MODE,ZZ); |
|
389 | PORT MAP (lclk2x, memo, SSRAM_CLK, | |
437 |
|
390 | nBWa, nBWb, nBWc, nBWd, nBWE, nADSC, nADSP, nADV, nGW, nCE1, CE2, nCE3, nOE, MODE, ZZ); | ||
438 | ---------------------------------------------------------------------- |
|
|||
439 | --- APB Bridge and various periherals ------------------------------- |
|
|||
440 | ---------------------------------------------------------------------- |
|
|||
441 |
|
391 | |||
442 | bpromgen : IF CFG_AHBROMEN /= 0 GENERATE |
|
392 | ||
443 | brom : ENTITY work.ahbrom |
|
|||
444 | GENERIC MAP (hindex => 5, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP) |
|
|||
445 | PORT MAP (rstn, clkm, ahbsi, ahbso(5)); |
|
|||
446 | END GENERATE; |
|
|||
447 | nobpromgen : IF CFG_AHBROMEN = 0 GENERATE |
|
|||
448 | ahbso(5) <= ahbs_none; |
|
|||
449 | END GENERATE; |
|
|||
450 |
|
393 | |||
451 | ---------------------------------------------------------------------- |
|
394 | ---------------------------------------------------------------------- | |
452 | --- APB Bridge and various periherals ------------------------------- |
|
395 | --- APB Bridge and various periherals ------------------------------- | |
453 | ---------------------------------------------------------------------- |
|
396 | ---------------------------------------------------------------------- | |
454 |
|
397 | |||
455 | apb0 : apbctrl -- AHB/APB bridge |
|
398 | apb0 : apbctrl -- AHB/APB bridge | |
456 | GENERIC MAP (hindex => 1, haddr => CFG_APBADDR) |
|
399 | GENERIC MAP (hindex => 1, haddr => CFG_APBADDR) | |
457 | PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo); |
|
400 | PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo); | |
458 |
|
401 | |||
459 | ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE |
|
402 | ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE | |
460 | uart1 : apbuart -- UART 1 |
|
403 | uart1 : apbuart -- UART 1 | |
461 | GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart, |
|
404 | GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart, | |
462 | fifosize => CFG_UART1_FIFO) |
|
405 | fifosize => CFG_UART1_FIFO) | |
463 | PORT MAP (rstn, clkm, apbi, apbo(1), u1i, u1o); |
|
406 | PORT MAP (rstn, clkm, apbi, apbo(1), u1i, u1o); | |
464 | u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd; |
|
407 | u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd; | |
465 | END GENERATE; |
|
408 | END GENERATE; | |
466 | noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE; |
|
409 | noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE; | |
467 |
|
410 | |||
468 | ua2 : IF CFG_UART2_ENABLE /= 0 GENERATE |
|
411 | ua2 : IF CFG_UART2_ENABLE /= 0 GENERATE | |
469 | uart2 : apbuart -- UART 2 |
|
412 | uart2 : apbuart -- UART 2 | |
470 | GENERIC MAP (pindex => 9, paddr => 9, pirq => 3, fifosize => CFG_UART2_FIFO) |
|
413 | GENERIC MAP (pindex => 9, paddr => 9, pirq => 3, fifosize => CFG_UART2_FIFO) | |
471 | PORT MAP (rstn, clkm, apbi, apbo(9), u2i, u2o); |
|
414 | PORT MAP (rstn, clkm, apbi, apbo(9), u2i, u2o); | |
472 | u2i.rxd <= rxd2; u2i.ctsn <= '0'; u2i.extclk <= '0'; txd2 <= u2o.txd; |
|
415 | u2i.rxd <= rxd2; u2i.ctsn <= '0'; u2i.extclk <= '0'; txd2 <= u2o.txd; | |
473 | END GENERATE; |
|
416 | END GENERATE; | |
474 | noua1 : IF CFG_UART2_ENABLE = 0 GENERATE apbo(9) <= apb_none; END GENERATE; |
|
417 | noua1 : IF CFG_UART2_ENABLE = 0 GENERATE apbo(9) <= apb_none; END GENERATE; | |
475 |
|
418 | |||
476 | irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE |
|
419 | irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE | |
477 | irqctrl0 : irqmp -- interrupt controller |
|
420 | irqctrl0 : irqmp -- interrupt controller | |
478 | GENERIC MAP (pindex => 2, paddr => 2, ncpu => NCPU) |
|
421 | GENERIC MAP (pindex => 2, paddr => 2, ncpu => NCPU) | |
479 | PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi); |
|
422 | PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi); | |
480 | END GENERATE; |
|
423 | END GENERATE; | |
481 | irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE |
|
424 | irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE | |
482 | x : FOR i IN 0 TO NCPU-1 GENERATE |
|
425 | x : FOR i IN 0 TO NCPU-1 GENERATE | |
483 | irqi(i).irl <= "0000"; |
|
426 | irqi(i).irl <= "0000"; | |
484 | END GENERATE; |
|
427 | END GENERATE; | |
485 | apbo(2) <= apb_none; |
|
428 | apbo(2) <= apb_none; | |
486 | END GENERATE; |
|
429 | END GENERATE; | |
487 |
|
430 | |||
488 | gpt : IF CFG_GPT_ENABLE /= 0 GENERATE |
|
431 | gpt : IF CFG_GPT_ENABLE /= 0 GENERATE | |
489 | timer0 : gptimer -- timer unit |
|
432 | timer0 : gptimer -- timer unit | |
490 | GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, |
|
433 | GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, | |
491 | sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, |
|
434 | sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, | |
492 | nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOG) |
|
435 | nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOG) | |
493 | PORT MAP (rstn, clkm, apbi, apbo(3), gpti, OPEN); |
|
436 | PORT MAP (rstn, clkm, apbi, apbo(3), gpti, OPEN); | |
494 | gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0'; |
|
437 | gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0'; | |
495 | END GENERATE; |
|
438 | END GENERATE; | |
496 | notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE; |
|
439 | notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE; | |
497 |
|
440 | |||
498 | gpio0 : IF CFG_GRGPIO_ENABLE /= 0 GENERATE -- GR GPIO unit |
|
441 | gpio0 : IF CFG_GRGPIO_ENABLE /= 0 GENERATE -- GR GPIO unit | |
499 | grgpio0 : grgpio |
|
442 | grgpio0 : grgpio | |
500 | GENERIC MAP(pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, |
|
443 | GENERIC MAP(pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, | |
501 | nbits => CFG_GRGPIO_WIDTH) |
|
444 | nbits => CFG_GRGPIO_WIDTH) | |
502 | PORT MAP(rstn, clkm, apbi, apbo(11), gpioi, gpioo); |
|
445 | PORT MAP(rstn, clkm, apbi, apbo(11), gpioi, gpioo); | |
503 |
|
446 | |||
504 | pio_pads : FOR i IN 0 TO CFG_GRGPIO_WIDTH-1 GENERATE |
|
447 | pio_pads : FOR i IN 0 TO CFG_GRGPIO_WIDTH-1 GENERATE | |
505 | pio_pad : iopad GENERIC MAP (tech => padtech) |
|
448 | pio_pad : iopad GENERIC MAP (tech => padtech) | |
506 | PORT MAP (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i)); |
|
449 | PORT MAP (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i)); | |
507 | END GENERATE; |
|
450 | END GENERATE; | |
508 | END GENERATE; |
|
451 | END GENERATE; | |
509 |
|
452 | |||
510 | ----------------------------------------------------------------------- |
|
453 | ----------------------------------------------------------------------- | |
511 | --- PCI ------------------------------------------------------------ |
|
454 | --- PCI ------------------------------------------------------------ | |
512 | ----------------------------------------------------------------------- |
|
455 | ----------------------------------------------------------------------- | |
513 |
|
456 | |||
514 | pp : IF CFG_PCI /= 0 GENERATE |
|
457 | pp : IF CFG_PCI /= 0 GENERATE | |
515 |
|
458 | |||
516 | pci_gr0 : IF CFG_PCI = 1 GENERATE -- simple target-only |
|
459 | pci_gr0 : IF CFG_PCI = 1 GENERATE -- simple target-only | |
517 | pci0 : pci_target GENERIC MAP (hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG, |
|
460 | pci0 : pci_target GENERIC MAP (hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG, | |
518 | device_id => CFG_PCIDID, vendor_id => CFG_PCIVID) |
|
461 | device_id => CFG_PCIDID, vendor_id => CFG_PCIVID) | |
519 | PORT MAP (rstn, clkm, pciclk, pcii, pcio, ahbmi, ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG)); |
|
462 | PORT MAP (rstn, clkm, pciclk, pcii, pcio, ahbmi, ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG)); | |
520 | END GENERATE; |
|
463 | END GENERATE; | |
521 |
|
464 | |||
522 | pci_mtf0 : IF CFG_PCI = 2 GENERATE -- master/target with fifo |
|
465 | pci_mtf0 : IF CFG_PCI = 2 GENERATE -- master/target with fifo | |
523 | pci0 : pci_mtf GENERIC MAP (memtech => memtech, hmstndx => NCPU+CFG_AHB_UART+CFG_AHB_JTAG, |
|
466 | pci0 : pci_mtf GENERIC MAP (memtech => memtech, hmstndx => NCPU+CFG_AHB_UART+CFG_AHB_JTAG, | |
524 | fifodepth => log2(CFG_PCIDEPTH), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID, |
|
467 | fifodepth => log2(CFG_PCIDEPTH), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID, | |
525 | hslvndx => 4, pindex => 4, paddr => 4, haddr => 16#E00#, |
|
468 | hslvndx => 4, pindex => 4, paddr => 4, haddr => 16#E00#, | |
526 | ioaddr => 16#400#, nsync => 2, hostrst => 1) |
|
469 | ioaddr => 16#400#, nsync => 2, hostrst => 1) | |
527 | PORT MAP (rstn, clkm, pciclk, pcii, pcio, apbi, apbo(4), |
|
470 | PORT MAP (rstn, clkm, pciclk, pcii, pcio, apbi, apbo(4), | |
528 | ahbmi, ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4)); |
|
471 | ahbmi, ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4)); | |
529 | END GENERATE; |
|
472 | END GENERATE; | |
530 |
|
473 | |||
531 | pci_mtf1 : IF CFG_PCI = 3 GENERATE -- master/target with fifo and DMA |
|
474 | pci_mtf1 : IF CFG_PCI = 3 GENERATE -- master/target with fifo and DMA | |
532 | dma : pcidma GENERIC MAP (memtech => memtech, dmstndx => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1, |
|
475 | dma : pcidma GENERIC MAP (memtech => memtech, dmstndx => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1, | |
533 | dapbndx => 5, dapbaddr => 5, blength => blength, mstndx => NCPU+CFG_AHB_UART+CFG_AHB_JTAG, |
|
476 | dapbndx => 5, dapbaddr => 5, blength => blength, mstndx => NCPU+CFG_AHB_UART+CFG_AHB_JTAG, | |
534 | fifodepth => log2(CFG_PCIDEPTH), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID, |
|
477 | fifodepth => log2(CFG_PCIDEPTH), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID, | |
535 | slvndx => 4, apbndx => 4, apbaddr => 4, haddr => 16#E00#, ioaddr => 16#800#, |
|
478 | slvndx => 4, apbndx => 4, apbaddr => 4, haddr => 16#E00#, ioaddr => 16#800#, | |
536 | nsync => 2, hostrst => 1) |
|
479 | nsync => 2, hostrst => 1) | |
537 | PORT MAP (rstn, clkm, pciclk, pcii, pcio, apbo(5), ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1), |
|
480 | PORT MAP (rstn, clkm, pciclk, pcii, pcio, apbo(5), ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1), | |
538 | apbi, apbo(4), ahbmi, ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4)); |
|
481 | apbi, apbo(4), ahbmi, ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4)); | |
539 | END GENERATE; |
|
482 | END GENERATE; | |
540 |
|
483 | |||
541 | pci_trc0 : IF CFG_PCITBUFEN /= 0 GENERATE -- PCI trace buffer |
|
484 | pci_trc0 : IF CFG_PCITBUFEN /= 0 GENERATE -- PCI trace buffer | |
542 | pt0 : pcitrace GENERIC MAP (depth => (6 + log2(CFG_PCITBUF/256)), |
|
485 | pt0 : pcitrace GENERIC MAP (depth => (6 + log2(CFG_PCITBUF/256)), | |
543 | memtech => memtech, pindex => 8, paddr => 16#100#, pmask => 16#f00#) |
|
486 | memtech => memtech, pindex => 8, paddr => 16#100#, pmask => 16#f00#) | |
544 | PORT MAP (rstn, clkm, pciclk, pcii, apbi, apbo(8)); |
|
487 | PORT MAP (rstn, clkm, pciclk, pcii, apbi, apbo(8)); | |
545 | END GENERATE; |
|
488 | END GENERATE; | |
546 |
|
489 | |||
547 | pcia0 : IF CFG_PCI_ARB = 1 GENERATE -- PCI arbiter |
|
490 | pcia0 : IF CFG_PCI_ARB = 1 GENERATE -- PCI arbiter | |
548 | pciarb0 : pciarb GENERIC MAP (pindex => 10, paddr => 10, |
|
491 | pciarb0 : pciarb GENERIC MAP (pindex => 10, paddr => 10, | |
549 | apb_en => CFG_PCI_ARBAPB) |
|
492 | apb_en => CFG_PCI_ARBAPB) | |
550 | PORT MAP (clk => pciclk, rst_n => pcii.rst, |
|
493 | PORT MAP (clk => pciclk, rst_n => pcii.rst, | |
551 | req_n => pci_arb_req_n, frame_n => pcii.frame, |
|
494 | req_n => pci_arb_req_n, frame_n => pcii.frame, | |
552 | gnt_n => pci_arb_gnt_n, pclk => clkm, |
|
495 | gnt_n => pci_arb_gnt_n, pclk => clkm, | |
553 | prst_n => rstn, apbi => apbi, apbo => apbo(10) |
|
496 | prst_n => rstn, apbi => apbi, apbo => apbo(10) | |
554 | ); |
|
497 | ); | |
555 | pgnt_pad : outpadv GENERIC MAP (tech => padtech, width => 4) |
|
498 | pgnt_pad : outpadv GENERIC MAP (tech => padtech, width => 4) | |
556 | PORT MAP (pci_arb_gnt, pci_arb_gnt_n); |
|
499 | PORT MAP (pci_arb_gnt, pci_arb_gnt_n); | |
557 | preq_pad : inpadv GENERIC MAP (tech => padtech, width => 4) |
|
500 | preq_pad : inpadv GENERIC MAP (tech => padtech, width => 4) | |
558 | PORT MAP (pci_arb_req, pci_arb_req_n); |
|
501 | PORT MAP (pci_arb_req, pci_arb_req_n); | |
559 | END GENERATE; |
|
502 | END GENERATE; | |
560 |
|
503 | |||
561 | pcipads0 : pcipads GENERIC MAP (padtech => padtech) -- PCI pads |
|
504 | pcipads0 : pcipads GENERIC MAP (padtech => padtech) -- PCI pads | |
562 | PORT MAP (pci_rst, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe, |
|
505 | PORT MAP (pci_rst, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe, | |
563 | pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr, |
|
506 | pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr, | |
564 | pci_par, pci_req, pci_serr, pci_host, pci_66, pcii, pcio); |
|
507 | pci_par, pci_req, pci_serr, pci_host, pci_66, pcii, pcio); | |
565 |
|
508 | |||
566 | END GENERATE; |
|
509 | END GENERATE; | |
567 |
|
510 | |||
568 | -- nop1 : IF CFG_PCI <= 1 GENERATE apbo(4) <= apb_none; END GENERATE; |
|
511 | -- nop1 : IF CFG_PCI <= 1 GENERATE apbo(4) <= apb_none; END GENERATE; | |
569 | -- nop2 : IF CFG_PCI <= 2 GENERATE apbo(5) <= apb_none; END GENERATE; |
|
512 | -- nop2 : IF CFG_PCI <= 2 GENERATE apbo(5) <= apb_none; END GENERATE; | |
570 | nop3 : IF CFG_PCI <= 1 GENERATE ahbso(4) <= ahbs_none; END GENERATE; |
|
513 | nop3 : IF CFG_PCI <= 1 GENERATE ahbso(4) <= ahbs_none; END GENERATE; | |
571 | notrc : IF CFG_PCITBUFEN = 0 GENERATE apbo(8) <= apb_none; END GENERATE; |
|
514 | notrc : IF CFG_PCITBUFEN = 0 GENERATE apbo(8) <= apb_none; END GENERATE; | |
572 | noarb : IF CFG_PCI_ARB = 0 GENERATE apbo(10) <= apb_none; END GENERATE; |
|
515 | noarb : IF CFG_PCI_ARB = 0 GENERATE apbo(10) <= apb_none; END GENERATE; | |
573 |
|
516 | |||
574 |
|
517 | |||
575 | ahbso(6) <= ahbs_none; |
|
518 | -- ahbso(6) <= ahbs_none; | |
576 |
|
519 | |||
577 | ----------------------------------------------------------------------- |
|
520 | ----------------------------------------------------------------------- | |
578 | --- AHB RAM ---------------------------------------------------------- |
|
521 | --- AHB RAM ---------------------------------------------------------- | |
579 | ----------------------------------------------------------------------- |
|
522 | ----------------------------------------------------------------------- | |
580 |
|
523 | |||
581 | ocram : IF CFG_AHBRAMEN = 1 GENERATE |
|
524 | ocram : IF CFG_AHBRAMEN = 1 GENERATE | |
582 | ahbram0 : ahbram GENERIC MAP (hindex => 7, haddr => CFG_AHBRADDR, |
|
525 | ahbram0 : ahbram GENERIC MAP (hindex => 7, haddr => CFG_AHBRADDR, | |
583 | tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ) |
|
526 | tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ) | |
584 | PORT MAP (rstn, clkm, ahbsi, ahbso(7)); |
|
527 | PORT MAP (rstn, clkm, ahbsi, ahbso(7)); | |
585 | END GENERATE; |
|
528 | END GENERATE; | |
586 | nram : IF CFG_AHBRAMEN = 0 GENERATE ahbso(7) <= ahbs_none; END GENERATE; |
|
529 | nram : IF CFG_AHBRAMEN = 0 GENERATE ahbso(7) <= ahbs_none; END GENERATE; | |
587 |
|
530 | |||
588 | ----------------------------------------------------------------------- |
|
531 | ----------------------------------------------------------------------- | |
589 | --- SPACEWIRE ------------------------------------------------------- |
|
532 | --- SPACEWIRE ------------------------------------------------------- | |
590 | ----------------------------------------------------------------------- |
|
533 | ----------------------------------------------------------------------- | |
591 | --This template does NOT currently support grspw2 so only use grspw1 |
|
534 | --This template does NOT currently support grspw2 so only use grspw1 | |
592 | spw : IF CFG_SPW_EN > 0 GENERATE |
|
535 | spw : IF CFG_SPW_EN > 0 GENERATE | |
593 | spw_rx_clk <= '0'; |
|
536 | spw_rx_clk <= '0'; | |
594 | spw_clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (spw_clk, spw_lclk); |
|
537 | spw_clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (spw_clk, spw_lclk); | |
595 | swloop : FOR i IN 0 TO CFG_SPW_NUM-1 GENERATE |
|
538 | swloop : FOR i IN 0 TO CFG_SPW_NUM-1 GENERATE | |
596 | sw0 : grspwm GENERIC MAP(tech => memtech, netlist => CFG_SPW_NETLIST, |
|
539 | sw0 : grspwm GENERIC MAP(tech => memtech, netlist => CFG_SPW_NETLIST, | |
597 | hindex => maxahbmsp+i, pindex => 12+i, paddr => 12+i, pirq => 10+i, |
|
540 | hindex => maxahbmsp+i, pindex => 12+i, paddr => 12+i, pirq => 10+i, | |
598 | sysfreq => sysfreq, nsync => 1, rmap => 0, ports => 1, dmachan => 1, |
|
541 | sysfreq => sysfreq, nsync => 1, rmap => 0, ports => 1, dmachan => 1, | |
599 | fifosize1 => CFG_SPW_AHBFIFO, fifosize2 => CFG_SPW_RXFIFO, |
|
542 | fifosize1 => CFG_SPW_AHBFIFO, fifosize2 => CFG_SPW_RXFIFO, | |
600 | rxclkbuftype => 1, spwcore => CFG_SPW_GRSPW) |
|
543 | rxclkbuftype => 1, spwcore => CFG_SPW_GRSPW) | |
601 | PORT MAP(resetn, clkm, spw_rx_clk, spw_rx_clk, spw_lclk, spw_lclk, |
|
544 | PORT MAP(resetn, clkm, spw_rx_clk, spw_rx_clk, spw_lclk, spw_lclk, | |
602 | ahbmi, ahbmo(maxahbmsp+i), |
|
545 | ahbmi, ahbmo(maxahbmsp+i), | |
603 | apbi, apbo(12+i), spwi(i), spwo(i)); |
|
546 | apbi, apbo(12+i), spwi(i), spwo(i)); | |
604 | spwi(i).tickin <= '0'; spwi(i).rmapen <= '1'; |
|
547 | spwi(i).tickin <= '0'; spwi(i).rmapen <= '1'; | |
605 | spwi(i).clkdiv10 <= conv_std_logic_vector(sysfreq/10000-1, 8); |
|
548 | spwi(i).clkdiv10 <= conv_std_logic_vector(sysfreq/10000-1, 8); | |
606 | spw_rxd_pad : inpad_ds GENERIC MAP (padtech, lvds, x25v) |
|
549 | spw_rxd_pad : inpad_ds GENERIC MAP (padtech, lvds, x25v) | |
607 | PORT MAP (spw_rxd(i), spw_rxdn(i), spwi(i).d(0)); |
|
550 | PORT MAP (spw_rxd(i), spw_rxdn(i), spwi(i).d(0)); | |
608 | spw_rxs_pad : inpad_ds GENERIC MAP (padtech, lvds, x25v) |
|
551 | spw_rxs_pad : inpad_ds GENERIC MAP (padtech, lvds, x25v) | |
609 | PORT MAP (spw_rxs(i), spw_rxsn(i), spwi(i).s(0)); |
|
552 | PORT MAP (spw_rxs(i), spw_rxsn(i), spwi(i).s(0)); | |
610 | spw_txd_pad : outpad_ds GENERIC MAP (padtech, lvds, x25v) |
|
553 | spw_txd_pad : outpad_ds GENERIC MAP (padtech, lvds, x25v) | |
611 | PORT MAP (spw_txd(i), spw_txdn(i), spwo(i).d(0), gnd(0)); |
|
554 | PORT MAP (spw_txd(i), spw_txdn(i), spwo(i).d(0), gnd(0)); | |
612 | spw_txs_pad : outpad_ds GENERIC MAP (padtech, lvds, x25v) |
|
555 | spw_txs_pad : outpad_ds GENERIC MAP (padtech, lvds, x25v) | |
613 | PORT MAP (spw_txs(i), spw_txsn(i), spwo(i).s(0), gnd(0)); |
|
556 | PORT MAP (spw_txs(i), spw_txsn(i), spwo(i).s(0), gnd(0)); | |
614 | END GENERATE; |
|
557 | END GENERATE; | |
615 | END GENERATE; |
|
558 | END GENERATE; | |
616 |
|
559 | |||
|
560 | ||||
|
561 | ||||
|
562 | ------------------------------------------------------------------------------- | |||
|
563 | -- BOOT MEMORY AND REGISTER | |||
|
564 | ------------------------------------------------------------------------------- | |||
|
565 | ||||
|
566 | lpp_bootloader_1: lpp_bootloader | |||
|
567 | GENERIC MAP ( | |||
|
568 | pindex => 13, | |||
|
569 | paddr => 13, | |||
|
570 | pmask => 16#fff#, | |||
|
571 | ||||
|
572 | hindex => 6, | |||
|
573 | haddr => 16#900#, | |||
|
574 | hmask => 16#F00#) | |||
|
575 | PORT MAP ( | |||
|
576 | HCLK => clkm, | |||
|
577 | HRESETn => resetn, | |||
|
578 | apbi => apbi, | |||
|
579 | apbo => apbo(13), | |||
|
580 | ahbsi => ahbsi, | |||
|
581 | ahbso => ahbso(6)); | |||
|
582 | ||||
|
583 | ||||
617 | ------------------------------------------------------------------------------- |
|
584 | ------------------------------------------------------------------------------- | |
618 | -- AHB DMA |
|
585 | -- AHB DMA | |
619 | ------------------------------------------------------------------------------- |
|
586 | ------------------------------------------------------------------------------- | |
620 |
|
587 | |||
621 | lpp_dma_1: lpp_dma |
|
588 | lpp_dma_1 : lpp_dma | |
622 | GENERIC MAP ( |
|
589 | GENERIC MAP ( | |
623 | tech => fabtech, |
|
590 | tech => fabtech, | |
624 | hindex => 2, |
|
591 | hindex => 2, | |
625 | pindex => 14, |
|
592 | pindex => 14, | |
626 | paddr => 14, |
|
593 | paddr => 14, | |
627 | pmask => 16#fff#, |
|
594 | pmask => 16#fff#, | |
628 | pirq => 0) |
|
595 | pirq => 0) | |
629 | PORT MAP ( |
|
596 | PORT MAP ( | |
630 | HCLK => clkm, |
|
597 | HCLK => clkm, | |
631 | HRESETn => resetn, |
|
598 | HRESETn => resetn, | |
632 | apbi => apbi, |
|
599 | apbi => apbi, | |
633 | apbo => apbo(14), |
|
600 | apbo => apbo(14), | |
634 | AHB_Master_In => ahbmi, |
|
601 | AHB_Master_In => ahbmi, | |
635 | AHB_Master_Out => ahbmo(2), |
|
602 | AHB_Master_Out => ahbmo(2), | |
636 |
fifo_data => |
|
603 | fifo_data => fifo_data, --dma_data, | |
637 |
fifo_empty => |
|
604 | fifo_empty => fifo_empty, --dma_empty, | |
638 |
fifo_ren => |
|
605 | fifo_ren => fifo_ren, --dma_ren, | |
639 | header => header, |
|
606 | header => header, | |
640 | header_val => header_val, |
|
607 | header_val => header_val, | |
641 | header_ack => header_ack); |
|
608 | header_ack => header_ack); | |
642 |
|
609 | |||
643 | fifo_latency_correction_1: fifo_latency_correction |
|
610 | --fifo_latency_correction_1 : fifo_latency_correction | |
644 | PORT MAP ( |
|
611 | -- PORT MAP ( | |
645 | HCLK => clkm, |
|
612 | -- HCLK => clkm, | |
646 | HRESETn => resetn, |
|
613 | -- HRESETn => resetn, | |
647 |
|
|
614 | -- fifo_data => fifo_data, | |
648 | fifo_empty => fifo_empty, |
|
615 | -- fifo_empty => fifo_empty, | |
649 | fifo_ren => fifo_ren, |
|
616 | -- fifo_ren => fifo_ren, | |
650 | dma_data => dma_data, |
|
617 | -- dma_data => dma_data, | |
651 |
|
|
618 | -- dma_empty => dma_empty, | |
652 | dma_ren => dma_ren); |
|
619 | -- dma_ren => dma_ren); | |
653 |
|
620 | |||
654 | fifo_test_dma_1 : fifo_test_dma |
|
621 | fifo_test_dma_1 : fifo_test_dma | |
655 | GENERIC MAP ( |
|
622 | GENERIC MAP ( | |
656 | tech => fabtech, |
|
623 | tech => fabtech, | |
657 | pindex => 15, |
|
624 | pindex => 15, | |
658 | paddr => 15, |
|
625 | paddr => 15, | |
659 | pmask => 16#fff#) |
|
626 | pmask => 16#fff#) | |
660 | PORT MAP ( |
|
627 | PORT MAP ( | |
661 |
HCLK |
|
628 | HCLK => clkm, | |
662 |
HRESETn |
|
629 | HRESETn => resetn, | |
663 |
apbi |
|
630 | apbi => apbi, | |
664 |
apbo |
|
631 | apbo => apbo(15), | |
665 |
fifo_data |
|
632 | fifo_data => fifo_data, | |
666 |
fifo_empty |
|
633 | fifo_empty => fifo_empty, | |
667 |
fifo_ren |
|
634 | fifo_ren => fifo_ren, | |
668 |
header |
|
635 | header => header, | |
669 |
header_val |
|
636 | header_val => header_val, | |
670 |
header_ack |
|
637 | header_ack => header_ack); | |
671 |
|
638 | |||
672 | ----------------------------------------------------------------------- |
|
639 | ----------------------------------------------------------------------- | |
673 | --- Boot message ---------------------------------------------------- |
|
640 | --- Boot message ---------------------------------------------------- | |
674 | ----------------------------------------------------------------------- |
|
641 | ----------------------------------------------------------------------- | |
675 |
|
642 | |||
676 | -- pragma translate_off |
|
643 | -- pragma translate_off | |
677 | x : report_version |
|
644 | x : report_version | |
678 | GENERIC MAP ( |
|
645 | GENERIC MAP ( | |
679 | msg1 => "LEON3 MP Demonstration design", |
|
646 | msg1 => "LEON3 MP Demonstration design", | |
680 | msg2 => "GRLIB Version " & tost(LIBVHDL_VERSION/1000) & "." & tost((LIBVHDL_VERSION MOD 1000)/100) |
|
647 | msg2 => "GRLIB Version " & tost(LIBVHDL_VERSION/1000) & "." & tost((LIBVHDL_VERSION MOD 1000)/100) | |
681 | & "." & tost(LIBVHDL_VERSION MOD 100) & ", build " & tost(LIBVHDL_BUILD), |
|
648 | & "." & tost(LIBVHDL_VERSION MOD 100) & ", build " & tost(LIBVHDL_BUILD), | |
682 | msg3 => "Target technology: " & tech_table(fabtech) & ", memory library: " & tech_table(memtech), |
|
649 | msg3 => "Target technology: " & tech_table(fabtech) & ", memory library: " & tech_table(memtech), | |
683 | mdel => 1 |
|
650 | mdel => 1 | |
684 | ); |
|
651 | ); | |
685 | -- pragma translate_on |
|
652 | -- pragma translate_on | |
686 | END; |
|
653 | END; |
@@ -1,24 +1,34 | |||||
1 | vcom -quiet -93 -work lpp ../../lib/lpp/./lpp_dma/fifo_latency_correction.vhd |
|
1 | vcom -quiet -93 -work lpp ../../lib/lpp/./lpp_dma/fifo_latency_correction.vhd | |
2 | vcom -quiet -93 -work lpp ../../lib/lpp/./lpp_dma/fifo_test_dma.vhd |
|
2 | vcom -quiet -93 -work lpp ../../lib/lpp/./lpp_dma/fifo_test_dma.vhd | |
3 | vcom -quiet -93 -work lpp ../../lib/lpp/./lpp_dma/lpp_dma_pkg.vhd |
|
3 | vcom -quiet -93 -work lpp ../../lib/lpp/./lpp_dma/lpp_dma_pkg.vhd | |
4 | vcom -quiet -93 -work lpp ../../lib/lpp/./lpp_dma/lpp_dma_send_16word.vhd |
|
4 | vcom -quiet -93 -work lpp ../../lib/lpp/./lpp_dma/lpp_dma_send_16word.vhd | |
5 | vcom -quiet -93 -work lpp ../../lib/lpp/./lpp_dma/lpp_dma_send_1word.vhd |
|
5 | vcom -quiet -93 -work lpp ../../lib/lpp/./lpp_dma/lpp_dma_send_1word.vhd | |
6 | vcom -quiet -93 -work lpp ../../lib/lpp/./lpp_dma/lpp_dma_apbreg.vhd |
|
6 | vcom -quiet -93 -work lpp ../../lib/lpp/./lpp_dma/lpp_dma_apbreg.vhd | |
|
7 | vcom -quiet -93 -work lpp ../../lib/lpp/./lpp_dma/lpp_dma_ip.vhd | |||
7 | ##vcom -quiet -93 -work lpp ../../lib/lpp/./lpp_dma/lpp_dma_fsm.vhd |
|
8 | ##vcom -quiet -93 -work lpp ../../lib/lpp/./lpp_dma/lpp_dma_fsm.vhd | |
8 | vcom -quiet -93 -work lpp ../../lib/lpp/./lpp_dma/lpp_dma.vhd |
|
9 | vcom -quiet -93 -work lpp ../../lib/lpp/./lpp_dma/lpp_dma.vhd | |
9 |
|
10 | |||
10 | vcom -quiet -93 -work lpp ../../lib/lpp/./lpp_memory/SSRAM_plugin.vhd |
|
11 | vcom -quiet -93 -work lpp ../../lib/lpp/./lpp_memory/SSRAM_plugin.vhd | |
11 | vcom -quiet -93 -work lpp ../../lib/lpp/./lpp_memory/lpp_memory.vhd |
|
12 | vcom -quiet -93 -work lpp ../../lib/lpp/./lpp_memory/lpp_memory.vhd | |
12 |
|
13 | |||
13 | vcom -quiet -93 -work work CY7C1360C/package_utility.vhd |
|
14 | vcom -quiet -93 -work work CY7C1360C/package_utility.vhd | |
14 | vcom -quiet -93 -work work CY7C1360C/CY7C1360C.vhd |
|
15 | vcom -quiet -93 -work work CY7C1360C/CY7C1360C.vhd | |
15 |
|
16 | |||
|
17 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_bootloader/./bootrom.vhd | |||
|
18 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_bootloader/./lpp_bootloader_pkg.vhd | |||
|
19 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_bootloader/./lpp_bootloader.vhd | |||
|
20 | ||||
16 | vcom -quiet -93 -work work config.vhd |
|
21 | vcom -quiet -93 -work work config.vhd | |
17 | vcom -quiet -93 -work work ahbrom.vhd |
|
22 | vcom -quiet -93 -work work ahbrom.vhd | |
18 | vcom -quiet -93 -work work leon3mp.vhd |
|
23 | vcom -quiet -93 -work work leon3mp.vhd | |
19 | vcom -quiet -93 -work work testbench.vhd |
|
24 | vcom -quiet -93 -work work testbench.vhd | |
20 |
|
25 | |||
21 | vsim work.testbench |
|
26 | vsim work.testbench | |
|
27 | ||||
22 | log -r * |
|
28 | log -r * | |
23 |
do wave_d |
|
29 | do wave_bootloader.do | |
24 | ##run -all No newline at end of file |
|
30 | run 20 us | |
|
31 | force -freeze sim:/testbench/d3/lpp_bootloader_1/reg.addr_start_execution 00000000000000000000000000000000 0 | |||
|
32 | run 60 ns | |||
|
33 | force -freeze sim:/testbench/d3/lpp_bootloader_1/reg.config_start_execution 1 0 | |||
|
34 | run -all No newline at end of file |
@@ -1,387 +1,190 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
19 | -- Author : Jean-christophe Pellion |
|
19 | -- Author : Jean-christophe Pellion | |
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
21 | -- jean-christophe.pellion@easii-ic.com |
|
21 | -- jean-christophe.pellion@easii-ic.com | |
22 | ---------------------------------------------------------------------------- |
|
22 | ------------------------------------------------------------------------------- | |
|
23 | -- 1.0 - initial version | |||
|
24 | -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS) | |||
|
25 | ------------------------------------------------------------------------------- | |||
23 | LIBRARY ieee; |
|
26 | LIBRARY ieee; | |
24 | USE ieee.std_logic_1164.ALL; |
|
27 | USE ieee.std_logic_1164.ALL; | |
25 | USE ieee.numeric_std.ALL; |
|
28 | USE ieee.numeric_std.ALL; | |
26 | LIBRARY grlib; |
|
29 | LIBRARY grlib; | |
27 | USE grlib.amba.ALL; |
|
30 | USE grlib.amba.ALL; | |
28 | USE grlib.stdlib.ALL; |
|
31 | USE grlib.stdlib.ALL; | |
29 | USE grlib.devices.ALL; |
|
32 | USE grlib.devices.ALL; | |
30 | USE GRLIB.DMA2AHB_Package.ALL; |
|
33 | USE GRLIB.DMA2AHB_Package.ALL; | |
31 |
|
34 | --USE GRLIB.DMA2AHB_TestPackage.ALL; | ||
32 | LIBRARY lpp; |
|
35 | LIBRARY lpp; | |
33 | USE lpp.lpp_amba.ALL; |
|
36 | USE lpp.lpp_amba.ALL; | |
34 | USE lpp.apb_devices_list.ALL; |
|
37 | USE lpp.apb_devices_list.ALL; | |
35 | USE lpp.lpp_memory.ALL; |
|
38 | USE lpp.lpp_memory.ALL; | |
36 | USE lpp.lpp_dma_pkg.ALL; |
|
39 | USE lpp.lpp_dma_pkg.ALL; | |
37 | LIBRARY techmap; |
|
40 | LIBRARY techmap; | |
38 | USE techmap.gencomp.ALL; |
|
41 | USE techmap.gencomp.ALL; | |
39 |
|
42 | |||
40 |
|
43 | |||
41 | ENTITY lpp_dma IS |
|
44 | ENTITY lpp_dma IS | |
42 | GENERIC ( |
|
45 | GENERIC ( | |
43 | tech : INTEGER := inferred; |
|
46 | tech : INTEGER := inferred; | |
44 | hindex : INTEGER := 2; |
|
47 | hindex : INTEGER := 2; | |
45 | pindex : INTEGER := 4; |
|
48 | pindex : INTEGER := 4; | |
46 | paddr : INTEGER := 4; |
|
49 | paddr : INTEGER := 4; | |
47 | pmask : INTEGER := 16#fff#; |
|
50 | pmask : INTEGER := 16#fff#; | |
48 | pirq : INTEGER := 0); |
|
51 | pirq : INTEGER := 0); | |
49 | PORT ( |
|
52 | PORT ( | |
50 | -- AMBA AHB system signals |
|
53 | -- AMBA AHB system signals | |
51 | HCLK : IN STD_ULOGIC; |
|
54 | HCLK : IN STD_ULOGIC; | |
52 | HRESETn : IN STD_ULOGIC; |
|
55 | HRESETn : IN STD_ULOGIC; | |
53 |
|
56 | |||
54 | -- AMBA APB Slave Interface |
|
57 | -- AMBA APB Slave Interface | |
55 | apbi : IN apb_slv_in_type; |
|
58 | apbi : IN apb_slv_in_type; | |
56 | apbo : OUT apb_slv_out_type; |
|
59 | apbo : OUT apb_slv_out_type; | |
57 |
|
60 | |||
58 | -- AMBA AHB Master Interface |
|
61 | -- AMBA AHB Master Interface | |
59 | AHB_Master_In : IN AHB_Mst_In_Type; |
|
62 | AHB_Master_In : IN AHB_Mst_In_Type; | |
60 | AHB_Master_Out : OUT AHB_Mst_Out_Type; |
|
63 | AHB_Master_Out : OUT AHB_Mst_Out_Type; | |
61 |
|
64 | |||
62 | -- fifo interface |
|
65 | -- fifo interface | |
63 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
66 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
64 | fifo_empty : IN STD_LOGIC; |
|
67 | fifo_empty : IN STD_LOGIC; | |
65 | fifo_ren : OUT STD_LOGIC; |
|
68 | fifo_ren : OUT STD_LOGIC; | |
66 |
|
69 | |||
67 | -- header |
|
70 | -- header | |
68 | header : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
71 | header : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
69 | header_val : IN STD_LOGIC; |
|
72 | header_val : IN STD_LOGIC; | |
70 | header_ack : OUT STD_LOGIC |
|
73 | header_ack : OUT STD_LOGIC | |
71 | ); |
|
74 | ); | |
72 | END; |
|
75 | END; | |
73 |
|
76 | |||
74 | ARCHITECTURE Behavioral OF lpp_dma IS |
|
77 | ARCHITECTURE Behavioral OF lpp_dma IS | |
75 | ----------------------------------------------------------------------------- |
|
|||
76 | SIGNAL DMAIn : DMA_In_Type; |
|
|||
77 | SIGNAL header_dmai : DMA_In_Type; |
|
|||
78 | SIGNAL component_dmai : DMA_In_Type; |
|
|||
79 | SIGNAL DMAOut : DMA_OUt_Type; |
|
|||
80 |
|
78 | |||
81 | SIGNAL ready_matrix_f0_0 : STD_LOGIC; |
|
79 | SIGNAL ready_matrix_f0_0 : STD_LOGIC; | |
82 | SIGNAL ready_matrix_f0_1 : STD_LOGIC; |
|
80 | SIGNAL ready_matrix_f0_1 : STD_LOGIC; | |
83 | SIGNAL ready_matrix_f1 : STD_LOGIC; |
|
81 | SIGNAL ready_matrix_f1 : STD_LOGIC; | |
84 | SIGNAL ready_matrix_f2 : STD_LOGIC; |
|
82 | SIGNAL ready_matrix_f2 : STD_LOGIC; | |
85 | SIGNAL error_anticipating_empty_fifo : STD_LOGIC; |
|
83 | SIGNAL error_anticipating_empty_fifo : STD_LOGIC; | |
86 | SIGNAL error_bad_component_error : STD_LOGIC; |
|
84 | SIGNAL error_bad_component_error : STD_LOGIC; | |
87 |
|
85 | |||
|
86 | SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
87 | ||||
88 |
|
|
88 | SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC; | |
89 | SIGNAL config_active_interruption_onError : STD_LOGIC; |
|
89 | SIGNAL config_active_interruption_onError : STD_LOGIC; | |
90 | SIGNAL status_ready_matrix_f0_0 : STD_LOGIC; |
|
90 | SIGNAL status_ready_matrix_f0_0 : STD_LOGIC; | |
91 | SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; |
|
91 | SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; | |
92 | SIGNAL status_ready_matrix_f1 : STD_LOGIC; |
|
92 | SIGNAL status_ready_matrix_f1 : STD_LOGIC; | |
93 | SIGNAL status_ready_matrix_f2 : STD_LOGIC; |
|
93 | SIGNAL status_ready_matrix_f2 : STD_LOGIC; | |
94 | SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC; |
|
94 | SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC; | |
95 | SIGNAL status_error_bad_component_error : STD_LOGIC; |
|
95 | SIGNAL status_error_bad_component_error : STD_LOGIC; | |
96 | SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
96 | SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
97 | SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
97 | SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
98 | SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
98 | SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
99 | SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
99 | SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
100 | ----------------------------------------------------------------------------- |
|
|||
101 |
|
||||
102 | ----------------------------------------------------------------------------- |
|
|||
103 | ----------------------------------------------------------------------------- |
|
|||
104 | TYPE state_DMAWriteBurst IS (IDLE, |
|
|||
105 | TRASH_FIFO, |
|
|||
106 | WAIT_HEADER_ACK, |
|
|||
107 | SEND_DATA, |
|
|||
108 | WAIT_DATA_ACK, |
|
|||
109 | CHECK_LENGTH |
|
|||
110 | ); |
|
|||
111 | SIGNAL state : state_DMAWriteBurst := IDLE; |
|
|||
112 |
|
||||
113 | SIGNAL nbSend : INTEGER; |
|
|||
114 | SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
|||
115 | SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
|||
116 | SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
|||
117 | SIGNAL header_check_ok : STD_LOGIC; |
|
|||
118 | SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
119 | SIGNAL send_matrix : STD_LOGIC; |
|
|||
120 | SIGNAL request : STD_LOGIC; |
|
|||
121 | SIGNAL remaining_data_request : INTEGER; |
|
|||
122 | SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
123 | ----------------------------------------------------------------------------- |
|
|||
124 | ----------------------------------------------------------------------------- |
|
|||
125 | SIGNAL header_select : STD_LOGIC; |
|
|||
126 |
|
||||
127 | SIGNAL header_send : STD_LOGIC; |
|
|||
128 | SIGNAL header_data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
129 | SIGNAL header_send_ok : STD_LOGIC; |
|
|||
130 | SIGNAL header_send_ko : STD_LOGIC; |
|
|||
131 |
|
||||
132 | SIGNAL component_send : STD_LOGIC; |
|
|||
133 | SIGNAL component_send_ok : STD_LOGIC; |
|
|||
134 | SIGNAL component_send_ko : STD_LOGIC; |
|
|||
135 | ----------------------------------------------------------------------------- |
|
|||
136 | SIGNAL fifo_ren_trash : STD_LOGIC; |
|
|||
137 | SIGNAL component_fifo_ren : STD_LOGIC; |
|
|||
138 |
|
||||
139 | SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
140 |
|
100 | |||
141 | BEGIN |
|
101 | BEGIN | |
142 |
|
102 | |||
143 | ----------------------------------------------------------------------------- |
|
103 | ----------------------------------------------------------------------------- | |
144 | -- DMA to AHB interface |
|
104 | -- LPP DMA IP | |
145 | ----------------------------------------------------------------------------- |
|
105 | ----------------------------------------------------------------------------- | |
146 |
|
||||
147 | DMA2AHB_1 : DMA2AHB |
|
|||
148 | GENERIC MAP ( |
|
|||
149 | hindex => hindex, |
|
|||
150 | vendorid => VENDOR_LPP, |
|
|||
151 | deviceid => 0, |
|
|||
152 | version => 0, |
|
|||
153 | syncrst => 1, |
|
|||
154 | boundary => 1) -- set TO TEST |
|
|||
155 | PORT MAP ( |
|
|||
156 | HCLK => HCLK, |
|
|||
157 | HRESETn => HRESETn, |
|
|||
158 | DMAIn => DMAIn, |
|
|||
159 | DMAOut => DMAOut, |
|
|||
160 | AHBIn => AHB_Master_In, |
|
|||
161 | AHBOut => AHB_Master_Out); |
|
|||
162 |
|
||||
163 |
|
||||
164 | debug_info: PROCESS (HCLK, HRESETn) |
|
|||
165 | BEGIN -- PROCESS debug_info |
|
|||
166 | IF HRESETn = '0' THEN -- asynchronous reset (active low) |
|
|||
167 | debug_reg <= (OTHERS => '0'); |
|
|||
168 | ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge |
|
|||
169 | debug_reg(0) <= debug_reg(0) OR (DMAOut.Retry ); |
|
|||
170 | debug_reg(1) <= debug_reg(1) OR (DMAOut.Grant AND DMAOut.Retry) ; |
|
|||
171 | IF state = TRASH_FIFO THEN debug_reg(2) <= '1'; END IF; |
|
|||
172 | debug_reg(3) <= debug_reg(3) OR (header_send_ko); |
|
|||
173 | debug_reg(4) <= debug_reg(4) OR (header_send_ok); |
|
|||
174 | debug_reg(5) <= debug_reg(5) OR (component_send_ko); |
|
|||
175 | debug_reg(6) <= debug_reg(6) OR (component_send_ok); |
|
|||
176 |
|
||||
177 | debug_reg(31 DOWNTO 7) <= (OTHERS => '1'); |
|
|||
178 | END IF; |
|
|||
179 | END PROCESS debug_info; |
|
|||
180 |
|
||||
181 |
|
||||
182 | matrix_type <= header(1 DOWNTO 0); |
|
|||
183 | component_type <= header(5 DOWNTO 2); |
|
|||
184 |
|
||||
185 | send_matrix <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0_0 = '0' ELSE |
|
|||
186 | '1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE |
|
|||
187 | '1' WHEN matrix_type = "10" AND status_ready_matrix_f1 = '0' ELSE |
|
|||
188 | '1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0' ELSE |
|
|||
189 | '0'; |
|
|||
190 |
|
||||
191 | header_check_ok <= '0' WHEN component_type = "1111" ELSE |
|
|||
192 | '1' WHEN component_type = "0000" AND component_type_pre = "1110" ELSE |
|
|||
193 | '1' WHEN component_type = component_type_pre + "0001" ELSE |
|
|||
194 | '0'; |
|
|||
195 |
|
||||
196 | address_matrix <= addr_matrix_f0_0 WHEN matrix_type = "00" ELSE |
|
|||
197 | addr_matrix_f0_1 WHEN matrix_type = "01" ELSE |
|
|||
198 | addr_matrix_f1 WHEN matrix_type = "10" ELSE |
|
|||
199 | addr_matrix_f2 WHEN matrix_type = "11" ELSE |
|
|||
200 | (OTHERS => '0'); |
|
|||
201 |
|
||||
202 | ----------------------------------------------------------------------------- |
|
|||
203 | -- DMA control |
|
|||
204 | ----------------------------------------------------------------------------- |
|
|||
205 | DMAWriteFSM_p : PROCESS (HCLK, HRESETn) |
|
|||
206 | BEGIN -- PROCESS DMAWriteBurst_p |
|
|||
207 | IF HRESETn = '0' THEN -- asynchronous reset (active low) |
|
|||
208 | state <= IDLE; |
|
|||
209 | header_ack <= '0'; |
|
|||
210 | ready_matrix_f0_0 <= '0'; |
|
|||
211 | ready_matrix_f0_1 <= '0'; |
|
|||
212 | ready_matrix_f1 <= '0'; |
|
|||
213 | ready_matrix_f2 <= '0'; |
|
|||
214 | error_anticipating_empty_fifo <= '0'; |
|
|||
215 | error_bad_component_error <= '0'; |
|
|||
216 | component_type_pre <= "1110"; |
|
|||
217 | fifo_ren_trash <= '1'; |
|
|||
218 | component_send <= '0'; |
|
|||
219 | address <= (OTHERS => '0'); |
|
|||
220 | header_select <= '0'; |
|
|||
221 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge |
|
|||
222 |
|
106 | |||
223 | CASE state IS |
|
107 | lpp_dma_ip_1: ENTITY work.lpp_dma_ip | |
224 | WHEN IDLE => |
|
108 | GENERIC MAP ( | |
225 | ready_matrix_f0_0 <= '0'; |
|
109 | tech => tech, | |
226 | ready_matrix_f0_1 <= '0'; |
|
110 | hindex => hindex, | |
227 | ready_matrix_f1 <= '0'; |
|
111 | pindex => pindex, | |
228 | ready_matrix_f2 <= '0'; |
|
112 | paddr => paddr, | |
229 | error_bad_component_error <= '0'; |
|
113 | pmask => pmask, | |
230 | header_select <= '1'; |
|
114 | pirq => pirq) | |
231 | IF header_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN |
|
115 | PORT MAP ( | |
232 | IF header_check_ok = '1' THEN |
|
116 | HCLK => HCLK, | |
233 | header_data <= header; |
|
117 | HRESETn => HRESETn, | |
234 | component_type_pre <= header(5 DOWNTO 2); |
|
118 | AHB_Master_In => AHB_Master_In, | |
235 | header_ack <= '1'; |
|
119 | AHB_Master_Out => AHB_Master_Out, | |
236 | -- |
|
120 | fifo_data => fifo_data, | |
237 | header_send <= '1'; |
|
121 | fifo_empty => fifo_empty, | |
238 | IF component_type = "0000" THEN |
|
122 | fifo_ren => fifo_ren, | |
239 | address <= address_matrix; |
|
123 | header => header, | |
240 | END IF; |
|
124 | header_val => header_val, | |
241 | header_data <= header; |
|
125 | header_ack => header_ack, | |
242 | -- |
|
126 | ------------------------------------------------------------------------- | |
243 | state <= WAIT_HEADER_ACK; |
|
127 | -- REG | |
244 | ELSE |
|
128 | ready_matrix_f0_0 => ready_matrix_f0_0, | |
245 | error_bad_component_error <= '1'; |
|
129 | ready_matrix_f0_1 => ready_matrix_f0_1, | |
246 | component_type_pre <= "1110"; |
|
130 | ready_matrix_f1 => ready_matrix_f1, | |
247 |
|
|
131 | ready_matrix_f2 => ready_matrix_f2, | |
248 | state <= TRASH_FIFO; |
|
132 | error_anticipating_empty_fifo => error_anticipating_empty_fifo, | |
249 | END IF; |
|
133 | error_bad_component_error => error_bad_component_error, | |
250 | END IF; |
|
|||
251 |
|
||||
252 | WHEN TRASH_FIFO => |
|
|||
253 | error_bad_component_error <= '0'; |
|
|||
254 | error_anticipating_empty_fifo <= '0'; |
|
|||
255 | IF fifo_empty = '1' THEN |
|
|||
256 | state <= IDLE; |
|
|||
257 | fifo_ren_trash <= '1'; |
|
|||
258 | ELSE |
|
|||
259 | fifo_ren_trash <= '0'; |
|
|||
260 | END IF; |
|
|||
261 |
|
||||
262 | WHEN WAIT_HEADER_ACK => |
|
|||
263 | header_send <= '0'; |
|
|||
264 | IF header_send_ko = '1' THEN |
|
|||
265 | state <= TRASH_FIFO; |
|
|||
266 | error_anticipating_empty_fifo <= '1'; |
|
|||
267 | -- TODO : error sending header |
|
|||
268 | ELSIF header_send_ok = '1' THEN |
|
|||
269 | header_select <= '0'; |
|
|||
270 | state <= SEND_DATA; |
|
|||
271 | address <= address + 4; |
|
|||
272 | END IF; |
|
|||
273 |
|
134 | |||
274 | WHEN SEND_DATA => |
|
135 | debug_reg => debug_reg, | |
275 | IF fifo_empty = '1' THEN |
|
|||
276 | state <= IDLE; |
|
|||
277 | IF component_type = "1110" THEN |
|
|||
278 | CASE matrix_type IS |
|
|||
279 | WHEN "00" => ready_matrix_f0_0 <= '1'; |
|
|||
280 | WHEN "01" => ready_matrix_f0_1 <= '1'; |
|
|||
281 | WHEN "10" => ready_matrix_f1 <= '1'; |
|
|||
282 | WHEN "11" => ready_matrix_f2 <= '1'; |
|
|||
283 | WHEN OTHERS => NULL; |
|
|||
284 | END CASE; |
|
|||
285 | END IF; |
|
|||
286 | ELSE |
|
|||
287 | component_send <= '1'; |
|
|||
288 | address <= address; |
|
|||
289 | state <= WAIT_DATA_ACK; |
|
|||
290 | END IF; |
|
|||
291 |
|
||||
292 | WHEN WAIT_DATA_ACK => |
|
|||
293 | component_send <= '0'; |
|
|||
294 | IF component_send_ok = '1' THEN |
|
|||
295 | address <= address + 64; |
|
|||
296 | state <= SEND_DATA; |
|
|||
297 | ELSIF component_send_ko = '1' THEN |
|
|||
298 | error_anticipating_empty_fifo <= '0'; |
|
|||
299 | state <= TRASH_FIFO; |
|
|||
300 | END IF; |
|
|||
301 |
|
||||
302 | WHEN CHECK_LENGTH => |
|
|||
303 | state <= IDLE; |
|
|||
304 | WHEN OTHERS => NULL; |
|
|||
305 | END CASE; |
|
|||
306 |
|
||||
307 | END IF; |
|
|||
308 | END PROCESS DMAWriteFSM_p; |
|
|||
309 |
|
136 | |||
310 | ----------------------------------------------------------------------------- |
|
137 | status_ready_matrix_f0_0 => status_ready_matrix_f0_0, | |
311 | -- SEND 1 word by DMA |
|
138 | status_ready_matrix_f0_1 => status_ready_matrix_f0_1, | |
312 | ----------------------------------------------------------------------------- |
|
139 | status_ready_matrix_f1 => status_ready_matrix_f1, | |
313 | lpp_dma_send_1word_1 : lpp_dma_send_1word |
|
140 | status_ready_matrix_f2 => status_ready_matrix_f2, | |
314 | PORT MAP ( |
|
141 | status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, | |
315 | HCLK => HCLK, |
|
142 | status_error_bad_component_error => status_error_bad_component_error, | |
316 | HRESETn => HRESETn, |
|
143 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, | |
317 | DMAIn => header_dmai, |
|
144 | config_active_interruption_onError => config_active_interruption_onError, | |
318 | DMAOut => DMAOut, |
|
145 | addr_matrix_f0_0 => addr_matrix_f0_0, | |
319 |
|
146 | addr_matrix_f0_1 => addr_matrix_f0_1, | ||
320 | send => header_send, |
|
147 | addr_matrix_f1 => addr_matrix_f1, | |
321 | address => address, |
|
148 | addr_matrix_f2 => addr_matrix_f2); | |
322 | data => header_data, |
|
149 | ||
323 | send_ok => header_send_ok, |
|
|||
324 | send_ko => header_send_ko |
|
|||
325 | ); |
|
|||
326 |
|
||||
327 | ----------------------------------------------------------------------------- |
|
|||
328 | -- SEND 16 word by DMA (in burst mode) |
|
|||
329 | ----------------------------------------------------------------------------- |
|
|||
330 | lpp_dma_send_16word_1 : lpp_dma_send_16word |
|
|||
331 | PORT MAP ( |
|
|||
332 | HCLK => HCLK, |
|
|||
333 | HRESETn => HRESETn, |
|
|||
334 | DMAIn => component_dmai, |
|
|||
335 | DMAOut => DMAOut, |
|
|||
336 | send => component_send, |
|
|||
337 | address => address, |
|
|||
338 | data => fifo_data, |
|
|||
339 | ren => component_fifo_ren, |
|
|||
340 | send_ok => component_send_ok, |
|
|||
341 | send_ko => component_send_ko); |
|
|||
342 |
|
||||
343 | DMAIn <= header_dmai WHEN header_select = '1' ELSE component_dmai; |
|
|||
344 | fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE component_fifo_ren; |
|
|||
345 |
|
||||
346 |
|
||||
347 |
|
|
150 | ----------------------------------------------------------------------------- | |
348 | -- APB REGISTER |
|
151 | -- APB REGISTER | |
349 | ----------------------------------------------------------------------------- |
|
152 | ----------------------------------------------------------------------------- | |
350 |
|
153 | |||
351 |
lpp_dma_apbreg_ |
|
154 | lpp_dma_apbreg_1 : lpp_dma_apbreg | |
352 | GENERIC MAP ( |
|
155 | GENERIC MAP ( | |
353 | pindex => pindex, |
|
156 | pindex => pindex, | |
354 | paddr => paddr, |
|
157 | paddr => paddr, | |
355 | pmask => pmask, |
|
158 | pmask => pmask, | |
356 | pirq => pirq) |
|
159 | pirq => pirq) | |
357 | PORT MAP ( |
|
160 | PORT MAP ( | |
358 | HCLK => HCLK, |
|
161 | HCLK => HCLK, | |
359 | HRESETn => HRESETn, |
|
162 | HRESETn => HRESETn, | |
360 | apbi => apbi, |
|
163 | apbi => apbi, | |
361 | apbo => apbo, |
|
164 | apbo => apbo, | |
362 | -- IN |
|
165 | -- IN | |
363 | ready_matrix_f0_0 => ready_matrix_f0_0, |
|
166 | ready_matrix_f0_0 => ready_matrix_f0_0, | |
364 | ready_matrix_f0_1 => ready_matrix_f0_1, |
|
167 | ready_matrix_f0_1 => ready_matrix_f0_1, | |
365 | ready_matrix_f1 => ready_matrix_f1, |
|
168 | ready_matrix_f1 => ready_matrix_f1, | |
366 | ready_matrix_f2 => ready_matrix_f2, |
|
169 | ready_matrix_f2 => ready_matrix_f2, | |
367 | error_anticipating_empty_fifo => error_anticipating_empty_fifo, |
|
170 | error_anticipating_empty_fifo => error_anticipating_empty_fifo, | |
368 | error_bad_component_error => error_bad_component_error, |
|
171 | error_bad_component_error => error_bad_component_error, | |
369 | -- |
|
172 | -- | |
370 | debug_reg => debug_reg, |
|
173 | debug_reg => debug_reg, | |
371 | -- OUT |
|
174 | -- OUT | |
372 | status_ready_matrix_f0_0 => status_ready_matrix_f0_0, |
|
175 | status_ready_matrix_f0_0 => status_ready_matrix_f0_0, | |
373 | status_ready_matrix_f0_1 => status_ready_matrix_f0_1, |
|
176 | status_ready_matrix_f0_1 => status_ready_matrix_f0_1, | |
374 | status_ready_matrix_f1 => status_ready_matrix_f1, |
|
177 | status_ready_matrix_f1 => status_ready_matrix_f1, | |
375 | status_ready_matrix_f2 => status_ready_matrix_f2, |
|
178 | status_ready_matrix_f2 => status_ready_matrix_f2, | |
376 | status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, |
|
179 | status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, | |
377 | status_error_bad_component_error => status_error_bad_component_error, |
|
180 | status_error_bad_component_error => status_error_bad_component_error, | |
378 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, -- TODO |
|
181 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, -- TODO | |
379 | config_active_interruption_onError => config_active_interruption_onError, -- TODO |
|
182 | config_active_interruption_onError => config_active_interruption_onError, -- TODO | |
380 | addr_matrix_f0_0 => addr_matrix_f0_0, |
|
183 | addr_matrix_f0_0 => addr_matrix_f0_0, | |
381 | addr_matrix_f0_1 => addr_matrix_f0_1, |
|
184 | addr_matrix_f0_1 => addr_matrix_f0_1, | |
382 | addr_matrix_f1 => addr_matrix_f1, |
|
185 | addr_matrix_f1 => addr_matrix_f1, | |
383 | addr_matrix_f2 => addr_matrix_f2); |
|
186 | addr_matrix_f2 => addr_matrix_f2); | |
384 |
|
187 | |||
385 | ----------------------------------------------------------------------------- |
|
188 | ----------------------------------------------------------------------------- | |
386 |
|
189 | |||
387 | END Behavioral; |
|
190 | END Behavioral; |
@@ -1,164 +1,204 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
19 | -- Author : Jean-christophe Pellion |
|
19 | -- Author : Jean-christophe Pellion | |
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
21 | -- jean-christophe.pellion@easii-ic.com |
|
21 | -- jean-christophe.pellion@easii-ic.com | |
22 | ---------------------------------------------------------------------------- |
|
22 | ---------------------------------------------------------------------------- | |
23 | LIBRARY ieee; |
|
23 | LIBRARY ieee; | |
24 | USE ieee.std_logic_1164.ALL; |
|
24 | USE ieee.std_logic_1164.ALL; | |
25 | LIBRARY grlib; |
|
25 | LIBRARY grlib; | |
26 | USE grlib.amba.ALL; |
|
26 | USE grlib.amba.ALL; | |
27 | USE std.textio.ALL; |
|
27 | USE std.textio.ALL; | |
28 | LIBRARY grlib; |
|
28 | LIBRARY grlib; | |
29 | USE grlib.amba.ALL; |
|
29 | USE grlib.amba.ALL; | |
30 | USE grlib.stdlib.ALL; |
|
30 | USE grlib.stdlib.ALL; | |
31 | USE GRLIB.DMA2AHB_Package.ALL; |
|
31 | USE GRLIB.DMA2AHB_Package.ALL; | |
32 | LIBRARY techmap; |
|
32 | LIBRARY techmap; | |
33 | USE techmap.gencomp.ALL; |
|
33 | USE techmap.gencomp.ALL; | |
34 | LIBRARY lpp; |
|
34 | LIBRARY lpp; | |
35 | USE lpp.lpp_amba.ALL; |
|
35 | USE lpp.lpp_amba.ALL; | |
36 | USE lpp.apb_devices_list.ALL; |
|
36 | USE lpp.apb_devices_list.ALL; | |
37 | USE lpp.lpp_memory.ALL; |
|
37 | USE lpp.lpp_memory.ALL; | |
38 |
|
38 | |||
39 | PACKAGE lpp_dma_pkg IS |
|
39 | PACKAGE lpp_dma_pkg IS | |
40 |
|
40 | |||
41 | COMPONENT lpp_dma |
|
41 | COMPONENT lpp_dma | |
42 | GENERIC ( |
|
42 | GENERIC ( | |
43 | tech : INTEGER; |
|
43 | tech : INTEGER; | |
44 | hindex : INTEGER; |
|
44 | hindex : INTEGER; | |
45 | pindex : INTEGER; |
|
45 | pindex : INTEGER; | |
46 | paddr : INTEGER; |
|
46 | paddr : INTEGER; | |
47 | pmask : INTEGER; |
|
47 | pmask : INTEGER; | |
48 | pirq : INTEGER); |
|
48 | pirq : INTEGER); | |
49 | PORT ( |
|
49 | PORT ( | |
50 | HCLK : IN STD_ULOGIC; |
|
50 | HCLK : IN STD_ULOGIC; | |
51 | HRESETn : IN STD_ULOGIC; |
|
51 | HRESETn : IN STD_ULOGIC; | |
52 | apbi : IN apb_slv_in_type; |
|
52 | apbi : IN apb_slv_in_type; | |
53 | apbo : OUT apb_slv_out_type; |
|
53 | apbo : OUT apb_slv_out_type; | |
54 | AHB_Master_In : IN AHB_Mst_In_Type; |
|
54 | AHB_Master_In : IN AHB_Mst_In_Type; | |
55 | AHB_Master_Out : OUT AHB_Mst_Out_Type; |
|
55 | AHB_Master_Out : OUT AHB_Mst_Out_Type; | |
56 | -- fifo interface |
|
56 | -- fifo interface | |
57 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
57 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
58 | fifo_empty : IN STD_LOGIC; |
|
58 | fifo_empty : IN STD_LOGIC; | |
59 | fifo_ren : OUT STD_LOGIC; |
|
59 | fifo_ren : OUT STD_LOGIC; | |
60 | -- header |
|
60 | -- header | |
61 | header : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
61 | header : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
62 | header_val : IN STD_LOGIC; |
|
62 | header_val : IN STD_LOGIC; | |
63 | header_ack : OUT STD_LOGIC); |
|
63 | header_ack : OUT STD_LOGIC); | |
64 | END COMPONENT; |
|
64 | END COMPONENT; | |
65 |
|
65 | |||
66 | COMPONENT fifo_test_dma |
|
66 | COMPONENT fifo_test_dma | |
67 | GENERIC ( |
|
67 | GENERIC ( | |
68 | tech : INTEGER; |
|
68 | tech : INTEGER; | |
69 | pindex : INTEGER; |
|
69 | pindex : INTEGER; | |
70 | paddr : INTEGER; |
|
70 | paddr : INTEGER; | |
71 | pmask : INTEGER); |
|
71 | pmask : INTEGER); | |
72 | PORT ( |
|
72 | PORT ( | |
73 | HCLK : IN STD_ULOGIC; |
|
73 | HCLK : IN STD_ULOGIC; | |
74 | HRESETn : IN STD_ULOGIC; |
|
74 | HRESETn : IN STD_ULOGIC; | |
75 | apbi : IN apb_slv_in_type; |
|
75 | apbi : IN apb_slv_in_type; | |
76 | apbo : OUT apb_slv_out_type; |
|
76 | apbo : OUT apb_slv_out_type; | |
77 | -- fifo interface |
|
77 | -- fifo interface | |
78 | fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
78 | fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
79 | fifo_empty : OUT STD_LOGIC; |
|
79 | fifo_empty : OUT STD_LOGIC; | |
80 | fifo_ren : IN STD_LOGIC; |
|
80 | fifo_ren : IN STD_LOGIC; | |
81 | -- header |
|
81 | -- header | |
82 | header : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
82 | header : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
83 | header_val : OUT STD_LOGIC; |
|
83 | header_val : OUT STD_LOGIC; | |
84 | header_ack : IN STD_LOGIC |
|
84 | header_ack : IN STD_LOGIC | |
85 | ); |
|
85 | ); | |
86 | END COMPONENT; |
|
86 | END COMPONENT; | |
87 |
|
87 | |||
88 | COMPONENT lpp_dma_apbreg |
|
88 | COMPONENT lpp_dma_apbreg | |
89 | GENERIC ( |
|
89 | GENERIC ( | |
90 | pindex : INTEGER; |
|
90 | pindex : INTEGER; | |
91 | paddr : INTEGER; |
|
91 | paddr : INTEGER; | |
92 | pmask : INTEGER; |
|
92 | pmask : INTEGER; | |
93 | pirq : INTEGER); |
|
93 | pirq : INTEGER); | |
94 | PORT ( |
|
94 | PORT ( | |
95 | HCLK : IN STD_ULOGIC; |
|
95 | HCLK : IN STD_ULOGIC; | |
96 | HRESETn : IN STD_ULOGIC; |
|
96 | HRESETn : IN STD_ULOGIC; | |
97 | apbi : IN apb_slv_in_type; |
|
97 | apbi : IN apb_slv_in_type; | |
98 | apbo : OUT apb_slv_out_type; |
|
98 | apbo : OUT apb_slv_out_type; | |
99 | -- IN |
|
99 | -- IN | |
100 | ready_matrix_f0_0 : IN STD_LOGIC; |
|
100 | ready_matrix_f0_0 : IN STD_LOGIC; | |
101 | ready_matrix_f0_1 : IN STD_LOGIC; |
|
101 | ready_matrix_f0_1 : IN STD_LOGIC; | |
102 | ready_matrix_f1 : IN STD_LOGIC; |
|
102 | ready_matrix_f1 : IN STD_LOGIC; | |
103 | ready_matrix_f2 : IN STD_LOGIC; |
|
103 | ready_matrix_f2 : IN STD_LOGIC; | |
104 | error_anticipating_empty_fifo : IN STD_LOGIC; |
|
104 | error_anticipating_empty_fifo : IN STD_LOGIC; | |
105 | error_bad_component_error : IN STD_LOGIC; |
|
105 | error_bad_component_error : IN STD_LOGIC; | |
106 | debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
106 | debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
107 |
|
107 | |||
108 | -- OUT |
|
108 | -- OUT | |
109 | status_ready_matrix_f0_0 : OUT STD_LOGIC; |
|
109 | status_ready_matrix_f0_0 : OUT STD_LOGIC; | |
110 | status_ready_matrix_f0_1 : OUT STD_LOGIC; |
|
110 | status_ready_matrix_f0_1 : OUT STD_LOGIC; | |
111 | status_ready_matrix_f1 : OUT STD_LOGIC; |
|
111 | status_ready_matrix_f1 : OUT STD_LOGIC; | |
112 | status_ready_matrix_f2 : OUT STD_LOGIC; |
|
112 | status_ready_matrix_f2 : OUT STD_LOGIC; | |
113 | status_error_anticipating_empty_fifo : OUT STD_LOGIC; |
|
113 | status_error_anticipating_empty_fifo : OUT STD_LOGIC; | |
114 | status_error_bad_component_error : OUT STD_LOGIC; |
|
114 | status_error_bad_component_error : OUT STD_LOGIC; | |
115 |
|
115 | |||
116 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; |
|
116 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; | |
117 | config_active_interruption_onError : OUT STD_LOGIC; |
|
117 | config_active_interruption_onError : OUT STD_LOGIC; | |
118 | addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
118 | addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
119 | addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
119 | addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
120 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
120 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
121 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
121 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |
122 | ); |
|
122 | ); | |
123 | END COMPONENT; |
|
123 | END COMPONENT; | |
124 |
|
124 | |||
125 | COMPONENT lpp_dma_send_1word |
|
125 | COMPONENT lpp_dma_send_1word | |
126 | PORT ( |
|
126 | PORT ( | |
127 | HCLK : IN STD_ULOGIC; |
|
127 | HCLK : IN STD_ULOGIC; | |
128 | HRESETn : IN STD_ULOGIC; |
|
128 | HRESETn : IN STD_ULOGIC; | |
129 | DMAIn : OUT DMA_In_Type; |
|
129 | DMAIn : OUT DMA_In_Type; | |
130 | DMAOut : IN DMA_OUt_Type; |
|
130 | DMAOut : IN DMA_OUt_Type; | |
131 | send : IN STD_LOGIC; |
|
131 | send : IN STD_LOGIC; | |
132 | address : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
132 | address : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
133 | data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
133 | data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
134 | send_ok : OUT STD_LOGIC; |
|
134 | send_ok : OUT STD_LOGIC; | |
135 | send_ko : OUT STD_LOGIC); |
|
135 | send_ko : OUT STD_LOGIC); | |
136 | END COMPONENT; |
|
136 | END COMPONENT; | |
137 |
|
137 | |||
138 | COMPONENT lpp_dma_send_16word |
|
138 | COMPONENT lpp_dma_send_16word | |
139 | PORT ( |
|
139 | PORT ( | |
140 | HCLK : IN STD_ULOGIC; |
|
140 | HCLK : IN STD_ULOGIC; | |
141 | HRESETn : IN STD_ULOGIC; |
|
141 | HRESETn : IN STD_ULOGIC; | |
142 | DMAIn : OUT DMA_In_Type; |
|
142 | DMAIn : OUT DMA_In_Type; | |
143 | DMAOut : IN DMA_OUt_Type; |
|
143 | DMAOut : IN DMA_OUt_Type; | |
144 | send : IN STD_LOGIC; |
|
144 | send : IN STD_LOGIC; | |
145 | address : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
145 | address : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
146 | data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
146 | data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
147 | ren : OUT STD_LOGIC; |
|
147 | ren : OUT STD_LOGIC; | |
148 | send_ok : OUT STD_LOGIC; |
|
148 | send_ok : OUT STD_LOGIC; | |
149 | send_ko : OUT STD_LOGIC); |
|
149 | send_ko : OUT STD_LOGIC); | |
150 | END COMPONENT; |
|
150 | END COMPONENT; | |
151 |
|
151 | |||
152 | COMPONENT fifo_latency_correction |
|
152 | COMPONENT fifo_latency_correction | |
153 | PORT ( |
|
153 | PORT ( | |
154 | HCLK : IN STD_ULOGIC; |
|
154 | HCLK : IN STD_ULOGIC; | |
155 | HRESETn : IN STD_ULOGIC; |
|
155 | HRESETn : IN STD_ULOGIC; | |
156 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
156 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
157 | fifo_empty : IN STD_LOGIC; |
|
157 | fifo_empty : IN STD_LOGIC; | |
158 | fifo_ren : OUT STD_LOGIC; |
|
158 | fifo_ren : OUT STD_LOGIC; | |
159 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
159 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
160 | dma_empty : OUT STD_LOGIC; |
|
160 | dma_empty : OUT STD_LOGIC; | |
161 | dma_ren : IN STD_LOGIC); |
|
161 | dma_ren : IN STD_LOGIC); | |
162 | END COMPONENT; |
|
162 | END COMPONENT; | |
|
163 | ||||
|
164 | COMPONENT lpp_dma_ip | |||
|
165 | GENERIC ( | |||
|
166 | tech : INTEGER; | |||
|
167 | hindex : INTEGER; | |||
|
168 | pindex : INTEGER; | |||
|
169 | paddr : INTEGER; | |||
|
170 | pmask : INTEGER; | |||
|
171 | pirq : INTEGER); | |||
|
172 | PORT ( | |||
|
173 | HCLK : IN STD_ULOGIC; | |||
|
174 | HRESETn : IN STD_ULOGIC; | |||
|
175 | AHB_Master_In : IN AHB_Mst_In_Type; | |||
|
176 | AHB_Master_Out : OUT AHB_Mst_Out_Type; | |||
|
177 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
178 | fifo_empty : IN STD_LOGIC; | |||
|
179 | fifo_ren : OUT STD_LOGIC; | |||
|
180 | header : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
181 | header_val : IN STD_LOGIC; | |||
|
182 | header_ack : OUT STD_LOGIC; | |||
|
183 | ready_matrix_f0_0 : OUT STD_LOGIC; | |||
|
184 | ready_matrix_f0_1 : OUT STD_LOGIC; | |||
|
185 | ready_matrix_f1 : OUT STD_LOGIC; | |||
|
186 | ready_matrix_f2 : OUT STD_LOGIC; | |||
|
187 | error_anticipating_empty_fifo : OUT STD_LOGIC; | |||
|
188 | error_bad_component_error : OUT STD_LOGIC; | |||
|
189 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
190 | status_ready_matrix_f0_0 : IN STD_LOGIC; | |||
|
191 | status_ready_matrix_f0_1 : IN STD_LOGIC; | |||
|
192 | status_ready_matrix_f1 : IN STD_LOGIC; | |||
|
193 | status_ready_matrix_f2 : IN STD_LOGIC; | |||
|
194 | status_error_anticipating_empty_fifo : IN STD_LOGIC; | |||
|
195 | status_error_bad_component_error : IN STD_LOGIC; | |||
|
196 | config_active_interruption_onNewMatrix : IN STD_LOGIC; | |||
|
197 | config_active_interruption_onError : IN STD_LOGIC; | |||
|
198 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
199 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
200 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
201 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); | |||
|
202 | END COMPONENT; | |||
163 |
|
203 | |||
164 | END; |
|
204 | END; |
@@ -1,7 +1,8 | |||||
|
1 | lpp_dma_pkg.vhd | |||
1 | fifo_test_dma.vhd |
|
2 | fifo_test_dma.vhd | |
2 | fifo_latency_correction.vhd |
|
3 | fifo_latency_correction.vhd | |
3 | lpp_dma_send_1word.vhd |
|
4 | lpp_dma_send_1word.vhd | |
4 | lpp_dma_send_16word.vhd |
|
5 | lpp_dma_send_16word.vhd | |
5 | lpp_dma_apbreg.vhd |
|
6 | lpp_dma_apbreg.vhd | |
|
7 | lpp_dma_ip.vhd | |||
6 | lpp_dma.vhd |
|
8 | lpp_dma.vhd | |
7 | lpp_dma_pkg.vhd |
|
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